High breakdown voltage gate driver

Abstract

To provide a high breakdown voltage gate driver capable of suppressing heat generation of a high breakdown voltage element, eliminating the need for a high breakdown voltage resistor or the like for detecting a high voltage, and preventing malfunction due to noise caused by a power supply voltage fluctuation.SOLUTION: A high breakdown voltage gate driver includes a first high breakdown voltage element that generates a signal corresponding to a rise of a drive signal of a high side driver based on a level shift of a discrete pulse signal of a low potential, and a second high breakdown voltage element that generates a signal corresponding to a fall of the drive signal. The high breakdown voltage gate driver comprises a differential signal output type first level shift circuit that triggers these signals to a latch circuit and a second level shift circuit that generates a signal obtained by level-shifting an output of the latch circuit and generates a stop signal of a low potential that stops a signal input to the first level shift circuit from the signal, and a discrete pulse signal is formed by an input signal applied to an input of the first level shift circuit and the stop signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a high-voltage gate driver that controls a high-voltage side power device of a half-bridge circuit using power devices, and in particular to a gate driver that includes a level shift circuit with excellent noise resistance. [Background technology]

[0002] In a half-bridge circuit for driving power devices in a power conversion device such as a switching power supply or an inverter for driving a motor, the higher-potential side of two totem-pole-connected power devices is driven by a high-side driver. The control signal required to drive the high-side driver is transmitted via a high-voltage gate driver equipped with a level shift circuit that shifts the input signal to a high potential. A conventional high-voltage gate driver will now be described using FIG. 13. Note that this figure shows a half-bridge circuit using IGBTs (Insulated Gate Bipolar Transistors) as power devices as a whole, but the low-side driver that drives the power device on the low-potential side and its preceding gate driver are not shown because they are not relevant to the present invention.

[0003] In this diagram, the level shift circuit 3 consists of n-type MOS transistors MN1 and MN2, resistors R1 and R2, clamp diodes D1 and D2, high-voltage n-type MOS transistors MN1 and MN2, and inverters INV1 and INV2. One end of resistors R1 and R2 is connected to the high-side power supply VHH, and the other end is connected to the drains of n-type MOS transistors MN1 and MN2, respectively, whose sources are connected to ground GND. Clamp diodes D1 and D2 are connected in antiparallel to resistors R1 and R2, respectively, to limit excessive voltage drops across resistors R1 and R2 and protect inverters INV1 and INV2. Note that clamp diodes D1 and D2 may also be Zener diodes.

[0004] The signals output from the drain terminals of n-type MOS transistors MN1 and MN2 are applied via inverters INV1 and INV2, respectively, to the set terminal S and reset terminal R of a latch circuit LAT consisting of an RS flip-flop. This triggers the inversion of the Q output of the latch circuit LAT, which is then applied to the high-side driver HSD. Therefore, if discrete pulse signals corresponding to the rising and falling edges of the drive signal to be applied to the power device IGBTH are generated and these pulse signals are applied alternately as drive signals to the gates of n-type MOS transistors MN1 and MN2 via input terminals IN1 and IN2, a differential signal is triggered and input to the set terminal S and reset terminal R of the latch circuit LAT, and a voltage signal with a shape similar to the drive signal appears at the Q output. This is applied to the high-side driver HSD, which then generates the drive signal. In this way, the IGBTH can be controlled on and off.

[0005] As mentioned above, the level shift circuit generates a high-voltage pulse based on a low-voltage pulse and transmits the signal to the downstream circuit. Therefore, for example, high-voltage elements (n-type MOS transistors MN1 and MN2 in the figure) capable of withstanding a drain-source voltage Vds of 1000 V or more are used. However, if these elements are kept ON while a high voltage is applied between their drain and source, significant power loss occurs and the elements themselves may even be destroyed. Conversely, if the pulse signal that turns ON the high-voltage elements is too short, noise generated by voltage fluctuations at the OUT terminal (the connection node between the high-potential side power device and the low-potential side power device) associated with the ON / OFF of the power devices can affect the operation and cause malfunctions. To avoid the above problems, conventional methods have been used, such as combining a high-voltage element with an element that limits current, or removing noise by filtering.

[0006] FIG. 14 shows an example of the invention disclosed in Patent Document 1, combining a high-voltage element with a current-limiting element. In this document, the source resistance of n-type MOS transistor MN1 is the combined resistance of the on-resistance of n-type MOS transistor MN8 and resistor R13, and the source resistance of n-type MOS transistor MN2 is the combined resistance of the on-resistance of n-type MOS transistor MN9 and resistor R14. The voltage of the high-side power supply VHH is divided by resistors R10 and R11 and applied to the gate of n-type MOS transistor MN7. Voltage fluctuations are detected at the drain output of n-type MOS transistor MN7. The detected voltage controls the on / off switching of n-type MOS transistors MN8 and MN9. Therefore, when a high voltage is detected, n-type MOS transistors MN8 and MN9 turn off, and the source resistance of n-type MOS transistors MN1 and MN2 becomes only resistors R12 and R13, limiting the current flowing through n-type MOS transistors MN1 and MN2.

[0007] FIG. 15 shows an example of the invention disclosed in Patent Document 2, in which noise is removed by filtering. In this example, a logic filter LF is inserted between the level shift circuit 3 and the latch circuit LAT. For simplicity of explanation, the other circuit configurations are the same as in FIG. 13. Before explaining this example, the mechanism by which a malfunction occurs in the conventional circuit shown in FIG. 13 will be explained using FIG. 16.

[0008] Figure 16 is a timing chart showing the voltages at input terminals IN1 and IN2, the drain currents of n-type MOS transistors MN1 and MN2, the voltage at the leg power supply VDDP, and the voltage at the OUT terminal when all input signals are low. Because the voltages at input terminals IN1 and IN2 are low and n-type MOS transistors MN1 and MN2 are turned off, there is no voltage drop across resistors R1 and R2, and the current flowing through level shift circuit 3 is initially zero. However, as the power device IGBTH is turned on and off, the recovery current of the freewheeling diode (not shown) causes the voltages at the leg power supply VDDP and OUT terminals to fluctuate, generating a dV / dt transient signal (approximately the center of the timing chart). This causes fluctuations in the floating power supply VDDH connected to the output node and the high-side power supply VHH connected to it. This causes discharge from the parasitic capacitance of n-type MOS transistors MN1 and MN2, exceeding the current threshold TH and inputting a common-mode signal to both the set terminal S and the reset terminal R of the latch circuit LAT. This results in malfunction of the latch circuit LAT.

[0009] The logic filter LF in Figure 15 holds the output Q of the latch circuit LAT when an in-phase signal such as the one described above occurs, thereby preventing circuit malfunction. Figure 17 shows the specific configuration of the logic filter LF, which is described below. The outputs of inverters INV1 and INV2 are connected to the input of the EXNOR circuit EN and to one input of the NAND circuits NAND3 and NAND4. The output of this EXNOR circuit EN is connected to the input of inverter INV8, whose output is connected to the other input of the NAND circuits NAND3 and NAND4. The outputs of NAND circuits NAND3 and NAND4 are connected to the inputs of inverters INV9 and INV10, respectively, whose outputs are connected to the set terminal S and reset terminal R of the latch circuit LAT, respectively. With this configuration, the output of the EXNOR circuit EN, which receives an in-phase signal (H, H), becomes H, which is inverted to L by inverter INV8 and applied to one input terminal of NAND3 and NAND4. Since the signals applied to the other input terminals of NAND3 and NAND4 are H, the outputs of these NAND circuits are both H. These outputs are inverted by INV9 and INV10, and L is applied to both the set terminal S and reset terminal R of the latch circuit LAT, resulting in the output Q maintaining its state. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2020-025158 [Patent Document 2] Japanese Patent Application Publication No. 09-200017 Summary of the Invention [Problem to be solved by the invention]

[0011] As mentioned above, in a high-voltage gate driver, if the pulse signal that turns on the high-voltage elements of the level shift circuit is too long, current will continue to flow through the high-voltage elements, which may be destroyed by heat generation. The invention disclosed in Patent Document 1 is one way to solve this problem, but it requires the formation of a resistor with a special structure that can withstand high voltages on the semiconductor chip.

[0012] On the other hand, if the pulse signal that turns on the high-voltage element of the level shift circuit is too short, the level shift circuit may malfunction due to noise (mainly caused by parasitic capacitance between the drain and source of the high-voltage element) associated with power supply voltage fluctuations due to voltage fluctuations at the output node. In the invention disclosed in Patent Document 2, a logic filter is placed before the latch circuit, so malfunction can be prevented if the same voltage is applied to the pull-up resistors of the level shift circuit. However, if a different noise voltage occurs, the latch circuit LAT will erroneously detect it. To prevent this, while the high-side power supply VHH is fluctuating, a potential difference corresponding to the input signal must be generated in the voltages generated across resistors R1 and R2. For this reason, the pulse signal input to level shift circuit 3 must be maintained for the transition time. In view of the above problems, one of the objects of the present invention is to provide a high-voltage gate driver that suppresses heat generation in high-voltage elements, does not require high-voltage resistors or the like for detecting high voltages, and can prevent malfunctions due to noise caused by fluctuations in the power supply voltage. [Means for solving the problem]

[0013] According to one aspect of the present invention, there is provided a high-voltage gate driver for driving a high-side power device of a half-bridge circuit in which a high-side power device and a low-side power device are totem-pole connected, the high-voltage gate driver comprising: a high-side driver that applies a drive signal to a gate of the high-side power device; a latch circuit that applies the drive signal to the high-side driver; a first high-voltage element that level-shifts a low-potential discrete pulse signal and, based on the level-shifted signal, generates a signal corresponding to a rising edge of the drive signal for the high-side driver; and a second high-voltage element that generates a signal corresponding to a falling edge of the drive signal, the first level-shift circuit being a differential signal output type that triggers input of these signals to the latch circuit; and a second level-shift circuit that level-shifts the output of the latch circuit and generates, from the level-shifted signal, a low-potential stop signal that stops signal input to the first level-shift circuit, the discrete pulse signal being formed by an input signal applied to the input of the first level-shift circuit and the stop signal that stops the input signal. [Effects of the Invention]

[0014] According to one aspect of the present invention, in addition to a first level shift circuit that transmits a signal from the low-voltage power supply side to the floating high-voltage power supply side, a second level shift circuit that transmits a signal from the high-voltage power supply side to the low-voltage power supply side is added.Therefore, after detecting a state in which a differential signal generated by turning on the high-voltage element of the first level shift circuit has been transmitted to the high-voltage power supply side, the signal is transmitted to the low-voltage power supply side via the second level shift circuit, and the high-voltage element of the first level shift circuit is turned off to stop the current flowing through the circuit. With the above-described configuration, the time for which current flows to the high-voltage element of the level shift circuit is optimized compared to conventional methods, and by continuing to flow current to the high-voltage element while the voltage on the high-voltage power supply side is fluctuating, it is possible to prevent malfunction of the level shift circuit and minimize losses that occur due to the continuous flow of current. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a diagram showing a high-voltage gate driver according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing a timing chart of the circuit shown in FIG. [Figure 3] FIG. 10 is a diagram showing a high-voltage gate driver according to a second embodiment of the present invention. [Figure 4] 4 is a diagram illustrating a specific example of the voltage detection circuit illustrated in FIG. 3. FIG. [Figure 5] FIG. 4 is a diagram showing a timing chart of the circuit shown in FIG. [Figure 6] FIG. 10 is a diagram showing a high-voltage gate driver according to a third embodiment of the present invention. [Figure 7] FIG. 7 is a diagram showing a timing chart of the circuit shown in FIG. 6. [Figure 8] FIG. 10 is a diagram showing a high-voltage gate driver according to a fourth embodiment of the present invention. [Figure 9] 9 is a diagram showing voltages or currents at various parts of the circuit in FIG. 8 when the leg power supply voltage fluctuates. [Figure 10] FIG. 10 is a diagram showing a high-voltage gate driver according to a fifth embodiment of the present invention. [Figure 11] FIG. 10 is a diagram showing a high-voltage gate driver according to a sixth embodiment of the present invention. [Figure 12] FIG. 1 is a layout diagram of a high-voltage gate driver according to the present invention. [Figure 13] FIG. 1 is a diagram showing a conventional example. [Figure 14] FIG. 1 is a diagram showing a conventional example. [Figure 15] FIG. 1 is a diagram showing a conventional example. [Figure 16] FIG. 10 is a diagram illustrating a malfunction that occurs in a conventional example. [Figure 17] FIG. 10 illustrates an example of a logic filter. DETAILED DESCRIPTION OF THE INVENTION

[0016] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0017] (First embodiment) The circuit structure and operation of the first embodiment will be described in detail with reference to FIGS. <Circuit structure> As shown in Figure 1, a second level shift circuit 2 is provided in addition to a first level shift circuit 1. The output terminals of AND circuits AND1 and AND2 are connected to the gates of n-type MOS transistors MN1 and MN2, respectively, of first level shift circuit 1. N-type high-voltage MOS transistors MNH1 and MNH2 are inserted between the drains of n-type MOS transistors MN1 and MN2 and one terminal of resistors R1 and R2, respectively, and the gates of these high-voltage MOS transistors MNH1 and MNH2 are connected to the low-side power supply VHL. Clamp diodes D5 and D6 are connected between the sources of high-voltage MOS transistors MNH1 and MNH2 and ground GND, respectively, and these clamp diodes limit excessive voltage increases at the sources of high-voltage MOS transistors MNH1 and MNH2 due to currents from parasitic capacitances CDS1 and CDS2.

[0018] On the other hand, the second level shift circuit 2 includes a p-type MOS transistor MP1, whose gate receives a signal from the output Q of the latch circuit LAT via an inverter INV3, and a p-type MOS transistor MP2, whose gate receives the signal directly from the output Q of the latch circuit LAT. The sources of the p-type MOS transistors MP1 and MP2 are connected to one terminal of resistors R3 and R4, respectively, and the other terminals of the resistors R3 and R4 are connected to the high-side power supply VHH. Clamp diodes D3 and D4 are connected in parallel to the resistors R3 and R4, respectively, to limit excessive voltage drops across the resistors R3 and R4. The drains of the p-type MOS transistors MP1 and MP2 are connected to the sources of p-type high-voltage MOS transistors MPH1 and MPH2, respectively, and the drains of the high-voltage MOS transistors MPH1 and MPH2 are connected to ground GND via resistors R5 and R6, respectively. The gates of the high-voltage MOS transistors MPH1 and MPH2 are connected to the OUT terminal (the negative pole of the floating power supply VDDH, the output node). The output signal of the second level shift circuit 2 is extracted by a comparator COMP1, whose inverting input terminal is connected to the connection node between the high-voltage MOS transistor MPH1 and resistor R5 and whose non-inverting input terminal is connected to the connection node between the high-voltage MOS transistor MPH2 and resistor R6. The output terminal of the comparator COMP1 is connected to one input terminal of an AND circuit AND1 via a delay circuit DEL1 and inverters INV4 and INV5, and is also connected to one input terminal of an AND circuit AND2 via a delay circuit and inverter INV4.

[0019] The first level shift circuit 1 level-shifts signals from the low-voltage side to the high-voltage side, while the second level shift circuit 2, in conjunction with delay circuit DEL1 and other components, level-shifts signals from the high-voltage side to the low-voltage side with a signal delayed by a predetermined time after the gate drive signal for the power device IGBTH switches. The output of this second level shift circuit 2 stops the current flowing through the high-voltage MOS transistor MNH1 or MNH2 through which current is flowing. In other words, the second level shift circuit 2 outputs a stop signal, causing the first level shift circuit to output a differential signal consisting of discrete pulses. The logic filter LF and latch circuit LAT shown in the figure have the same configuration as those disclosed in Patent Document 2, and their outputs switch only when a differential signal is input. The reason why high-voltage MOS transistors (MNH1, MNH2, MPH1, MPH2) are inserted between the resistors (R1, R2, R3, R4) of the level shift circuit and the MOS transistors (MN1, MN2, MP1, MP2) driven by the input signal is that driving low-voltage MOS transistors can increase the switching speed rather than directly driving high-voltage MOS transistors. In this embodiment, for example, LDMOS can be used as the high-voltage MOS transistors.

[0020] <Circuit operation> Figure 2 is a timing chart showing the voltages of various components in the circuit shown in Figure 1 and the drain currents of the high-voltage MOS transistors MNH1 and MNH2. The signals input to input terminals IN1 and IN2 are inverted pulses, unlike conventional discrete pulses. When the input voltage of input terminal IN1 switches to high and input terminal IN2 switches to low, n-type MOS transistor MN1 and high-voltage MOS transistor MNH1 turn on, current flows through resistor R1, and a voltage drop across resistor R1 from the high-side power supply VHH is applied to inverter INV1, triggering a high-level signal to the set terminal S of the latch circuit LAT via the logic filter LF. Meanwhile, high-voltage MOS transistor MNH2 turns off, applying the voltage of the high-side power supply VHH to inverter INV2 and applying a low-level signal to the reset terminal R of the latch circuit LAT via the logic filter LF. As a result, the output Q of the latch circuit LAT switches to high.

[0021] The high-level signal from the output Q of the latch circuit LAT turns on the power device IGBTH via the high-side driver HSD. It is also inverted by inverter INV3 and applied as a low-level signal to the gate of p-type MOS transistor MP1 of the second level shift circuit 2, while being applied as a high-level signal to the gate of p-type MOS transistor MP2. This turns on p-type MOS transistor MP1 and turns off p-type MOS transistor MP2. When p-type MOS transistor MP1 turns on, p-type high-voltage MOS transistor MPH1 also turns on, causing a drain current to flow. This causes a voltage drop across resistor R5, and this voltage is applied to the inverting input terminal of comparator COMP1. Meanwhile, ground level voltage is applied to the non-inverting input terminal of comparator COMP1, causing the output of comparator COMP1 to switch from high to low. The low-level output of comparator COMP1 is delayed by a predetermined time in delay circuit DEL1 and then applied to one input of AND circuit AND1 via inverters INV4 and INV5. The output of the AND circuit AND1 switches to L level, which is applied to the gate of the n-type MOS transistor MN1, turning the n-type MOS transistor MN1 OFF, cutting off the source current of the high-voltage MOS transistor MNH1 and turning MNH1 OFF.

[0022] When input terminal IN1 switches from H level to L level and input terminal IN2 switches from L level to H level, current stops flowing through resistor R1 and starts flowing through resistor R2, causing output Q of latch circuit LAT to switch from H level to L level. This output Q turns off power device IGBTH, turns off p-type MOS transistor MP1 and high-voltage MOS transistor MPH1, and turns on p-type MOS transistor MP2 and high-voltage MOS transistor MPH2. The drain current of high-voltage MOS transistor MPH2 causes a voltage drop across resistor R6, and this voltage is applied to the non-inverting input terminal of comparator COMP1, while ground voltage is applied to the inverting input terminal of comparator COMP1. As a result, the output voltage of comparator COMP1 switches from L level to H level. The H-level output of comparator COMP1 is converted to a L-level signal via inverter INV4 after a predetermined delay time in delay circuit DEL1 and then applied to one input of AND circuit AND2. The output of the AND circuit AND2 switches to L level, which is applied to the gate of the n-type MOS transistor MN2, turning the n-type MOS transistor MN2 OFF, cutting off the source current of the high-voltage MOS transistor MNH2 and turning MNH2 OFF.

[0023] The above is the main circuit operation. Note that the n-type MOS transistors MN1 and MN2 are ON for a short period of time, resulting in a discrete pulse signal being input to the first level shift circuit. This discrete pulse signal is formed by the signal input to the input terminals IN1 and IN2 and the stop signal from the second level shift circuit. The pulse width is determined by the delay time set by the delay circuit DEL1, which is determined based on the time it takes for voltage fluctuations due to dV / dt to occur at the OUT terminal. On the other hand, the current flowing through the second level shift circuit 2 does not stop even when the output switches. Instead, the current flowing through the high-voltage MOS transistors MPH1 and MPH2 is set by resistors R3 and R4 to a value smaller than the current flowing through the first level shift circuit 1, so that it can continue to flow without causing any problems. This is because the second level shift circuit 2 is not directly related to the turn-on / off delay of the power device IGBTH, and therefore does not need to pass as large a current through the high-voltage elements as in the first level shift circuit 1 to shorten the delay time between input and output.

[0024] Furthermore, as shown in Figure 2, voltage fluctuations at the OUT terminal due to dV / dt cause discharge from the parasitic capacitances CDS1 and CDS2, causing current I1' to flow, which is superimposed in phase on the drain currents of the high-voltage MOS transistors MNH1 and MNH2. Furthermore, as explained with reference to Figure 16, even when both n-type MOS transistors MN1 and MN2 of the first level shift circuit 1 are OFF, a common-mode signal may be generated due to discharge from the parasitic capacitances of the high-voltage MOS transistors MNH1 and MNH2 due to the influence of dV / dt. Even if this current I1' is large and the outputs of the inverters INV1 and INV2 both become H level, the Q output of the latch circuit LAT is held by the upstream logic filter LF, so no malfunction of the circuit occurs.

[0025] <Explanation of effect> The rise and fall times of the OUT terminal voltage of the inverter vary depending on the connected load. The first level shift circuit 1 also changes the time it takes to switch because the charge stored in the parasitic capacitance of the high-voltage MOSFET varies depending on the voltage of the high-side power supply VHH. Therefore, the following advantages are achieved by this embodiment: (1) After the output of the latch circuit LAT switches, the second level shift circuit 2 sends a signal to the low-side power supply VHL side, and that output is used to stop the current in the high-voltage MOS transistor MNH1 or MNH2. When discrete pulse signals with fixed widths are applied to the input terminals IN1 and IN2 as in the past, if the pulse width is too short, the current may stop during the transition of the OUT terminal voltage, causing the level shift circuit to malfunction. However, this embodiment can prevent this from happening. (2) If the pulse width is made longer than necessary to prevent the malfunction described in (1) above, the high-voltage MOS transistors MNH1 and MNH2 will generate heat. In particular, if the signal switching period is short, there is a risk of the elements being destroyed. However, in this embodiment, the time for which the current flows is optimized, so this problem is avoided and the operating frequency of the inverter circuit can be easily increased.

[0026] (Second embodiment) The second embodiment will be described with reference to FIGS. <Circuit structure> The difference from the first embodiment is that the delay circuit DEL1 and inverters INV4 and INV5 are replaced with voltage detection circuits VD1 and VD2, NAND circuits NAND1 and NAND2, and an inverter INV6. The voltage detection circuit VD1 has its IN terminal connected to the connection node between the high-voltage MOS transistor MPH1 and resistor R5, and its O terminal connected to one input terminal of the NAND circuit NAND1. The voltage detection circuit VD2 has its IN terminal connected to the connection node between the high-voltage MOS transistor MPH2 and resistor R6, and its O terminal connected to one input terminal of the NAND circuit NAND2. The output terminal of the comparator COMP1 is connected to the other input terminal of the NAND circuit NAND1 via the inverter INV6, and is also connected to the other input terminal of the NAND circuit NAND2. The output terminals of the NAND circuits NAND1 and NAND2 are connected to the AND circuits AND1, AND2, respectively. and one input terminal of AND2.

[0027] The voltage detection circuits VD1 and VD2 may be so-called window comparators, as shown in Figure 4, which are composed of two threshold voltage sources, VREFL and VREFH, two comparators COMP3 and COMP4 that compare the threshold voltages with the input voltage, an AND circuit that takes the logical product of the outputs of these two comparators, and a delay circuit DEL2 that delays the output.This makes it possible to output a stop signal that stops the current flowing to the high-voltage MOS transistor MNH1 or MNH2 only when the input voltage to the voltage detection circuit is equal to or greater than the lower threshold voltage (VREFL) and equal to or less than the upper threshold voltage (VREFH).Note that the delay circuit DEL2 may not be provided.

[0028] <Circuit operation> When the OUT terminal voltage and the voltage of the high-side power supply VHH fluctuate as the power devices IGBTH and IGBTL are turned on and off, the drain-source potential difference of the high-voltage MOS transistors MPH1 and MPH2 in the second level shift circuit 2 also fluctuates. As a result, current flows through the parasitic capacitances CDS3 and CDS4 and into the resistors R5 and R6. The circuit in Figure 6 detects this current flowing through the parasitic capacitance and continues to pass current through the high-voltage MOS transistor MNH1 or MNH2 during this period, preventing malfunction of the first level shift circuit 1 when the OUT terminal voltage fluctuates. Figure 5 shows a timing chart showing the voltages and currents of each part of the circuit in Figure 3.

[0029] For example, if the input signal level to input terminal IN1 switches from low to high, turning on power device IGBTH and increasing the voltage at the OUT terminal and the voltage at the high-side power supply VHH, the terminal potential difference across parasitic capacitance CDS3 widens. Current flows through this parasitic capacitance from the high-side power supply VHH via clamp diode D3 and p-type MOS transistor MP1, raising the voltage at the node connecting high-voltage MOS transistor MPH1 and resistor R5. Similarly, the voltage at the node connecting high-voltage MOS transistor MPH2 and resistor R6 also rises due to parasitic capacitance CDS4. While the voltage at the node connecting high-voltage MOS transistor MPH1 and resistor R5 exceeds the voltage value of threshold voltage source VREFH in Figure 4, the output of comparator COMP3 goes low, and the output of AND circuit AND3 remains low. Therefore, the output of voltage detection circuit VD1 remains low. As a result, the output of the AND circuit AND1 is fixed at H level, the gate voltage of the n-type MOS transistor MN1 remains at H level, and current continues to flow together with the high-voltage MOS transistor MNH1.

[0030] After that, when the OUT terminal voltage settles to the default value of the leg power supply VDDP, the current flowing through the parasitic capacitance stops. Here, the voltage of the IN terminal of the voltage detection circuit VD1 converges to the following value, for example, when current flows through the high-voltage MOS transistor MPH1 and the high-voltage MOS transistor MPH2 is stopped. VIN1=(VDDH-Vgsmph1)·R5 / R3…(Formula 1) In Equation 1, VIN1 is the IN terminal voltage of the voltage detection circuit VD1, VDDH is the voltage of the floating power supply, Vgsmph1 is the gate-source potential difference of the high-voltage MOS transistor MPH1, R3 is the resistance value of resistor R3, and R5 is the resistance value of resistor R5. Note that resistors R3 and R4 have the same resistance value, and resistors R5 and R6 have the same resistance value. By setting this VIN1 value to a value equal to or lower than the voltage of the threshold voltage source VREFH, when the current flowing through the parasitic capacitance CDS3 stops, the output of the voltage detection circuit VD1 becomes H level and the n-type MOS transistor MN1 turns OFF.

[0031] Next, we consider the case where the voltage level of the input signal to input terminal IN1 switches from H to L, turning off the power device IGBTH and causing the OUT terminal voltage to drop from the leg power supply VDDP voltage to GND. In this case, the OUT terminal voltage and the high-side power supply VHH voltage fluctuate due to the effects of dV / dt, causing current to flow through the parasitic capacitance CDS4. At this time, the IN terminal voltage of the voltage detection circuit VD2 drops below the voltage specified in Equation 1. This is compared with the value of the threshold voltage source VREFL, and the O terminal voltage of the voltage detection circuit VD2 is set to maintain a low level while this current is flowing. As a result, the output of the AND circuit AND2 is fixed at a high level, and the gate voltage of n-type MOS transistor MN2 remains high, continuing to pass current along with the high-voltage MOS transistor MNH2. When the OUT terminal voltage eventually settles to ground GND, the current flowing through the parasitic capacitance stops, the output of the voltage detection circuit VD2 switches from a low level to a high level, and n-type MOS transistor MN2 turns off. As shown in Figure 4, the voltage detection circuit has a delay circuit DEL2 provided before its output terminal O. The purpose of this is to prevent the voltage at the terminal O of the voltage detection circuit VD2 from fluctuating momentarily when the voltage at the terminal IN of the voltage detection circuit VD2 temporarily passes between the voltage values ​​of the threshold power supplies VREFH and VREFL when the power device is switched ON / OFF. With the above configuration, while the OUT terminal voltage fluctuates and current flows through the parasitic capacitance of the high-voltage MOSFET, the current of the first level shift circuit 1 can continue to flow.

[0032] <Explanation of effect> In the first embodiment, a delay circuit DEL1 is provided after the comparator COMP1, so that the current in the first level shift circuit does not stop while the OUT terminal voltage is changing. In this embodiment, by detecting a change in the OUT terminal voltage using the current flowing in the parasitic capacitance due to fluctuations in the OUT terminal voltage, it is possible to prevent malfunctions due to the current flowing in the parasitic capacitance and to suppress loss in the high-voltage element because it is possible to pass current through the high-voltage element only while the OUT terminal voltage is fluctuating. In addition to turning the power device IGBTH on and off using the input signal to the input terminals IN1 and IN2, the voltage detection circuit can also detect sudden voltage fluctuations in the leg power supply VDDP, for example, and allow current to flow to the required side of the high-voltage element in the first level shift circuit. This prevents malfunctions even if there is some abnormality in the voltage of the leg power supply VDDP.

[0033] (Third embodiment) The third embodiment will be described with reference to FIGS. <Circuit structure> The difference from the second embodiment is that the connection node between the high-voltage MOS transistor MPH1 and resistor R5 and the connection node between the high-voltage MOS transistor MPH2 and R6 are connected by a series circuit of resistors R7 and R8, which have the same resistance, and that the voltage at the connection node between these resistors is detected, thereby reducing the number of voltage detection circuits to one. The voltage detection circuit VD may be formed by a window comparator, as in the second embodiment.

[0034] <Circuit operation> As mentioned above, the effect of dV / dt associated with the ON / OFF switching of power devices IGBTH and IGBTL causes current to flow through parasitic capacitances CDS3 and CDS4 into resistors R5 and R6. The circuit in Figure 6 detects this current flowing through parasitic capacitance using the series circuit of resistors R7 and R8, and during this time continues to flow current through high-voltage MOS transistor MNH1 or MNH2, preventing malfunction of the first level shift circuit 1 when the OUT terminal voltage fluctuates. Figure 7 shows a timing chart showing the voltages and currents at various points in the circuit in Figure 6.

[0035] For example, if the voltage level at input terminal IN1 switches from low to high, turning on power device IGBTH and increasing the voltage at the OUT terminal and the voltage at the high-side power supply VHH, the terminal potential difference across parasitic capacitance CDS3 widens. Current flows through this parasitic capacitance from the high-side power supply VHH via clamp diode D3 and p-type MOS transistor MP1. The voltage drop across resistor R5 raises the voltage at the junction of resistors R5 and R7. Similarly, the voltage at the junction of resistors R4 and R8 rises. While the voltage at the junction of the series-connected resistors R7 and R8 exceeds the voltage of threshold voltage source VREFH, the output of terminal O of voltage detection circuit VD remains low. As a result, the output of AND circuit AND1 is fixed high, and the gate voltage of n-type MOS transistor MN1 remains high, allowing current to flow along with high-voltage MOS transistor MNH1.

[0036] After that, when the OUT terminal voltage settles to the default value of the leg power supply VDDP, the current flowing through the parasitic capacitances CDS3 and CDS4 stops. Here, the voltage at the IN terminal of the voltage detection circuit VD1 converges to the following value, assuming that current flows through the high-voltage MOS transistor MPH1 and the high-voltage MOS transistor MPH2 is stopped: VIN=(VDDH-Vgsmph1)·R5 / (2·R3) …(Formula 2) In Equation 2, the same symbols as in Equation 1 indicate the same things. The value is half that of Equation 1 because it is assumed that resistors R7 and R8 have the same resistance value, and that the resistance value is sufficiently higher than the resistance values ​​of resistors R5 and R6. By setting this VIN value to a value equal to or lower than the voltage of the threshold voltage source VREFH, when the current flowing through the parasitic capacitance CDS3 stops, the output of the voltage detection circuit VD1 becomes H level and the n-type MOS transistor MN1 turns OFF. When the OUT terminal voltage drops from the voltage of the leg power supply VDDP to the GND level, the IN terminal voltage of the voltage detection circuit VD conversely drops below the voltage in equation 2. By comparing this with the value of the threshold voltage source VREFL and setting the output of the voltage detection circuit to the L level, in this case the n-type MOS transistor MN2 continues to be ON until the OUT terminal voltage drops to the GND level. With the above configuration, while the OUT terminal voltage fluctuates and current flows through the parasitic capacitance of the high-voltage MOSFET, the current of the first level shift circuit 1 can continue to flow.

[0037] <Explanation of effect> As in the second embodiment, this embodiment detects the flow of current through the parasitic capacitance of the high-voltage elements MPH1 and MPH2 by detecting voltage fluctuations across resistors R5 and R6, and continues to allow current to flow through the n-type MOS transistor MN1 or MN2 of the first level shift circuit while the current is flowing. However, in this embodiment, the midpoint of the potential difference between resistors R5 and R6 is generated by resistors R7 and R8, and this voltage is detected by the voltage detection circuit VD, so the voltage detection circuit can be implemented with just one circuit. This makes it possible to simplify the circuit.

[0038] (Fourth embodiment) The fourth embodiment will be described with reference to FIGS. <Circuit structure> As shown in FIG. 8, in this embodiment, a series circuit of an n-type MOS transistor MN3 and a current source IL1 is connected between the drain of n-type MOS transistor MN1 and ground GND, and a series circuit of an n-type MOS transistor MN4 and a current source IL2 is connected between the drain of n-type MOS transistor MN2 and ground GND. Furthermore, the gate of n-type MOS transistor MN3 is connected to input terminal IN1, and the gate of n-type MOS transistor MN4 is connected to input terminal IN2. Except for the omission of current sources I1 and I2, the remaining parts are the same as those in FIG. 6 of the third embodiment. Current sources IL1 and IL2 are set to values ​​sufficiently smaller than the drain currents that would flow when n-type MOS transistors MN1 and MN2 are turned on if these current sources were not present. These current sources may be replaced with resistors or the like to limit the current.

[0039] <Circuit operation> In the first to third embodiments, the current of the high-voltage MOS transistor MNH1 or MNH2 flows only temporarily when the power device IGBTH is turned on or off. In the present embodiment, the current value is switched to continue to flow through the high-voltage MOS transistor MNH1 or MNH2 in accordance with the ON or OFF state of the IGBTH. Figure 9 shows the voltage or current at each part of the circuit in Figure 8 when the voltage of the leg power supply VDDP fluctuates.

[0040] Figure 9 shows the drain currents of high-voltage MOS transistors MNH1 and MNH2 when a high-level signal is input to input terminal IN1 and a low-level signal is input to input terminal IN2. As shown in the figure, if the voltage of the leg power supply VDDP fluctuates for some reason, the parasitic capacitance of high-voltage MOS transistors MNH1 and MNH2 discharges, causing current to flow. At this time, n-type MOS transistor MN3 is ON, MN1 is OFF, and a constant superimposed current flows through high-voltage MOS transistor MNH1 due to current source IL1. Meanwhile, n-type MOS transistors MN2 and MN4 are both OFF, meaning that only the discharge current from parasitic capacitance CDS2 flows through high-voltage MOS transistor MNH2. This creates a difference in the currents flowing through high-voltage MOS transistors MNH1 and MNH2. By using this difference to determine the current threshold TH' of the downstream circuit, it is possible to prevent common-mode signals from being input to latch circuit LAT.

[0041] <Explanation of effect> A constant potential difference is input to both inputs of the logic filter LF even when not switching, preventing malfunction of the second level shift circuit 2 even when there is a sudden fluctuation in the voltage of the leg power supply VDDP at times other than when the power device IGBTH is switching ON / OFF. Furthermore, even if discharge currents from the parasitic capacitances of the high-voltage MOS transistors MNH1 and MNH2 occur with a time lag due to some influence, a constant current flows from the current source IL1 or IL2, allowing the first level shift circuit to always output a differential signal.

[0042] (Fifth embodiment) The fifth embodiment will be described with reference to FIG. <Circuit structure> A temperature sensor TS is provided to detect the temperature of the high-voltage MOS transistors MNH1 and MNH2, and a control circuit (not shown) controls the current source IL1 and / or IL2 based on the output of this sensor, reducing the current value of the n-type MOS transistors MN3 and / or MN4 when the temperature rises and increasing the current value of the n-type MOS transistors MN3 and / or MN4 when the temperature falls. Also, as shown in Fig. 10, the temperature sensor TS may have a function of notifying an external control circuit of the temperature detection result of the high-voltage MOS transistors MNH1 and MNH2. The other parts are the same as those in Fig. 8 of the fourth embodiment.

[0043] <Circuit operation> The larger the current constantly flowing through the n-type MOS transistors MN3 and MN4, the more margin there is to prevent malfunctions caused by noise generated in the first level shift circuit 1 when the voltage of the leg power supply VDDP fluctuates. However, if the current is too high, the high-voltage MOS transistors MNH1 and MNH2 will heat up and, in the worst case, will be destroyed. The appropriate current value varies depending on the voltage applied to these elements, the ambient temperature, and the switching frequency of the OUT terminal. The configuration of this embodiment uses a temperature sensor to monitor the temperatures of these elements and prevent them from rising too high. Furthermore, if the temperature of the high-voltage MOS transistors MNH1 and MNH2 rises more than expected due to an abnormal increase in the switching frequency of the power device IGBTH or the voltage of the leg power supply VDDP, the external notification function described above notifies an external control circuit or the like, and the switching frequency of the power device is reduced or stopped.

[0044] <Explanation of effect> By using a temperature sensor to manage the temperature rise of high-voltage elements, it is possible to secure a noise margin while preventing damage to the elements due to temperature. This temperature sensor can be configured with a bandgap circuit (BGR) or similar and formed on the same chip. Furthermore, if the temperature sensor is configured with a bandgap circuit, for example, the external notification function can be configured with a comparator that compares the output voltage level with a predetermined voltage value, and a switch that, when the comparator output is greater than the predetermined voltage value, connects the output of the bandgap circuit to a specific pad on the semiconductor chip connected to the external notification terminal.

[0045] (Sixth embodiment) The sixth embodiment will be described with reference to FIG. <Circuit structure> Figure 11 shows a configuration in which the logic filter LF and latch circuit LAT of Figure 10 are replaced with a second comparator COMP2 that compares the voltages across resistors R1 and R2, and a comparator input latch circuit CIL that uses the output of the second comparator COMP2 to pull down the voltage of the lower of resistors R1 and R2. The comparator input latch circuit consists of a series circuit of resistor R9 and n-type MOS transistor MN5, a series circuit of resistor R10 and n-type MOS transistor MN6, and an inverter INV7 that inverts the output of the second comparator COMP2. One end of resistor R9 is connected to the connection node between resistor R1 and high-voltage MOS transistor MNH1, and one end of resistor R10 is connected to the connection node between resistor R2 and high-voltage MOS transistor MNH2. The drain of n-type MOS transistor MN5 is connected to the other end of resistor R9, its source is connected to the OUT terminal, and its gate is connected to the output of the second comparator COMP2. The n-type MOS transistor MN6 has a drain connected to the other end of the resistor R10, a source connected to the OUT terminal, and a gate connected to the output of the inverter INV7.

[0046] <Circuit operation> In the first to fifth embodiments, the receiving side (VDDH side) of the first level shift circuit 1 was composed of a logic filter LF made up of a logic circuit and an LAT that latched its output, but in this embodiment, the voltages of the resistors R1 and R2 are compared by a comparator, and the voltage of the resistor with the lower voltage R1 or R2 is pulled down by the output of the comparator, thereby latching on the input side of the comparator. Other operations are unchanged from the first to fifth embodiments.

[0047] <Explanation of effect> As in the fourth and fifth embodiments, a constant current continues to flow while the high-voltage MOS transistor is operating, so the output signal of the first level shift circuit 1 can always be a differential signal. This eliminates the need to use a logic filter that rejects common-mode signal inputs, allowing for a simpler circuit.

[0048] Seventh embodiment A seventh embodiment will be described with reference to FIG. 12. This embodiment relates to the layout of a semiconductor chip. High-voltage transistors such as high-side drivers HSD are formed on the high-voltage side of the area surrounded by an insulating region, and low-voltage transistors such as n-type MOS transistors MN1 to MN6 used for switching are formed on the low-voltage side outside the insulating region. The high-voltage MOS transistors MNH1, NMH2, MPH1, and MPH2 are formed within the insulating region. A specific structure disclosed in Japanese Patent No. 4654574 can be used. The present invention provides a second level shift circuit in addition to a first level shift circuit. These level shift circuits use high-voltage elements, but by using a layout method in which high-voltage elements are formed within an insulating region as shown in Figure 12, even if a second level shift circuit 2 is added, the layout area on the semiconductor chip does not increase. Furthermore, because a high-voltage resistor is not required as in Patent Document 1, a special manufacturing process for forming such a resistor is not required.

[0049] Although the embodiments of the present invention have been described in detail above, the present invention can be implemented by making various changes and modifications to the embodiments within the technical scope of the present invention. For example, in the fourth and fifth embodiments, the logic filter LF can be eliminated by appropriately selecting the current sources IL1 and IL2 for continuously supplying current to the high-voltage elements and setting an appropriate current threshold. In this case, the latch circuit of the sixth embodiment can be used instead of the flip-flop as the latch circuit. [Explanation of symbols]

[0050] 1: first level shift circuit, 2: second level shift circuit, 3: level shift circuit, MN1 to MN9: n-type MOS transistor, MP1, MP2: p-type MOS transistor, MNH1, MNH2, MPH1, MPH2: high-voltage MOS transistor, R1 to R10: resistor, D1 to D6: clamp diode, I1, I2, IL1, IL2: current source, INV1 to INV10: inverter, LF: logic filter, LAT, CIL: latch circuit, HSD: high-side driver, VD, VD1, VD2: voltage detection circuit, AND1 to AND3: AND circuit, NAND1 to NAND4: NAND circuit, EN: EXNOR circuit, IGBTH: high-voltage side power device, IGBTL: low-voltage side power device, VDDP: leg power supply, VHH: high-side power supply, VHL: low-side power supply, VDDH: floating power supply, CDS1 to CDS4: parasitic capacitance

Claims

1. A high-voltage gate driver that drives a high-potential side power device of a half-bridge circuit in which a high-potential side power device and a low-potential side power device are totem-pole connected, a high-side driver that applies a drive signal to a gate of the high-potential side power device; a latch circuit that applies a drive signal to the high-side driver; a first level shift circuit of a differential signal output type, which includes a first high-voltage element that level-shifts a low-potential discrete pulse signal and generates a signal corresponding to the rising edge of a drive signal of the high-side driver based on the level shifted signal, and a second high-voltage element that generates a signal corresponding to the falling edge of the drive signal, and which triggers inputs these signals to the latch circuit; a second level shift circuit that generates a signal obtained by level-shifting the output of the latch circuit and generates, from the signal, a low-potential stop signal that stops signal input to the first level shift circuit; 10. A high-voltage gate driver, wherein the discrete pulse signal is formed by an input signal applied to the input of the first level shift circuit and a stop signal for stopping the input signal.

2. 2. The high-voltage gate driver according to claim 1, wherein the second level shift circuit includes a delay circuit that delays the output of the stop signal by a predetermined time.

3. 2. The high-voltage gate driver according to claim 1, wherein the second level shift circuit includes a voltage detection circuit that detects potential fluctuations caused by dV / dt accompanying ON / OFF of the high-potential side power device and stops output of the stop signal while the potential fluctuations continue.

4. the second level shift circuit includes a third high-voltage element that is turned on by a signal obtained by inverting the output of the latch circuit, and a fourth high-voltage element that is turned on by the output of the latch circuit; the third and fourth high-withstand-voltage elements are arranged between a high-side power supply connected to an output node via a floating power supply and ground, and have parasitic capacitance that is discharged by the potential fluctuation; a first resistor and a second resistor having the same resistance value are inserted between the third and fourth high-voltage elements and the ground, respectively; the voltage detection circuit includes a first window comparator having an input connected to a connection node between the third high-voltage element and the first resistor, and a second window comparator having an input connected to a connection node between the fourth high-voltage element and the second resistor, 4. The high-voltage gate driver according to claim 3, wherein output of the stop signal is stopped by stopping output when an input voltage to the first window comparator or the second window comparator is outside a predetermined range.

5. the second level shift circuit includes a third high-voltage element that is turned on by a signal obtained by inverting the output of the latch circuit, and a fourth high-voltage element that is turned on by the output of the latch circuit; the third and fourth high-withstand-voltage elements are arranged between a high-side power supply connected to an output node via a floating power supply and ground, and have parasitic capacitance that is discharged by the potential fluctuation; a first resistor and a second resistor having the same resistance value are inserted between the third and fourth high-voltage elements and the ground, respectively; a third resistor and a fourth resistor connected in series between a connection node of the third high-voltage element and the first resistor and a connection node of the fourth high-voltage element and the second resistor, the third resistor and the fourth resistor having the same resistance value and sufficiently larger than the resistance values ​​of the first and second resistors, respectively; the voltage detection circuit is composed of one window comparator having a connection node between the third resistor and the fourth resistor as an input; 4. The high-voltage gate driver according to claim 3, wherein output of the stop signal is stopped by stopping output when an input voltage to the one window comparator is outside a predetermined range.

6. the first level shift circuit has a first low-voltage element interposed between the first high-voltage element and ground, and a second low-voltage element interposed between the second high-voltage element and ground; the first and second low-voltage elements are turned on by discrete pulse signals, thereby turning on the first and second high-voltage elements, respectively; a third low-withstand voltage element and a fourth low-withstand voltage element that are alternately turned on by the input signal are connected in parallel to the first and second low-withstand voltage elements, respectively; a first current source is interposed between the third low-voltage element and ground, and a second current source is interposed between the fourth low-voltage element and ground; 6. The high-voltage gate driver according to claim 1, wherein a constant current is passed through the first high-voltage element or the second high-voltage element until the input signal is switched, thereby causing the first level shift circuit to always output a differential signal.

7. a temperature sensor that detects heat generation from the first high-voltage element and / or the second high-voltage element of the first level shift circuit; 7. The high-voltage gate driver according to claim 6, further comprising a control circuit that controls the first current source and / or the second current source based on an output of the temperature sensor.

8. 8. The high-voltage gate driver according to claim 7, wherein the temperature sensor has a notification function for notifying an external device of its output.

9. a first level shift circuit disposed between the first level shift circuit and the latch circuit; 6. The high-voltage gate driver according to claim 1, further comprising a logic filter that holds the output of the latch circuit when an in-phase signal is output from the first level shift circuit.

10. a temperature sensor that detects heat generation from the first high-voltage element and / or the second high-voltage element of the first level shift circuit; 10. The high-voltage gate driver according to claim 9, further comprising a control circuit that controls the first current source and / or the second current source based on an output of the temperature sensor.

11. 11. The high-voltage gate driver according to claim 10, wherein the temperature sensor has a notification function for notifying an external device of its output.

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