Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device and a method for manufacturing a semiconductor device that can improve flexibility in mounting.SOLUTION: A semiconductor device 1 includes: a conductive base material 100 having a first main surface 101; semiconductor chips 110, 120, 130 that are provided on the first main surface and respectively include electrodes 111, 112, 113, 121, 122, 131, 132; a first insulating layer 210 that is provided on the first main surface and covers the semiconductor chips; a first wiring layer 310 that is provided on the first insulating layer and includes first wiring 311 electrically connected to the electrodes; a second insulating layer 220 that is provided on the first insulating layer and covers the first wiring layer; and a second wiring layer that is provided on the second insulating layer and includes external terminals 321, 322 electrically connected to wiring. The external terminals extend outward beyond a side surface of the second insulating layer in a plan view perpendicular to the first main surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor device has been proposed in which a semiconductor chip is mounted on a metal plate, the semiconductor chip is covered with an insulating layer, and wiring electrically connected to the semiconductor chip is provided on the insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-133675 [Patent Document 2] Special Publication No. 2023-133676 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the applications of semiconductor devices have expanded, and there has been an increasing demand for structures that allow greater flexibility in the mounting of semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the degree of freedom in packaging. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure comprises a conductive substrate having a first main surface, a semiconductor chip provided on the first main surface and having a first electrode, a first insulating layer provided on the first main surface and covering the semiconductor chip, a first wiring layer provided on the first insulating layer and including a first wiring electrically connected to the first electrode, a second insulating layer provided on the first insulating layer and covering the first wiring layer, and a second wiring layer provided on the second insulating layer and including an external terminal electrically connected to the first wiring, wherein the external terminal extends outward beyond a side surface of the second insulating layer in a plan view perpendicular to the first main surface. [Effects of the Invention]

[0007] According to the present disclosure, the degree of freedom in implementation can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 2) showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10]FIG. 10 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a mounting example of the semiconductor device according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 1) showing the semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 2) showing the semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing a semiconductor device according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a conductive substrate having a first main surface, a semiconductor chip provided on the first main surface and having a first electrode, a first insulating layer provided on the first main surface and covering the semiconductor chip, a first wiring layer provided on the first insulating layer and including a first wiring electrically connected to the first electrode, a second insulating layer provided on the first insulating layer and covering the first wiring layer, and a second wiring layer provided on the second insulating layer and including an external terminal electrically connected to the first wiring, wherein the external terminal extends outward beyond a side surface of the second insulating layer in a plan view perpendicular to the first main surface.

[0011] Because the external terminals extend outward beyond the side surfaces of the second insulating layer, the semiconductor device can be housed inside an opening formed in a printed wiring board, and the external terminals can be connected to terminals of the printed wiring board, thereby improving the degree of freedom in packaging.

[0012] [2] In [1], the dielectric loss of the first insulating layer may be lower than the dielectric loss of the second insulating layer. In this case, the first insulating layer provides good high-frequency characteristics, allowing greater freedom in selecting a material for the second insulating layer. Therefore, a material that is more soluble in an alkaline solution than the first insulating layer can be used for the second insulating layer, making it easier to process the second insulating layer.

[0013] [3] In [2], an opening that reaches the first wiring may be formed in the second insulating layer. In this case, the opening can be formed using an alkaline solution.

[0014] [4] In [3], a conductive layer may be provided on the bottom and sidewall surfaces of the opening and in contact with the first wiring and the external terminal. In this case, the electrical resistance between the first wiring and the external terminal can be reduced. Furthermore, the conductive layer can improve heat dissipation.

[0015] [5] In [4], a metal sintered body may be provided on the conductive layer. In this case, it is possible to further reduce electrical resistance and further improve heat dissipation.

[0016] [6] In [4], a third insulating layer may be provided on the conductive layer, and the dielectric loss of the third insulating layer may be lower than the dielectric loss of the second insulating layer. In this case, the third insulating layer can protect the conductive layer from intrusion of moisture from the outside.

[0017] [7] In any one of [3] to [6], a covering member may be provided to cover the opening. In this case, the covering member can protect the conductive layer from the intrusion of moisture from the outside.

[0018] [8] In any of [1] to [7], a molding material may be provided to cover the second wiring layer, the second insulating layer, the first wiring layer, and the first insulating layer. In this case, the molding material can protect the conductive layer from intrusion of moisture from the outside.

[0019] [9] In any of [2] to [7], a molding material may be provided to cover the second wiring layer, the second insulating layer, the first wiring layer, and the first insulating layer, and the dielectric loss of the molding material may be lower than the dielectric loss of the second insulating layer. In this case, the molding material can protect the conductive layer from external moisture intrusion, etc. Furthermore, good high-frequency characteristics can be obtained even with the molding material.

[0020]

[10] In any one of [1] to [9], the second wiring layer may include a second wiring and an electronic component electrically connected to the second wiring. In this case, the semiconductor device can include more electronic components.

[0021]

[11] In

[10] , the semiconductor chip may have a second electrode, and the first wiring layer may include a third wiring electrically connected to the second electrode and the second wiring. In this case, the second electrode and an electronic component can be electrically connected.

[0022]

[12] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of: providing a semiconductor chip having a first electrode on a first main surface of a conductive substrate; providing a first insulating layer on the first main surface to cover the semiconductor chip; providing a first wiring layer on the first insulating layer, the first wiring layer including a first wiring electrically connected to the first electrode; providing a second insulating layer on the first insulating layer to cover the first wiring layer; and providing a second wiring layer on the second insulating layer, the second wiring layer including an external terminal electrically connected to the first wiring, wherein the external terminal extends outward beyond a side surface of the second insulating layer in a plan view perpendicular to the first main surface.

[0023] According to this method, it is possible to manufacture a semiconductor device that allows for improved flexibility in packaging as described above.

[0024] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0025] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a semiconductor chip.

[0026] [Configuration of semiconductor device] The configuration of the semiconductor device according to the first embodiment will be described. Figures 1 and 2 are cross-sectional views showing the semiconductor device according to the first embodiment. Figure 1 corresponds to a cross-sectional view taken along line II in Figure 2, and Figure 2 corresponds to a cross-sectional view taken along line II-II in Figure 1.

[0027] As shown in Figures 1 and 2, the semiconductor device 1 of the first embodiment has a metal plate 100, chips 110, 120 and 130, a first insulating layer 210, a first wiring layer 310, a second insulating layer 220, a second wiring layer 320, and an electronic component 610.

[0028] The material of the metal plate 100 is, for example, copper (Cu) or a copper alloy. The copper alloy is, for example, a copper-iron (Fe) alloy. The thickness of the metal plate 100 is, for example, 800 μm or more and 1400 μm or less. The metal plate 100 has a first main surface 101. The metal plate 100 is an example of a conductive substrate.

[0029] Chips 110, 120, and 130 are provided on the first main surface 101. For example, chip 110 is a semiconductor chip including a transistor, and chips 120 and 130 are capacitor chips.

[0030] The chip 110 has a main body 115 and electrodes 111, 112, and 113. The transistor is, for example, a gallium nitride (GaN)-based high electron mobility transistor (HEMT). For example, the electrode 111 is connected to the drain of the transistor, the electrode 112 is connected to the gate of the transistor, and the electrode 113 is connected to the source of the transistor. The electrode 113 is mechanically joined to and electrically connected to the metal plate 100. The electrodes 111 and 112 are provided on the opposite surface to the electrode 113. The chip 110 is an example of a semiconductor chip, the electrode 111 is an example of a first electrode, and the electrode 112 is an example of a second electrode.

[0031] Chip 120 has a main body 125 and electrodes 121 and 122, and chip 130 has a main body 135 and electrodes 131 and 132. Electrodes 121 and 122 are provided on the surface of main body 125 opposite to the surface facing first main surface 101. Electrodes 131 and 132 are provided on the surface of main body 135 opposite to the surface facing first main surface 101.

[0032] The first insulating layer 210 is provided on the first main surface 101 and covers the chips 110, 120, and 130. The thickness of the first insulating layer 210 is, for example, 100 μm or more and 300 μm or less. The first insulating layer 210 contains, for example, an epoxy resin. For example, the relative dielectric constant of the first insulating layer 210 is 3.0 or more and 3.7 or less at 6 GHz, and the dielectric loss is 0.007 or less at 6 GHz. The first insulating layer 210 may contain a filler such as silica.

[0033] A plurality of via holes 211 are formed in the first insulating layer 210. One via hole 211 reaches the electrode 111, and one via hole 211 reaches the electrode 112. One via hole 211 reaches the electrode 121, and one via hole 211 reaches the electrode 122. One via hole 211 reaches the electrode 131, and one via hole 211 reaches the electrode 132.

[0034] The first wiring layer 310 is provided on the first insulating layer 210. The first wiring layer 310 has wires 311, 312, 313, 314, and 315. The wire 311 is electrically connected to the electrode 111 through one via hole 211. The wire 312 is electrically connected to the electrode 112 through one via hole 211. The wire 313 is electrically connected to the electrode 121 through one via hole 211. The wire 314 is electrically connected to the electrode 122 through one via hole 211 and is also connected to the electrode 131 through another via hole 211. The wire 315 is electrically connected to the electrode 132 through one via hole 211. The thickness of the first wiring layer 310 on the first insulating layer 210 is, for example, 35 μm or more and 45 μm or less. The material of the first wiring layer 310 is, for example, copper. The first wiring layer 310 is a redistribution layer. The wiring 311 is an example of a first wiring, and the wiring 312 is an example of a third wiring.

[0035] The second insulating layer 220 is provided on the first insulating layer 210 and covers the first wiring layer 310. The thickness of the second insulating layer 220 is, for example, 50 μm or more and 200 μm or less. The second insulating layer 220 contains, for example, an epoxy resin. The dielectric loss of the second insulating layer 220 may be higher than the dielectric loss of the first insulating layer 210. For example, the relative dielectric constant of the second insulating layer 220 is 3.0 or more and 4.4 or less at 6 GHz, and the dielectric loss is 0.04 or less at 6 GHz. The second insulating layer 220 may contain a filler such as silica.

[0036] A plurality of via holes 221 are formed in the second insulating layer 220. The plurality of via holes 221 reach the wiring 311, and one via hole 221 reaches the wiring 312. One via hole 221 reaches the wiring 313, and the plurality of via holes 221 reach the wiring 315.

[0037] The second wiring layer 320 is provided on the second insulating layer 220. The second wiring layer 320 has external terminals 321 and 322 and wires 323 and 324. The external terminal 321 is electrically connected to the wire 311 through a plurality of via holes 221. The external terminal 322 is electrically connected to the wire 315 through a plurality of via holes 221. The wire 323 is electrically connected to the wire 312 through one via hole 221. The wire 324 is electrically connected to the wire 313 through one via hole 221. The thickness of the second wiring layer 320 on the second insulating layer 220 is, for example, 80 μm or more and 200 μm or less. The material of the second wiring layer 320 is, for example, copper. The second wiring layer 320 is a redistribution layer. The wire 323 is an example of a second wire.

[0038] The external terminal 321 extends outward beyond one side surface 226 of the second insulating layer 220 in a plan view perpendicular to the first main surface 101. The external terminal 322 extends outward beyond a side surface 227 of the second insulating layer 220 opposite the side surface 226 in a plan view perpendicular to the first main surface 101.

[0039] The electronic component 610 is connected to the wiring 323 and 324. For example, the electronic component 610 is a surface mounted device (SMD) and is a discrete component such as a chip capacitor, a chip inductor, or a chip resistor. The electronic component 610 has a main body 615 and electrodes 611 and 612. The electrode 611 is connected to the wiring 323, and the electrode 612 is connected to the wiring 324.

[0040] [Method of manufacturing semiconductor device] A method for manufacturing a semiconductor device according to the first embodiment will now be described. Fig. 3 is a plan view showing the method for manufacturing a semiconductor device according to the first embodiment. Figs. 4 to 14 are cross-sectional views showing the method for manufacturing a semiconductor device according to the first embodiment. Figs. 4 to 14 correspond to cross-sectional views taken along line IV-IV in Fig. 3.

[0041] First, as shown in FIG. 3, a lead frame 150 is prepared. The lead frame 150 has a plurality of main portions 151 and a frame portion 152. In a plan view, the frame portion 152 has rectangular inner and outer edges. In a plan view, the main portion 151 has a rectangular shape with long and short sides. The plurality of main portions 151 are arranged parallel to each short side. In a direction parallel to the short sides of the main portions 151, there are gaps 155 between adjacent main portions 151 and between the main portions 151 and the frame portion 152. Then, the lead frame 150 and layers provided on the lead frame 150 are cut along cutting lines 156. The cutting lines 156 extend along the short sides of the main portions 151 in the vicinity of both short sides and intersect with the gaps 155.

[0042] Next, as shown in FIG. 4, chips 110, 120, and 130 are provided on the upper surface 151A of the main portion 151. The chips 110, 120, and 130 can be fixed to the first main surface 101 using a conductive adhesive such as nanosilver (Ag) paste. Next, a first insulating layer 210 is formed on the upper surface (including the upper surface 151A) of the lead frame 150 to cover the chips 110, 120, and 130. The first insulating layer 210 is formed by, for example, supplying and temporarily curing a material using a mold. The material for the first insulating layer 210 is an organic resin material that does not dissolve in a strong alkaline solution or a strong acid solution within a short time, such as 30 minutes, after final curing, and has a thermal decomposition temperature higher than the temperature at which the second insulating layer 220 is final cured. Examples of such materials include (1) a resin composition containing bisphenol F epoxy resin (approximately 2% by mass), aniline (approximately 3% by mass), and silica particles (90% by mass or more), and (2) a resin composition containing epoxy resin (5% to 10% by mass), phenolic resin (1% to 5% by mass), and silica particles (70% by mass or more).The glass transition temperature Tg of these resin compositions is in the range of 100°C to 200°C, and the main curing conditions under which the crosslinking reaction of the epoxy resin is saturated are in the range of 150°C to 230°C and 1 hour to 5 hours.

[0043] 5, a plurality of via holes 211 are formed in the first insulating layer 210. The via holes 211 can be formed by, for example, irradiating with laser light. After the via holes 211 are formed, a desmear process is performed.

[0044] Next, as shown in FIG. 6, a first wiring layer 310 including wirings 311, 312, 313, 314, and 315 is formed. The formation of the first wiring layer 310 involves, for example, forming an electroless plating layer (seed layer), forming a mask on the seed layer, forming an electrolytic plating layer, removing the mask, and flash etching the seed layer, in that order. This is followed by full curing of the first insulating layer 210. Because the mask will be subjected to pressure from a chemical solution during a subsequent wet process, a spacer may be provided in the gap 155 within the lead frame 150 between the formation of the electroless plating layer and the formation of the mask to maintain the flatness of the mask.

[0045] 7, a laminate of the second insulating layer 220 and a metal foil 320X is prepared. The metal foil 320X may be subjected to a roughening treatment in advance, and after the roughening treatment, the surface of the metal foil 320X may have irregularities with a depth of about 1 μm. For example, the metal foil 320X is a copper foil, and the thickness of the metal foil 320X is 80 μm or more and 200 μm or less. The metal foil 320X and the second insulating layer 220 can be laminated together by thermocompression bonding.

[0046] The second insulating layer 220 is made of a material that dissolves in an alkaline solution after hardening, for example. An example of such a material is a novolac epoxy acrylate having a carboxyl group. Novolac epoxy acrylate has excellent heat resistance and electrical properties and is soluble in an alkaline solution. Novolac epoxy acrylate can be obtained, for example, by adding acrylic acid or methacrylic acid to 90% or more of the epoxy groups of a phenol novolac epoxy or cresol novolac epoxy having a weight-average molecular weight of 1,000 or more, and then adding an acid anhydride to the resulting hydroxyl groups.

[0047] A material that dissolves in an alkaline solution in a partially cured state may be used as the material for the second insulating layer 220. An example of such a material is a thermosetting epoxy resin such as bisphenol A epoxy resin. If the thermosetting epoxy resin is in a partially cured state where the cross-linking reaction between the epoxy groups in the resin and the curing agent (such as a modified diamine or phenol compound) is not saturated, the thermosetting epoxy resin can also dissolve in an alkaline solution.

[0048] 8, the laminate of the second insulating layer 220 and the metal foil 320X is bonded to the first insulating layer 210 and the first wiring layer 310 so as to cover the first insulating layer 210 and the first wiring layer 310 on each main portion 151 and the voids 155. The second insulating layer 220 contacts the first insulating layer 210 and the first wiring layer 310.

[0049] 9, the portions of second insulating layer 220 that overlap with voids 155 in a plan view are removed. Next, second insulating layer 220 is fully cured. Because the thermal decomposition temperature of the material of first insulating layer 210 is higher than the temperature for fully curing second insulating layer 220, first insulating layer 210 does not thermally decompose when second insulating layer 220 is fully cured. If a material that dissolves in an alkaline solution in a pre-cured state is used as the material for second insulating layer 220, second insulating layer 220 is put into a pre-cured state.

[0050] Next, as shown in FIG. 10 , multiple openings 329 are formed in the metal foil 320X, and multiple via holes 221 are formed in the second insulating layer 220 using the metal foil 320X with the openings 329 formed as an etching mask. The openings 329 are formed in the areas where the via holes 221 are to be formed. The openings 329 can be formed by wet etching (window etching) using an acidic solution containing, for example, cupric chloride. The via holes 221 can be formed by, for example, laser light irradiation. The via holes 221 can also be formed by wet etching using, for example, an alkaline solution, using the metal foil 320X with the openings 329 formed as an etching mask. The alkaline solution can be, for example, an alkaline solution containing potassium hydroxide as the main component. The material of the first insulating layer 210 does not dissolve in a strong alkaline solution within a short period of time, such as 30 minutes, because the polymerization reaction and crosslinking reaction of functional groups within the resin are saturated after main curing. Therefore, the first insulating layer 210 does not dissolve when the via holes 221 are formed using an alkaline solution. After the via holes 221 are formed, a desmear process is performed, which includes roughening the sidewall surfaces of the via holes 221. The desmear process makes it easier for an electroless plating layer to adhere to the sidewall surfaces of the via holes 221 later.

[0051] When a material that dissolves in an alkaline solution after full curing is used as the material for second insulating layer 220, opening 329 is formed so that second insulating layer 220 does not dissolve excessively when via hole 221 is formed. Furthermore, when a material that dissolves in an alkaline solution in a pre-cured state is used as the material for second insulating layer 220, second insulating layer 220 is fully cured after the formation of via hole 221 and before desmearing, so that second insulating layer 220 does not dissolve during desmearing.

[0052] Next, as shown in FIG. 11, a plating layer 320Y is formed to fill each opening 329 and the via hole 221. The plating layer 320Y is also formed on the metal foil 320X. The thickness of the plating layer 320Y on the metal foil 320X is, for example, 10 μm or more and 50 μm or less. When forming the plating layer 320Y, for example, an electroless plating layer (seed layer) and an electrolytic plating layer are formed in this order. As the electroless plating layer, for example, a copper layer having a thickness of 0.1 μm or more and 1 μm is formed.

[0053] 12, the laminate of the metal foil 320X and the plating layer 320Y is patterned to form the wiring 323 and 324, the portion that becomes the external terminal 321, and the external terminal 322. The laminate of the metal foil 320X and the plating layer 320Y is patterned by wet etching using an acidic solution containing, for example, cupric chloride.

[0054] 13, electronic component 610 is mounted with electrode 611 connected to wiring 323 and electrode 612 connected to wiring 324.

[0055] Next, as shown in Fig. 14, the laminate of the metal foil 320X and the plating layer 320Y is cut by etching in the area that overlaps with the void 155 in a plan view. As a result, external terminals 321 and 322 are obtained. Furthermore, the lead frame 150 and the layers provided on the lead frame 150 are cut along cutting lines 156 (see Fig. 3). As a result, the main portion 151 is separated from the frame portion 152, and the metal plate 100 is obtained.

[0056] In this manner, the semiconductor device 1 according to the first embodiment can be manufactured.

[0057] 15, the semiconductor device 1 can be used by being housed inside an opening 725 formed in a printed wiring board 720 provided on a heat sink 710 with a flat upper surface, with the metal plate 100 in contact with the heat sink 710. In this example, an external terminal 321 is connected to a terminal 721 of the printed wiring board 720, and an external terminal 322 is connected to a terminal 722. FIG. 15 is a cross-sectional view showing an example of mounting the semiconductor device 1 according to the first embodiment.

[0058] Since the external terminal 321 extends outward beyond the side surface 226 of the second insulating layer 220 and the external terminal 322 extends outward beyond the side surface 227, the semiconductor device 1 can be accommodated inside the opening 725 formed in the printed wiring board 720, and the external terminal 321 can be connected to the terminal 721 of the printed wiring board 720, and the external terminal 322 can be connected to the terminal 722. Also, by bringing the metal plate 100 into contact with the heat sink 710, heat generated in the semiconductor device 1 can be released to the outside through the heat sink 710. Furthermore, it is also possible to apply a ground potential to the semiconductor device 1 through the heat sink 710. In this way, the degree of freedom in mounting can be improved.

[0059] Since the dielectric loss of the first insulating layer 210 is lower than the dielectric loss of the second insulating layer 220, good high-frequency characteristics can be obtained for the first insulating layer 210, and therefore there is a high degree of freedom in selecting the material for the second insulating layer 220. Therefore, a material that is more soluble in an alkaline solution than the first insulating layer 210 can be used as the material for the second insulating layer 220, making it easier to process the second insulating layer 220. For example, the via hole 221 can be formed using an alkaline solution.

[0060] The second wiring layer 320 includes the wiring 323 and has the electronic component 610 electrically connected to the wiring 323, so that more electronic components can be included in the semiconductor device 1. Furthermore, the first wiring layer 310 includes the wiring 312 electrically connected to the electrode 112 of the chip 110 and the wiring 323, so that the electrode 112 and the electronic component 610 can be electrically connected.

[0061] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in that a molding material is included. Fig. 16 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0062] As shown in FIG. 16 , the semiconductor device 2 according to the second embodiment includes a molding material 500. The molding material 500 covers the electronic component 610, the second wiring layer 320, the second insulating layer 220, the first wiring layer 310, and the first insulating layer 210. The thickness of the molding material 500 on the second insulating layer 220 is, for example, 1000 μm or more and 3000 μm or less. The dielectric loss of the molding material 500 is lower than that of the second insulating layer 220. The molding material 500 contains, for example, an epoxy resin. For example, the relative dielectric constant of the molding material 500 is 3.0 or more and 3.7 or less at 6 GHz, and the dielectric loss is 0.007 or less at 6 GHz. The molding material 500 may contain a filler such as silica. The molding material 500 can be formed, for example, after the semiconductor device 1 is completed. The molding material 500 may be made of the same material as the first insulating layer 210.

[0063] Other configurations of the second embodiment are the same as those of the first embodiment.

[0064] The second embodiment also provides the same effects as the first embodiment. Furthermore, the second embodiment can protect the electronic component 610, the second wiring layer 320, the second insulating layer 220, the first wiring layer 310, and the first insulating layer 210 from the intrusion of moisture from the outside.

[0065] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the second insulating layer 220.

[0066] [Configuration of semiconductor device] The configuration of a semiconductor device according to the third embodiment will be described. Figures 17 and 18 are cross-sectional views showing the semiconductor device according to the third embodiment. Figure 17 corresponds to a cross-sectional view taken along line XVII-XVII in Figure 18, and Figure 18 corresponds to a cross-sectional view taken along line XVIII-XVIII in Figure 17.

[0067] In the semiconductor device 3 according to the third embodiment, as shown in FIGS. 17 and 18 , an opening 400 is formed in the second insulating layer 220, reaching the wiring 311 and the first insulating layer 210. The semiconductor device 3 has a conductive layer 410. The conductive layer 410 is made of, for example, copper. The conductive layer 410 is provided on a bottom surface 401 and a sidewall surface 402 of the opening 400, and is in contact with the wiring 311 and the external terminal 321. A portion of the conductive layer 410 may be located on the second insulating layer 220. The thickness of the conductive layer 410 above the wiring 311 is, for example, not less than 30 μm and not more than 50 μm.

[0068] Other configurations of the third embodiment are the same as those of the first embodiment.

[0069] [Method of manufacturing semiconductor device] A method for manufacturing a semiconductor device according to the third embodiment will now be described. Figures 19 to 21 are cross-sectional views showing the method for manufacturing a semiconductor device according to the third embodiment.

[0070] First, as in the first embodiment, processing is performed up to removing the portions of the second insulating layer 220 that overlap with the voids 155 in a plan view (see FIG. 9). Next, as shown in FIG. 19, a plurality of openings 329 and openings 450 are formed in the metal foil 320X, and a plurality of via holes 221 and openings 400 are formed in the second insulating layer 220. The openings 450 are formed above the areas where the openings 400 are to be formed. The openings 450 can be formed simultaneously with the openings 329. The openings 400 can be formed simultaneously with the via holes 221. The openings 329 and the via holes 221 can be formed by the same method as in the first embodiment.

[0071] 20, a plating layer 320Y is formed. The plating layer 320Y can be formed by the same method as in the first embodiment. The plating layer 320Y is also formed on the bottom surface 401 and the side wall surface 402 of the opening 400.

[0072] 21, the laminate of the metal foil 320X and the plating layer 320Y is patterned to form wiring 323 and 324 and a conductive layer 410. In addition, portions that will become external terminals 321 and 322 by subsequent etching are also formed.

[0073] Thereafter, as in the first embodiment, electronic components 610 are mounted, and the laminate of metal foil 320X and plating layer 320Y is cut by etching, and cutting is performed along cutting lines 156.

[0074] In this manner, the semiconductor device 3 according to the third embodiment can be manufactured.

[0075] The third embodiment also provides the same effects as the first embodiment.

[0076] If the dielectric loss of the second insulating layer 220 is higher than that of the first insulating layer 210, the high-frequency characteristics may be lower than when the dielectric loss of the second insulating layer 220 is equal to that of the first insulating layer 210. Furthermore, when the electrode 111 of the chip 110 is connected to the drain of the transistor included in the chip 110, the external terminal 321 functions as an output terminal. In other words, the wiring 311 is connected to the output terminal. In the third embodiment, an opening 400 reaching the wiring 311 is formed in the second insulating layer 220. Therefore, even if the dielectric loss of the second insulating layer 220 is higher than that of the first insulating layer 210, good high-frequency characteristics can be obtained. For example, the 3 dB gain compression point, efficiency, and power gain can be improved compared to the first embodiment.

[0077] Furthermore, since the conductive layer 410 is electrically connected to the wiring 311 and the external terminal 321, the effective cross-sectional area between the wiring 311 and the external terminal 321 increases, and the electrical resistance decreases. This also improves the high-frequency characteristics. Furthermore, since the heat generated in the chip 110 is released via the conductive layer 410, heat dissipation is improved.

[0078] In order to obtain good high frequency characteristics, it is also possible to use a material for second insulating layer 220 that has a dielectric loss of 0.007 or less, similar to that of first insulating layer 210. However, in this case, it may be difficult to properly form via holes 221 in second insulating layer 220 using an alkaline solution.

[0079] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in that a metal sintered body is included. Fig. 22 is a cross-sectional view showing a semiconductor device according to the fourth embodiment.

[0080] 22, the semiconductor device 4 according to the fourth embodiment has a metal sintered body 420. The metal sintered body 420 is provided on the conductive layer 410 inside the opening 400. The metal sintered body 420 includes, for example, copper or silver.

[0081] Other configurations of the fourth embodiment are the same as those of the third embodiment.

[0082] The fourth embodiment also provides the same effects as the third embodiment. Furthermore, according to the fourth embodiment, since the metal sintered body 420 is provided, the effective cross-sectional area between the wiring 311 and the external terminal 321 is further increased, and the electrical resistance is further reduced. Therefore, the high-frequency characteristics are further improved. Furthermore, since the heat generated in the chip 110 is released through the metal sintered body 420, the heat dissipation performance is further improved. Furthermore, since the metal sintered body 420 is provided, the conductive layer 410 can be protected from the intrusion of moisture from the outside.

[0083] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment differs from the third embodiment mainly in that a third insulating layer is provided. Fig. 23 is a cross-sectional view showing a semiconductor device according to the fifth embodiment.

[0084] As shown in FIG. 23 , the semiconductor device 5 according to the fifth embodiment includes a third insulating layer 230. The third insulating layer 230 is provided on the conductive layer 410 inside the opening 400. The dielectric loss of the third insulating layer 230 is lower than the dielectric loss of the second insulating layer 220. The third insulating layer 230 includes, for example, polyphenylene ether (PPE) or liquid crystal polymer (LCP). The dielectric loss of polyphenylene ether is 0.005 or less at 10 GHz. The dielectric loss of liquid crystal polymer is 0.003 or less at 1 GHz.

[0085] Other configurations of the fifth embodiment are the same as those of the third embodiment.

[0086] The fifth embodiment also provides the same effects as the third embodiment. Furthermore, the fifth embodiment has the third insulating layer 230, which can protect the conductive layer 410 from the intrusion of moisture from the outside.

[0087] (Sixth embodiment) Next, a sixth embodiment will be described. The sixth embodiment differs from the third embodiment mainly in that a covering member is provided. Fig. 24 is a cross-sectional view showing a semiconductor device according to the sixth embodiment.

[0088] 24, the semiconductor device 6 according to the sixth embodiment has a solid covering member 430. The covering member 430 covers the opening 400 in a hollow state. The covering member 430 contains, for example, polyether ether ketone (PEEK), ABS resin containing acrylonitrile, butadiene, and styrene, or epoxy resin.

[0089] Other configurations of the sixth embodiment are the same as those of the third embodiment.

[0090] The sixth embodiment also provides the same effects as the third embodiment. Furthermore, the sixth embodiment has the covering member 430, which can protect the conductive layer 410 from the intrusion of moisture from the outside.

[0091] The sixth embodiment may further include a metal sintered body 420 or a third insulating layer 230.

[0092] Seventh embodiment Next, a seventh embodiment will be described. The seventh embodiment differs from the third embodiment mainly in that a molding material is provided. Fig. 25 is a cross-sectional view showing a semiconductor device according to the seventh embodiment.

[0093] 25, the semiconductor device 7 according to the seventh embodiment has a molding material 500, similar to the second embodiment. Other configurations of the seventh embodiment are the same as those of the third embodiment.

[0094] The seventh embodiment also provides the same effects as the third embodiment. Furthermore, the seventh embodiment can protect the electronic component 610, the second wiring layer 320, the second insulating layer 220, the first wiring layer 310, and the first insulating layer 210 from the intrusion of moisture from the outside.

[0095] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0096] 1, 2, 3, 4, 5, 6, 7: Semiconductor device 100: Metal plate 101: First main surface 110, 120, 130: Chip 111, 112, 113, 121, 122, 131, 132, 611, 612: Electrode 115, 125, 135, 615: Main body 150: Lead frame 151: Main section 151A:Top surface 152: Frame 155:Void 156: Cutting line 210: First insulating layer 211, 221: Beer hall 220: Second insulating layer 226, 227: Side 230: Third insulating layer 310: 1st wiring layer 311, 312, 313, 314, 315, 323, 324: Wiring 320: 2nd wiring layer 320X: Metal foil 320Y: plating layer 321, 322: External terminals 329, 400, 450, 725: Opening 401: Bottom 402: Side wall 410: Conductive layer 420: Metal sintered body 430: Covering material 500:Molding material 610: Electronic Components 710: Heat sink 720: Printed wiring board 721, 722: Terminals

Claims

1. a conductive substrate having a first main surface; a semiconductor chip provided on the first main surface and having a first electrode; a first insulating layer provided on the first main surface and covering the semiconductor chip; a first wiring layer provided on the first insulating layer and including a first wiring electrically connected to the first electrode; a second insulating layer provided on the first insulating layer and covering the first wiring layer; a second wiring layer provided on the second insulating layer and including an external terminal electrically connected to the first wiring; and The external terminal extends outward beyond a side surface of the second insulating layer in a plan view perpendicular to the first main surface.

2. The semiconductor device according to claim 1 , wherein the first insulating layer has a lower dielectric loss than the second insulating layer.

3. 3. The semiconductor device according to claim 2, wherein an opening reaching said first wiring is formed in said second insulating layer.

4. 4. The semiconductor device according to claim 3, further comprising a conductive layer provided on a bottom surface and a sidewall surface of said opening, said conductive layer being in contact with said first wiring and said external terminal.

5. 5. The semiconductor device according to claim 4, further comprising a metal sintered body provided on said conductive layer.

6. a third insulating layer provided on the conductive layer; The semiconductor device according to claim 4 , wherein the third insulating layer has a lower dielectric loss than the second insulating layer.

7. The semiconductor device according to claim 3 , further comprising a covering member that covers the opening.

8. 7. The semiconductor device according to claim 1, further comprising a molding material that covers the second wiring layer, the second insulating layer, the first wiring layer, and the first insulating layer.

9. a molding material that covers the second wiring layer, the second insulating layer, the first wiring layer, and the first insulating layer; 7. The semiconductor device according to claim 2, wherein the molding material has a dielectric loss lower than a dielectric loss of the second insulating layer.

10. the second wiring layer includes a second wiring, The semiconductor device according to claim 1 , further comprising an electronic component electrically connected to the second wiring.

11. the semiconductor chip includes a second electrode; 11. The semiconductor device according to claim 10, wherein said first wiring layer includes a third wiring electrically connected to said second electrode and said second wiring.

12. a step of providing a semiconductor chip having a first electrode on a first main surface of a conductive substrate; providing a first insulating layer on the first main surface to cover the semiconductor chip; providing a first wiring layer on the first insulating layer, the first wiring layer including a first wiring electrically connected to the first electrode; providing a second insulating layer on the first insulating layer to cover the first wiring layer; providing a second wiring layer on the second insulating layer, the second wiring layer including an external terminal electrically connected to the first wiring; and The external terminal extends outward beyond a side surface of the second insulating layer in a plan view perpendicular to the first main surface.

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