Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same that can form wires more appropriately.SOLUTION: A semiconductor device according to the present embodiment includes a plurality of pads, a bump, and a plurality of wires. The bump is provided on one pad of two adjacent pads. The plurality of wires are provided on the other pad of the two adjacent pads and on the bump. Each wire includes a ball portion and a wire portion. The ball portion is bonded to the other pad of the two adjacent pads or to the bump. The wire portion extends from the ball portion.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In the semiconductor packaging process, for example, wires may be formed by wire bonding on multiple pads provided on a semiconductor chip. If the pad pitch is narrow, the capillary may come into contact with already formed wires. The wires that come into contact with the capillary are deformed, which causes a decrease in yield. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2002 / 0050653 [Patent Document 2] US Patent Application Publication No. 2008 / 0136044 [Patent Document 3] US Patent Application Publication No. 2009 / 0236742 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of more appropriately forming wires and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a plurality of pads, a bump, and a plurality of wires. The bump is provided on one of two adjacent pads. The plurality of wires are provided on the other of the two adjacent pads and the bump. The wire has a ball portion and a wire portion. The ball portion is bonded to the other of the two adjacent pads or the bump. The wire portion extends from the ball portion. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a top view showing an example of the configuration of a semiconductor chip according to a first embodiment. [Figure 3] 1 is a perspective view showing an example of the configuration of a connection portion between a bonding wire and a pad according to the first embodiment. FIG. [Figure 4] 2 is a cross-sectional view showing an example of the configuration of a connection portion between a bonding wire and a pad according to the first embodiment. FIG. [Figure 5] FIG. 10 is a perspective view showing an example of the configuration of a connection portion between a bonding wire and a pad according to a comparative example. [Figure 6] 10 is a cross-sectional view showing an example of the configuration of a connection portion between a bonding wire and a pad according to a comparative example. FIG. [Figure 7] FIG. 10 is a cross-sectional view showing an example of simulation parameters according to a comparative example. [Figure 8] FIG. 3 is a cross-sectional view showing an example of simulation parameters according to the first embodiment. [Figure 9] 10 is a graph showing an example of wire height according to the first embodiment and a comparative example. [Figure 10] 10 is a table showing an example of a magnification ratio according to the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a top view showing an example of the configuration of a semiconductor chip according to a third embodiment. [Figure 13] FIG. 11 is a top view showing an example of the configuration of a semiconductor chip according to a modified example of the third embodiment. [Figure 14] FIG. 11 is a cross-sectional view showing an example of the configuration of a bonding wire according to a modified example of the third embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth embodiment. [Figure 16]FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing an example of the configuration of a bonding wire according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a wiring substrate 10, a semiconductor chip 20, bonding wires 81, and a sealing resin 91. The semiconductor device 1 is, for example, a package of a NAND flash memory.

[0009] 1 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate (wiring substrate 10), and the Z direction, which is perpendicular to the surface of the substrate (wiring substrate 10). In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0010] The wiring board 10 may be a printed circuit board or an interposer including a wiring layer (not shown) and an insulating layer (not shown). The wiring layer may be made of a low-resistance metal such as copper (Cu), nickel (Ni), or an alloy thereof. The insulating layer may be made of an insulating material such as glass epoxy resin. The wiring board 10 may have a multilayer wiring structure formed by laminating multiple wiring layers and multiple insulating layers. The wiring board 10 may have through electrodes that penetrate from its front surface to its back surface, like an interposer, for example.

[0011] A solder resist layer is provided on the surface of the wiring board 10, and is provided on the wiring layer. The solder resist layer protects the wiring layer and is also used as an insulating layer to prevent short-circuit defects. Pads 17 are provided on the surface of the wiring board 10. The pads 17 are wiring layers exposed from the solder resist layer. The pads 17 are electrically connected to the semiconductor chip 20. The pads 17 include, for example, aluminum (Al). However, the pads 17 may also be, for example, gold (Au) plated electrodes.

[0012] A solder resist layer is provided on the wiring layer on the back surface of the wiring board 10. Metal bumps 13 are provided on the wiring layer exposed from the solder resist layer. The metal bumps 13 are provided to electrically connect the wiring board 10 to other components (not shown).

[0013] The semiconductor chip 20 is, for example, a memory chip including a NAND flash memory. The semiconductor chip 20 has a semiconductor element (not shown) on its surface (top surface). The semiconductor element may be, for example, a memory cell array and its peripheral circuit (CMOS (Complementary Metal Oxide Semiconductor) circuit). The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. In the figure, the semiconductor chip 20 is provided as one memory chip. However, two or more semiconductor chips may be stacked.

[0014] The bonding wires 81 are connected to the wiring substrate 10 and any pads 20p of the semiconductor chip 20. The bonding wires 81 are, for example, gold (Au) wires.

[0015] The bonding wires 81 electrically connect the semiconductor chip 20 to the wiring substrate 10. More specifically, the bonding wires 81 electrically connect the semiconductor chip 20 to the pads 17.

[0016] 1, the bonding wire 81 has a ball portion 811 at the end on the pad 20p side of the semiconductor chip 20. That is, the bonding wire 81 is formed by normal bonding. Details of the bonding wire 81 will be described later with reference to FIGS. 3 and 4.

[0017] Furthermore, the semiconductor chip 20, the bonding wires 81, etc. are sealed with a sealing resin 91. As a result, the semiconductor device 1 is configured as a single semiconductor package with the semiconductor chip 20 mounted on the wiring board 10.

[0018] Fig. 2 is a top view showing an example of the configuration of the semiconductor chip 20 according to the first embodiment, as viewed from the Z direction.

[0019] The semiconductor chip 20 is substantially rectangular when viewed in the Z direction.

[0020] The pads 20p are provided on the semiconductor chip 20, for example, along one of the two long sides of the semiconductor chip 20. The number of pads 20p is not limited to the example shown in FIG.

[0021] Fig. 3 is a perspective view showing an example of the configuration of the connection portion between the bonding wire 81 and the pad 20p according to the first embodiment. Fig. 3 is an enlarged perspective view of the vicinity of the connection portion between the bonding wire 81 and the pad 20p.

[0022] Two adjacent pads 20p are provided at a pad pitch such that when continuous bonding is performed, the capillary C comes into contact with the adjacent bonding wire 81. Note that Fig. 3 also shows the position of the capillary C during bonding.

[0023] The semiconductor device 1 further includes a bump B.

[0024] The bump B is provided on one of two adjacent pads 20p. The bump B is provided between the pad 20p and the bonding wire 81. The material of the bump B is the same as the material of the bonding wire 81, for example.

[0025] 3 are provided on the other of the two adjacent pads 20p and on the bump B. The bonding wire 81 provided on the other of the two adjacent pads 20p is an example of a first wire. The bonding wire 81 provided on the bump B is an example of a second wire.

[0026] The bonding wire 81 has a ball portion 811, a wire portion 812, and a wedge portion (not shown).

[0027] The ball portion 811 is bonded to the other of the two adjacent pads 20p or to the bump B. The ball portion 811 on the pad 20p on which the bump B is not provided is bonded to the pad 20p. The ball portion 811 above the pad 20p on which the bump B is provided is bonded to the bump B.

[0028] The wire portion 812 extends from the ball portion 811. As shown in FIG. 3, the wire portion 812 extends, for example, substantially straight up from the ball portion 811 and then extends so as to tilt toward the pad 17.

[0029] As described above, the bonding wire 81 is formed by positive bonding.

[0030] In normal bonding, first, a first bonding (ball bonding) is performed on a pad 20p or a bump B of the semiconductor chip 20 to form a ball portion 811. Next, the capillary C moves so as to obtain a wire portion 812 of a desired shape. Next, a second bonding (wedge bonding) is performed on a pad 17 of the wiring substrate 10 to form a wedge portion, which is the end portion opposite to the ball portion 811.

[0031] 4 is a cross-sectional view showing an example of the configuration of the connection portion between the bonding wire 81 and the pad 20p according to the first embodiment.

[0032] The numbers written on the ball portion 811 and the bump B in FIG. 4 indicate the order (processing group) of the successive bonding processes by the capillary C. The order of successive bonding processes within the same processing group is arbitrary. Also, the height h1 shown in FIG. 4 is the height of the bump B from the semiconductor chip 20. The height h2 is the height of the ball portion 811 from the semiconductor chip 20.

[0033] First, in processing group 1, bumps B are formed on one of two adjacent pads 20p (pad group 20pG1) among the plurality of pads 20p. The bumps B are, for example, stud bumps formed by wire bonding. As shown in FIG. 4, the bumps B are formed on every other pad 20p among the plurality of pads 20p aligned in a first direction (for example, the Y direction shown in FIG. 2), which is the left-right direction on the paper surface of FIG. 4. In other words, the pads 20p on which the bumps B are formed and the pads 20p on which the bumps B are not formed are arranged alternately along the first direction.

[0034] When the pads 20p are provided in two or more rows, the first direction may include the X direction.

[0035] Next, in processing group 2, a bonding wire 81 is formed on the other pad 20p (pad group 20pG2) of the two adjacent pads 20p. A ball portion 811 is provided on the pad 20p by ball bonding.

[0036] Next, in processing group 3, bonding wires 81 are formed on bumps B. Ball portions 811 are provided on bumps B by ball bonding. Note that FIG. 4 also shows the position of capillary C during ball bonding in processing group 3.

[0037] 4, the bonding wire 81 formed in processing group 3 is formed at a position higher by the height h1 of the bump B from the position where the bonding wire 81 is formed in processing group 2. This increases the clearance (gap) between the bonding wire 81 already formed in processing group 2 and the capillary C in processing group 3. As a result, deformation of the bonding wire 81 due to contact with the capillary C can be suppressed, and a decrease in yield can be suppressed. stomach.

[0038] As described above, according to the first embodiment, the bump B is provided on one of two adjacent pads 20p (pad group 20pG1). The multiple bonding wires 81 are provided on the other of the two adjacent pads 20p (pad group 20pG2) and the bump B. This increases the clearance between the formed wire portion 812 and the capillary C. As a result, the bonding wires 81 can be more appropriately formed even with a narrow pad pitch.

[0039] The bonding wires 81 and the bumps B are not limited to gold (Au), and may contain silver (Ag) or copper (Cu).

[0040] Furthermore, the material of the bump B may be different from the material of the bonding wire 81 provided on the bump B. For example, the material of the bump B may be changed to suppress alloying between the pad 20p and the bump B.

[0041] The semiconductor device 1 may further include a controller chip that controls the memory chip.

[0042] 4, the bump B is higher than the ball portion 811, but this is not limited to this. The height of the bump B can be changed depending on the forming conditions. The parameters of the forming conditions include, for example, the size of the ball at the tip of the capillary C before the first bonding (ball bonding), the load during the first bonding, etc.

[0043] 5 is a perspective view showing an example of the configuration of the connection portion between the bonding wire 81 and the pad 20p according to the comparative example. The comparative example differs from the first embodiment in that the bump B is not provided.

[0044] 6 is a cross-sectional view showing an example of the configuration of the connection portion between the bonding wire 81 and the pad 20p according to a comparative example.

[0045] 6 indicates the order (processing group) of successive bonding processes by the capillary C. Note that the order of successive bonding processes within the same processing group is arbitrary.

[0046] In process group 1, a bonding wire 81 is formed on the pad 20p on the left side shown in FIG. 6, and then a bonding wire 81 is formed on the pad 20p on the right side.

[0047] However, if the pad pitch of the pads 20p is narrow, the capillary C will come into contact with the formed bonding wire 81. The bonding wire 81 that comes into contact with the capillary C will be deformed, which will cause a decrease in yield.

[0048] In contrast to this, in the first embodiment, by providing the bump B, it is possible to increase the clearance between the formed wire portion 812 and the capillary C. As a result, even if the pad pitch is narrow, the bonding wire 81 can be formed more appropriately.

[0049] Next, a simulation result of a comparison of wire height between the first embodiment and a comparative example will be described.

[0050] Fig. 7 is a cross-sectional view showing an example of simulation parameters according to a comparative example, and Fig. 8 is a cross-sectional view showing an example of simulation parameters according to the first embodiment.

[0051] The "wire height at which the capillary C does not come into contact" is the highest point of the bonding wire 81 extending vertically in the Z direction from the pad 20p when the capillary C descends to just before contacting the adjacent bonding wire 81 (the length of the bonding wire 81 as seen in the cross-sectional view at the pad 20p). The pad pitch is the distance between the centers of adjacent pads 20p. The wire diameter of the wire portion 812 is, for example, 18 μm. The tip diameter of the capillary C is, for example, 60 μm. The taper angle of the tip of the capillary C is, for example, 5°. The height h1 of the bump B according to the first embodiment is, for example, 15 μm.

[0052] 9 is a graph showing an example of wire height according to the first embodiment and a comparative example. The vertical axis of the graph represents the wire height (μm) at which the capillary C does not come into contact. The horizontal axis of the graph represents the pad pitch (μm).

[0053] 9, the wire height at which the capillary C does not come into contact and the pad pitch are in a proportional relationship. That is, the smaller the pad pitch, the smaller the wire height at which the capillary C does not come into contact.

[0054] Furthermore, for the same pad pitch, the wire height at which the capillary C according to the first embodiment does not come into contact is greater than the wire height at which the capillary C according to the comparative example does not come into contact.

[0055] Fig. 10 is a table showing an example of the magnification ratio according to the first embodiment. The table shown in Fig. 10 is a table in which values ​​are extracted from the simulation results shown in Fig. 9. The magnification ratio (%) is the ratio of the wire height at which the capillary C according to the first embodiment does not contact to the wire height at which the capillary C according to the comparative example does not contact.

[0056] 10 shows, as an example, simulation results for pad pitches in the range of 40 μm to 80 μm. At any pad pitch, the wire height at which the capillary C according to the first embodiment does not come into contact is larger by 15 μm, which is the height of the bump B, compared to the wire height at which the capillary C according to the comparative example does not come into contact. Also, the smaller the pad pitch, the larger the magnification factor.

[0057] It should be noted that the values ​​of the pad pitch and the height of the bumps B described with reference to FIGS. 7 to 10 are not limited to the examples shown in FIGS.

[0058] (Second embodiment) 11 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the second embodiment. The second embodiment differs from the first embodiment in that bumps B are provided in multiple stages that are stacked.

[0059] The semiconductor device 1 further includes multiple stacked bumps B on the pad 20p, i.e., between the pad 20p and the ball portion 811. The bonding wire 81 is provided on the top bump B. This allows the height of the ball portion 811 to be adjusted. Also, the clearance between the formed wire portion 812 and the capillary C can be further increased.

[0060] 11 shows bumps B stacked in two stages, but bumps B may be stacked in three or more stages.

[0061] As in the second embodiment, it is also possible to provide stacked bumps B in multiple stages. The semiconductor device 1 according to the second embodiment can achieve the same effects as the first embodiment.

[0062] (Third embodiment) 12 is a top view showing an example of the configuration of a semiconductor chip 20 according to the third embodiment. The third embodiment differs from the first embodiment in that the semiconductor chip 20 is a logic chip.

[0063] The semiconductor chip 20 is, for example, a controller chip (logic chip) that controls a memory chip. The semiconductor chip 20 has a semiconductor element (not shown) on its surface (top surface). The semiconductor element may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit that constitutes a controller.

[0064] The semiconductor chip 20 is substantially square when viewed in the Z direction.

[0065] The pads 20p are provided on the semiconductor chip 20, for example, along the four sides of the semiconductor chip 20. The number of pads 20p is not limited to the example shown in FIG.

[0066] As in the third embodiment, the semiconductor chip 20 may be a logic chip. The semiconductor device 1 according to the third embodiment can obtain the same effects as the first embodiment.

[0067] (Modification of the third embodiment) 13 is a top view showing an example of the configuration of a semiconductor chip 20 according to a modification of the third embodiment. The modification of the third embodiment differs from the third embodiment in that pads 20p are provided in multiple rows.

[0068] The pads 20p may be arranged in three rows in a grid pattern. Alternatively, the pads 20p may be arranged in two rows or four or more rows. Furthermore, the pads 20p may be arranged in a staggered pattern or the like.

[0069] Fig. 14 is a cross-sectional view showing an example of the configuration of a bonding wire 81 according to a modified example of the third embodiment. Note that Fig. 14 shows some of the pads 17, 20p, the bonding wire 81, and the surrounding configuration. Also, in Fig. 14, the pads 20p are provided in three rows.

[0070] 14, the bonding wires 81 connected to the pads 20p provided on the inner side of the semiconductor chip 20 must be provided so as to exceed the bonding wires 81 connected to the pads 20p provided on the outer side of the semiconductor chip 20. That is, the loop height of the bonding wires 81 connected to the pads 20p provided on the inner side of the semiconductor chip 20 must be higher than the loop height of the bonding wires 81 connected to the pads 20p provided on the outer side of the semiconductor chip 20. Therefore, it is preferable that the height of one bump B is higher toward the inner side of the semiconductor chip 20, or that multiple bumps B are stacked as in the second embodiment. That is, the bumps B on the pads 20p are higher toward the inner side of the semiconductor chip 20.

[0071] Of the multiple pads 20p in which the wire portion 812 extends in the second direction (-X direction in Figure 14) on the end side opposite the ball portion 811, bump B is provided so that the height of the ball portion 811 provided above the pad 20p provided on the opposite side to the second direction is higher than the height of the ball portion 811 provided above the pad 20p provided on the second direction side.

[0072] 14 do not have the same X coordinate. The pads 17 are arranged adjacent to each other at different positions along the direction toward the pads 20p (X direction).

[0073] Furthermore, the inner pads are connected to each other, and the outer pads are connected to each other. Of the multiple pads 20p, the pad 20p closest to pad 17 is connected to the pad 17 closest to pad 20p via a bonding wire 81. Of the multiple pads 20p, the pad 20p farthest from pad 17 is connected to the pad 17 farthest from pad 20p via a bonding wire 81.

[0074] As in the modified example of the third embodiment, the pads 20p may be provided in multiple rows. The semiconductor device 1 according to the modified example of the third embodiment can obtain the same effects as the third embodiment. Furthermore, the semiconductor device 1 according to the modified example of the third embodiment may be combined with the first and second embodiments. That is, the pads 20p of the semiconductor chip 20, which is a memory chip, may be provided in multiple rows.

[0075] (Fourth embodiment) 15 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the fourth embodiment. The fourth embodiment differs from the first embodiment in that the bonding wires 81 are formed by reverse bonding.

[0076] In the example shown in FIG. 15, the bonding wire 81 has a ball portion 811 at the end on the pad 17 side of the wiring board 10.

[0077] Furthermore, a bump B (not shown) is provided on one of two adjacent pads 17. The bump B is provided between the pad 17 and the bonding wire 81.

[0078] In reverse bonding, first, a first bonding (ball bonding) is performed on a pad 17 or a bump B of the wiring substrate 10, thereby forming a ball portion 811. Next, the capillary C moves so as to obtain a wire portion 812 of a desired shape. Next, a second bonding (wedge bonding) is performed on a pad 20p of the semiconductor chip 20, thereby forming a wedge portion, which is the end portion opposite to the ball portion 811.

[0079] In reverse bonding, compared to forward bonding, the wire portion 812 often extends higher above the pad 17 bonded to the ball portion 811. As a result, the capillary C is more likely to come into contact with the bonding wire 81. Therefore, for the same pad pitch, in the fourth embodiment, it is more preferable to provide a bump B than in the case of forward bonding (first embodiment).

[0080] The bonding wires 81 may be formed by mixing forward bonding and reverse bonding.

[0081] As in the fourth embodiment, the bonding wire 81 may be formed by reverse bonding. The semiconductor device 1 according to the fourth embodiment can achieve the same effects as the first embodiment. Furthermore, the semiconductor device 1 according to the fourth embodiment may be combined with the second and third embodiments. That is, in the second and third embodiments, the bonding wire 81 may be formed by reverse bonding.

[0082] (Fifth embodiment) 16 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the fifth embodiment. The fifth embodiment differs from the first embodiment in that bumps B are also provided on pads 17.

[0083] The bump B is also provided between the pad 17 and the wedge portion of the bonding wire 81. This allows the clearance between the formed wire portion 812 and the capillary C to be increased in the second bonding as well. As a result, the bonding wire 81 can be more appropriately formed even with a narrow pad pitch.

[0084] As in the fifth embodiment, bumps B may also be provided on the pads 17. The semiconductor device 1 according to the fifth embodiment can achieve the same effects as the first embodiment.

[0085] (Sixth embodiment) 17 is a cross-sectional view showing an example of the configuration of a bonding wire 81 according to the sixth embodiment. The sixth embodiment differs from the fifth embodiment in that pads p20 are provided in multiple rows. That is, the sixth embodiment is a combination of a modified example of the third embodiment and the fifth embodiment.

[0086] The height of the bumps B on the pads 17 may be adjusted in the same manner as the bumps B described in the modified example of the third embodiment. That is, the further away from the semiconductor chip 20, the higher the bumps B on the pads 17 become.

[0087] Of the multiple pads 17 whose wire portions 812 extend in a third direction (the +X direction in Figure 14) toward the ball portion 811, the bumps B of the pads 17 are arranged so that the height of the wedge portion provided above the pads 17 provided on the opposite side to the third direction is higher than the height of the wedge portion provided above the pads 17 provided on the third direction side.

[0088] The pads p20 may be provided in multiple rows as in the sixth embodiment. The semiconductor device 1 according to the sixth embodiment can achieve the same effects as the fifth embodiment.

[0089] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0090] 1 semiconductor device, 10 wiring substrate, 17 pad, 20 semiconductor chip, 20p pad, 81 bonding wire, 811 ball portion, 812 wire portion, B bump, C capillary

Claims

1. a plurality of first pads; a first bump provided on one of two adjacent first pads; a first wire provided on the other of the two adjacent first pads; a second wire provided on the first bump; Equipped with The first wire is a first ball portion joined to the other of the two adjacent first pads; a first wire portion extending from the first ball portion; and The second wire is a second ball portion bonded to the first bump; a second wire portion extending from the second ball portion; and The semiconductor device, wherein the first bumps are provided on every other first pad among a plurality of the first pads arranged in a first direction.

2. a plurality of stacked first bumps on the first pad; 2. The semiconductor device according to claim 1, wherein the second wire provided on the first bump is provided on the first bump in the uppermost stage.

3. 2. The semiconductor device of claim 1, wherein the first bump is arranged so that, among the plurality of first pads to which the second wire portion extends in the second direction on the end side opposite the second ball portion, the height of the second ball portion arranged above the first pad arranged on the opposite side to the second direction is higher than the height of the second ball portion arranged above the first pad arranged on the second direction side.

4. A substrate; a semiconductor chip provided on the substrate and electrically connected to the substrate via the first wire or the second wire; a plurality of second pads electrically connected to the plurality of first pads via the first wires or the second wires; Furthermore, a plurality of the first pads are provided on one of the substrate and the semiconductor chip; The semiconductor device according to claim 1 , wherein the second pads are provided on the other of the substrate and the semiconductor chip.

5. The semiconductor device according to claim 4 , wherein the second pads are arranged adjacent to each other at different positions along a direction toward the first pads.

6. the first pad, among the plurality of first pads, that is closer to the second pad, is connected to the second pad, among the plurality of second pads, that is closer to the first pad, via the first wire or the second wire; 5. The semiconductor device according to claim 4, wherein the first pad farthest from the second pad among the plurality of first pads is connected to the second pad farthest from the first pad among the plurality of second pads via the first wire or the second wire.

7. The semiconductor device according to claim 4 , further comprising a second bump provided on one of two adjacent second pads.

8. a plurality of the first pads are provided on the semiconductor chip; The semiconductor device according to claim 4 , wherein a plurality of said second pads are provided on said substrate.

9. a plurality of the first pads are provided on the substrate; The semiconductor device according to claim 4 , wherein a plurality of said second pads are provided on said semiconductor chip.

10. The semiconductor device according to claim 1 , wherein the material of the first bump is different from the material of the first wire or the second wire provided on the first bump.

11. 2. The semiconductor device according to claim 1, wherein the first bump is a stud bump.

12. forming a first bump on one of two adjacent first pads among the plurality of first pads; forming a first wire on the other of the two adjacent first pads by ball bonding; forming a second wire on the first bump by ball bonding; A method for manufacturing a semiconductor device, comprising:

13. 9. The method for manufacturing a semiconductor device according to claim 8, wherein forming the first bump includes forming a stud bump by wire bonding.

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