Switching power supply

Abstract

To suppress destruction of a control chip due to application of an overvoltage or a negative voltage.SOLUTION: A switching power supply is provided that includes: a main transformer; a switching element that performs switching control of a main current flowing through the main transformer; a control chip that has a first terminal and controls the switching element; a first capacitor that is connected to the first terminal of the control chip; and a first resistance element that is connected to the first terminal. The control chip has a semiconductor substrate that includes a first connection area connected to the first terminal. The first resistance element is disposed between the first connection area and the first capacitor. The first terminal is a power supply terminal to which power supply power is supplied.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a switching power supply. [Background technology]

[0002] Figure 1 of Patent Document 1 shows a resistance component connected to power supply terminal P1 and a voltage VW between both ends of the resistance component, and paragraph 0036 states that "VW is a voltage generated when a surge current IESD flows through the resistance component of power supply wiring 4." Figure 1 of Patent Document 2 shows a capacitor 35 connected to the VCC terminal of control IC 32. Patent Document 1: JP 2017-152462 A Patent Document 2: JP 2023-9397 A Summary of the Invention [Problem to be solved by the invention]

[0003] This prevents the control chip from being destroyed by the application of excessive voltage or negative voltage. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a switching power supply. The switching power supply may include a main transformer. Any of the above switching power supplies may include a switching element that controls switching of a main current flowing through the main transformer. Any of the above switching power supplies may include a control chip having a first terminal and controlling the switching element. Any of the above switching power supplies may include a first capacitor connected to the first terminal of the control chip. Any of the above switching power supplies may include a first resistive element connected to the first terminal. In any of the above switching power supplies, the control chip may have a semiconductor substrate including a first connection region connected to the first terminal. In any of the above switching power supplies, the first resistive element may be disposed between the first connection region and the first capacitor. In any of the above switching power supplies, the first terminal may be a power supply terminal to which power is supplied.

[0005] A second aspect of the present invention provides a switching power supply. The switching power supply may include a main transformer. Any of the above switching power supplies may include a switching element that controls switching of a main current flowing through the main transformer. Any of the above switching power supplies may include a control chip having a first terminal and controlling the switching element. Any of the above switching power supplies may include a first capacitor connected to the first terminal of the control chip and having a capacitance value of 5 μF or more and 100 μF or less. Any of the above switching power supplies may include a first resistive element connected to the first terminal. In any of the above switching power supplies, the control chip may have a semiconductor substrate including a first connection region connected to the first terminal. In any of the above switching power supplies, the first resistive element may be disposed between the first connection region and the first capacitor. In any of the above switching power supplies, the first terminal may be a power supply terminal to which power from a power source is supplied.

[0006] In any of the above switching power supplies, the first resistor element may be disposed outside the control chip between the first terminal and the first capacitor.

[0007] In any of the above switching power supplies, the first resistor element may be disposed inside the control chip, between the first terminal and the first connection region.

[0008] In any of the above switching power supplies, the resistance value of the first resistor element may be 10Ω or more and 100Ω or less.

[0009] Any of the above switching power supplies may include an auxiliary winding that supplies the power supply power to the first terminal, and a second resistor element that is disposed between the auxiliary winding and the first capacitor and has a resistance value of 10 Ω or more and 100 Ω or less.

[0010] Any of the above switching power supplies may include a second capacitor connected between the first resistive element and the first terminal, the second capacitor having a capacitance value of 50 nF or more and 1000 nF or less.

[0011] In any of the above switching power supplies, the semiconductor substrate may include a first parasitic transistor connected to the first connection region. In any of the above switching power supplies, the control chip may have a second terminal to which a reference potential is applied. In any of the above switching power supplies, the first terminal may be connected to the second terminal via the first parasitic transistor.

[0012] In any of the above switching power supplies, the semiconductor substrate may include a protection element provided between the first terminal and the second terminal, for passing a current from the first terminal to the second terminal when the voltage of the first terminal exceeds an upper limit voltage. In any of the above switching power supplies, the semiconductor substrate may include a second connection region connected to the second terminal. In any of the above switching power supplies, the semiconductor substrate may include a second parasitic transistor for passing a current to the protection element depending on the potential of the second connection region. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of a switching power supply 300. [Figure 2] 3 is a diagram illustrating an example of the operation of the control chip 100. FIG. [Figure 3] 1 is a cross-sectional view of a semiconductor substrate 10 in a control chip 100. FIG. [Figure 4] 1 is a diagram showing an example of the configuration of a switching power supply 200 according to an embodiment of the present invention. [Figure 5] 5 is a diagram illustrating an example of the operation of the control chip 100 shown in FIG. 4. FIG. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor substrate 10 in a control chip 100 according to a modified example. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor substrate 10 in a control chip 100 according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. In a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements. In this specification, terms such as "same" or "equal" may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0015] In describing a circuit, when it is said that element C is provided "between" element A and element B, it means that element C is provided between element A and element B in the electrical path. The above description does not limit the spatial position of element C.

[0016] In this specification, when two elements are described as being "electrically connected," this refers to a state in which an electrical signal, voltage, or current can be transmitted between the two elements. The two elements may be directly connected by wiring or the like, or another electrical element may be present between the two elements.

[0017] 1 is a diagram showing an example of a switching power supply 300. The switching power supply 300 generates a predetermined voltage or current in a secondary winding 112 of the main transformer 110 by repeatedly controlling a switching element 120 connected to a primary winding 111 of a main transformer 110 between an on state and an off state. The switching power supply 300 of this example includes a power supply circuit 230, a primary circuit 210, a secondary circuit 220, and the main transformer 110.

[0018] The primary side circuit 210 may include a power supply circuit 230. The power supply circuit 230 supplies power to the primary side circuit 210. The power supply circuit 230 in this example includes an AC power supply 142, a coil 144, a capacitor 146, a diode bridge section 148, a diode 150, a diode 152, and a capacitor 154. The AC power supply 142 may be an external power supply such as a commercial power supply.

[0019] The coil 144 is connected to the AC power supply 142. The coil 144 may be provided for both the positive output terminal and the negative output terminal of the AC power supply 142. The coil 144 may be a transformer connected to the positive output terminal and the negative output terminal of the AC power supply 142. The capacitor 146 is provided between the positive output terminal and the negative output terminal of the AC power supply 142. The coil 144 and the capacitor 146 remove noise from the AC power output by the AC power supply 142.

[0020] The diode bridge section 148 full-wave rectifies the AC power output by the AC power supply 142. The capacitor 154 smoothes the power rectified by the diode bridge section 148. As a result, the power supply circuit 230 rectifies and smoothes the voltage and current from the AC power supply 142 and outputs them.

[0021] The primary side circuit 210 of this example includes a control chip 100, a primary side winding 111, a switching element 120, a resistor 130, an auxiliary winding 113, a diode 128, a second resistor element 122, a first capacitor 131, a second capacitor 135, a capacitor 134, a capacitor 136, a resistor 132, a thermistor 138, and a resistor 140. Power is supplied to the primary side winding 111 of this example from a power supply circuit 230.

[0022] The secondary side circuit 220 of this example includes a secondary side winding 112, a diode 160, a capacitor 162, a light emitting element 164, a resistor 166, and a diode 168. The secondary side winding 112 is magnetically coupled to the primary side winding 111. The light receiving element 170 shown in FIG. 1 may be provided in the primary side circuit 210.

[0023] The switching element 120 controls the switching of the main current flowing through the main transformer 110. In this example, the switching element 120 is connected in series with the primary winding 111, and controls whether or not the main current flows through the primary winding 111. The switching element 120 is, for example, a power MOSFET. A resistor 130 is provided between the switching element 120 and a reference potential. The resistor 130 adjusts the magnitude of the main current.

[0024] The control chip 100 controls the on and off states of the switching element 120. The control chip 100 may output a control signal OUT to be input to the gate terminal of the switching element 120. The control chip is, for example, an integrated circuit chip. In this example, the OUT terminal of the control chip 100 that outputs the control signal OUT is referred to as the third terminal 103. In addition, in the control chip 100, the GND terminal to which the reference potential GND is applied is referred to as the second terminal 102, and the VCC terminal to which the power supply voltage VCC is applied is referred to as the first terminal 101.

[0025] When switching element 120 is turned on and an excitation current flows through primary winding 111, a load current according to the turn ratio flows through secondary winding 112. The load current flowing through secondary winding 112 is rectified by diode 160. A capacitor 162 is charged by the output of diode 160. An output voltage Vout is applied to the load according to the amount of charge accumulated in capacitor 162.

[0026] The auxiliary winding 113 supplies power to the first terminal 101. In this example, the auxiliary winding 113 is arranged between the first terminal 101 of the control chip 100 and a reference potential. The auxiliary winding 113 is magnetically coupled to the secondary winding 112. That is, a current corresponding to the current of the secondary winding 112 flows through the auxiliary winding 113. A second resistor element 122 and a diode 128 may be arranged between the auxiliary winding 113 and the first terminal 101. The diode 128 rectifies the current flowing through the auxiliary winding 113. The second resistor element 122 is arranged between the diode 128 and the first terminal 101. The current passing through the diode 128 charges the first capacitor 131 and the second capacitor 135.

[0027] The first capacitor 131 is electrically connected to the first terminal 101 of the control chip 100. In this example, the first capacitor 131 is directly connected to the first terminal 101 of the control chip 100 without any other elements passing through. The second capacitor 135 is electrically connected to the first terminal 101 of the control chip 100. The power stored in the first capacitor 131 is supplied as power supply to the control chip 100. In this example, the first capacitor 131 is an electrolytic capacitor. The capacitance of the first capacitor 131 may be larger than the capacitance of the second capacitor 135. Similarly, the capacitance of the first capacitor 131 may be larger than the capacitance of capacitor 134 and capacitor 136. By providing the second capacitor 135, noise in the power supplied to the first terminal 101 is absorbed.

[0028] The control chip 100 may have a CS terminal that detects the magnitude of the main current (in this example, the drain current) flowing through the switching element 120. The CS terminal receives a potential indicating the magnitude of the voltage drop across the resistor 130. A voltage drop occurs across the resistor 130 according to the magnitude of the main current, so the magnitude of the main current can be detected from this potential. The CS terminal in this example receives the potential at the end of the resistor 130 that is connected to the switching element 120. A filter composed of a resistor 132 and a capacitor 134 may be provided between the CS terminal and the resistor 130. When an overcurrent flows through the switching element 120, the control chip 100 may control the switching element 120 to an off state.

[0029] The control chip 100 may have an FB terminal to which a signal indicating the magnitude of the output voltage Vout of the secondary side circuit 220 is input. The light emitting element 164, resistor 166, and diode 168 in the secondary side circuit 220 are connected in series between a terminal that outputs the output voltage Vout and a reference potential. A current corresponding to the magnitude of the output voltage Vout flows through the light emitting element 164, and the light emitting element 164 outputs light with an intensity corresponding to the magnitude of the current. The light emitting element 164 is, for example, a light emitting diode.

[0030] The light receiving element 170 receives the light output by the light emitting element 164. The light receiving element 170 is, for example, a phototransistor. The light receiving element 170 inputs a current corresponding to the intensity of the received light to the FB terminal. As a result, a current corresponding to the output voltage Vout flows through the FB terminal. The primary side circuit 210 may include a capacitor 136 connected in parallel with the light receiving element 170. This makes it possible to remove high frequency components from the current flowing through the FB terminal.

[0031] The voltage at the FB terminal changes depending on the output voltage Vout. The control chip 100 controls the ON and OFF periods of the switching element 120 depending on the voltage at the FB terminal. For example, the control chip 100 shortens the ON period of the switching element 120 in each switching cycle as the output voltage Vout increases.

[0032] The control chip 100 has a VH terminal that supplies a charging current to the VCC terminal when the switching power supply 300 starts up. This charges the first capacitor 131 connected to the VCC terminal. When the voltage of the first capacitor 131 rises and the control chip 100 starts switching control, the supply of charging current from the VH terminal stops. This allows the control chip 100 to start up quickly while reducing power consumption. In this example, the VH terminal is connected to the power supply circuit 230 via diodes 150, 152, and resistor 140.

[0033] The control chip 100 may have an RT terminal for detecting the temperature of the switching power supply 300. A temperature detection element such as a thermistor 138 may be connected to the RT terminal.

[0034] FIG. 2 is a diagram illustrating an example of the operation of the control chip 100. In this example, an overvoltage or negative voltage is applied to any terminal of the control chip 100 other than the first terminal 101 (VCC terminal) and the second terminal 102 (GND terminal). The terminal in question is, for example, the third terminal 103 (OUT terminal), but is not limited to this. An overvoltage is a voltage greater than the maximum rating of the control chip 100, and a negative voltage is a voltage less than 0 V. The maximum rating is the maximum voltage at which the terminal of the control chip 100 is not destroyed by the voltage. An overvoltage or negative voltage can occur, for example, due to a lightning surge. In this specification, an overvoltage or negative voltage may be referred to as a surge voltage or a surge.

[0035] The control chip 100 includes a circuit such as a CMOS formed on a semiconductor substrate. When a surge voltage is applied to the control chip 100, parasitic elements formed on the semiconductor substrate may operate, causing an unexpected current to flow within the semiconductor substrate and potentially destroying the control chip 100. For example, if a surge voltage is applied to the semiconductor substrate, causing the parasitic elements to operate, and the power supply voltage VCC applied to the first terminal 101 is maintained, a current will flow from the first terminal 101 to the semiconductor substrate. This causes the GND potential of the semiconductor substrate to momentarily rise (+ΔV). The rise in GND potential causes other parasitic elements present in the semiconductor substrate to operate, causing an unexpected current to flow through a low-voltage element in the semiconductor substrate, resulting in the destruction of that element. Furthermore, a decrease in the anode potential of a protection element or parasitic diode of the control chip 100 may cause breakdown and thermal destruction.

[0036] 3 is a cross-sectional view of the semiconductor substrate 10 in the control chip 100. The semiconductor substrate 10 is, for example, a silicon substrate, but may also be a compound semiconductor substrate such as a SiC substrate. The semiconductor substrate 10 shown in FIG. 3 is a P-type substrate, but may also be an N-type substrate.

[0037] In this example, semiconductor substrate 10 is provided with elements 20, 30, 40, and 50. In this example, element 20 is an N-channel MOSFET formed in a P-type region of semiconductor substrate 10, and element 30 is a P-channel MOSFET formed in an N-type well region 32 of semiconductor substrate 10. Elements 20 and 30 constitute a CMOSFET.

[0038] Element 40 is formed in an N-type well region 41, and element 50 is formed in an N-type well region 51. Elements 40 and 50 are protection elements provided in series between first terminal 101 and second terminal 102. When the power supply voltage VCC of first terminal 101 exceeds an upper limit voltage, elements 40 and 50 pass a current from first terminal 101 to second terminal 102, thereby protecting elements 20 and 30. In this example, elements 40 and 50 are diodes, and the upper limit voltage is determined by the reverse breakdown voltage of each diode.

[0039] The element 20 has an N+ type source region 23, an N+ type drain region 24, a P+ type contact region 22, and a gate electrode 21. The contact region 22 and the source region 23 are electrically connected to a second terminal 102. A resistor 12 in FIG. 3 indicates a parasitic resistance component between the second terminal 102 and the semiconductor substrate 10. The drain region 24 is electrically connected to a third terminal 103. The gate electrode 21 is disposed opposite a channel region 25 between the source region 23 and the drain region 24. A gate insulating film is provided between the gate electrode 21 and the channel region 25. When a predetermined on-voltage is applied to the gate electrode 21, the channel region 25 is inverted to an N+ type region, and the source region 23 and the drain region 24 become conductive. FIG. 3 shows the state in which the channel region 25 is inverted to an N+ type.

[0040] The element 30 has a P+ type drain region 33, a P+ type source region 34, an N+ type contact region 35, and a gate electrode 31. The contact region 35 and the source region 34 are electrically connected to a first terminal 101. The drain region 33 is electrically connected to a third terminal 103. The gate electrode 31 is disposed opposite an N- type channel region between the source region 34 and the drain region 33. When a predetermined on-voltage is applied to the gate electrode 31, the channel region is inverted to P+ type, and the source region 34 and the drain region 33 become conductive.

[0041] The element 40 has an N+ type cathode region 42 and a P+ type anode region 43. In this example, the element 40 is a PN junction diode. The cathode region 42 is electrically connected to the first terminal 101. The anode region 43 is electrically connected to the cathode region 52 of the element 50. A well region 41 may be provided between the cathode region 42 and the anode region 43.

[0042] The element 50 has an N+ type cathode region 52 and a P+ type anode region 53. In this example, the element 50 is a PN junction diode. The cathode region 52 is electrically connected to the anode region 43 of the element 40. The anode region 53 is electrically connected to the second terminal 102. A well region 51 may be provided between the cathode region 52 and the anode region 53.

[0043] In this example, the semiconductor substrate 10 is provided with a P+ type contact region 14 and a P+ type contact region 16. The contact region 14 and the contact region 16 are electrically connected to the second terminal 102. The contact region 14 and the contact region 16 may be part of an element different from the elements 20 to 50.

[0044] A large number of parasitic elements exist in the semiconductor substrate 10. In the example of FIG. 3, a first parasitic transistor 61 and a second parasitic transistor 62 are shown. The semiconductor substrate 10 also has a first connection region electrically connected to a first terminal 101 and a second connection region electrically connected to a second terminal 102. In the example of FIG. 3, the source region 34, the contact region 35, and the cathode region 42 correspond to the first connection region. In addition, the contact region 14, the contact region 22, the source region 23, the anode region 53, and the contact region 16 correspond to the second connection region.

[0045] The first parasitic transistor 61 is connected to a first connection region (contact region 35 in this example). The first parasitic transistor 61 in this example is an npn transistor in which the contact region 35 functions as a collector region, the drain region 24 functions as an emitter region, and the body of the semiconductor substrate 10 functions as a base region. The first terminal 101 in this example is connected to the second terminal 102 via the first parasitic transistor 61.

[0046] The second parasitic transistor 62 passes a current through the protection element (element 50 in this example) depending on the potential of the second connection region (contact region 14 in this example). The second parasitic transistor 62 in this example is an npn transistor in which the well region 51 functions as a collector region, the drain region 24 functions as an emitter region, and the contact region 14 (or the body of the semiconductor substrate 10) functions as a base region.

[0047] A case will be described in which a negative voltage is applied to one of the terminals of the control chip 100 due to a lightning surge. In this example, the terminal in question is the third terminal 103. When a negative voltage is applied to the third terminal 103, a potential difference occurs between the base and emitter of the first parasitic transistor 61, causing the first parasitic transistor 61 to turn on. As a result, as described in FIG. 2 , a current flows from the first terminal 101 to the second terminal 102. Specifically, the current flows from the first terminal 101 to the second terminal 102 via the contact region 35, the well region 32, the body of the semiconductor substrate 10, the drain region 24, the channel region 25, the source region 23, and the resistor 12.

[0048] 2, when a current flows from the first terminal 101 to the second terminal 102, the GND potential of the contact region 14 rises in accordance with the voltage drop ΔV across the resistor 12. This operation raises the GND potential in the second connection region, allowing the parasitic elements of the semiconductor substrate 10 to operate.

[0049] When the potential of the contact region 14 rises, a potential difference occurs between the base and emitter of the second parasitic transistor 62, turning the second parasitic transistor 62 on. As a result, a current flows from the well region 51 of the protection element 50 to the second terminal 102. Specifically, a current flows from the element 50 to the second terminal 102 via the body of the semiconductor substrate 10, the drain region 24, the channel region 25, the source region 23, and the resistor 12. As a result, the potentials of the well region 51 and the cathode region 52 decrease. Because the element 40 is directly connected to the VCC terminal, the potentials of the well region 41 and the cathode region 42 of the element 40 are fixed to the potential of the VCC terminal. On the other hand, the well region 51 and the cathode region 52 of the element 50 are connected to the anode region 43 of the element 40. Therefore, the potentials of the well region 51 and the cathode region 52 are less stable than those of the well region 41 and the cathode region 42. When the second parasitic transistor 62 operates, a drop in potential is likely to occur in the well region 51 and the cathode region 52, where the potential is unstable.

[0050] As the potential of the cathode region 52 drops, the potential of the anode region 43 of the element 40 also drops. This causes the element 40 to break down. When the broken-down element 40 is thermally destroyed, the element 40 enters a short-circuit state. When the element 40 enters a short-circuit state, the element 50 also breaks down, leading to thermal destruction.

[0051] 3, a protection element is provided on the semiconductor substrate 10, which is made up of two stages of diodes (elements 40 and 50) connected in series. In other examples, the protection element may be made up of more stages of diodes. For example, the protection element may have five stages of diodes connected in series.

[0052] More specifically, one or more stages (for example, three stages) of diodes may be inserted in series between element 40 and element 50. When the protection element is configured with multi-stage diodes, it is preferable that well region 41 and well region 51 are separated by a P-type region to ensure a sufficient breakdown voltage. Furthermore, one or more stages (for example, three stages) of diodes are formed between well region 41 and well region 51.

[0053] In this case, the well region 41 and cathode region 52 of the element 40 are also connected to the VCC terminal. Therefore, the potentials of the well region 41 and cathode region 42 are fixed to the potential of the VCC terminal. Meanwhile, the well region 51 and cathode region 52 of the element 50 are connected to the VCC potential of the well region 41, etc., via the anode region 43 of the element 40 and one or more (e.g., three) diode stages. Therefore, the potential of the well region 51 of the element 50 becomes even more unstable than in the example of FIG. 3, making potential drops even more likely to occur. As a result, each diode (e.g., element 40, etc.) on the higher potential side than the element 50 breaks down, resulting in thermal destruction. Similar to the example of FIG. 3, if the element 40, etc., is short-circuited, the element 50 also breaks down and is thermally destroyed.

[0054] In this example, a case where a negative voltage is applied to the third terminal 103 has been described. However, if an overvoltage or negative voltage is applied to any of the terminals, the GND potential of the second connection region may rise due to the same operation as the first parasitic transistor 61. If the GND potential of the second connection region rises, an unexpected current may flow in any of the elements due to the same operation as the second parasitic transistor 62. For this reason, in the switching power supply 300 described in Figures 1 to 3, the control chip 100 does not have sufficient resistance to lightning surges and the like.

[0055] 4 is a diagram showing an example of the configuration of a switching power supply 200 according to an embodiment of the present invention. The switching power supply 200 of this example includes a first resistor element 121 in addition to the configuration of the switching power supply 300 described with reference to FIGS. 1 to 3. The configuration other than the first resistor element 121 is the same as that of the switching power supply 300.

[0056] The first resistor element 121 is electrically connected to the first terminal 101 of the control chip 100. More specifically, the first resistor element 121 is disposed between the first connection region (e.g., any one of the source region 34, the contact region 35, and the cathode region 42) described in FIG. 3 and the first capacitor 131. The first resistor element 121 is not a parasitic resistance component of wiring or the like, but is a resistance element that is intentionally inserted. The resistance value of the first resistor element 121 is larger than the parasitic resistance component of the wiring from the first terminal 101 to the first capacitor 131.

[0057] By providing the first resistance element 121, it is possible to reduce the current flowing through the first parasitic transistor 61. This makes it possible to suppress or prevent an increase in the GND potential in the second connection region. This makes it possible to suppress an unexpected current from flowing through an element provided on the semiconductor substrate 10 and also to suppress thermal destruction of the protection element.

[0058] In this example, the first terminal 101 is a power supply terminal VCC to which power is supplied. A larger current is supplied to the power supply terminal VCC than to other terminals. Therefore, when a surge voltage is applied to the control chip 100, the first parasitic transistor 61 connected to the power supply terminal VCC passes a large current, significantly raising the GND potential. By providing a first resistor element 121 at the power supply terminal VCC, the current flowing from the power supply terminal VCC to the first parasitic transistor 61 can be suppressed, effectively suppressing the rise in the GND potential.

[0059] The first terminal 101 may be a terminal other than the power supply terminal VCC. Even if the first terminal 101 is a terminal other than the power supply terminal VCC, if the capacitance of the first capacitor 131 connected to the first terminal 101 is large, a parasitic element connected to the first terminal 101 will pass a large current when a surge voltage is applied to the control chip 100. The capacitance of the first capacitor 131 connected to the first terminal 101 may be 5 μF or more and 100 μF or less. As shown in FIG. 4, the first terminal 101 may be the power supply terminal VCC, and the capacitance of the first capacitor 131 may be 5 μF or more and 100 μF or less. The capacitance of the first capacitor 131 may be 10 μF or more, or 20 μF or more.

[0060] The first resistor element 121 may be disposed between the first capacitor 131 and the first terminal 101, and between the second capacitor 135 and the first terminal 101. When the capacitance of the second capacitor 135 is relatively large, the first resistor element 121 is preferably disposed between the first capacitor 131 and the first terminal 101 and between the second capacitor 135 and the first terminal 101. In this example, the capacitance of the second capacitor 135 is 50 nF or more and 1000 nF or less. When the capacitance of the second capacitor 135 is small, as in this case, the second capacitor 135 may be connected to the wiring between the first resistor element 121 and the first terminal 101, as shown in FIG. 4. By providing the second capacitor 135 with a small capacitance, surges generated in the auxiliary winding 113, etc., can be absorbed.

[0061] The resistance value of the first resistor element 121 may be 10 Ω or more and 100 Ω or less. By setting the resistance value of the first resistor element 121 to 10 Ω or more, the current flowing through the first parasitic transistor 61 can be effectively suppressed. The resistance value of the first resistor element 121 may be 20 Ω or more, 30 Ω or more, or 50 Ω or more. By setting the resistance value of the first resistor element 121 to 100 Ω or less, the increase in power consumption due to the provision of the first resistor element 121 can be suppressed.

[0062] In this example, the first resistor element 121 is disposed outside the control chip 100, between the first terminal 101 and the first capacitor 131. This allows the first resistor element 121 to be easily provided. In another example, the first resistor element 121 may be disposed inside the control chip 100, between the first terminal 101 and the first connection region. This allows the withstand capability of the switching power supply 200 to be improved without changing the circuit configuration other than that of the control chip 100.

[0063] The second resistor element 122 is arranged between the auxiliary winding 113 and the first capacitor 131. By providing the second resistor element 122, it is possible to protect the downstream circuit from a surge generated in the auxiliary winding 113. In this example, the second resistor element 122 is arranged between the auxiliary winding 113 and the first capacitor 131 and the first terminal 101. The resistance value of the second resistor element 122 may be 10 Ω or more and 100 Ω or less. The resistance value of the first resistor element 121 may be greater than, the same as, or smaller than the resistance value of the second resistor element 122.

[0064] 5 is a diagram illustrating an example of the operation of the control chip 100 shown in FIG. 4. As described above, the first resistor element 121 is connected to the first terminal 101 of the control chip 100. This makes it possible to suppress the current flowing from the first terminal 101 to the first parasitic transistor 61 when an overvoltage or negative voltage is applied to any terminal of the control chip 100. Furthermore, the voltage at the first terminal 101 is reduced in accordance with the voltage drop across the first resistor element 121.

[0065] The rise in the GND potential can be suppressed or prevented by suppressing the current flowing through the first parasitic transistor 61. This prevents the second parasitic transistor 62 from being turned on, improving the resistance to lightning surges and the like.

[0066] 6 is a cross-sectional view of the semiconductor substrate 10 in the control chip 100 according to a modified example. In this example, a first resistor element 121 is provided between the first terminal 101 and a first connection region (e.g., any one of the source region 34, the contact region 35, and the cathode region 42). The structure other than the first resistor element 121 is the same as the example in FIG. 3.

[0067] The first resistor element 121 may be a polysilicon resistor formed on the semiconductor substrate 10. When the first resistor element 121 is provided inside the control chip 100, the first resistor element 121 may not be provided outside the control chip 100 as shown in FIG. 4. Alternatively, the first resistor elements 121 may be provided both inside and outside the control chip 100. In this case, the combined resistance value of the two first resistor elements 121 may be 10 Ω or more and 100 Ω or less.

[0068] 7 is a cross-sectional view of the semiconductor substrate 10 in the control chip 100 according to a modified example. The semiconductor substrate 10 is not limited to the one including elements 20 to 50 as described in FIG. 3 or 6. If a high-energy surge overvoltage is applied to any terminal of the control chip 100, and a current flows through a parasitic element connected to that terminal, causing a change in the potential of any region, then providing the first resistive element 121 can improve the resistance to the surge voltage.

[0069] The control chip 100 of this example has a fourth terminal 104. The semiconductor substrate 10 is also provided with a P+ type region 71, an N+ type region 72, a P+ type region 73, an N+ type region 74, an N+ type region 75, and an N- type region 76. Regions 71, 72, and 76 are, for example, PN junction diodes functioning as protection elements, but are not limited to this. Regions 73, 74, and 75 may be regions provided in any of the elements. Regions 73, 74, and 75 may be regions of a transistor, a diode, or another element. Regions 73, 74, and 75 function as an NPN-type parasitic transistor 64.

[0070] When an overvoltage surge voltage is applied to the fourth terminal 104 connected to the region 71, a current flows from the fourth terminal 104 to the GND terminal. Specifically, a current flows from the fourth terminal 104 to the GND terminal via the region 71, the region 72, and the resistor 12. This increases the GND potential of the region 73. When the GND potential of the region 73 increases, the parasitic transistor 64 turns on, and a current flows from the region 75 to the region 74. If the region 75 is part of a protection element similar to the element 40 shown in FIG. 3, a breakdown occurs similar to that of the element 40. In contrast, providing a first resistor element 121 can suppress the increase in the GND potential of the region 73. In this example, the first resistor element 121 may be connected to the fourth terminal 104. As shown in FIG. 7, the first resistor element 121 may be provided at the VCC terminal. The first resistor element 121 may be provided inside the control chip 100 as shown in FIG. 7, or may be provided outside the control chip 100 as in the example of FIG. 4.

[0071] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0072] 10 semiconductor substrate, 12 resistor, 14 contact region, 16 contact region, 20 element, 21 gate electrode, 22 contact region, 23 source region, 24 drain region, 25 channel region, 30 element, 31 gate electrode, 32 well region, 33 drain region, 34 source region, 35 contact region, 40 element, 41 well region, 42 Cathode region, 43 Anode region, 50 Element, 51 Well region, 52 Cathode region, 53 Anode region, 61 First parasitic transistor, 62 Second parasitic transistor, 64 Parasitic transistor, 71, 72, 73, 74, 75, 76 Region, 100 Control chip, 101 First terminal, 102 Second terminal, 103 Third terminal, 104 Fourth terminal, 110 Main transistor 111 primary winding, 112 secondary winding, 113 auxiliary winding, 120 switching element, 121 first resistor element, 122 second resistor element, 128 diode, 130 resistor, 131 first capacitor, 132 resistor, 134 capacitor, 135 second capacitor, 136 capacitor, 138 thermistor, 140 resistor, 142 AC power supply, 144 Coil, 146 capacitor, 148 diode bridge section, 150 diode, 152 diode, 154 capacitor, 160 diode, 162 capacitor, 164 light emitting element, 166 resistor, 168 diode, 170 light receiving element, 200 switching power supply, 210 primary side circuit, 220 secondary side circuit, 230 power supply circuit, 300 switching power supply

Claims

1. The main transformer and a switching element that controls switching of a main current flowing through the main transformer; a control chip having a first terminal and controlling the switching element; a first capacitor connected to the first terminal of the control chip; a first resistor element connected to the first terminal; Equipped with the control chip has a semiconductor substrate including a first connection region connected to the first terminal; the first resistor element is disposed between the first connection region and the first capacitor; The first terminal is a power supply terminal to which power is supplied. Switching power supply.

2. The main transformer and a switching element that controls switching of a main current flowing through the main transformer; a control chip having a first terminal and controlling the switching element; a first capacitor connected to the first terminal of the control chip and having a capacitance of 5 μF or more and 100 μF or less; a first resistor element connected to the first terminal; Equipped with the control chip has a semiconductor substrate including a first connection region connected to the first terminal; The first resistor element is disposed between the first connection region and the first capacitor. Switching power supply.

3. The first terminal is a power supply terminal to which power is supplied.

3. The switching power supply according to claim 2.

4. The first resistor element is disposed outside the control chip between the first terminal and the first capacitor.

4. The switching power supply according to claim 1.

5. The first resistor element is disposed inside the control chip between the first terminal and the first connection region.

4. The switching power supply according to claim 1.

6. The resistance value of the first resistor element is 10Ω or more and 100Ω or less.

4. The switching power supply according to claim 1.

7. an auxiliary winding for supplying the power supply power to the first terminal; a second resistor element having a resistance value of 10 Ω or more and 100 Ω or less, which is disposed between the auxiliary winding and the first capacitor; Further provided with 4. The switching power supply according to claim 1 or 3.

8. a second capacitor connected between the first resistor element and the first terminal and having a capacitance value of 50 nF or more and 1000 nF or less 5. The switching power supply according to claim 4.

9. the semiconductor substrate includes a first parasitic transistor connected to the first connection region; the control chip has a second terminal to which a reference potential is applied; The first terminal is connected to the second terminal via the first parasitic transistor.

4. The switching power supply according to claim 1.

10. The semiconductor substrate is a protection element provided between the first terminal and the second terminal, the protection element causing a current to flow from the first terminal to the second terminal when the voltage of the first terminal exceeds an upper limit voltage; a second connection region connected to the second terminal; a second parasitic transistor that causes a current to flow through the protection element in accordance with the potential of the second connection region; 10. The switching power supply of claim 9, comprising:

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