Fan-out type wafer level packaging unit

Abstract

To provide a fan-out type wafer level packaging unit that solves the problem in which a prior art conductive wire requires high manufacturing cost and is disadvantageous for environmental protection.SOLUTION: A fan-out type wafer level packaging unit includes a carrier, at least one lower layer die, a first dielectric layer, at least one first conductive wire, a second dielectric layer, at least one second conductive wire, at least one upper layer die, a third dielectric layer, at least one third conductive wire, a fourth dielectric layer, at least one fourth conductive wire, and an outer protective layer. The at least one lower layer die and the at least one upper layer die form correspondence in which the dies are vertically laminated at an interval. Each of the fourth conductive wires forms a welding pad in each opening of the outer protective layer. The at least one lower layer die and the at least one upper layer die can be electrically connected to the outside from the welding pads located around a chip region of a second surface of each upper layer die.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a packaging unit, and more particularly to a fan-out type wafer-level packaging unit. [Background technology]

[0002] Packaging technology that is light, thin, short, small, and has high efficiency and high reliability is the trend in the development of the semiconductor industry, among which, fan-out type wafer level packaging unit is a conventional packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer is the most important element. Each conductive line in the RDL provides electrical expansion and interconnection to multiple pads on the die in the XY plane, allowing for multiple, more dispersed pads around each die, thereby improving the design space for each conductive line. However, achieving a certain level of lightness, thinness, and compactness in the RDL is crucial in the fabrication of each conductive line in the RDL. However, in conventional FOWLP packaging, the conductive lines are formed using chemical plating or electroplating techniques. This results in relatively high material and production costs, and the traditional process does not meet environmental protection requirements. Furthermore, when using FOWLP to provide products with higher performance or more functionality, at least two dies are typically placed in the FOWLP, forming a multi-die FOWLP unit through the RDL. This increases the design space requirements for each conductive line in the RDL of the FOWLP, and the fabrication technology for each conductive line in the RDL also becomes more important. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2023-551401 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a FOWLP unit including a carrier, at least one lower die, a first dielectric layer, at least one first conductive line, a second dielectric layer, at least one second conductive line, at least one upper die, a third dielectric layer, at least one third conductive line, a fourth dielectric layer, at least one fourth conductive line, and an outer protective layer, wherein each of the lower die and each of the upper die form a corresponding stacked relationship with a gap between them, and each of the fourth conductive lines forms a welding pad in each opening of the outer protective layer, and each of the lower die and each of the upper die can be electrically connected to the outside through each welding pad located around a chip area on a second surface of each of the upper die. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a FOWLP unit, the FOWLP unit including a carrier, at least one lower die, a first dielectric layer, at least one first conductive line, a second dielectric layer, at least one second conductive line, at least one upper die, a third dielectric layer, at least one third conductive line, a fourth dielectric layer, at least one fourth conductive line, and an outer protective layer, wherein the carrier has a first surface, and each of the lower dies is formed by dividing it from at least one wafer, and each of the lower dies has a first surface and an opposing second surface, and the second surface is a first dielectric layer covering each of the lower dies and having a plurality of first grooves extending in a horizontal direction, the pads of each of the lower dies being electrically connected to the outside through the first grooves; each of the first conductive lines being made of a metal paste filled in the first grooves, and each of the first conductive lines being electrically connected to the pads of each of the lower dies; a second dielectric layer covering each of the lower dies and having a plurality of second grooves extending in a horizontal direction, the second grooves communicating with the first grooves; each of the second conductive lines is formed by a metal paste filled in each of the second grooves and is electrically connected to each of the first conductive lines; each of the upper die is formed by dividing at least one wafer and has a first surface and an opposing second surface, the second surface has a plurality of pads, and a range of the second surface in a chip vertical direction is defined as a chip area; the third dielectric layer covers each of the upper dies correspondingly, and has a plurality of third grooves extending horizontally, the pads of each of the upper dies are formed by metal paste filled in the third grooves, and the third conductive lines are electrically connected to the second conductive lines; the fourth dielectric layer covers each of the upper dies correspondingly, and has a plurality of fourth grooves formed on the third dielectric layer and extending in a horizontal direction, each of the fourth grooves communicating with each of the third grooves; each of the fourth conductive lines is formed by a metal paste filled in each of the fourth grooves, and is electrically connected to the third conductive lines or to each of the pads of each of the upper dies; the outer protective layer is provided on the fourth dielectric layer and has a plurality of openings, at least one of the openings being arranged around the chip area on the second surface of each of the lower dies and around the chip area on the second surface of each of the upper dies, and each of the fourth conductive lines is exposed to the outside through each of the openings to form a welding pad within each of the openings; each of the lower layer dies and each of the upper layer dies form a vertically corresponding relationship and are stacked on the carrier with a gap therebetween; Each of the lower die is electrically connected to each of the upper die through each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, and each of the fourth conductive lines, and each of the lower die can be electrically connected to the outside through each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, each of the fourth conductive lines, and each of the fourth conductive lines, and each of the upper die can be electrically connected to the outside through each of the fourth conductive lines and each of the weld pads, which are located around the chip area on the second surface of each of the upper die, thereby forming the FOWLP unit; The manufacturing method of the FOWLP unit includes step S1 of providing a carrier; and step S2 of placing a plurality of lower die separated from at least one wafer on the carrier, fixing a first surface of each lower die on the carrier, each lower die having a second surface opposite to the first surface and a plurality of pads on the second surface. Step 3: Covering the at least one lower die with a first dielectric layer, forming a plurality of first grooves in the first dielectric layer in a horizontal direction, and allowing each of the pads of each lower die to be exposed to the outside through each of the first grooves in the first dielectric layer; then filling each of the first grooves with a metal paste, the thickness of which is greater than the surface of the first dielectric layer, and polishing the metal paste to be flush with the surface of the first dielectric layer to form a plurality of first conductive lines; then covering the first dielectric layer with a second dielectric layer, forming a plurality of second grooves in the second dielectric layer in a horizontal direction, and allowing each of the first conductive lines in each of the first grooves to be exposed to the outside through each of the second grooves; finally, filling each of the second grooves with a metal paste, the thickness of which is greater than the second dielectric layer, and polishing the metal paste to be flush with the surface of the second dielectric layer to form a plurality of second conductive lines. and placing a plurality of upper dies separated from at least one wafer on the second dielectric layer of each of the lower dies, each of the upper dies having a first surface and an opposite second surface, each having a plurality of pads on the second surface, and defining a chip area in a vertical direction of the second surface; step 4; first covering each of the upper dies with a third dielectric layer, forming a plurality of third grooves in the third dielectric layer in a horizontal direction, and allowing each of the pads of each of the upper dies to be exposed to the outside from each of the third grooves in the third dielectric layer; then filling each of the third grooves with a metal paste, the thickness of the metal paste being higher than the surface of the third dielectric layer, and polishing the metal paste to be higher than the surface of the third dielectric layer, and making the surface of the metal paste flush with the surface of the third dielectric layer to form a plurality of third conductive lines; then covering a fourth dielectric layer on the third dielectric layer, forming a plurality of fourth grooves in the fourth dielectric layer in a horizontal direction, and allowing each of the third conductive lines in each of the fourth grooves to be exposed to the outside from each of the fourth grooves; and finally,The method includes: Step S5: filling each of the fourth grooves with a metal paste, the height of the metal paste being higher than the fourth dielectric layer, and polishing the metal paste that is higher than the surface of the fourth dielectric layer to make the surface of the metal paste flush with the surface of the fourth dielectric layer to form a plurality of fourth conductive lines; Step S6: arranging an outer protective layer on the fourth dielectric layer; Step S7: forming a plurality of openings in the outer protective layer, at least one of the openings being formed around the chip region of the second surface of each of the upper die, exposing each of the fourth conductive lines to the outside through each of the openings to form a welding pad in each of the openings; and Step S8: performing a dividing operation to divide and form a plurality of FOWLP units.

[0007] In a preferred embodiment of the present invention, the FOWLP unit of claim 1 further defines a vertical chip area on the second surface of each of the lower dies, and each of the lower dies is electrically connectable to the outside via each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, each of the fourth conductive lines, and each of the weld pads located around the chip area on the second surface of each of the lower dies in sequence.

[0008] In a preferred embodiment of the present invention, the at least one lower die and the at least one upper die are formed by separation from the same wafer or different wafers.

[0009] In a preferred embodiment of the present invention, the carrier comprises a silicon carrier, a glass carrier, or a ceramic carrier.

[0010] In one preferred embodiment of the present invention, the metal paste constituting each of the first conductive wires, each of the second conductive wires, each of the third conductive wires, and each of the fourth conductive wires includes silver paste, nanosilver paste, copper paste, or nanocopper paste.

[0011] In one preferred embodiment of the present invention, the first surface of each of the lower die is covered with a die attach film ( The upper layer die is further disposed on the carrier using a Die Attach Film (DAF), and the first surface of each upper layer die is further disposed on the second dielectric layer using a die attach film.

[0012] In a preferred embodiment of the present invention, each of the openings is further provided with a solder ball, and each of the solder balls can be electrically connected to each of the welding pads in each of the openings, and the FOWLP unit can be electrically connected using each of the solder balls and installed on an electronic component.

[0013] In a preferred embodiment of the present invention, each of the openings is further provided with a bump, and each of the bumps can be electrically connected to each of the welding pads in each of the openings, and the FOWLP unit can be connected by wire bonding ( A solder joint is formed on each of the bumps and the electronic component via a solder wire using a wire bonding process, thereby electrically connecting them. [Effects of the Invention]

[0014] The FOWLP unit 1 of the present invention has the following advantages over conventional FOWLP units. (1) Steps S3 to S9 and S12 in the manufacturing method of the FOWLP unit 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can not only save costs, but also effectively improve the usage efficiency and reliability of the FOWLP unit 1. (2) The method of forming the first, second, third and fourth conductive wires 40, 60, 90 and 110 of the present invention can effectively solve the problems that the conventional FOWLP technology tends to increase the manufacturing cost when manufacturing each conductive wire and is unfavorable for environmental protection. (3) The conductive lines in the RDL of the present invention can generate electrical expansion and interconnection functions in the XY plane, while at the same time achieving a certain degree of light, thin, short, and small integration effect in the multi-die type FOWLP unit, thereby providing products with higher performance (e.g., the lower and upper dies 20, 70 all have the same specifications, performance, or functions) or more functions (e.g., the lower and upper dies 20, 70 all have different specifications, performance, or functions), thereby improving the market competitiveness of the products. (4) The FOWLP unit 1 of the present invention can be electrically connected to the electronic component 2 using the solder balls 140, as shown in Fig. 1. Alternatively, solder joints can be formed between the bumps 150 and the electronic component 2 by wire bonding, and the electronic component 2 can be electrically connected by bonding wires 3, as shown in Fig. 2. This is sufficient to increase the versatility of product applications and enhance the market competitiveness of the product. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a side cross-sectional view of a FOWLP unit of the present invention installed on an electronic component. [Figure 2] FIG. 1 is a cross-sectional side view of a FOWLP unit of the present invention electrically connected to an electronic component via wire bonding. [Figure 3] FIG. 2 is a side cross-sectional view of the lower die of the present invention mounted on a carrier. [Figure 4] 4 is a cross-sectional side view of the lower die of FIG. 3 covered with a first dielectric layer. [Figure 5] 5 is a side cross-sectional view of the first groove of FIG. 4 filled with metal paste. [Figure 6] 6 is a side cross-sectional view of polishing the metal paste higher than the surface of the first dielectric layer of FIG. 5. [Figure 7] FIG. 7 is a side cross-sectional view of a second dielectric layer placed on the first dielectric layer of FIG. 6. [Figure 8] FIG. 8 is a side cross-sectional view of the second groove of FIG. 7 filled with metal paste. [Figure 9]9 is a side cross-sectional view of polishing the metal paste higher than the surface of the second dielectric layer of FIG. 8. [Figure 10] 10 is a cross-sectional side view of the upper die placed on the second dielectric layer of FIG. 9. [Figure 11] 11 is a cross-sectional side view of the top die of FIG. 10 covered with a third dielectric layer. [Figure 12] FIG. 12 is a side cross-sectional view of the third groove of FIG. 11 filled with metal paste. [Figure 13] 13 is a side cross-sectional view of polishing the metal paste higher than the surface of the third dielectric layer of FIG. 12. [Figure 14] FIG. 14 is a side cross-sectional view of a fourth dielectric layer placed on the third dielectric layer of FIG. [Figure 15] FIG. 15 is a side cross-sectional view of the fourth groove of FIG. 14 filled with metal paste. [Figure 16] 16 is a side cross-sectional view of polishing the metal paste higher than the surface of the fourth dielectric layer of FIG. 15. [Figure 17] FIG. 17 is a side cross-sectional view of the fourth dielectric layer of FIG. 16 with an outer protective layer provided thereon. [Figure 18] FIG. 18 is a side cross-sectional view of FIG. 17 in which solder balls are provided in each opening. [Figure 19] FIG. 18 is a side cross-sectional view of the openings of FIG. 17, in which bumps are provided in the openings. DETAILED DESCRIPTION OF THE INVENTION

[0016] Referring to Figure 17, fan-out type wafer level packaging ( The FOWLP unit 1 includes a carrier 10, at least one lower die 20, a first dielectric layer 30, at least one conductive line 40, a second dielectric layer 50, at least one second conductive line 60, at least one upper die 70, a third dielectric layer 80, at least one third conductive line 90, a fourth dielectric layer 100, at least one fourth conductive line 110, and an outer protective layer 120.

[0017] 17, each lower layer die 20 and each upper layer die 70 are stacked on the carrier 10 with a gap therebetween, forming a vertically corresponding relationship. Each lower layer die 20 may be further arranged with a plurality of lower layer dies 20 arranged in parallel with each other at intervals in the horizontal direction in each layer, and correspondingly, each upper layer die 70 may be further arranged with a plurality of upper layer dies 70 arranged in parallel with each other at intervals in the horizontal direction in each layer (not shown).

[0018] In Fig. 3, the carrier 10 has a first surface 11. Each of the lower die 20 is separated from at least one wafer and has a second surface 22 opposite to the first surface 21, with a plurality of pads 23 on the second surface 22. The first surface 21 of each of the lower die 20 is fixed on the first surface 11 of the carrier 10. In Fig. 3, each of the pads 23 of each of the lower die 20 is illustrated as two pads 23, but this is not intended to limit the present invention.

[0019] 4, the first dielectric layer 30 covers the lower die 20, and the first dielectric layer 30 has a plurality of first grooves 31 extending horizontally. Each of the pads 23 of each of the lower die 20 is exposed to the outside through each of the first grooves 31.

[0020] 6 , each of the first conductive lines 40 is formed by filling each of the first grooves 31 with a metal paste 40a. The metal paste 40a may be, but is not limited to, a silver paste, a nano-silver paste, a copper paste, a nano-copper paste, etc. Each of the first conductive lines 40 is electrically connected to each of the pads 23 of each of the lower dies 20.

[0021] 7, the second dielectric layer 50 covers each of the lower dies 20 and the first dielectric layer 30, and the second dielectric layer 50 has a plurality of second grooves 51 extending horizontally. Each of the second grooves 51 communicates with each of the first grooves 31.

[0022] 9, each of the second conductive lines 60 is formed by filling each of the second grooves 51 with a metal paste 60a. Examples of the metal paste 60a include, but are not limited to, silver paste, nano-silver paste, copper paste, and nano-copper paste. Each of the second conductive lines 60 is electrically connected to each of the first conductive lines 40.

[0023] Each upper die 70 is separated from at least one wafer, and has a first surface 71 and a corresponding second surface 72. The first surface 71 is fixed on the second dielectric layer 50, and a plurality of pads 73 are provided on the second surface 72. The range of the second surface 72 in the chip vertical direction is defined as a chip area 1a, as shown in FIG. 11. In FIG. 11, each upper die 70 has two pads 73, but the present invention is not limited to this.

[0024] 11 , the third dielectric layer 80 covers the upper die 70, and the third dielectric layer 80 has a plurality of third grooves 81 extending horizontally. Each of the pads 73 of each of the upper dies 70 is exposed to the outside through each of the third grooves 81.

[0025] 13 , each of the third conductive lines 90 is formed by filling each of the third grooves 81 with a metal paste 90a. Examples of the metal paste 90a include, but are not limited to, silver paste, nano-silver paste, copper paste, and nano-copper paste. Each of the third conductive lines 90 is electrically connected to each of the second conductive lines 60.

[0026] 14, the fourth dielectric layer 100 is provided to cover each of the upper dies 70 and the third dielectric layer 80. The fourth dielectric layer 100 has a plurality of fourth grooves 101 extending in the horizontal direction. Each of the fourth grooves 101 is connected to a third groove 81.

[0027] 16 , each of the fourth conductive lines 110 is formed by filling each of the fourth grooves 101 with a metal paste 110a. The metal paste 110a may be, but is not limited to, a silver paste, a nano-silver paste, a copper paste, a nano-copper paste, etc. Each of the fourth conductive lines 110 is electrically connected to the third conductive line 90 or to each of the pads 73 of each of the upper dies 70.

[0028] 17 , the outer protective layer 120 is disposed on the fourth dielectric layer 100, and the outer protective layer 120 has a plurality of openings 121, at least one of which is located around the chip area 1 a on the second surface 22 of each lower die 20 and around the chip area 1 a on the second surface 72 of each upper die 70. Each of the fourth conductive lines 110 is exposed to the outside through each of the openings 121, and a welding pad 111 is formed in each of the openings 121.

[0029] 17 , each lower die 20 may be electrically connected to each upper die 70 via the first conductive lines 40, the second conductive lines 60, the third conductive lines 90, and the fourth conductive lines 110. Each lower die 20 may also be electrically connected to the outside via the first conductive lines 40, the second conductive lines 60, the third conductive lines 90, the fourth conductive lines 110, and the welding pads 111 located around the chip area 1 a on the second surface 72 of each upper die 70. Each upper die 70 may be electrically connected to the outside via the fourth conductive lines 110 and the welding pads 111 located around the chip area 1 a on the second surface 72 of each upper die 70, thereby forming the fan-out wafer-level packaging unit 1.

[0030] The manufacturing method of the fan-out type wafer level packaging unit 1 includes the following steps. Step S1: Provide a carrier 10 as shown in FIG. Step S2: A plurality of lower die 20 separated from at least one wafer are placed on a carrier 10, and a first surface 21 of each lower die 20 is fixed on the carrier 10 as shown in Fig. 3. Each lower die 20 has a second surface 22 opposite to the first surface 21, and has a plurality of pads 23 on the second surface 22. Step S3: First, as shown in FIG. 4, a first dielectric layer 30 is formed on each of the lower dies 20. A plurality of first grooves 31 are formed on the first dielectric layer 30, extending horizontally, and the pads 23 of each of the lower dies 20 are exposed to the outside through the first grooves 31. Next, as shown in FIG. 5, a metal paste 40a is filled into each of the first grooves 31, and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30. Next, as shown in FIG. 5, the metal paste 40a that is higher than the surface of the first dielectric layer 30 is polished so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30, thereby forming a plurality of first conductive lines 40, as shown in FIG. Next, a second dielectric layer 50 is placed over the first dielectric layer 30, and a plurality of first grooves 31 are formed in the second dielectric layer 50 in the horizontal direction, such that the first conductive lines 40 in the first grooves 31 of the first dielectric layer 30 are exposed to the outside through the second grooves 51 of the second dielectric layer 50, as shown in Fig. 7. Finally, a metal paste 60a is filled into the second grooves 51 of the second dielectric layer 50, and as shown in Fig. 8, the metal paste 60a is thicker than the second dielectric layer 50 and is polished to be higher than the surface of the second dielectric layer 50, so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50, thereby forming a plurality of second conductive lines 60, as shown in Fig. 9. Step S4: As shown in Figure 10, a plurality of upper dies 70 separated from at least one wafer are placed on the second dielectric layer 50 on each of the lower dies 20. Each of the upper dies 70 has a first surface 71 and an opposing second surface 72. Each of the upper dies 70 has a plurality of pads 73 on the second surface 72. The extent of the second surface 72 of each of the upper dies 70 in the chip vertical direction is defined as a chip area 1a, as shown in Figure 11. Step S5: First, a third dielectric layer 80 is placed over each of the upper dies 70, and a plurality of third grooves 81 are horizontally formed on the third dielectric layer 80. As shown in FIG. 11, each of the pads 73 of each of the upper dies 70 is exposed to the outside through each of the third grooves 81. Next, as shown in FIG. 12, a metal paste 90a is filled into each of the third grooves 81, and the thickness of the metal paste 90a is greater than the surface of the third dielectric layer 80. The metal paste 90a is polished to make the surface of the metal paste 90a flush with the surface of the third dielectric layer 80, thereby forming a plurality of third conductive lines 90, as shown in FIG. 13. Next, as shown in FIG. 14, a fourth dielectric layer 100 is placed over the third dielectric layer 80, and a plurality of fourth grooves 101 are horizontally formed on the fourth dielectric layer 100, allowing each of the third conductive lines 90 in each of the fourth grooves 101 to be exposed to the outside through each of the fourth grooves 101 in the fourth dielectric layer 100. Finally, as shown in FIG. 15, a metal paste 110a is filled into each of the fourth grooves 101, and the thickness of the metal paste 110a is greater than the thickness of the fourth dielectric layer 100. The metal paste 110a is polished to make the surface of the metal paste 110a flush with the surface of the fourth dielectric layer 100, thereby forming a plurality of fourth conductive lines 110, as shown in FIG. 16. Step S6: As shown in FIG. 17, an outer protective layer 120 is laid on the fourth dielectric layer 100. Step S7: A plurality of openings 121 are formed in the outer protective layer 120, and at least one of the openings 121 is formed around the chip area 1a on the second surface 72 of each of the upper die 70, and each of the fourth conductive lines 110 is exposed to the outside through each of the openings 121, and a welding pad 111 can be formed in each of the openings 121, as shown in FIG. 17. Step S8: A division operation is performed to divide and form a plurality of FOWLP units 1 as shown in FIG.

[0031] The above-mentioned steps S3 and S5 can be regarded as key steps for fabricating the RDL of the FOWLP unit 1. Since steps S3 and S5 are both easy to precisely perform, the process is relatively simplified and is sufficient to generate electrical expansion and interconnection in the XY plane for the first, second, third, and fourth conductive lines 40, 60, 90, and 110 in the RDL. At the same time, the FOWLP unit 1 maintains or achieves a certain degree of lightness, thinness, and compactness by stacking the lower die 20 and the upper die 70 one above the other on the carrier 10 with a gap therebetween.

[0032] 17 , the range of the second surface 22 of each lower die 20 in the chip vertical direction is further defined as a chip area 1b. Each of the at least one lower die 20 can be electrically connected to the outside via the first conductive lines 40, the second conductive lines 60, the third conductive lines 90, the fourth conductive lines 110, and the weld pads 111 located around the chip area 1b on the second surface 22 of each lower die 20, in order.

[0033] Referring to FIG. 17, each of the lower die 20 and each of the upper die 70 can be formed by dividing from the same wafer or different wafers, which is advantageous for various product developments and applications.

[0034] Referring to FIG. 3, the carrier 10 includes, but is not limited to, a silicon (Si) carrier, a glass carrier, or a ceramic carrier, which is advantageous for various product developments and applications.

[0035] Referring to FIG. 3, the first surface 21 of each of the lower die 20 is further covered with a die attach film ( 10, the first surface 71 of each upper layer die 70 is further disposed on the second dielectric layer 50 using a die attach film 130.

[0036] 18, each of the openings 121 is further provided with a solder ball 140, and each of the solder balls 140 can be electrically connected to each of the pads 111 in each of the openings 121. The FOWLP unit 1 can be electrically connected to an electronic component 2 using each of the solder balls 140, as shown in FIG.

[0037] Referring to FIG. 19, each of the openings 121 is further provided with a bump 150, and each of the bumps 150 can be electrically connected to each of the welding pads 111 in each of the openings 121. The FOWLP unit 1 can be connected by wire bonding ( By using a solder bonding (Wire Bonding) operation, solder joints can be formed between each of the bumps 150 and the electronic component 2, and electrical connection can be established via bonding wires 3, as shown in FIG.

[0038] The FOWLP unit 1 of the present invention has the following advantages over conventional FOWLP units. (1) Steps S3 to S9 and S12 in the manufacturing method of the FOWLP unit 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can not only save costs, but also effectively improve the usage efficiency and reliability of the FOWLP unit 1. (2) The method of forming the first, second, third and fourth conductive wires 40, 60, 90 and 110 of the present invention can effectively solve the problems that the conventional FOWLP technology tends to increase the manufacturing cost when manufacturing each conductive wire and is unfavorable for environmental protection. (3) The conductive lines in the RDL of the present invention can generate electrical expansion and interconnection functions in the XY plane, while at the same time achieving a certain degree of light, thin, short, and small integration effect in the multi-die type FOWLP unit, thereby providing products with higher performance (e.g., the lower and upper dies 20, 70 all have the same specifications, performance, or functions) or more functions (e.g., the lower and upper dies 20, 70 all have different specifications, performance, or functions), thereby improving the market competitiveness of the products. (4) The FOWLP unit 1 of the present invention can be electrically connected to the electronic component 2 using the solder balls 140, as shown in Fig. 1. Alternatively, solder joints can be formed between the bumps 150 and the electronic component 2 by wire bonding, and the electronic component 2 can be electrically connected by bonding wires 3, as shown in Fig. 2. This is sufficient to increase the versatility of product applications and enhance the market competitiveness of the product. [Explanation of symbols]

[0039] 1 Fan-out type wafer level packaging ( FOWLP) unit 1a Chip area 1b Chip Area 10. Career 11 Page 1 20 Lower Die 21 Page 1 22 Side 2 23 Pad 30 First dielectric layer 31 First groove 40 First conductive wire 40a Metal Paste 50 Second dielectric layer 51 2nd groove 60 Second conductive wire 60a metal paste 70 Upper Die 71 Page 1 72 2nd page 80 Third dielectric layer 81 Third groove 90 Third conductive wire 90a Metal Paste 100 Fourth dielectric layer 101 4th groove 110 4th conductive wire 110a metal paste 111 Welding Pad 120 Outer protective layer 121 Aperture 130 Die Attach Film 140 solder balls 150 Bump 2. Electronic materials

Claims

1. A fan-out wafer level packaging (FOWLP) unit includes a carrier, at least one lower die, a first dielectric layer, at least one first conductive line, a second dielectric layer, at least one second conductive line, at least one upper die, a third dielectric layer, at least one third conductive line, a fourth dielectric layer, at least one fourth conductive line, and an outer protective layer, wherein the carrier has a first surface, and each of the lower dies is formed by dividing at least one wafer, and each lower die has a first surface and an opposite second surface, and the second surface has a plurality of pads, and the first surface is fixed to the first surface of the carrier, and the first dielectric layer covers each of the lower dies correspondingly and has a plurality of first grooves extending in a horizontal direction, and each of the pads of each lower die is exposed to the outside through each of the first grooves, each of the first conductive lines is made of a metal paste filled in each of the first grooves, and each of the first conductive lines is electrically connected to each of the pads of each of the lower die; the second dielectric layer covers each of the lower die correspondingly, and has a plurality of second grooves formed on the first dielectric layer and extending horizontally, each of the second grooves communicating with each of the first grooves; each of the second conductive lines is made of a metal paste filled in each of the second grooves, and each of the second conductive lines is electrically connected to each of the first conductive lines; each of the upper die is formed by dividing it from at least one wafer, has a first surface and an opposing second surface, has a plurality of pads on the second surface, and is fixed to the second dielectric layer, and the range of the second surface of each of the upper die in the chip vertical direction is defined as a chip area; the third dielectric layer covers the upper die correspondingly and has a plurality of third grooves extending horizontally, the pads of the upper die are formed by metal paste filled in the third grooves, and the third conductive lines are electrically connected to the second conductive lines; the fourth dielectric layer covers the upper die correspondingly and has a plurality of fourth grooves extending horizontally, the fourth grooves are provided to cover the third dielectric layer, and each fourth groove is connected to a third groove;each of the fourth conductive lines is made of a metal paste filled in each of the fourth grooves, and each of the fourth conductive lines is electrically connected to each of the third conductive lines or to each of the pads of each of the upper dies; the outer protective layer is provided on the fourth dielectric layer and has a plurality of openings, at least one of which is arranged around the chip area defined on the second surface of each of the lower dies and the chip area defined on the second surface of each of the upper dies, and each of the fourth conductive lines is exposed to the outside from each of the openings to form a welding pad within each of the openings; each of the lower dies and each of the upper dies forms a vertically corresponding relationship, and is stacked on the carrier with an interval therebetween; Each of the lower die is electrically connected to each of the upper die via the first conductive lines, the second conductive lines, the third conductive lines, and the fourth conductive lines, in order; each of the lower die can also be electrically connected to the outside via the first conductive lines, the second conductive lines, the third conductive lines, the fourth conductive lines, and welding pads around the chip area located on the second surface of each of the upper die, in order; and each of the upper die can be electrically connected to the outside via the fourth conductive lines and welding pads around the chip area on the second surface of each of the upper die, thereby forming the FOWLP unit. A manufacturing method of the FOWLP unit includes: Step S1 of providing a carrier; Step S2 of placing a plurality of lower dies separated from at least one wafer on the carrier, fixing a first surface of each of the lower dies on the carrier, each of the lower dies having a second surface opposite to the first surface, and each of the lower dies having a plurality of pads on the second surface.Step 3: first, covering each of the lower die with a first dielectric layer, forming a plurality of first grooves in the first dielectric layer in a horizontal direction, and allowing each of the pads of each of the lower die to be exposed to the outside through each of the first grooves in the first dielectric layer; next, filling each of the first grooves with a metal paste, the thickness of which is greater than the surface of the first dielectric layer, and polishing the metal paste to be flush with the surface of the first dielectric layer to form a plurality of first conductive lines; then, covering a second dielectric layer on the first dielectric layer, forming a plurality of second grooves in the second dielectric layer in a horizontal direction, and allowing each of the first conductive lines in each of the first grooves to be exposed to the outside through each of the second grooves; finally, filling each of the second grooves with a metal paste, the thickness of which is greater than the second dielectric layer, and polishing the metal paste to be flush with the surface of the second dielectric layer to form a plurality of second conductive lines; Step 4: placing a plurality of upper die separated from at least one wafer on the second dielectric layer, each upper die having a first surface and an opposing second surface, each upper die having a plurality of pads on the second surface, and defining a chip area in a chip vertical direction of the second surface of each upper die; Step S5: first, covering each of the upper die with a third dielectric layer, forming a plurality of third grooves in the third dielectric layer in a horizontal direction, and allowing each of the pads of each of the upper die to be exposed to the outside through each of the third grooves; next, filling each of the third grooves with a metal paste, the thickness of which is greater than the surface of the third dielectric layer, and polishing the metal paste to be flush with the surface of the third dielectric layer to form a plurality of third conductive lines; then, covering a fourth dielectric layer on the third dielectric layer, forming a plurality of fourth grooves in the fourth dielectric layer in a horizontal direction, and allowing each of the third conductive lines to be exposed to the outside through each of the fourth grooves; finally, filling each of the fourth grooves with a metal paste, the height of which is greater than the surface of the fourth dielectric layer, and polishing the metal paste to be flush with the surface of the fourth dielectric layer to form a plurality of fourth conductive lines; and step S6: arranging an outer protective layer on the fourth dielectric layer.Step S7: forming a plurality of openings in the outer protective layer, at least one of the openings being formed around a chip area defined on the second surface of each of the upper dies, and exposing each of the fourth conductive lines to the outside through each of the openings to form a welding pad within each of the openings; and Step S8: performing a dividing operation to divide and form a plurality of FOWLP units.

2. 2. The FOWLP unit of claim 1, wherein the second surface of each lower die further defines a chip area in the chip vertical direction, and each lower die is electrically connectable to the outside via each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, each of the fourth conductive lines, and each of the weld pads located around the chip area defined on the second surface of each lower die.

3. Each of the lower die and each of the upper die may be separated from the same wafer or from different wafers.

4. The FOWLP unit of claim 1 , wherein the carrier comprises a silicon carrier, a glass carrier, or a ceramic carrier.

5. 2. The FOWLP unit of claim 1, wherein the metal paste constituting each of the first conductive wires, each of the second conductive wires, each of the third conductive wires, and each of the fourth conductive wires includes silver paste, nanosilver paste, copper paste, or nanocopper paste.

6. 2. The FOWLP unit of claim 1, wherein the first surface of each of the lower die is further disposed on the carrier using a die attach film, and the first surface of each of the upper die is further disposed on the second dielectric layer using a die attach film.

7. 2. The FOWLP unit of claim 1, wherein each of the openings is further provided with a solder ball, each of the solder balls being electrically connectable to each of the welding pads in each of the openings, and the fan-out type wafer level packaging unit is electrically connected using each of the solder balls and can be installed on an electronic component.

8. 2. The FOWLP unit of claim 1, wherein each opening further includes a bump, and each bump can be electrically connected to each welding pad in each opening, and the fan-out type wafer level packaging unit uses a wire bonding operation to form solder joints on each bump and electronic component, respectively, and electrically connects them via solder wires.

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