Ceramic electronic component and method for manufacturing the same

Abstract

To provide a ceramic electronic component capable of achieving both high insulation resistance and high capacitance, and a method for manufacturing the same.SOLUTION: A multilayer ceramic capacitor 100 includes: a lamination structure formed to be exposed to two end surfaces which a plurality of laminated inner electrode layers 12 alternately face; and a cover layer 13 provided on the upper and lower surfaces of the lamination structure in the lamination direction and using ceramics as a main component. The lamination structure has a capacity area where the internal electrode layers exposed to the different end surfaces face each other and a side margin area provided so that the plurality of inner electrode layers laminated in the lamination structure cover end parts extended on two side surfaces except the two end surfaces; the periphery of the capacity area is covered with the cover layer and the side margin area; the capacity area has a central area and a peripheral vicinity area surrounding the central area in the vicinity of the periphery; and a Sn concentration in the peripheral vicinity area is higher than that in the central area.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors have a structure in which internal electrode layers are stacked with dielectric layers sandwiched between them. The ferroelectric properties of the dielectric layer regions sandwiched between the internal electrode layers enable ceramic electronic components to achieve a high capacitance density (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 024538 Summary of the Invention [Problem to be solved by the invention]

[0004] The metal contained in the internal electrode layers may diffuse into the main ceramic component of the dielectric layer during the firing process and form a solid solution. If the metal contained in the internal electrode layers forms a solid solution in the main ceramic component of the dielectric layer, oxygen defects may form in the main ceramic component of the dielectric layer, reducing the insulating properties of the dielectric layer and shortening the life of the ceramic electronic component.

[0005] Therefore, by dissolving Sn in the main component ceramic of the dielectric layer, the main component metal of the internal electrode layer is prevented from dissolving in the main component ceramic of the dielectric layer, thereby improving the insulation properties of the dielectric layer and extending its lifespan.

[0006] However, Sn has the effect of promoting sintering of the dielectric layers and promoting spheroidization of the internal electrode layers. Therefore, while adding Sn can improve the insulation properties of the dielectric layers, it also causes a problem of reduced capacitance due to disruption of the laminated structure caused by spheroidization of the internal electrode layers.

[0007] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component that can achieve both high insulation resistance and high capacitance, and a method for manufacturing the same. [Means for solving the problem]

[0008] The ceramic electronic component according to the present invention comprises a laminated structure having a substantially rectangular parallelepiped shape in which dielectric layers and internal electrode layers, each composed primarily of ceramic, are alternately stacked, and in which the laminated internal electrode layers are exposed at two end faces that alternately face each other; and a cover layer, composed primarily of ceramic, provided on the upper and lower faces in the stacking direction of the laminated structure, wherein at least one of the Sn concentration of the main component ceramic in the cover layer and the Sn concentration of the main component ceramic in a side margin region that is provided to cover the ends of the multiple internal electrode layers stacked in the laminated structure that extend to two side faces other than the two end faces, is higher than the Sn concentration of the main component ceramic in a capacitance region in which the internal electrode layers exposed at different end faces face each other.

[0009] In the ceramic electronic component, the main component ceramic of the capacitance region, the cover layer, and the side margin may have a perovskite structure, and at least one of the atomic concentration ratio of Sn / B site elements in the cover layer and the atomic concentration ratio of Sn / B site elements in the side margin may be higher by 0.001 or more than the atomic concentration ratio of Sn / B site elements in the capacitance region.

[0010] In the ceramic electronic component, the main component ceramic of the capacitance region, the cover layer, and the side margin may have a perovskite structure, and at least one of the atomic concentration ratio of Sn / B site elements in the cover layer and the atomic concentration ratio of Sn / B site elements in the side margin may be 0.005 or more.

[0011] In the ceramic electronic component, the main component ceramic of the side margin may have a perovskite structure, and the atomic concentration ratio of Sn / B site elements in the side margin may be 0.01 or more.

[0012] In the ceramic electronic component, the main component ceramic of the capacitance region may have a perovskite structure, and the atomic concentration ratio of Sn / B site elements in the capacitance region may be 0.005 or less.

[0013] In the laminated structure of the ceramic electronic component, the Sn concentration in the main component ceramic in an end margin region where internal electrode layers exposed on the same end face face each other without being sandwiched between internal electrode layers exposed on different end faces may be higher than the Sn concentration in the main component ceramic in the capacitance region.

[0014] In the ceramic electronic component, the main component ceramic of the dielectric layers may be barium titanate, and the main component metal of the internal electrode layers may be nickel.

[0015] The method for manufacturing ceramic electronic components according to the present invention includes the steps of preparing a ceramic laminate including a laminated portion in which dielectric green sheets containing ceramic particles and patterns containing metal particles are stacked so that the patterns are alternately exposed on two opposing end faces, side margin sheets containing ceramic particles arranged on the sides of the laminated portion, and cover sheets containing ceramic particles arranged on the upper and lower faces of the laminated portion, and firing the ceramic laminate, wherein at least one of the Sn concentration in the main component ceramic in the cover sheets before firing and the Sn concentration in the main component ceramic in the side margin sheets before firing is higher than the Sn concentration in the main component ceramic in the dielectric green sheets before firing.

[0016] Another method for manufacturing a ceramic electronic component according to the present invention includes the steps of: arranging a first pattern containing metal particles on a dielectric green sheet containing ceramic particles; and arranging a second pattern containing ceramic particles around the first pattern; obtaining a ceramic laminate in which a cover sheet containing ceramic particles is laminated on the upper and lower surfaces of the laminated portion in which the laminated units obtained by the above step are stacked in multiple layers so that the positions of the first patterns are alternately shifted; and at least one of the Sn concentration in the main component ceramic in the cover sheet before firing and the Sn concentration in the main component ceramic in the second pattern before firing is higher than the Sn concentration in the main component ceramic in the dielectric green sheet before firing. [Effects of the Invention]

[0017] According to the present invention, it is possible to provide a ceramic electronic component that can achieve both high insulation resistance and high capacitance, and a method for manufacturing the same. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] (a) is an enlarged view of a cross section of a side margin, and (b) is an enlarged view of a cross section of an end margin. [Figure 5] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 6] 1(a) and 1(b) are diagrams illustrating the lamination process. [Figure 7] 1A to 1C are diagrams illustrating a lamination process. [Figure 8] 1A to 1C are diagrams illustrating a lamination process. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings.

[0020] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0021] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and three or more internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may have the same primary ceramic component as the dielectric layers 11.

[0022] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0023] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), Sn (tin), etc. The internal electrode layers 12 may also be made of precious metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys containing these metals.

[0024] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc., can be used. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0025] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0026] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0027] As illustrated in FIG. 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. That is, the side margins 16 are regions provided to cover the ends of the multiple internal electrode layers 12 stacked in the laminated structure, which extend toward the two side surfaces. The side margins 16 are also regions that do not generate capacitance. Because the outer periphery of the capacitance region 14 in the cross section of FIG. 3 is covered by the cover layer 13 and the side margins 16, in the following description, the cover layer 13 and the side margins 16 may be referred to as the outer periphery region 50.

[0028] 4(a) is an enlarged view of a cross section of the side margin 16. The side margin 16 has a structure in which the dielectric layers 11 and the reverse pattern layers 17 are alternately stacked in the stacking direction of the dielectric layers 11 and the internal electrode layers 12 in the capacitive region 14. The dielectric layers 11 in the capacitive region 14 and the dielectric layers 11 in the side margin 16 are continuous layers. With this configuration, the step between the capacitive region 14 and the side margin 16 is suppressed.

[0029] FIG. 4(b) is an enlarged view of the cross section of the end margin 15. Compared to the side margin 16, in the end margin 15, every other one of the multiple stacked internal electrode layers 12 extends to the end face of the end margin 15. Furthermore, in the layers where the internal electrode layers 12 extend to the end face of the end margin 15, no reverse pattern layer 17 is stacked. Each dielectric layer 11 in the capacitive region 14 and each dielectric layer 11 in the end margin 15 are layers that are continuous with each other. With this configuration, the step between the capacitive region 14 and the end margin 15 is suppressed.

[0030] The multilayer chip 10 can be obtained by stacking and firing layers formed from powdered materials. However, the main component metal of the internal electrode layer 12 may dissolve into the main component ceramic of the dielectric layer 11 during the firing process. For example, if the internal electrode layer 12 contains Ni, some of the Ni oxidizes during the firing process, and the ionized Ni dissolves into the main component ceramic of the dielectric layer 11. If the main component metal of the internal electrode layer 12 dissolves into the main component ceramic of the dielectric layer 11, oxygen defects will form in the main component ceramic of the dielectric layer 11, which may reduce the insulating properties of the dielectric layer 11 and shorten the life of the multilayer ceramic capacitor 100.

[0031] Therefore, by dissolving Sn in the main component ceramic of the dielectric layer 11, the main component metal of the internal electrode layer 12 is prevented from dissolving in the main component ceramic of the dielectric layer 11, thereby improving the insulation of the dielectric layer 11 and extending the life of the multilayer ceramic capacitor 100.

[0032] However, Sn has the effect of promoting sintering of the dielectric layers 11 and promoting spheroidization of the internal electrode layers 12. Therefore, while the addition of Sn can improve the insulating properties of the dielectric layers 11, it also causes a problem of a decrease in the capacitance of the multilayer ceramic capacitor 100 due to disturbance in the laminated structure caused by the spheroidization of the internal electrode layers 12. Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration that can achieve both high insulation resistance and high capacitance.

[0033] In the multilayer ceramic capacitor 100 according to this embodiment, each dielectric layer 11 contains Sn. For example, Sn is dissolved in the main component ceramic of each dielectric layer 11. This prevents the main component metal of the internal electrode layers 12 from dissolving in the main component ceramic of the dielectric layers 11 during firing. As a result, the insulation properties of the dielectric layers 11 can be improved, and the life of the multilayer ceramic capacitor 100 can be extended. Next, at least one of the Sn concentration in the main component ceramic in the cover layer 13 and the Sn concentration in the main component ceramic in the side margin 16 is higher than the Sn concentration in the main component ceramic of each dielectric layer 11 in the capacitance region 14.

[0034] According to this configuration, Sn diffuses from at least one of the cover layer 13 and the side margin 16 into the capacitance region 14, increasing the Sn concentration near the periphery of the capacitance region 14. This improves the insulation near the periphery of the capacitance region 14. Because the periphery of the capacitance region 14 is close to the external environment and prone to IR degradation and life degradation, the insulation improvement effect can be effectively obtained. On the other hand, because the Sn concentration is low in the central region of the capacitance region 14, a decrease in the continuity ratio of the internal electrode layer 12 in the central region of the capacitance region 14 is suppressed, and therefore a decrease in capacitance can be suppressed. This makes it possible to achieve both high insulation and high capacitance.

[0035] If the difference in concentration between the Sn concentration in the capacitance region 14 and the Sn concentration in the peripheral region 50 is not sufficiently large, Sn may not diffuse sufficiently into the capacitance region 14, resulting in an insufficient Sn concentration near the periphery of the capacitance region 14. Therefore, it is preferable to set a lower limit for the difference in concentration between the Sn concentration in the capacitance region 14 and the Sn concentration in the peripheral region 50. For example, at least one of the atomic concentration ratio of Sn / B-site elements in the cover layer 13 and the atomic concentration ratio of Sn / B-site elements in the side margin 16 is preferably higher than the atomic concentration ratio of Sn / B-site elements in the capacitance region 14 by 0.001 or more, more preferably by 0.005 or more, and even more preferably by 0.01 or more. The B-site elements are elements located at the B site in a perovskite structure represented by the general formula ABO3.

[0036] If the difference in concentration between the Sn concentration in the capacitance region 14 and the Sn concentration in the peripheral region 50 is too large, uneven sintering may occur due to the sintering-promoting effect of Sn, resulting in a risk of poor balance between capacitance and dielectric loss. Therefore, it is preferable to set an upper limit on the difference in concentration between the Sn concentration in the capacitance region 14 and the Sn concentration in the peripheral region 50. For example, the difference between the atomic concentration ratio of Sn / B site elements in the cover layer 13 and the atomic concentration ratio of Sn / B site elements in the side margin 16 and the atomic concentration ratio of Sn / B site elements in the capacitance region 14 is preferably 0.1 or less, more preferably 0.05 or less, and even more preferably 0.03 or less.

[0037] Furthermore, if the Sn concentration in the outer circumferential region 50 is not sufficiently high, Sn may not diffuse sufficiently into the capacitance region 14, resulting in an insufficient Sn concentration near the periphery of the capacitance region 14. Therefore, it is preferable to set a lower limit for the Sn concentration in the outer circumferential region 50. For example, at least one of the atomic concentration ratio of Sn to B-site elements in the cover layer 13 and the atomic concentration ratio of Sn to B-site elements in the side margin 16 is preferably 0.005 or greater, more preferably 0.01 or greater, and even more preferably 0.015 or greater.

[0038] A high Sn concentration in the side margin 16 effectively increases the amount of Sn diffused into the electrode end region where electric field concentration is likely to occur, thereby effectively improving the insulation properties of the multilayer ceramic capacitor 100. Therefore, it is preferable to set a lower limit for the Sn concentration in the side margin 16. For example, the atomic concentration ratio of Sn / B site elements in the side margin 16 is preferably 0.01 or more, more preferably 0.015 or more, and even more preferably 0.02 or more.

[0039] On the other hand, if the Sn concentration in the outer peripheral region 50 is too high, sintering of the dielectric near the periphery may be excessively accelerated, potentially resulting in a decrease in capacity due to electrode disconnection. Therefore, it is preferable to set an upper limit on the Sn concentration in the outer peripheral region 50. For example, the atomic concentration ratio of Sn to B-site elements in the cover layer 13 and the atomic concentration ratio of Sn to B-site elements in the side margin 16 are each preferably 0.1 or less, more preferably 0.05 or less, and even more preferably 0.03 or less.

[0040] If the Sn concentration is high in the capacitance region 14, the spheroidization of the internal electrode layers 12 may not be sufficiently suppressed, which may result in a decrease in capacitance. Therefore, it is preferable to set an upper limit on the Sn concentration in the capacitance region 14. For example, the atomic concentration ratio of Sn / B site elements in the capacitance region 14 is preferably 0.01 or less, more preferably 0.0075 or less, and even more preferably 0.005 or less.

[0041] On the other hand, if the Sn concentration in the capacitance region 14 is too low, it may not be possible to sufficiently suppress the dissolution of the main component metal of the internal electrode layer 12 into the dielectric layer 11. Therefore, it is preferable to set a lower limit for the Sn concentration in the capacitance region 14. For example, the atomic concentration ratio of Sn / B site elements in the capacitance region 14 is preferably 0.001 or more, more preferably 0.002 or more, and even more preferably 0.003 or more.

[0042] It is preferable that the Sn concentration in the end margin 15 is also higher than the Sn concentration in the capacitance region 14. In this case, Sn diffuses from the end margin 15 to the capacitance region 14, and the Sn concentration in the vicinity of the end margin 15 of the capacitance region 14 increases. This improves the insulation properties in the vicinity of the end margin 15 of the capacitance region 14.

[0043] The thickness of each internal electrode layer 12 is, for example, 0.01 μm to 5 μm, or 0.05 μm to 3 μm, or 0.1 μm to 1 μm. For example, if the thickness of the internal electrode layer 12 is 1 μm or less, the continuity rate is likely to decrease due to fracture during firing, so the effect of the configuration according to this embodiment is significantly exhibited. In the multilayer ceramic capacitor 100, the number of stacked internal electrode layers 12 is, for example, 10 to 5,000, 50 to 4,000, or 100 to 3,000.

[0044] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0045] (raw powder production process) The A-site and B-site elements contained in the dielectric layer 11 are typically present in the form of a sintered compact of ABO3 particles. For example, barium titanate is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. Barium titanate can be synthesized from a finely divided barium compound raw material, such as barium carbonate, and a finely divided titanium compound raw material, such as titanium dioxide. Known methods include the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be employed in this embodiment. To synthesize ceramic particles other than barium titanate, a particulate ceramic material having a perovskite structure can be synthesized from a compound raw material of the A-site element and a compound raw material of the B-site element. Note that a Mo source may be added during the ceramic material synthesis process to form a substitutional solid solution of Mo in the ceramic material.

[0046] The resulting ceramic powder is then doped with a predetermined additive compound depending on the purpose, such as oxides of tin (Sn), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0047] For example, a compound containing an additive compound is wet mixed with a ceramic material, followed by drying and pulverization. The resulting material may be pulverized as needed to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through these steps, a ceramic raw material powder that will be the main component of the dielectric layer is obtained.

[0048] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained ceramic raw material powder and wet mixed. Using the obtained slurry, a dielectric green sheet 51 is coated on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

[0049] 6(a), a metal conductive paste containing metal particles for forming an internal electrode and an organic binder is printed on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like to form a first pattern 52 for the internal electrode layer. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main ceramic component of the dielectric layer 11.

[0050] 6(a), a reverse pattern paste is printed on the dielectric green sheet 51 in the peripheral area where the first pattern 52 is not printed, thereby arranging the second pattern 53 and filling in the step with the first pattern 52. The reverse pattern paste contains, for example, the same components as the dielectric green sheet 51, but has a higher Sn concentration relative to the main component ceramic.

[0051] 6(b), the dielectric green sheets 51, the first pattern 52, and the second pattern 53 are laminated so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged, and so that the edges of the internal electrode layers 12 are alternately exposed at both end faces in the length direction of the dielectric layer 11 and are alternately drawn out to a pair of external electrodes 20a, 20b having opposite polarities. For example, the number of laminated dielectric green sheets 51 is set to 100 to 500.

[0052] Next, as shown in FIG. 7, a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are laminated on the top and bottom of the laminated dielectric green sheets 51, thermocompression bonded, and cut to a predetermined chip size (e.g., 1.0 mm x 0.5 mm). The cover sheets 54, for example, contain the same components as the dielectric green sheets 51, but have a higher Sn concentration relative to the main ceramic component. Thereafter, a metal conductive paste that will become the external electrodes 20a, 20b is applied to both sides of the cut laminate by a dipping method or the like and dried. This results in a ceramic laminate. Alternatively, a predetermined number of cover sheets 54 may be laminated and compressed, and then attached to the top and bottom of the laminated dielectric green sheets 51.

[0053] The laminated portion of the second pattern 53 may be attached after lamination. Specifically, as illustrated in Fig. 8, the laminated portion is obtained by alternately laminating dielectric green sheets 51 and first patterns 52 having the same width as the dielectric green sheets 51. Next, side margin sheets 55 are attached to the side surfaces of the laminated portion. The side margin paste used for the side margin sheets 55 contains, for example, the same components as the dielectric green sheets 51, but with a higher Sn concentration.

[0054] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping, and the ceramic laminate was heated in an atmosphere with an oxygen partial pressure of 10 -5 ~10 -8 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0055] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0056] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0057] The base layers of the external electrodes 20a and 20b may be formed by baking after the firing step.

[0058] According to the manufacturing method of this embodiment, the Sn concentration in the second pattern 53 is higher than that in the dielectric green sheet 51, and therefore, after firing, the Sn concentration in the side margins 16 and end margins 15 is higher than that in the capacitance region 14. Furthermore, the Sn concentration in the cover sheet 54 is higher than that in the dielectric green sheet 51, and therefore, after firing, the Sn concentration in the cover layer 13 is higher than that in the capacitance region 14. This causes Sn to diffuse into the capacitance region 14, increasing the Sn concentration near the periphery of the capacitance region 14 and improving the insulation near the periphery of the capacitance region 14. Because the periphery of the capacitance region 14 is close to the external environment and prone to IR degradation and life degradation, this effectively improves insulation. Meanwhile, because the Sn concentration in the central region of the capacitance region 14 is lower, the decrease in the continuity ratio of the internal electrode layers 12 in the central region of the capacitance region 14 is suppressed, thereby suppressing a decrease in capacitance. This allows for both high insulation and high capacitance.

[0059] In the above example, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this and other electronic components such as a varistor or a thermistor may also be used. [Example]

[0060] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0061] Example 1 Additives were added to barium titanate powder, which was then thoroughly wet mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder, toluene, and ethyl alcohol were added to the dielectric material, and a dielectric green sheet was applied to a PET substrate using the doctor blade method.

[0062] A metal conductive paste containing Ni metal powder, a binder, a solvent, and other auxiliary agents as needed was prepared. The organic binder and solvent used in the metal conductive paste were different from those used in the dielectric green sheet 51. A first pattern 52 of the metal conductive paste was screen-printed on the dielectric green sheet 51.

[0063] Five hundred dielectric green sheets 51 with a first pattern 52 printed thereon were stacked, and cover sheets 54 were laminated on the top and bottom of each. Then, a ceramic laminate was obtained by thermocompression bonding and cut into a predetermined shape (1005 shape). Side margin sheets 55 were attached to both sides of the obtained ceramic laminate. After that, the binder was removed in an N2 atmosphere, and then a metal paste that would become the base layer of the external electrodes was applied by dipping, and the laminate was fired in a reducing atmosphere.

[0064] In the side margin sheet 55 before firing, the amount of Sn added relative to Ti was 1.0 at %. In the cover sheet 54, the amount of Sn added relative to Ti was 0.0 at %. In the dielectric green sheet 51, the amount of Sn added relative to Ti was 0.0 at %.

[0065] After firing, the atomic concentration ratio of Sn to Ti in the side margin 16 was 0.007. In the cover layer 13, the atomic concentration ratio of Sn to Ti was 0.000. In the capacitance region 14, the atomic concentration ratio of Sn to Ti was 0.000. To determine the elemental concentration ratio of Sn to Ti in each region, the chip was cut near the center with a slicer and the cross section was polished using an ion milling device until it became clean. Laser ablation ICP mass spectrometry was performed on the target region of the cross section of the chip to quantify the elements. The spot diameter of the heating laser was 5 μm.

[0066] Example 2 In Example 2, the amount of Sn added to Ti in the side margin sheet 55 before firing was 2.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 0.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0067] After firing, the atomic concentration ratio of Sn to Ti was 0.017 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.000 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0068] Example 3 In Example 3, the amount of Sn added to Ti in the side margin sheet 55 before firing was 3.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 0.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0069] After firing, the atomic concentration ratio of Sn to Ti was 0.026 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.000 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0070] Example 4 In Example 4, the amount of Sn added to Ti in the side margin sheet 55 before firing was 0.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 1.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0071] After firing, the atomic concentration ratio of Sn to Ti was 0.000 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.009 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.000 in the capacitance region 14.

[0072] Example 5 In Example 5, the amount of Sn added to Ti in the side margin sheet 55 before firing was 1.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 1.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0073] After firing, the atomic concentration ratio of Sn to Ti was 0.008 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.009 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0074] Example 6 In Example 6, the amount of Sn added to Ti in the side margin sheet 55 before firing was 2.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 1.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0075] After firing, the atomic concentration ratio of Sn to Ti was 0.017 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.009 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0076] Example 7 In Example 7, the amount of Sn added to Ti in the side margin sheet 55 before firing was 3.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 1.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0077] After firing, the atomic concentration ratio of Sn to Ti was 0.027 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.009 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.002 in the capacitance region 14.

[0078] Example 8 In Example 8, the amount of Sn added to Ti in the side margin sheet 55 before firing was 0.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 2.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0079] After firing, the atomic concentration ratio of Sn to Ti was 0.000 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.018 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0080] Example 9 In Example 9, the amount of Sn added to Ti in the side margin sheet 55 before firing was 1.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 2.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0081] After firing, the atomic concentration ratio of Sn to Ti was 0.007 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.018 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0082] Example 10 In Example 10, the amount of Sn added to Ti in the side margin sheet 55 before firing was 2.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 2.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0083] After firing, the atomic concentration ratio of Sn to Ti was 0.018 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.018 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.002 in the capacitance region 14.

[0084] Example 11 In Example 11, the amount of Sn added to Ti in the side margin sheet 55 before firing was 3.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 2.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0085] After firing, the atomic concentration ratio of Sn to Ti was 0.026 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.018 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.002 in the capacitance region 14.

[0086] Example 12 In Example 12, the amount of Sn added to Ti in the side margin sheet 55 before firing was 0.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 3.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0087] After firing, the atomic concentration ratio of Sn to Ti was 0.000 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.027 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.001 in the capacitance region 14.

[0088] Example 13 In Example 13, the amount of Sn added to Ti in the side margin sheet 55 before firing was 1.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 3.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0089] After firing, the atomic concentration ratio of Sn to Ti was 0.008 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.027 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.002 in the capacitance region 14.

[0090] Example 14 In Example 14, the amount of Sn added to Ti in the side margin sheet 55 before firing was 2.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 3.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0091] After firing, the atomic concentration ratio of Sn to Ti was 0.018 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.027 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.002 in the capacitance region 14.

[0092] Example 15 In Example 15, the amount of Sn added to Ti in the side margin sheet 55 before firing was 3.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 3.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %.

[0093] After firing, the atomic concentration ratio of Sn to Ti was 0.027 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.027 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.003 in the capacitance region 14.

[0094] Example 16 In Example 16, the amount of Sn added to Ti in the side margin sheet 55 before firing was 2.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 2.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 1.0 at %.

[0095] After firing, the atomic concentration ratio of Sn to Ti was 0.020 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.019 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.011 in the capacitance region 14.

[0096] Example 17 In Example 17, the amount of Sn added to Ti in the side margin sheet 55 before firing was 2.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 2.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 2.0 at %.

[0097] After firing, the atomic concentration ratio of Sn to Ti was 0.021 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.019 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.020 in the capacitance region 14.

[0098] (Comparative Example) In the comparative example, the amount of Sn added to Ti in the side margin sheet 55 before firing was 0.0 at %. The amount of Sn added to Ti in the cover sheet 54 was 0.0 at %. The amount of Sn added to Ti in the dielectric green sheet 51 was 0.0 at %. In other words, no Sn was added.

[0099] After firing, the atomic concentration ratio of Sn to Ti was 0.000 in the side margin 16. The atomic concentration ratio of Sn to Ti was 0.000 in the cover layer 13. The atomic concentration ratio of Sn to Ti was 0.000 in the capacitance region 14.

[0100] The lifespan (50% value) was measured for each of Examples 1 to 17 and the Comparative Example. DC 12V was applied in a thermostatic chamber at 120°C, and the time when the current value exceeded 10 mA was measured as the lifespan of each chip. Measurements were made on 100 chips of each type.

[0101] The IR defect rate was measured for 100 samples each of Examples 1 to 17 and Comparative Example, and samples with a direct current resistance value of less than 1 MΩ at room temperature were determined to be defective using a tester.

[0102] The capacitance was measured for each of Examples 1 to 17 and Comparative Example. When measuring the capacitance, the samples were kept at 150°C (a temperature above the Curie point of the dielectric) for 1 hour, then returned to room temperature, and the capacitance was measured 24 hours later. The measurements were carried out using an LCR meter at 120 Hz and 0.5 Vrms.

[0103] The measurement results are shown in Table 1. As shown in Table 1, the IR defect rate in the comparative example was high at 14%. This is thought to be because, since Sn was not added to either the side margin 16 or the cover layer 13, Sn did not diffuse into the outer peripheral region of the capacitance region 14, and Ni, the main component metal of the internal electrode layer 12, dissolved in the dielectric layer 11, resulting in a decrease in insulation.

[0104] In contrast, the IR defect rate improved in all of Examples 1 to 3. This is thought to be because the Sn concentration in the side margin 16 was higher than that in the capacitance region 14, causing Sn to diffuse into the outer peripheral region of the capacitance region 14. Note that in Examples 1 to 3, there was almost no decrease in capacitance. This is thought to be because the Sn concentration in the capacitance region 14 was low.

[0105] Next, in Example 4, the IR defect rate was improved compared to the comparative example. This is thought to be because the Sn concentration in the cover layer 13 was higher than the Sn concentration in the capacitance region 14, causing Sn to diffuse to the outer peripheral region of the capacitance region 14. Note that in Example 4, the capacitance did not decrease compared to the comparative example. This is thought to be because the Sn concentration in the capacitance region 14 was low.

[0106] Next, in Examples 5 to 7, the IR defect rate was lower than in Examples 1 to 3. This is thought to be because the Sn concentration in both the side margin 16 and the cover layer 13 was higher than the Sn concentration in the capacitance region 14, causing Sn to diffuse into the outer peripheral region of the capacitance region 14. Note that in Examples 5 to 7, the capacitance was hardly reduced. This is thought to be because the Sn concentration in the capacitance region 14 was low.

[0107] Next, in Examples 8 to 11, the IR defect rate was lower than in Examples 4 to 7. This is thought to be because the Sn concentration in the side margin 16 was higher in Examples 8 to 11 than in Examples 4 to 7. Note that in Examples 8 to 11, the capacitance was hardly reduced. This is thought to be because the Sn concentration in the capacitance region 14 was low.

[0108] Next, in Examples 12 to 15, the IR defect rate was lower than in Examples 8 to 11. This is thought to be because the Sn concentration in the side margin 16 was higher in Examples 12 to 15 than in Examples 8 to 11. Note that in Examples 12 to 15, there was almost no decrease in capacitance. This is thought to be because the Sn concentration in the capacitance region 14 was low.

[0109] Next, in Example 16, the IR defect rate was further reduced compared to Example 10. This is thought to be because the insulating properties were further improved by adding Sn to the capacitance region 14 as well. However, the capacitance of Example 16 was lower than that of Example 10. This is thought to be because the Sn concentration in the capacitance region 14 was low. [Table 1]

[0110] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims.

[0111] The inventions described in the claims of the original application of this application are as follows: [1] a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, the laminated structure having a substantially rectangular parallelepiped shape, and the laminated internal electrode layers are exposed at two end faces that alternately face each other; a cover layer provided on the upper and lower surfaces of the laminated structure in the lamination direction, the cover layer containing ceramic as a main component; A ceramic electronic component characterized in that at least one of the Sn concentration in the main component ceramic in the cover layer and the Sn concentration in the main component ceramic in a side margin region in which the multiple internal electrode layers stacked in the laminated structure are arranged to cover ends extending to two side surfaces other than the two end faces is higher than the Sn concentration in the main component ceramic in a capacitance region in which internal electrode layers exposed on different end faces face each other. [2] the ceramics that are the main components of the capacitance region, the cover layer, and the side margin have a perovskite structure; The ceramic electronic component according to [1], characterized in that at least one of the atomic concentration ratio of Sn / B site elements in the cover layer and the atomic concentration ratio of Sn / B site elements in the side margin is higher by 0.001 or more than the atomic concentration ratio of Sn / B site elements in the capacitance region. [3] the ceramics that are the main components of the capacitance region, the cover layer, and the side margin have a perovskite structure; The ceramic electronic component according to [1], characterized in that at least one of the atomic concentration ratio of Sn / B site elements in the cover layer and the atomic concentration ratio of Sn / B site elements in the side margin is 0.005 or more. [4] The main component ceramic of the side margin has a perovskite structure, The ceramic electronic component according to [1], wherein the atomic concentration ratio of Sn / B site elements in the side margin is 0.01 or more. [5] The ceramic that is the main component of the capacitance region has a perovskite structure, The ceramic electronic component according to [1], wherein the atomic concentration ratio of Sn / B site elements in the capacitance region is 0.005 or less. [6] The ceramic electronic component according to any one of [1] to [5], characterized in that the Sn concentration in the main component ceramic in an end margin region, where internal electrode layers exposed on the same end face in the laminated structure face each other without being sandwiched between internal electrode layers exposed on different end faces, is higher than the Sn concentration in the main component ceramic in the capacitance region. [7] The main component ceramic of the dielectric layer is barium titanate, The ceramic electronic component according to any one of [1] to [6], wherein the main component metal of the internal electrode layers is nickel. [8] preparing a ceramic laminate including: a laminated portion in which dielectric green sheets containing ceramic particles and patterns containing metal particles are laminated so that the patterns are alternately exposed on two opposing end surfaces; side margin sheets containing ceramic particles and disposed on the side surfaces of the laminated portion; and cover sheets containing ceramic particles and provided on the upper and lower surfaces of the laminated portion; and firing the ceramic laminate. A method for manufacturing a ceramic electronic component, characterized in that at least one of the Sn concentration in the main component ceramic in the cover sheet before firing and the Sn concentration in the main component ceramic in the side margin sheet before firing is higher than the Sn concentration in the main component ceramic in the dielectric green sheet before firing. [9] a step of arranging a first pattern including metal particles on a dielectric green sheet including ceramic particles, and arranging a second pattern including ceramic particles around the first pattern; a step of obtaining a ceramic laminate in which a cover sheet containing ceramic particles is laminated on the upper and lower surfaces of a laminate portion in which a plurality of lamination units obtained by the step are laminated so that the arrangement positions of the first patterns are alternately shifted; A method for manufacturing a ceramic electronic component, characterized in that at least one of the Sn concentration in the main component ceramic in the cover sheet before firing and the Sn concentration in the main component ceramic in the second pattern before firing is higher than the Sn concentration in the main component ceramic in the dielectric green sheet before firing. [Explanation of symbols]

[0112] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 capacity area 15 End Margin 16 Side Margin 17 Reverse Pattern Layer 20a,20b external electrode 51 Dielectric green sheet 52 First Pattern 53 Second Pattern 54 Cover Sheet 55 Side margin sheet 100 Multilayer ceramic capacitors

Claims

1. a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, the laminated structure having a substantially rectangular parallelepiped shape, and the laminated internal electrode layers are exposed at two end faces that alternately face each other; a cover layer provided on the upper and lower surfaces of the laminated structure in the lamination direction, the cover layer containing ceramic as a main component; the laminated structure has a capacitance region in which internal electrode layers exposed on different end faces face each other, and a side margin region provided so as to cover end portions of the plurality of internal electrode layers laminated in the laminated structure extending to two side faces other than the two end faces, an outer periphery of the capacitance region is covered by the cover layer and the side margin region; the capacitance region has a central region and a peripheral vicinity region surrounding the central region and located near the peripheral region, The ceramic electronic component is characterized in that the Sn concentration in the peripheral region is higher than the Sn concentration in the central region.

2. the outer periphery vicinity region has a cover layer facing region facing the cover layer, the Sn concentration in the cover layer facing region is higher than the Sn concentration in the central region; The ceramic electronic component according to claim 1 .

3. Sn is dissolved in the ceramic as a main component of the dielectric layer. The ceramic electronic component according to claim 1 or 2.

4. the ceramics that are the main components of the capacitance region, the cover layer, and the side margin have a perovskite structure; 2. The ceramic electronic component according to claim 1, wherein at least one of the atomic concentration ratio of Sn / B-site elements in the cover layer and the atomic concentration ratio of Sn / B-site elements in the side margin is higher by 0.001 or more than the atomic concentration ratio of Sn / B-site elements in the capacitance region.

5. the ceramics that are the main components of the capacitance region, the cover layer, and the side margin have a perovskite structure; 2. The ceramic electronic component according to claim 1, wherein at least one of the atomic concentration ratio of Sn / B site elements in the cover layer and the atomic concentration ratio of Sn / B site elements in the side margin is 0.005 or more.

6. The main component ceramic of the side margin has a perovskite structure, 2. The ceramic electronic component according to claim 1, wherein the atomic concentration ratio of Sn / B site elements in the side margin is 0.01 or more.

7. The ceramic that is the main component of the capacitance region has a perovskite structure, 2. The ceramic electronic component according to claim 1, wherein the atomic concentration ratio of Sn / B site elements in the capacitance region is 0.005 or less.

8. 6. The ceramic electronic component according to claim 1, wherein an Sn concentration in the main component ceramic in an end margin region, in which internal electrode layers exposed on the same end face in the laminated structure face each other without an internal electrode layer exposed on a different end face therebetween, is higher than an Sn concentration in the main component ceramic in the capacitance region.

9. The main component ceramic of the dielectric layer is barium titanate, 7. The ceramic electronic component according to claim 1, wherein the main component metal of the internal electrode layers is nickel.

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