Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the occurrence of cracks in a sealing resin and a manufacturing method thereof.SOLUTION: A semiconductor device A10 includes: a terminal 10 having a connection surface 10A facing one side in a first direction z; a semiconductor element 30 electrically connected to the connection surface 10A; and a sealing resin 40 covering a portion of the terminal 10 and the semiconductor element 30. The terminal 10 is located on the other side in the first direction z with respect to the connection surface 10A and has a first surface 101 recessed into the terminal 10, and a second surface 102 connected to the connection surface 10A and the first surface 101. When viewed in the first direction z, the first surface 101 overlaps the connection surface 10A. The second surface 102 is convex and is in contact with the sealing resin 40.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses an example of a semiconductor device including a conductive member having a main surface facing in the thickness direction, a semiconductor element conductively joined to the conductive member, and a sealing resin covering a portion of the conductive member and the semiconductor element. The conductive member has a protruding portion including the main surface. The protruding portion is formed by half-etching the lead frame. Both sides of the protruding portion in the thickness direction and the end face of the protruding portion facing in a direction perpendicular to the thickness direction are covered with the sealing resin. This effectively prevents the conductive member from falling off the sealing resin.

[0003] In the protruding portion of the conductive member of the semiconductor device disclosed in Patent Document 1, the boundary between the main surface and the end surface generally has a sharper shape. When the boundary has such a shape, thermal stress caused by heat generated by the semiconductor element tends to concentrate at the boundary. This may cause cracks to occur in the sealing resin in contact with the boundary. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-77723

[0005] [overview] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of suppressing the occurrence of cracks in the sealing resin, and a method for manufacturing the same.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a terminal having a connection surface facing one side in a first direction; a semiconductor element electrically connected to the connection surface; and a sealing resin covering a portion of the terminal and the semiconductor element. The terminal has a first surface located on the other side in the first direction with respect to the connection surface and recessed into the terminal; and a second surface connected to the connection surface and the first surface. When viewed in the first direction, the first surface overlaps the connection surface. The second surface is convex and contacts the sealing resin.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: forming a terminal having a connection surface facing one side in a first direction; arranging a semiconductor element that is electrically connected to the connection surface; and forming a sealing resin that covers a portion of the terminal and the semiconductor element. The step of forming the terminal includes a first step of forming a first surface that is located on the other side of the first direction with respect to the connection surface and that recesses into the terminal; and a second step of forming a second surface that is connected to the connection surface and the first surface. In the first step, the first surface is formed by penetrating a lead frame including the connection surface in the first direction. In the second step, the second surface is formed by etching away a portion of the lead frame that forms a boundary between the connection surface and the first surface.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, showing the semiconductor element and the sealing resin. [Figure 3] FIG. 3 is a bottom view of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a right side view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a front view of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a partially enlarged cross-sectional view of FIG. [Figure 10] FIG. 10 is a partially enlarged view of FIG. [Figure 11] 11A to 11C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 15] 15A to 15C are partially enlarged cross-sectional views illustrating the manufacturing process of the semiconductor device shown in FIG. [Figure 16] 16A to 16C are partially enlarged cross-sectional views illustrating the manufacturing process of the semiconductor device shown in FIG. [Figure 17] 17A to 17C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 18] 18A to 18C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 19] 19A to 19C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 20] 20A to 20C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 21] 21A to 21C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 22]FIG. 22 is a partially enlarged cross-sectional view of the semiconductor device according to the second embodiment of the present disclosure, and corresponds to FIG. [Figure 23] FIG. 23 is a partially enlarged cross-sectional view of the semiconductor device according to the third embodiment of the present disclosure, and corresponds to FIG. [Figure 24] FIG. 24 is a partially enlarged cross-sectional view of the semiconductor device according to the fourth embodiment of the present disclosure, and corresponds to FIG.

[0010] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0011] [First embodiment] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 10. The semiconductor device A10 includes multiple terminals 10, four dummy terminals 19, multiple bonding layers 20, a semiconductor element 30, a sealing resin 40, and multiple covering layers 50. The semiconductor device A10 is a resin package that is surface-mounted on a wiring board. The resin package is a QFN (quad flat non-leaded package) in which multiple leads do not protrude from the sealing resin 40. For ease of understanding, FIG. 2 shows the semiconductor element 30 and the sealing resin 40 in a perspective view. In FIG. 2, the semiconductor element 30 and the sealing resin 40 are each shown with imaginary lines (two-dot chain lines). Furthermore, in FIG. 2, line VI-VI is shown with a dashed line.

[0012] In describing the semiconductor device A10, for convenience, the normal direction of each connection surface 10A of the multiple terminals 10 described below will be referred to as the "first direction z." The direction perpendicular to the first direction z will be referred to as the "second direction x." The direction perpendicular to the first direction z and the second direction x will be referred to as the "third direction y." As shown in FIG. 1, the semiconductor device A10 is rectangular when viewed in the first direction z.

[0013] 6 to 8, the sealing resin 40 covers a portion of each of the terminals 10 and the semiconductor element 30. The sealing resin 40 has electrical insulating properties. An example of the material of the sealing resin 40 is black epoxy resin.

[0014] As shown in FIGS. 4 to 8 , the sealing resin 40 has a top surface 41, a bottom surface 42, a plurality of first side surfaces 43, and a plurality of second side surfaces 44. The top surface 41 and the bottom surface 42 face opposite each other in the first direction z. The bottom surface 42 faces the side opposite the semiconductor element 30 in the first direction z, relative to the plurality of terminals 10. Each of the plurality of first side surfaces 43 faces in a direction perpendicular to the first direction z. The plurality of second side surfaces 44 are located between the top surface 41 and the plurality of first side surfaces 43 in the first direction z. Each of the plurality of second side surfaces 44 faces in a direction perpendicular to the first direction z. As viewed in the first direction z, each of the plurality of second side surfaces 44 is located outward of the plurality of first side surfaces 43 from the semiconductor device A10. Therefore, as viewed in the first direction z, the plurality of first side surfaces 43 are surrounded by the plurality of second side surfaces 44. The dimension of each of the multiple second side surfaces 44 in the first direction z is greater than the dimension of each of the multiple first side surfaces 43 in the first direction z.

[0015] As shown in Figures 6 to 8, the multiple terminals 10 are mounted with semiconductor elements 30. Each of the multiple terminals 10 forms a conductive path between the semiconductor element 30 and a wiring board on which the semiconductor device A10 is mounted. The multiple terminals 10 contain copper (Cu). The multiple terminals 10 are obtained from a lead frame 81, which will be described later.

[0016] As shown in FIGS. 6 to 8 , each of the multiple terminals 10 has a connection surface 10A, a mounting surface 10B, a first end surface 10C, and a second end surface 10D. The connection surface 10A faces the same side as the top surface 41 of the sealing resin 40 in the first direction z. The connection surface 10A faces the semiconductor element 30. The connection surface 10A is covered by the sealing resin 40. The mounting surface 10B faces the opposite side to the connection surface 10A in the first direction z. The mounting surface 10B is exposed from the bottom surface 42 of the sealing resin 40. The first end surface 10C and the second end surface 10D each face in a direction perpendicular to the first direction z. The first end surface 10C is exposed from one of the multiple first side surfaces 43 of the sealing resin 40. The second end surface 10D is located between the connection surface 10A and the first end surface 10C in the first direction z. The second end face 10D is located further outward from the semiconductor device A10 than the first end face 10C when viewed in the first direction z. The second end face 10D is exposed from one of the second side faces 44 of the sealing resin 40.

[0017] As shown in FIG. 9 , each of the multiple terminals 10 has a first surface 101, a second surface 102, a third surface 103, and a fourth surface 104. The first surface 101 is located on the side where the mounting surface 10B is located in the first direction z, with the connection surface 10A as the reference. The first surface 101 is recessed into one of the corresponding multiple terminals 10. When viewed in the first direction z, the first surface 101 overlaps the connection surface 10A. The first surface 101 is concave and covered with the sealing resin 40. The second surface 102 is connected to the connection surface 10A and the first surface 101. The second surface 102 is convex and in contact with the sealing resin 40.

[0018] As shown in FIG. 10, the surface roughness of the second surface 102 is smaller than the surface roughness of each of the connecting surface 10A and the first surface 101.

[0019] As shown in FIG. 9 , the third surface 103 is located on the opposite side of the connecting surface 10A from the first surface 101 in the first direction z. The third surface 103 is recessed into one of the corresponding terminals 10. As viewed in the first direction z, the third surface 103 overlaps the connecting surface 10A. The third surface 103 is concave and covered with the sealing resin 40. In each of the terminals 10, the degree of recession of the third surface 103 is greater than the degree of recession of the first surface 101. The fourth surface 104 is connected to the first surface 101 and the fourth surface 104. The fourth surface 104 is convex and in contact with the sealing resin 40. As viewed in the first direction z, the second surface 102 overlaps the fourth surface 104.

[0020] As shown in FIG. 9, in a cross section of any of the terminals 10 including the first direction z as an in-plane direction, the second surface 102 and the fourth surface 104 are individually defined by a first section L1 and a second section L2. Each of the first section L1 and the second section L2 is a curve. The length of the first section L1 is shorter than the length of the second section L2. Furthermore, the radius of curvature r2 of the second section L2 is greater than the radius of curvature r1 of the first section L1.

[0021] 2, the four dummy terminals 19 are arranged at the four corners of the semiconductor device A10. In the semiconductor device A10, the four dummy terminals 19 do not form a conductive path between the semiconductor element 30 and the wiring board on which the semiconductor device A10 is mounted. Each of the four dummy terminals 19 is exposed from the bottom surface 42 of the sealing resin 40, two adjacent first side surfaces 43 of the multiple first side surfaces 43, and two adjacent second side surfaces 44 of the multiple second side surfaces 44.

[0022] As shown in FIG. 2 and FIGS. 6 to 8, each of the multiple bonding layers 20 is mounted on one of the connection surfaces 10A of the multiple terminals 10. Each of the multiple bonding layers 20 is in contact with the connection surface 10A. Each of the multiple bonding layers 20 contains nickel (Ni), tin (Sn), and silver (Ag). Alternatively, each of the multiple bonding layers 20 may contain nickel, tin, and antimony (Sb), or may be a sintered body of metal particles. The metal particles may contain, for example, silver.

[0023] 6 to 8, the semiconductor element 30 is mounted on a plurality of terminals 10. The semiconductor element 30 is, for example, an LSI (Large Scale Integration). The semiconductor element 30 has a plurality of electrodes 31.

[0024] 6 to 8, each of the plurality of electrodes 31 faces a respective connection surface 10A of the plurality of terminals 10. Each of the plurality of electrodes 31 is conductively bonded to one of the connection surfaces 10A of the plurality of terminals 10 via one of the plurality of bonding layers 20. This provides electrical continuity between the semiconductor element 30 and the connection surface 10A of each of the plurality of terminals 10.

[0025] 3 to 8, the multiple coating layers 50 are exposed to the outside. Each of the multiple coating layers 50 covers the mounting surface 10B and the first end face 10C of each of the multiple terminals 10. The second end face 10D of each of the multiple terminals 10 is exposed to the outside from the multiple coating layers 50. Furthermore, one of the multiple coating layers 50 covers the area of ​​one of the four dummy terminals 19 that is exposed from the sealing resin 40.

[0026] The multiple coating layers 50 are conductive. The multiple coating layers 50 are conductively bonded to a wiring board via solder, thereby mounting the semiconductor device A10 on the wiring board. Each of the multiple coating layers 50 contains a metal element. The metal element is tin.

[0027] Furthermore, each of the multiple coating layers 50 may include multiple metal layers. The multiple metal layers are formed by laminating a nickel layer, a palladium (Pd) layer, and a gold (Au) layer in this order from the side closest to the region of either the multiple terminals 10 or the multiple dummy terminals 19 that is exposed from the sealing resin 40. Therefore, in each of the multiple coating layers 50, the gold layer is exposed to the outside.

[0028] Next, an example of a manufacturing method for the semiconductor device A10 will be described with reference to Figures 11 to 21. Here, Figures 11 to 14 and Figures 17 to 21 each correspond to Figure 6. Figures 15 and 16 each correspond to Figure 9.

[0029] First, in the steps shown in FIGS. 11 to 16, a plurality of terminals 10 are formed from a lead frame 81. The lead frame 81 is an element that includes a plurality of terminals 10. Therefore, the lead frame 81 includes a connection surface 10A and a mounting surface 10B that face opposite each other in the first direction z. The steps of forming the plurality of terminals 10 include a first step S1 shown in FIGS. 11 to 14 and a second step S2 shown in FIGS. 15 and 16.

[0030] In a first step S1, the first surface 101 of each of the multiple terminals 10 is formed on the lead frame 81. In the first step S1, the first surface 101 is formed by penetrating the lead frame 81, which includes the connection surface 10A and the mounting surface 10B, in the first direction z. First, as shown in FIG. 11 , a first resist layer 82 is formed to cover the connection surface 10A and the mounting surface 10B of the lead frame 81. The first resist layer 82 is formed by photolithography patterning. At this time, a plurality of first openings 821 are formed in the first resist layer 82, each penetrating in the first direction z. A partial area of ​​the mounting surface 10B is exposed from each of the multiple first openings 821.

[0031] 12, a plurality of recessed surfaces 811 are formed in the lead frame 81, each recessed from a plurality of regions of the mounting surface 10B that are individually exposed through each of the plurality of first openings 821 in the first resist layer 82. The plurality of recessed surfaces 811 are formed by etching. After the plurality of recessed surfaces 811 are formed, the first resist layer 82 is removed.

[0032] 13, a second resist layer 83 is formed to cover the connection surface 10A, the mounting surface 10B, and the recessed surfaces 811 of the lead frame 81. The second resist layer 83 is formed by photolithography patterning. At this time, a plurality of second openings 831 are formed in the second resist layer 83, each penetrating the second resist layer 83 in the first direction z. A partial region of each of the recessed surfaces 811 is individually exposed from each of the second openings 831.

[0033] Finally, as shown in FIG. 14 , a plurality of through holes 812 are formed in the lead frame 81, penetrating in the first direction z from each region of the plurality of recessed surfaces 811 individually exposed from each of the plurality of second openings 831 in the second resist layer 83. The plurality of through holes 812 are formed by etching. As the plurality of through holes 812 are formed, the lead frame 81 is provided with the first surfaces 101 of the plurality of terminals 10 and a plurality of boundary portions 813, each of which forms a boundary between the connection surface 10A and one of the first surfaces 101 of the plurality of terminals 10. After the plurality of through holes 812 are formed, the second resist layer 83 is removed. This completes the first step S1.

[0034] Next, in the second step S2, the second surface 102 of each of the plurality of terminals 10 is formed on the lead frame 81. In the second step S2, as shown in Fig. 15, the second surface 102 of each of the plurality of terminals 10 is formed on the lead frame 81 by removing the plurality of boundary portions 813 formed on the lead frame 81 by etching. In this way, the second step S2 is completed and the plurality of terminals 10 are formed on the lead frame 81.

[0035] 16 shows another manufacturing method in the second step S2. In this manufacturing method, a third resist layer 84 covering the lead frame 81 is formed before forming the second surface 102 of each of the plurality of terminals 10. The third resist layer 84 is formed by photolithography patterning. At this time, a plurality of third openings 841 are formed in the third resist layer 84, which individually expose the plurality of boundary portions 813 formed in the lead frame 81. Next, the plurality of boundary portions 813 individually exposed from the plurality of third openings 841 are removed by etching. Finally, the third resist layer 84 is removed. As a result, the second surface 102 of each of the plurality of terminals 10 is formed on the lead frame 81.

[0036] Next, as shown in FIG. 17 , a semiconductor element 30 is placed on the connection surface 10A of each of the terminals 10, electrically connected to the connection surface 10A of each of the terminals 10. First, multiple bonding layers 20 are formed on the connection surface 10A of each of the terminals 10. The multiple bonding layers 20 are formed by photolithographically patterning the connection surface 10A of each of the terminals 10, and then depositing multiple metal layers by electroplating using the lead frame 81 as a conductive path. Thereafter, each of the multiple electrodes 31 of the semiconductor element 30 is conductively bonded to one of the multiple terminals 10. The conductive bonding of the semiconductor element 30 is achieved by flip-chip bonding. The conductive bonding of the semiconductor element 30 is achieved by temporarily attaching each of the multiple electrodes 31 to the multiple bonding layers 20 individually, and then melting and solidifying the multiple bonding layers 20 by reflow.

[0037] 18, a sealing resin 40 is formed to cover a portion of each of the plurality of terminals 10 and the semiconductor element 30. Through this process, a top surface 41 and a bottom surface 42 are formed in the sealing resin 40, and the mounting surface 10B of each of the plurality of terminals 10 is exposed from the bottom surface 42.

[0038] 19, a plurality of grooves 814 are formed recessed from the mounting surface 10B of each of the plurality of terminals 10 and from the bottom surface 42 of the sealing resin 40. The plurality of grooves 814 are formed by removing a portion of the bottom surface 42 using a first blade 88. The plurality of grooves 814 are formed in a lattice pattern along the second direction x and the third direction y. This process forms a plurality of first side surfaces 43 in the sealing resin 40, and forms a first end surface 10C exposed from any of the plurality of first side surfaces 43 in each of the plurality of terminals 10.

[0039] 20, a plurality of coating layers 50 are formed to individually cover the mounting surface 10B and the first end surface 10C of each of the plurality of terminals 10. The plurality of coating layers 50 are formed by electrolytic plating using the lead frame 81 as a conductive path. Alternatively, the plurality of coating layers 50 can be formed by electroless plating.

[0040] Finally, as shown in FIG. 21 , the lead frame 81 and the sealing resin 40 are cut using a second blade 89. In this step, the lead frame 81 and the sealing resin 40 are cut by inserting the second blade 89 into multiple grooves 814 formed in the sealing resin 40. The thickness of the second blade 89 is set to be smaller than the thickness of the first blade 88. This step forms multiple second side surfaces 44 in the sealing resin 40, and forms second end surfaces 10D exposed from any of the multiple second side surfaces 44 on each of the multiple terminals 10. By going through the above steps, the semiconductor device A10 is obtained.

[0041] Next, the effects of the semiconductor device A10 will be described.

[0042] The semiconductor device A10 includes a terminal 10, a semiconductor element 30, and a sealing resin 40. The terminal 10 has a connection surface 10A, a first surface 101, and a second surface 102. When viewed in the first direction z, the first surface 101 overlaps the connection surface 10A. The second surface 102 is convex and contacts the sealing resin 40. This configuration makes the shape of the second surface 102 more rounded than conventional configurations. As a result, even if thermal stress caused by heat generated by the semiconductor element 30 occurs on the second surface 102, the thermal stress transmitted from the second surface 102 to the sealing resin 40 is reduced. Therefore, this configuration makes it possible to suppress the occurrence of cracks in the sealing resin 40 in the semiconductor device A10.

[0043] The first surface 101 of the terminal 10 is concave and is covered with the sealing resin 40. With this configuration, the sealing resin 40 exhibits an anchoring effect on the terminal 10. This effectively prevents the terminal 10 from falling off the sealing resin 40.

[0044] The terminal 10 has a third surface 103. When viewed in the first direction z, the third surface 103 overlaps the connection surface 10A. The third surface 103 is concave and contacts the sealing resin 40. In the terminal 10, the degree of recession of the third surface 103 is greater than the degree of recession of the first surface 101. By adopting this configuration, the areas of the sealing resin 40 that contact each of the connection surface 10A and the third surface 103 in the terminal 10 are further enlarged. This makes it possible to more effectively prevent the terminal 10 from falling off the sealing resin 40.

[0045] The surface roughness of second surface 102 is smaller than the surface roughness of connecting surface 10A and first surface 101. By adopting this configuration, the thermal stress transmitted from second surface 102 to sealing resin 40 can be effectively reduced.

[0046] The terminal 10 has a fourth surface 104. The fourth surface 104 is convex and contacts the sealing resin 40. In a cross section of the terminal 10 that includes the first direction z as an in-plane direction, the second surface 102 and the fourth surface 104 are defined by a first section L1 and a second section L2, respectively. The first section L1 and the second section L2 are each curved. The length of the first section L1 is shorter than the length of the second section L2. This configuration reduces the thermal stress transmitted from the second surface 102 to the sealing resin 40 while preventing excessive reduction in the area of ​​the connection surface 10A.

[0047] The radius of curvature r2 of the second section L2 is larger than the radius of curvature r1 of the first section L1. By adopting this configuration, the distribution of the thermal stress transmitted from the terminal 10 to the sealing resin 40 can be made more uniform.

[0048] The semiconductor device A10 further includes a covering layer 50 that covers the mounting surface 10B of the terminal 10. The covering layer 50 contains a metal element. This configuration improves the wettability of the solder to the terminal 10 when the semiconductor device A10 is mounted on a wiring board. This improves the mounting strength of the semiconductor device A10 on the wiring board.

[0049] The semiconductor device A10 further includes four dummy terminals 19 arranged at the four corners of the semiconductor device A10 when viewed in the first direction z. The four dummy terminals 19 do not form a conductive path between the semiconductor element 30 and the wiring board on which the semiconductor device A10 is mounted. This configuration allows thermal stress caused by heat generated by the semiconductor device A10 to be concentrated on the four dummy terminals 19. This makes it possible to prevent cracks from occurring in the solder joining the wiring board and the terminals 10.

[0050] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Fig. 22. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. Here, Fig. 22 corresponds to Fig. 9, which shows the semiconductor device A10.

[0051] In the semiconductor device A20, the configuration of the multiple terminals 10 is different from that of the semiconductor device A10.

[0052] In each of the plurality of terminals 10, as shown in FIG. 22, the second surface 102 overlaps the third surface 103 when viewed in the first direction z.

[0053] Next, the effects of the semiconductor device A20 will be described.

[0054] The semiconductor device A20 includes a terminal 10, a semiconductor element 30, and a sealing resin 40. The terminal 10 has a connection surface 10A, a first surface 101, and a second surface 102. When viewed in the first direction z, the first surface 101 overlaps the connection surface 10A. The second surface 102 is convex and contacts the sealing resin 40. Therefore, with this configuration, the semiconductor device A20 can also suppress the occurrence of cracks in the sealing resin 40. Furthermore, by having a configuration in common with the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0055] In the semiconductor device A20, the second surface 102 of the terminal 10 overlaps the third surface 103 of the terminal 10 when viewed in the first direction z. By adopting this configuration, the first section L1 defining the second surface 102 becomes longer and the radius of curvature r1 of the first section L1 becomes larger, as shown in FIG. 22. This more effectively reduces the thermal stress transmitted from the second surface 102 to the sealing resin 40 due to the heat generated by the semiconductor element 30.

[0056] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Fig. 23. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. Here, Fig. 23 corresponds to Fig. 9, which shows the semiconductor device A10.

[0057] In the semiconductor device A30, the configuration of the multiple terminals 10 is different from that of the semiconductor device A10.

[0058] 23, each of the multiple terminals 10 has a fifth surface 105. The fifth surface 105 is connected to the third surface 103 and the mounting surface 10B. The fifth surface 105 is convex. In the semiconductor device A30, the fifth surface 105 is in contact with the sealing resin 40.

[0059] Next, the effects of the semiconductor device A30 will be described.

[0060] The semiconductor device A30 includes a terminal 10, a semiconductor element 30, and a sealing resin 40. The terminal 10 has a connection surface 10A, a first surface 101, and a second surface 102. When viewed in the first direction z, the first surface 101 overlaps the connection surface 10A. The second surface 102 is convex and contacts the sealing resin 40. Therefore, with this configuration, the semiconductor device A30 can also suppress the occurrence of cracks in the sealing resin 40. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0061] In the semiconductor device A30, the terminal 10 has a fifth surface 105 that connects to the third surface 103 and the mounting surface 10B. The fifth surface 105 is convex. During the manufacturing process of the semiconductor device A10, metal burrs may be formed at the boundary between the third surface 103 and the mounting surface 10B in the process shown in FIG. 12. When mounting a semiconductor device A10 with metal burrs on a wiring board, there is a concern that the mounting condition of the semiconductor device A10 on the wiring board may be deteriorated. Therefore, by adopting this configuration, the metal burrs are removed from the semiconductor device A30. This improves the mounting condition of the semiconductor device A30 on the wiring board.

[0062] [Fourth embodiment] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Fig. 24. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. Here, Fig. 24 corresponds to Fig. 9, which shows the semiconductor device A10.

[0063] In the semiconductor device A40, the configuration of the multiple terminals 10 is different from that of the semiconductor device A30.

[0064] As shown in FIG. 24, the fifth surface 105 of each of the plurality of terminals 10 is in contact with one of the plurality of coating layers 50.

[0065] Next, the effects of the semiconductor device A40 will be described.

[0066] The semiconductor device A40 includes a terminal 10, a semiconductor element 30, and a sealing resin 40. The terminal 10 has a connection surface 10A, a first surface 101, and a second surface 102. When viewed in the first direction z, the first surface 101 overlaps the connection surface 10A. The second surface 102 is convex and contacts the sealing resin 40. Therefore, with this configuration, the semiconductor device A40 can also suppress the occurrence of cracks in the sealing resin 40. Furthermore, by having a configuration in common with the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0067] In the semiconductor device A40, the fifth surface 105 of the terminal 10 is in contact with the covering layer 50. With this configuration, when the semiconductor device A40 is mounted on a wiring board, an anchoring effect is exerted on the covering layer 50 relative to the fifth surface 105. This improves the mounting strength of the semiconductor device A40 while improving the mounting state of the semiconductor device A40 on the wiring board.

[0068] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0069] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] a terminal (10) having a connection surface (10A) facing one side in a first direction (z); a semiconductor element (30) that is electrically connected to the connection surface; a sealing resin (40) that covers a portion of the terminal and the semiconductor element, The terminal has a first surface (101) located on the other side in the first direction with respect to the connection surface and recessed into the terminal, and a second surface (102) connected to the connection surface and the first surface, When viewed in the first direction, the first surface overlaps the connecting surface, The second surface is convex and in contact with the sealing resin. [Appendix 2] The semiconductor device (A10) according to Appendix 1, wherein the first surface (101) is concave. [Appendix 3] The semiconductor device (A10) according to appendix 2, wherein the first surface (101) is covered with the sealing resin (40). [Appendix 4] The terminal (10) has a third surface (103) that is located on the opposite side of the connecting surface (10A) with respect to the first surface (101) and recessed into the terminal, The semiconductor device (A10) according to appendix 3, wherein the third surface overlaps the connection surface when viewed in the first direction (z). [Appendix 5] The semiconductor device (A10) according to appendix 4, wherein the third surface (103) is concave and covered with the sealing resin (40). [Appendix 6] The semiconductor device (A10) according to Appendix 5, wherein the degree of recession of the third surface (103) of the terminal (10) is greater than the degree of recession of the first surface (101). [Appendix 7] The terminal (10) has a fourth surface (104) connected to the first surface (101) and the third surface (103), The semiconductor device (A10) according to appendix 6, wherein the fourth surface is convex and in contact with the sealing resin (40). [Appendix 8] In a cross section of the terminal (10) including the first direction (z) as an in-plane direction, the second surface (102) and the fourth surface (104) are individually defined by a first section (L1) and a second section (L2), respectively; each of the first section and the second section is a curved line; The semiconductor device (A10) according to appendix 7, wherein the length of the first section is shorter than the length of the second section. [Appendix 9] The semiconductor device (A10) according to appendix 8, wherein the radius of curvature (r1) of the first section (L1) is smaller than the radius of curvature (r2) of the second section (L2). [Appendix 10] The semiconductor device (A20) according to appendix 7, wherein the second surface (102) overlaps the third surface (103) when viewed in the first direction (z). [Appendix 11] The terminal (10) has a mounting surface (10B) facing the opposite side to the connection surface (10A) in the first direction (z), The semiconductor device (A10) according to any one of appendices 7 to 10, wherein the mounting surface is exposed from the sealing resin (40). [Appendix 12] The semiconductor element (30) has an electrode (31) facing the connection surface (10A), The semiconductor device (A10) according to Appendix 11, wherein the electrode is conductively bonded to the connection surface. [Appendix 13] Further provided is a covering layer (50) that covers the mounting surface (10B), The semiconductor device (A10) according to Appendix 11, wherein the coating layer contains a metal element. [Appendix 14] The terminal (10) has a fifth surface (105) connected to the third surface (103) and the mounting surface (10B), The semiconductor device (A30, A40) according to Appendix 13, wherein the fifth surface is convex. [Appendix 15] The semiconductor device (A40) according to Appendix 14, wherein the fifth surface (105) is in contact with the covering layer (50). [Appendix 16] The terminal (10) has a first end surface (10C) facing in a direction perpendicular to the first direction (z), The semiconductor device (A10) according to Appendix 13, wherein the first end face is covered with the covering layer (50). [Appendix 17] A step of forming a terminal (10) having a connection surface (10A) facing one side in a first direction (z); a step of placing a semiconductor element (30) that is electrically connected to the connection surface; and forming a sealing resin (40) that covers a portion of the terminal and the semiconductor element, The step of forming the terminal includes a first step (S1) of forming a first surface (101) that is located on the other side of the connection surface in the first direction and that recesses into the terminal, and a second step (S2) of forming a second surface (102) that is connected to the connection surface and the first surface, In the first step, the first surface is formed by penetrating a lead frame (81) including the connection surface in the first direction, A method for manufacturing a semiconductor device (A10), wherein in the second step, the second surface is formed by removing by etching a portion of the lead frame that forms a boundary between the connection surface and the first surface. [Appendix 18] the lead frame (81) includes a mounting surface (10B) facing the opposite side to the connection surface (10A) in the first direction (z), The first step (S1) includes the steps of: forming a first resist layer (82) that has a first opening (821) that exposes the mounting surface and covers the lead frame; forming a recessed surface (811) in the lead frame that is recessed from the mounting surface exposed from the first opening; forming a second resist layer (83) that has a second opening (831) that exposes the recessed surface and covers the lead frame; and forming a through portion (812) in the lead frame that penetrates in the first direction from the recessed surface exposed from the second opening, The first surface (101) defines the through portion, The method for manufacturing a semiconductor device (A10) according to Appendix 17, wherein the recessed surface and the through portion are each formed by etching. [Appendix 19] The second step (S2) includes a step of forming a third resist layer (84) covering the lead frame (81) before forming the second surface (102), A method for manufacturing a semiconductor device (A10) described in Appendix 18, wherein the third resist layer has a third opening (841) that exposes a portion of the lead frame that forms the boundary between the connection surface (10A) and the first surface (101). [Appendix 20] The semiconductor device (A10) according to Appendix 5, wherein the second surface (102) has a surface roughness smaller than the surface roughness of each of the connecting surface (10A) and the first surface (101). [Appendix 21] The semiconductor device (A10) according to Appendix 14, wherein the metal element includes either tin or gold. [Appendix 22] The semiconductor device (A30) according to Appendix 15, wherein the fifth surface (105) is in contact with the sealing resin (40). [Explanation of symbols]

[0070] A10 to A40: Semiconductor device 10: Terminal 10A: Connection surface 10B: Mounting surface 10C, 10D: 1st end face, 2nd end face 101~105: 1st side~5th side 19: Dummy terminal 20: Bonding layer 30: Semiconductor element 31: Electrode 40: Sealing resin 41:Top surface 42: Bottom 43, 2nd side: 1st side, 2nd side 50: Covering layer 81: Lead frame 811: Indented surface 812: Penetration 813: Boundary 814: Groove 82: First resist layer 821: First opening 83: Second resist layer 831: Second opening 84: Third resist layer 841: Third opening 88, 89: 1st blade, 2nd blade L1, L2: First section, second section r1,r2: radius of curvature S1, S2: 1st process, 2nd process z,x,y: 1st direction, 2nd direction, 3rd direction

Claims

1. a terminal having a connection surface facing one side in the first direction; a semiconductor element electrically connected to the connection surface; a sealing resin that covers a portion of the terminal and the semiconductor element, the terminal has a first surface located on the other side in the first direction with respect to the connection surface and recessed into the terminal, and a second surface connected to the connection surface and the first surface, When viewed in the first direction, the first surface overlaps the connecting surface, The second surface is convex and in contact with the sealing resin.

2. The semiconductor device according to claim 1 , wherein the first surface is concave.

3. The semiconductor device according to claim 2 , wherein the first surface is covered with the sealing resin.

4. the terminal has a third surface located on the opposite side of the connecting surface with respect to the first surface and recessed into the terminal; The semiconductor device according to claim 3 , wherein the third surface overlaps the connection surface when viewed in the first direction.

5. The semiconductor device according to claim 4 , wherein said third surface is concave and is covered with said sealing resin.

6. 6. The semiconductor device according to claim 5, wherein the degree of recession of the third surface of the terminal is greater than the degree of recession of the first surface.

7. the terminal has a fourth surface connected to the first surface and the third surface, The semiconductor device according to claim 6 , wherein said fourth surface is convex and in contact with said sealing resin.

8. In a cross section of the terminal that includes the first direction as an in-plane direction, the second surface and the fourth surface are individually defined by a first section and a second section, respectively; each of the first section and the second section is a curved line; The semiconductor device according to claim 7 , wherein the length of said first section is shorter than the length of said second section.

9. The semiconductor device according to claim 8 , wherein the radius of curvature of said first section is smaller than the radius of curvature of said second section.

10. The semiconductor device according to claim 7 , wherein the second surface overlaps the third surface when viewed in the first direction.

11. the terminal has a mounting surface facing away from the connection surface in the first direction, 11. The semiconductor device according to claim 7, wherein the mounting surface is exposed from the sealing resin.

12. the semiconductor element has an electrode facing the connection surface, The semiconductor device according to claim 11 , wherein the electrode is conductively bonded to the connection surface.

13. a covering layer that covers the mounting surface, The semiconductor device according to claim 11 , wherein the covering layer contains a metal element.

14. the terminal has a fifth surface connected to the third surface and the mounting surface, The semiconductor device according to claim 13 , wherein the fifth surface is convex.

15. The semiconductor device according to claim 14 , wherein the fifth surface is in contact with the covering layer.

16. the terminal has a first end surface facing in a direction perpendicular to the first direction, The semiconductor device according to claim 13 , wherein the first end face is covered with the covering layer.

17. forming a terminal having a connection surface facing one side in a first direction; a step of placing a semiconductor element that is electrically connected to the connection surface; forming a sealing resin to cover a portion of the terminal and the semiconductor element; The step of forming the terminal includes a first step of forming a first surface that is located on the other side in the first direction with respect to the connection surface and that recesses into the terminal, and a second step of forming a second surface that is connected to the connection surface and the first surface, In the first step, the first surface is formed by penetrating a lead frame including the connection surface in the first direction; In the second step, the second surface is formed by removing a portion of the lead frame that forms a boundary between the connection surface and the first surface by etching.

18. the lead frame includes a mounting surface facing away from the connection surface in the first direction, the first step includes the steps of: forming a first resist layer that has a first opening that exposes the mounting surface and covers the lead frame; forming a recessed surface in the lead frame that is recessed from the mounting surface exposed from the first opening; forming a second resist layer that has a second opening that exposes the recessed surface and covers the lead frame; and forming a through portion in the lead frame that penetrates in the first direction from the recessed surface exposed from the second opening, the first surface defines the through portion; The method for manufacturing a semiconductor device according to claim 17 , wherein each of the recessed surface and the through portion is formed by etching.

19. the second step includes a step of forming a third resist layer covering the lead frame before forming the second surface; 20. The method for manufacturing a semiconductor device according to claim 18, wherein the third resist layer has a third opening that exposes a portion of the lead frame that forms a boundary between the connection surface and the first surface.

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