Semiconductor device and semiconductor module

Abstract

To provide a semiconductor device capable of further facilitating the positioning of an external connection member relative to power terminals.SOLUTION: A semiconductor device A10 includes: a base material 10 that includes a first conductive layer 13; a first semiconductor element that is joined to one side of the first conductive layer 13 in a first direction z; a first power terminal 34 that is electrically conducted to the first conductive layer 13 and the first semiconductor element; and a sealing resin 60 that covers the first semiconductor element. The sealing resin 60 has a first surface 631 facing the one side in the first direction z. The first power terminal 34 is exposed from the first surface 631, and is surrounded by the sealing resin 60 when viewed in the first direction z. The sealing resin 60 has a first regulating surface 641 rising from the first surface 631. The first regulating surface 641 faces a side where the first power terminal 34 is positioned on the basis of the first semiconductor element in a second direction x.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a semiconductor module including the semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices incorporating multiple semiconductor elements with switching functions, such as MOSFETs and IGBTs, have been widely known. Such semiconductor devices are primarily used for power conversion. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in this document includes a first wiring layer and a second wiring layer, a first semiconductor element conductively bonded to the first wiring layer, a second semiconductor element conductively bonded to the second wiring layer and electrically connected to the first semiconductor element, and a substrate supporting the first wiring layer and the second wiring layer. The semiconductor device further includes a first terminal electrically connected to the first semiconductor element, a second terminal electrically connected to the second semiconductor element, and a sealing resin covering the first semiconductor element and the second semiconductor element. A portion of each of the first terminal and the second terminal protrudes from a side surface of the sealing resin.

[0003] In the semiconductor device disclosed in Patent Document 1, an external connection member such as a bus bar may be conductively joined to each of the first terminal and the second terminal. In this case, if each of the first terminal and the second terminal is surrounded by a sealing resin in a plan view, it may be time-consuming to position the external connection member when conductively joining the external connection member to each of the first terminal and the second terminal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-53801

[0005] [overview] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that allows for easier positioning of an external connection member relative to a power terminal.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a substrate including a first conductive layer; a first semiconductor element bonded to one side of the first conductive layer in a first direction; a first power terminal electrically connected to the first conductive layer and the first semiconductor element; and a sealing resin covering the first semiconductor element. The sealing resin has a first surface facing one side of the first direction. The first power terminal is exposed from the first surface and is surrounded by the sealing resin when viewed in the first direction. The sealing resin has a first restricting surface rising from the first surface. The first restricting surface faces the side where the first power terminal is located relative to the first semiconductor element in a second direction perpendicular to the first direction.

[0007] A semiconductor module according to a second aspect of the present disclosure includes a heat dissipation member and a plurality of semiconductor devices, each of which has the same configuration as the semiconductor device according to the first aspect of the present disclosure, and a base material of each of the semiconductor devices is bonded to one side of the heat dissipation member in a first direction.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view of a semiconductor module including a plurality of semiconductor devices according to the first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a plan view corresponding to FIG. 2, showing the sealing resin and the heat dissipation member. [Figure 4] FIG. 4 is a plan view corresponding to FIG. 3, further showing the first and second conductive members in perspective. [Figure 5] FIG. 5 is a bottom view of the semiconductor device shown in FIG. 2, in which the heat dissipation member and the bonding layer are omitted. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a partially enlarged view of FIG. 6, showing the first semiconductor element and its vicinity. [Figure 9] FIG. 9 is a partially enlarged view of FIG. 6, showing the second semiconductor element and its vicinity. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a partially enlarged view of FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a partially enlarged view of FIG. 16, showing the third power terminal and its vicinity. [Figure 16] FIG. 16 is a plan view of the semiconductor module shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a plan view of the semiconductor device according to the second embodiment of the present disclosure, showing the sealing resin, the heat dissipation member, the first conductive member, and the second conductive member. [Figure 19] FIG. 19 is a bottom view of the semiconductor device shown in FIG. 18, with the heat dissipation member and bonding layer not shown. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a partially enlarged cross-sectional view of the semiconductor device according to the third embodiment of the present disclosure, and corresponds to FIG. [Figure 22] FIG. 22 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 21, and corresponds to FIG. [Figure 23] FIG. 23 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 21, and corresponds to FIG. [Figure 24] FIG. 24 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 25] FIG. 25 is a cross-sectional view of the semiconductor device shown in FIG. 24, and corresponds to FIG.

[0010] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0011] [First embodiment] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 15. The semiconductor device A10 constitutes a part of a semiconductor module B, which will be described later. The semiconductor device A10 includes a substrate 10, a first signal wiring 21, a second signal wiring 22, a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, two thermistors 33, a first power terminal 34, a second power terminal 35, a third power terminal 36, a sealing resin 60, a plurality of external connection members 71, and a heat dissipation member 81. The semiconductor device A10 further includes a plurality of sleeves 29, a first signal terminal 41 to a fourth signal terminal 44, two fifth signal terminals 45, two sixth signal terminals 46, a seventh signal terminal 47, an eighth signal terminal 48, a plurality of first wires 51 to a plurality of fourth wires 54, a fifth wire 55, and a sixth wire 56. For ease of understanding, FIG. 3 shows the sealing resin 60 and the heat dissipation member 81 in a see-through manner. For ease of understanding, Fig. 4 shows the first conductive member 37 and the second conductive member 38 in a more transparent manner than Fig. 3. In Fig. 3, the transparent sealing resin 60 and heat dissipation member 81 are each shown by imaginary lines (two-dot chain lines). In Fig. 4, the transparent first conductive member 37, second conductive member 38, sealing resin 60, and heat dissipation member 81 are each shown by imaginary lines.

[0012] In the description of the semiconductor device A10, for convenience, the normal direction of the first mounting surface 13A of the first conductive layer 13, which will be described later, is referred to as the "first direction z." The direction perpendicular to the first direction z is referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x is referred to as the "third direction y." Furthermore, in the description of the semiconductor device A10, "overlapping" refers to two different elements, and includes cases where one element entirely overlaps the other, as well as cases where one element partially overlaps the other.

[0013] The semiconductor device A10 converts DC power input to a first power terminal 34 and a second power terminal 35 into AC power using a plurality of first semiconductor elements 31 and a plurality of second semiconductor elements 32. The converted AC power is output from a third power terminal 36 and input to a power supply target such as a motor. The semiconductor device A10 forms part of a power conversion circuit such as an inverter.

[0014] As shown in FIGS. 6, 10, and 11, the sealing resin 60 covers the plurality of first semiconductor elements 31 and the plurality of second semiconductor elements 32. The sealing resin 60 has electrical insulation properties. The sealing resin 60 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 2 and 4, the sealing resin 60 has a top surface 61, a bottom surface 62, first surfaces 631 to 634, a plurality of first housing portions 632A, a second housing portion 634A, and a plurality of pedestals 68.

[0015] 6, 7, and 10, the top surface 61 faces the same side in the first direction z as a first mounting surface 13A of the first conductive layer 13, which will be described later. The bottom surface 62 faces the opposite side to the top surface 61 in the first direction z.

[0016] As shown in FIGS. 2, 6, and 7, the first surface 631 to the fourth surface 634 each face the same side as the top surface 61 in the first direction z. The first surface 631 is located on one side of the top surface 61 in the second direction x. The second surface 632 is located between the top surface 61 and the first surface 631 in the second direction x. The third surface 633 is located on the opposite side of the first surface 631 with respect to the top surface 61 in the second direction x. The fourth surface 634 is located between the top surface 61 and the third surface 633 in the second direction x.

[0017] 2 and 6, each of the multiple first accommodating portions 632A opens from the second surface 632 and is recessed from the second surface 632. The multiple first accommodating portions 632A are arranged along the third direction y. Each of the multiple second accommodating portions 634A opens from the fourth surface 634 and is recessed from the fourth surface 634. The multiple second accommodating portions 634A are arranged along the third direction y.

[0018] As shown in FIG. 2, when viewed in the first direction z, the multiple pedestal portions 68 are located at four corners of the sealing resin 60. Each of the multiple pedestal portions 68 has a seating surface 681. The seating surface 681 faces the same side as the top surface 61 in the first direction z. In the first direction z, the seating surface 681 is farther from the base material 10 than the top surface 61. Each of the multiple pedestal portions 68 has an opening recessed from the seating surface 681.

[0019] 4 to 7, the base material 10 is located on one side in the first direction z of each of the plurality of first semiconductor elements 31 and the plurality of second semiconductor elements 32. The base material 10 includes a first insulating layer 11, a second insulating layer 12, a first conductive layer 13, a second conductive layer 14, a third conductive layer 15, a first heat dissipation layer 16, and a second heat dissipation layer 17. Of these, the elements excluding a second layer 132 of the first conductive layer 13 and a fourth layer 142 of the second conductive layer 14, which will be described later, are composed of a substrate formed by, for example, active metal brazing (AMB).

[0020] As shown in FIGS. 6 and 10 , the first insulating layer 11 is located on the opposite side of the first conductive layer 13 from the multiple first semiconductor elements 31 in the first direction z. The first insulating layer 11 is provided with the first conductive layer 13 and the third conductive layer 15. The first insulating layer 11 includes a ceramic such as aluminum nitride (AlN). The first insulating layer 11 is covered with a sealing resin 60.

[0021] As shown in FIGS. 6 and 10 , the first conductive layer 13 is located between the first insulating layer 11 and the plurality of first semiconductor elements 31 in the first direction z. The first conductive layer 13 carries the plurality of first semiconductor elements 31, first signal wiring 21, and first power terminals 34. The first conductive layer 13 contains copper (Cu). The first conductive layer 13 is covered with a sealing resin 60. The first conductive layer 13 has a first mounting surface 13A facing the side opposite to the side facing the first insulating layer 11 in the first direction z.

[0022] As shown in FIGS. 6 and 10 , the first conductive layer 13 includes a first layer 131 and a second layer 132. The first layer 131 is bonded to the first insulating layer 11. The first layer 131 carries a first power terminal 34. The second layer 132 is located on the opposite side of the first insulating layer 11 in the first direction z relative to the first layer 131. The second layer 132 includes a first mounting surface 13A. The second layer 132 carries a plurality of first semiconductor elements 31 and first signal wiring 21. The second layer 132 is conductively bonded to the first layer 131 via a bonding layer 39. The dimension of the second layer 132 in the first direction z is larger than the dimension of the first layer 131 in the first direction z. Here, the bonding layer 39 is, for example, solder. Alternatively, the bonding layer 39 may be a sintered body of metal particles. In this case, the metal particles include, for example, silver (Ag).

[0023] As shown in FIG. 14 , the third conductive layer 15 is located between the first insulating layer 11 and the second power terminal 35 in the first direction z. As shown in FIG. 4 , the third conductive layer 15 is spaced apart from the first conductive layer 13 in a direction perpendicular to the first direction z. The third conductive layer 15 carries the second power terminal 35. The third conductive layer 15 contains copper. The third conductive layer 15 is covered with a sealing resin 60.

[0024] As shown in FIGS. 6, 7, and 10, the first heat dissipation layer 16 is located on the opposite side of the first insulating layer 11 from the first conductive layer 13 in the first direction z. The first heat dissipation layer 16 is bonded to the first insulating layer 11. As shown in FIG. 5, the first heat dissipation layer 16 is exposed from the bottom surface 62 of the sealing resin 60. The first heat dissipation layer 16 contains copper. When viewed in the first direction z, the first heat dissipation layer 16 overlaps the first conductive layer 13.

[0025] As shown in FIGS. 6 and 11 , the second insulating layer 12 is located on the opposite side of the second conductive layer 14 from the multiple second semiconductor elements 32 in the first direction z. As shown in FIG. 4 , the second insulating layer 12 is spaced apart from the first insulating layer 11 in the second direction x. The second insulating layer 12 carries the second conductive layer 14. The second insulating layer 12 includes a ceramic such as aluminum nitride. The second insulating layer 12 is covered with a sealing resin 60.

[0026] As shown in FIGS. 6 and 11 , the second conductive layer 14 is located between the second insulating layer 12 and the plurality of second semiconductor elements 32 in the first direction z. As shown in FIG. 4 , the second conductive layer 14 is spaced apart from the first conductive layer 13 in the second direction x. The third conductive layer 15 carries the plurality of second semiconductor elements 32, second signal wiring 22, and third power terminals 36. The second conductive layer 14 contains copper. The second conductive layer 14 is covered with a sealing resin 60. The second conductive layer 14 has a second mounting surface 14A facing the side opposite to the side facing the second insulating layer 12 in the first direction z.

[0027] As shown in FIGS. 6 and 11 , the second conductive layer 14 includes a third layer 141 and a fourth layer 142. The third layer 141 is bonded to the second insulating layer 12. The third layer 141 carries the third power terminal 36. The fourth layer 142 is located on the opposite side of the third layer 141 from the second insulating layer 12 in the first direction z. The fourth layer 142 includes a second mounting surface 14A. The fourth layer 142 carries a plurality of second semiconductor elements 32 and second signal wiring 22. The fourth layer 142 is conductively bonded to the third layer 141 via a bonding layer 39. The dimension of the fourth layer 142 in the first direction z is larger than the dimension of the third layer 141 in the first direction z.

[0028] As shown in FIGS. 6, 7, and 11, the second heat dissipation layer 17 is located on the opposite side of the second insulating layer 12 from the second conductive layer 14 in the first direction z. The second heat dissipation layer 17 is bonded to the second insulating layer 12. As shown in FIG. 5, the second heat dissipation layer 17 is separated from the first heat dissipation layer 16 in the second direction x. The second heat dissipation layer 17 is exposed from the bottom surface 62 of the sealing resin 60. The composition of the second heat dissipation layer 17 includes copper. As viewed in the first direction z, the second heat dissipation layer 17 overlaps the second conductive layer 14.

[0029] As shown in FIGS. 6 and 10 , the multiple first semiconductor elements 31 are bonded to the first mounting surface 13A of the first conductive layer 13 (second layer 132). Each of the multiple first semiconductor elements 31 is the same element. Here, the multiple first semiconductor elements 31 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In addition, the multiple first semiconductor elements 31 include field-effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) and bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors). In the description of the semiconductor device A10, the multiple first semiconductor elements 31 are n-channel MOSFETs with a vertical structure. The multiple first semiconductor elements 31 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC). The multiple first semiconductor elements 31 are arranged along the third direction y.

[0030] As shown in FIGS. 4 and 8, each of the plurality of first semiconductor elements 31 has a first electrode 311, a second electrode 312, a first gate electrode 313, and two first detection electrodes 314.

[0031] 8 , the first electrode 311 faces the first mounting surface 13A of the first conductive layer 13 in the first direction z. In the semiconductor device A10, a current corresponding to the power before being converted by the first semiconductor element 31 flows through the first electrode 311. That is, the first electrode 311 corresponds to the drain of the first semiconductor element 31. The first electrode 311 is conductively bonded to the first mounting surface 13A via the bonding layer 39. As a result, the first electrode 311 of each of the multiple first semiconductor elements 31 is electrically connected to the first conductive layer 13.

[0032] 8, the second electrode 312 is located on the opposite side to the first electrode 311 in the first direction z. In the semiconductor device A10, a current corresponding to the power converted by the first semiconductor element 31 flows through the second electrode 312. In other words, the second electrode 312 corresponds to the source of the first semiconductor element 31.

[0033] 8, the first gate electrode 313 is located on the same side as the second electrode 312 in the first direction z. A gate voltage for driving the first semiconductor element 31 is applied to the first gate electrode 313. As shown in FIG. 4, the area of ​​the first gate electrode 313 is smaller than the area of ​​the second electrode 312 when viewed in the first direction z.

[0034] 4, the two first detection electrodes 314 are located on the same side as the second electrode 312 and the first gate electrode 313 in the first direction z. The first detection electrodes 314 are located on opposite sides of each other in the third direction y, with the first gate electrode 313 sandwiched therebetween. A voltage equivalent to the voltage applied to the second electrode 312 is applied to each of the two first detection electrodes 314. When viewed in the first direction z, the area of ​​each of the two first detection electrodes 314 is approximately equal to the area of ​​the first gate electrode 313.

[0035] As shown in Figures 6 and 11, the multiple second semiconductor elements 32 are bonded to the second mounting surface 14A of the second conductive layer 14 (fourth layer 142). Each of the multiple second semiconductor elements 32 is the same element as each of the multiple first semiconductor elements 31 shown in Figure 8. Therefore, the multiple second semiconductor elements 32 are n-channel type MOSFETs with a vertical structure. The multiple second semiconductor elements 32 are arranged along the third direction y.

[0036] As shown in FIGS. 4 and 9, each of the plurality of second semiconductor elements 32 has a third electrode 321, a fourth electrode 322, a second gate electrode 323, and two second detection electrodes 324.

[0037] 9, the third electrode 321 faces the second mounting surface 14A of the second conductive layer 14. In the semiconductor device A10, a current corresponding to the power before being converted by the second semiconductor element 32 flows through the third electrode 321. That is, the third electrode 321 corresponds to the drain of the second semiconductor element 32. The third electrode 321 is conductively bonded to the second mounting surface 14A via the bonding layer 39. As a result, the third electrode 321 of each of the multiple second semiconductor elements 32 is electrically connected to the second conductive layer 14.

[0038] 9, the fourth electrode 322 is located on the opposite side to the third electrode 321 in the first direction z. In the semiconductor device A10, a current corresponding to the power converted by the second semiconductor element 32 flows through the fourth electrode 322. In other words, the fourth electrode 322 corresponds to the source of the second semiconductor element 32.

[0039] 9, the second gate electrode 323 is located on the same side as the fourth electrode 322 in the first direction z. A gate voltage for driving the second semiconductor element 32 is applied to the second gate electrode 323. As shown in FIG. 4, the area of ​​the second gate electrode 323 is smaller than the area of ​​the fourth electrode 322 when viewed in the first direction z.

[0040] 4, the two second detection electrodes 324 are located on the same side as the fourth electrode 322 and the second gate electrode 323 in the first direction z. The second detection electrodes 324 are located on opposite sides of each other in the third direction y, with the second gate electrode 323 sandwiched therebetween. A voltage equivalent to the voltage applied to the fourth electrode 322 is applied to each of the two second detection electrodes 324. When viewed in the first direction z, the area of ​​each of the two second detection electrodes 324 is approximately equal to the area of ​​the second gate electrode 323.

[0041] As shown in Fig. 6, the first signal wiring 21 is located on the opposite side of the first insulating layer 11 with respect to the first conductive layer 13 in the first direction z. As shown in Fig. 4, the first signal wiring 21 is located between the multiple first semiconductor elements 31 and the first and second power terminals 34 and 35 in the second direction x. The first signal wiring 21 is covered with a sealing resin 60. The first signal wiring 21 has a first base layer 211, a first metal layer 212, a first wiring layer 213, a third wiring layer 214, two fifth wiring layers 215, and a seventh wiring layer 216.

[0042] 4 and 13, the first base layer 211 includes a first wiring layer 213, a third wiring layer 214, two fifth wiring layers 215, and a seventh wiring layer 216. The first base layer 211 is made of, for example, ceramics. Alternatively, the first base layer 211 may be made of a resin sheet.

[0043] 13, the first metal layer 212 is located between the first mounting surface 13A of the first conductive layer 13 (second layer 132) and the first base layer 211 in the first direction z. The first metal layer 212 is bonded to the first base layer 211. The first metal layer 212 contains copper. The first metal layer 212 is bonded to the first mounting surface 13A via a bonding layer 39.

[0044] 13, the first wiring layer 213 is located on the opposite side of the first base layer 211 from the first metal layer 212 in the first direction z. The first wiring layer 213 is bonded to the first base layer 211. The first wiring layer 213 contains copper. The first wiring layer 213 includes a portion extending in the third direction y.

[0045] 13, the third wiring layer 214 is located on the opposite side of the first metal layer 212 from the first base layer 211 in the first direction z. The third wiring layer 214 is bonded to the first base layer 211. The third wiring layer 214 contains copper. The third wiring layer 214 includes a portion extending in the third direction y. The extending portion is located adjacent to the first wiring layer 213 in the second direction x.

[0046] 13, the two fifth wiring layers 215 are located on the opposite side of the first metal layer 212 from the first base layer 211 in the first direction z. The two fifth wiring layers 215 are bonded to the first base layer 211. As shown in FIG. 4, the two fifth wiring layers 215 are adjacent to each other in the third direction y. The composition of the two fifth wiring layers 215 includes copper.

[0047] 4, the seventh wiring layer 216 is located on one side of the two fifth wiring layers 215 in the third direction y. The seventh wiring layer 216 is located on the opposite side of the first metal layer 212 in the first direction z with the first base layer 211 as the reference. The seventh wiring layer 216 is bonded to the first base layer 211. The composition of the seventh wiring layer 216 includes copper.

[0048] As shown in Fig. 6, the second signal wiring 22 is located on the opposite side of the second insulating layer 12 with respect to the second conductive layer 14 in the first direction z. As shown in Fig. 4, the second signal wiring 22 is located between the plurality of second semiconductor elements 32 and the third power terminal 36 in the second direction x. The second signal wiring 22 is covered with a sealing resin 60. The second signal wiring 22 has a second base layer 221, a second metal layer 222, a second wiring layer 223, a fourth wiring layer 224, two sixth wiring layers 225, and an eighth wiring layer 226.

[0049] 4 and 15, the second base layer 221 includes a second wiring layer 223, a fourth wiring layer 224, two sixth wiring layers 225, and an eighth wiring layer 226. The second base layer 221 is made of, for example, ceramics. Alternatively, the second base layer 221 may be made of a resin sheet.

[0050] 15, the second metal layer 222 is located between the second mounting surface 14A of the second conductive layer 14 (fourth layer 142) and the second base layer 221 in the first direction z. The second metal layer 222 is bonded to the second base layer 221. The composition of the second metal layer 222 includes copper. The second metal layer 222 is bonded to the second mounting surface 14A via a bonding layer 39.

[0051] 15, the second wiring layer 223 is located on the opposite side of the second metal layer 222 from the second base layer 221 in the first direction z. The second wiring layer 223 is bonded to the second base layer 221. The composition of the second wiring layer 223 includes copper. The second wiring layer 223 includes a portion extending in the third direction y.

[0052] 15, the fourth wiring layer 224 is located on the opposite side of the second metal layer 222 with respect to the second base layer 221 in the first direction z. The fourth wiring layer 224 is bonded to the second base layer 221. The composition of the fourth wiring layer 224 includes copper. The fourth wiring layer 224 includes a portion extending in the third direction y. The extending portion is located adjacent to the second wiring layer 223 in the second direction x.

[0053] 15, the two sixth wiring layers 225 are located on the opposite side of the second metal layer 222 from the second base layer 221 in the first direction z. The two sixth wiring layers 225 are bonded to the second base layer 221. As shown in FIG. 4, the two sixth wiring layers 225 are adjacent to each other in the third direction y. The composition of the two sixth wiring layers 225 includes copper.

[0054] 4, the eighth wiring layer 226 is located on one side of the two sixth wiring layers 225 in the third direction y. The eighth wiring layer 226 is located on the opposite side of the second metal layer 222 with respect to the second base layer 221 in the first direction z. The eighth wiring layer 226 is bonded to the second base layer 221. The composition of the eighth wiring layer 226 includes copper.

[0055] 4 and 13, the multiple sleeves 29 are individually conductively bonded to the first wiring layer 213, the third wiring layer 214, the two fifth wiring layers 215, and the seventh wiring layer 216 of the first signal wiring 21 via bonding layers 39. In addition, the multiple sleeves 29 are individually conductively bonded to the second wiring layer 223, the fourth wiring layer 224, the two sixth wiring layers 225, and the eighth wiring layer 226 of the second signal wiring 22 via bonding layers 39. Each of the multiple sleeves 29 has a cylindrical shape extending in the first direction z. The multiple sleeves 29 are made of a material containing a conductor such as a metal.

[0056] 4, one of the two thermistors 33 is conductively joined to two fifth wiring layers 215 of the first signal wiring 21. The other of the two thermistors 33 is conductively joined to two sixth wiring layers 225 of the second signal wiring 22. The two thermistors 33 are used as temperature detection sensors for the semiconductor device A10.

[0057] As shown in FIG. 4 , the first power terminal 34 is located on the opposite side of the first signal wiring 21 from the multiple first semiconductor elements 31 in the second direction x. As shown in FIG. 6 , the first power terminal 34 is conductively bonded to the first layer 131 of the first conductive layer 13. This allows the first power terminal 34 to be electrically connected to the first electrodes 311 of each of the multiple first semiconductor elements 31. As shown in FIG. 2 , the first power terminal 34 is surrounded by a sealing resin 60. The first power terminal 34 is exposed from a first surface 631 of the sealing resin 60. In the semiconductor device A10, the first power terminal 34 is a P terminal (positive electrode) to which DC power to be converted is input. The first power terminal 34 contains copper. As shown in FIGS. 13 and 14 , the first power terminal 34 has a first end surface 34A, a first circumferential surface 34B, a second circumferential surface 34C, a first engagement portion 341, and a first protrusion 342.

[0058] As shown in FIGS. 13 and 14 , the first end face 34A faces the same side as the first surface 631 of the sealing resin 60 in the first direction z. The first end face 34A is exposed from the first surface 631. The first engagement portion 341 is exposed from the first surface 631. As shown in FIG. 2 , the first engagement portion 341 is surrounded by the first end face 34A when viewed in the first direction z. When viewed in the first direction z, the area of ​​the first end face 34A is larger than the area of ​​the first engagement portion 341. The first engagement portion 341 opens from the first end face 34A. The first engagement portion 341 extends in the first direction z. The first engagement portion 341 penetrates in the first direction z.

[0059] As shown in FIGS. 13 and 14 , the first circumferential surface 34B faces in a direction perpendicular to the first direction z. The first circumferential surface 34B defines a first engagement portion 341. A thread is formed on the first circumferential surface 34B. The thread is, for example, a female thread. The second circumferential surface 34C faces the opposite side to the first circumferential surface 34B in the direction perpendicular to the first direction z. The second circumferential surface 34C is in contact with the sealing resin 60. As shown in FIGS. 12 and 14 , the first protruding portion 342 protrudes from the second circumferential surface 34C. The first protruding portion 342 is conductively bonded to the first layer 131 of the first conductive layer 13. The first protruding portion 342 includes two portions spaced apart from each other in the third direction y.

[0060] As shown in FIG. 4, the second power terminal 35 is located on the opposite side of the first semiconductor elements 31 from the first signal wiring 21 in the second direction x. The second power terminal 35 is spaced apart from the first power terminal 34 in the third direction y. As shown in FIG. 7, the second power terminal 35 is conductively bonded to the third conductive layer 15. As shown in FIG. 2, the second power terminal 35 is surrounded by the sealing resin 60. The second power terminal 35 is exposed from a first surface 631 of the sealing resin 60. In the semiconductor device A10, the second power terminal 35 is an N-terminal (negative electrode) to which DC power to be converted is input. The second power terminal 35 contains copper. As shown in FIG. 14, the second power terminal 35 has a second end surface 35A and a second engagement portion 351.

[0061] As shown in FIG. 14, the second end surface 35A faces the same side as the first surface 631 of the sealing resin 60 in the first direction z. The second end surface 35A is exposed from the first surface 631. The second engagement portion 351 is exposed from the first surface 631. As shown in FIG. 2, the second engagement portion 351 is surrounded by the second end surface 35A as viewed in the first direction z. As viewed in the first direction z, the area of ​​the second end surface 35A is larger than the area of ​​the second engagement portion 351. The second engagement portion 351 opens from the second end surface 35A. The second engagement portion 351 extends in the first direction z. The second engagement portion 351 penetrates in the first direction z.

[0062] As shown in FIG. 4 , the third power terminal 36 is located on the opposite side of the second signal wiring 22 from the second semiconductor elements 32 in the second direction x. As shown in FIGS. 6 and 7 , the third power terminal 36 is conductively bonded to the third layer 141 of the second conductive layer 14. This allows the third power terminal 36 to be electrically connected to the third electrodes 321 of each of the second semiconductor elements 32. As shown in FIG. 2 , the third power terminal 36 is surrounded by a sealing resin 60. The third power terminal 36 is exposed from a third surface 633 of the sealing resin 60. AC power converted by the first semiconductor elements 31 and the second semiconductor elements 32 is output from the third power terminal 36. The third power terminal 36 contains copper. As shown in FIG. 15 , the third power terminal 36 has a third end surface 36A and a third engagement portion 361.

[0063] As shown in FIG. 15, the third end face 36A faces the same side as the third surface 633 of the sealing resin 60 in the first direction z. The third end face 36A is exposed from the third surface 633. The third engagement portion 361 is exposed from the third surface 633. As shown in FIG. 2, the third engagement portion 361 is surrounded by the third end face 36A as viewed in the first direction z. The area of ​​the third end face 36A is larger than the area of ​​the third engagement portion 361 as viewed in the first direction z. The third engagement portion 361 opens from the third end face 36A. The third engagement portion 361 extends in the first direction z. The third engagement portion 361 penetrates in the first direction z.

[0064] As shown in FIG. 6 , the first conductive member 37 is located on the opposite side of the first conductive layer 13 with respect to the multiple first semiconductor elements 31. The first conductive member 37 is spaced apart from the first conductive layer 13. The first conductive member 37 is a metal clip. The first conductive member 37 contains copper. The first conductive member 37 is covered with a sealing resin 60. As shown in FIGS. 3 and 8 , one side of the first conductive member 37 in the second direction x is conductively bonded to the second electrodes 312 of each of the multiple first semiconductor elements 31 via a bonding layer 39. This allows the first conductive member 37 to be electrically connected to the second electrodes 312 of each of the multiple first semiconductor elements 31. The other side of the first conductive member 37 is conductively bonded to the second mounting surface 14A of the second conductive layer 14 (fourth layer 142) via the bonding layer 39. As a result, the first conductive member 37 is electrically connected to the third electrode 321 of each of the multiple second semiconductor elements 32. Therefore, the second electrode 312 of each of the multiple first semiconductor elements 31 is electrically connected to the third electrode 321 of each of the multiple second semiconductor elements 32.

[0065] As shown in FIG. 7 , the second conductive member 38 is located on the opposite side of the second semiconductor elements 32 from the second conductive layer 14. The second conductive member 38 is spaced apart from the first conductive layer 13 and the first conductive member 37. The second conductive member 38 is a metal clip. The second conductive member 38 contains copper. The second conductive member 38 is covered with a sealing resin 60. As shown in FIGS. 3 and 9 , one side of the second conductive member 38 in the second direction x is conductively bonded to the fourth electrodes 322 of each of the second semiconductor elements 32 via a bonding layer 39. This allows the second conductive member 38 to be electrically connected to the fourth electrodes 322 of each of the second semiconductor elements 32. The other side of the second conductive member 38 is conductively bonded to the third conductive layer 15 via the bonding layer 39. This allows the second conductive member 38 to be electrically connected to the third power terminal 36. Therefore, the third power terminal 36 is electrically connected to the fourth electrode 322 of each of the plurality of second semiconductor elements 32 .

[0066] As shown in FIG. 4 , the first signal terminal 41 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the first wiring layer 213 of the first signal wiring 21. This electrically connects the first signal terminal 41 to the first wiring layer 213. A gate voltage for driving the multiple first semiconductor elements 31 is applied to the first signal terminal 41. The first signal terminal 41 is a metal pin extending in the first direction z. As shown in FIG. 10 , a portion of the first signal terminal 41 protrudes from the second surface 632 of the sealing resin 60. As shown in FIG. 2 , the first signal terminal 41 overlaps one of the multiple first housing portions 632A of the sealing resin 60 when viewed in the first direction z.

[0067] As shown in FIGS. 4 and 8, each of the multiple first wires 51 is conductively bonded to the first gate electrode 313 of each of the multiple first semiconductor elements 31 and the first wiring layer 213 of the first signal wiring 21. As a result, the first signal terminal 41 is electrically connected to the first gate electrode 313 of each of the multiple first semiconductor elements 31. As shown in FIG. 6, the multiple first wires 51 are covered with a sealing resin 60. The composition of the multiple first wires 51 includes gold (Au). Alternatively, the composition of the multiple first wires 51 may include either aluminum (Al) or copper.

[0068] As shown in FIG. 4, the second signal terminal 42 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the second wiring layer 223 of the second signal wiring 22. This electrically connects the second signal terminal 42 to the second wiring layer 223. A gate voltage for driving the multiple second semiconductor elements 32 is applied to the second signal terminal 42. The second signal terminal 42 is a metal pin that extends in the first direction z. As shown in FIG. 11, a portion of the second signal terminal 42 protrudes from the fourth surface 634 of the sealing resin 60. As shown in FIG. 2, the second signal terminal 42 overlaps one of the multiple second housing portions 634A of the sealing resin 60 when viewed in the first direction z.

[0069] As shown in FIGS. 4 and 9, each of the multiple second wires 52 is conductively bonded to the second gate electrode 323 of each of the multiple second semiconductor elements 32 and the second wiring layer 223 of the second signal wiring 22. This allows the second signal terminal 42 to be electrically connected to the second gate electrode 323 of each of the multiple second semiconductor elements 32. As shown in FIG. 6, the multiple second wires 52 are covered with a sealing resin 60. The composition of the multiple second wires 52 includes gold. Alternatively, the composition of the multiple second wires 52 may include either aluminum or copper.

[0070] As shown in FIG. 4 , the third signal terminal 43 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the third wiring layer 214 of the first signal wiring 21. This electrically connects the third signal terminal 43 to the third wiring layer 214. A voltage having the same potential as the voltage applied to the two first detection electrodes 314 of each of the multiple first semiconductor elements 31 is applied to the third signal terminal 43. The third signal terminal 43 is a metal pin extending in the first direction z. As shown in FIG. 10 , a portion of the third signal terminal 43 protrudes from the second surface 632 of the sealing resin 60. As shown in FIG. 2 , the third signal terminal 43 overlaps one of the multiple first housing portions 632A of the sealing resin 60 when viewed in the first direction z.

[0071] 4, each of the multiple third wires 53 is conductively bonded to one of the two first detection electrodes 314 of each of the multiple first semiconductor elements 31 and to the third wiring layer 214 of the first signal wiring 21. As a result, the third signal terminal 43 is electrically connected to one of the two first detection electrodes 314 of each of the multiple first semiconductor elements 31. The multiple third wires 53 are covered with a sealing resin 60. The composition of the multiple third wires 53 includes gold. Alternatively, the composition of the multiple third wires 53 may include either aluminum or copper.

[0072] As shown in FIG. 4 , the fourth signal terminal 44 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the fourth wiring layer 224 of the second signal wiring 22. This electrically connects the fourth signal terminal 44 to the fourth wiring layer 224. A voltage having the same potential as the voltage applied to the two second detection electrodes 324 of each of the multiple second semiconductor elements 32 is applied to the fourth signal terminal 44. The fourth signal terminal 44 is a metal pin extending in the first direction z. As shown in FIG. 11 , a portion of the fourth signal terminal 44 protrudes from the fourth surface 634 of the sealing resin 60. As shown in FIG. 2 , the fourth signal terminal 44 overlaps one of the multiple second housing portions 634A of the sealing resin 60 when viewed in the first direction z.

[0073] 4, each of the multiple fourth wires 54 is conductively bonded to one of the two second detection electrodes 324 of each of the multiple second semiconductor elements 32 and to the fourth wiring layer 224 of the second signal wiring 22. As a result, the fourth signal terminal 44 is electrically connected to one of the two second detection electrodes 324 of each of the multiple second semiconductor elements 32. The multiple fourth wires 54 are covered with a sealing resin 60. The composition of the multiple fourth wires 54 includes gold. Alternatively, the composition of the multiple fourth wires 54 may include either aluminum or copper.

[0074] As shown in FIGS. 4 and 13 , the two fifth signal terminals 45 are individually press-fitted into two of the multiple sleeves 29 that are conductively bonded to the two fifth wiring layers 215 of the first signal wiring 21. As a result, the two fifth signal terminals 45 are individually electrically connected to the two fifth wiring layers 215. As the temperature of the semiconductor device A10 rises, when the two thermistors 33 that are conductively bonded to the two fifth wiring layers 215 become conductive, the two fifth signal terminals 45 become mutually electrically connected. As shown in FIG. 10 , a portion of each of the two fifth signal terminals 45 protrudes from the second surface 632 of the sealing resin 60. As shown in FIG. 2 , when viewed in the first direction z, the two fifth signal terminals 45 individually overlap two of the multiple first housing portions 632A of the sealing resin 60.

[0075] As shown in FIGS. 4 and 15 , the two sixth signal terminals 46 are individually press-fitted into two of the multiple sleeves 29 that are conductively bonded to the two sixth wiring layers 225 of the second signal wiring 22. As a result, the two sixth signal terminals 46 are individually electrically connected to the two sixth wiring layers 225. As the temperature of the semiconductor device A10 rises, when the two thermistors 33 that are conductively bonded to the two sixth wiring layers 225 become conductive, the two sixth signal terminals 46 become mutually electrically connected. As shown in FIG. 11 , a portion of each of the two sixth signal terminals 46 protrudes from the fourth surface 634 of the sealing resin 60. As shown in FIG. 2 , when viewed in the first direction z, the two sixth signal terminals 46 individually overlap two of the multiple second housing portions 634A of the sealing resin 60.

[0076] As shown in FIG. 4, the seventh signal terminal 47 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the seventh wiring layer 216 of the first signal wiring 21. This electrically connects the seventh signal terminal 47 to the seventh wiring layer 216. A voltage having the same potential as that applied to the first conductive layer 13 is applied to the seventh signal terminal 47. The seventh signal terminal 47 is a metal pin extending in the first direction z. As shown in FIG. 10, a portion of the seventh signal terminal 47 protrudes from the second surface 632 of the sealing resin 60. As shown in FIG. 2, the seventh signal terminal 47 overlaps one of the multiple first housing portions 632A of the sealing resin 60 when viewed in the first direction z.

[0077] 4, the fifth wire 55 is conductively bonded to the seventh wiring layer 216 of the first signal wiring 21 and the first mounting surface 13A of the first conductive layer 13 (second layer 132). As a result, the seventh signal terminal 47 is electrically connected to the first conductive layer 13. The fifth wire 55 is covered with a sealing resin 60. The composition of the fifth wire 55 includes gold. Alternatively, the composition of the fifth wire 55 may include either aluminum or copper.

[0078] As shown in FIG. 4, the eighth signal terminal 48 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the eighth wiring layer 226 of the second signal wiring 22. This electrically connects the eighth signal terminal 48 to the eighth wiring layer 226. A voltage having the same potential as that applied to the second conductive layer 14 is applied to the eighth signal terminal 48. The eighth signal terminal 48 is a metal pin extending in the first direction z. As shown in FIG. 11, a portion of the eighth signal terminal 48 protrudes from the fourth surface 634 of the sealing resin 60. As shown in FIG. 2, the eighth signal terminal 48 overlaps one of the multiple second housing portions 634A of the sealing resin 60 when viewed in the first direction z.

[0079] 4, the sixth wire 56 is conductively bonded to the eighth wiring layer 226 of the second signal wiring 22 and the second mounting surface 14A of the second conductive layer 14 (fourth layer 142). As a result, the eighth signal terminal 48 is electrically connected to the second conductive layer 14. The sixth wire 56 is covered with a sealing resin 60. The composition of the sixth wire 56 includes gold. Alternatively, the composition of the sixth wire 56 may include either aluminum or copper.

[0080] As shown in FIGS. 2 and 12, the sealing resin 60 has a first restriction surface 641, a second restriction surface 642, a third restriction surface 643, a fourth restriction surface 644, a first recess 65, a second recess 66, and a third recess 67.

[0081] 12 and 13, the first restricting surface 641 rises from the first surface 631 of the sealing resin 60. The first restricting surface 641 faces the side where the first power terminals 34 are located, with the plurality of first semiconductor elements 31 as the reference in the second direction x. The second surface 632 of the sealing resin 60 is located on the opposite side of the first surface 631 with the first restricting surface 641 as the reference in the second direction x. The first restricting surface 641 includes a portion located on the opposite side of the first surface 631 with the second surface 632 as the reference in the first direction z.

[0082] 12 and 14, the second restricting surface 642 rises from the first surface 631 of the sealing resin 60. The second restricting surface 642 faces the side where the first power terminal 34 is located with the second power terminal 35 as the reference in the third direction y. The second restricting surface 642 is located between the first power terminal 34 and the second power terminal 35 in the third direction y.

[0083] 2 and 15 , the third restriction surface 643 rises from the third surface 633 of the sealing resin 60. The third restriction surface 643 faces the side where the third power terminals 36 are located, with the plurality of second semiconductor elements 32 as the reference in the second direction x. The fourth surface 634 of the sealing resin 60 is located on the opposite side of the third surface 633 with the third restriction surface 643 as the reference in the second direction x. The third restriction surface 643 includes a portion located on the opposite side of the third surface 633 with the fourth surface 634 as the reference in the first direction z.

[0084] 12 and 14, the fourth restriction surface 644 rises from the first surface 631 of the sealing resin 60. The fourth restriction surface 644 faces the side where the second power terminal 35 is located with respect to the first power terminal 34 in the third direction y. The fourth restriction surface 644 is located between the second restriction surface 642 and the second power terminal 35 in the third direction y.

[0085] 13, the first recess 65 is recessed from the second surface 632 of the sealing resin 60. As shown in Fig. 12, the first recess 65 is located between the first signal terminal 41 and the first and second power terminals 34, 35 in the second direction x. The first recess 65 extends in the third direction y.

[0086] As shown in Fig. 14, the second recess 66 is recessed in the first direction z from the side where the first surface 631 of the sealing resin 60 is located. As shown in Fig. 12, the second recess 66 is located between the second restriction surface 642 and the second power terminal 35 in the third direction y. The second recess 66 extends in the second direction x. The second recess 66 is connected to the first recess 65.

[0087] 15, the third recess 67 is recessed from the fourth surface 634 of the sealing resin 60. As shown in Fig. 2, the third recess 67 is located between the second signal terminal 42 and the third power terminal 36 in the second direction x. The third recess 67 extends in the third direction y.

[0088] As shown in FIG. 2 , the multiple external connection members 71 are individually conductively connected to the first power terminal 34, the second power terminal 35, and the third power terminal 36. The multiple external connection members 71 include, for example, bus bars. Each of the multiple external connection members 71 is conductively connected to one of the first power terminal 34, the second power terminal 35, and the third power terminal 36 via a fastening member 72. The fastening member 72 is, for example, a bolt. As shown in FIG. 13 , in the external connection member 71 conductively connected to the first power terminal 34, the fastening member 72 is threadedly engaged with the first engagement portion 341 of the first power terminal 34. The external connection member 71 contacts the first end face 34A of the first power terminal 34.

[0089] As shown in FIGS. 6 and 7, the heat dissipation member 81 is bonded to the first heat dissipation layer 16 and the second heat dissipation layer 17 via a bonding layer 83. The heat dissipation member 81 is used to cool the semiconductor device A10. The heat dissipation member 81 contains metal. The heat dissipation member 81 is made of a material containing aluminum, for example. The bonding layer 83 contains a sintered body of metal particles. The metal particles contain silver. Alternatively, the metal particles may contain copper. The bottom surface 62 of the sealing resin 60 is in contact with the heat dissipation member 81.

[0090] Next, a semiconductor module B according to an embodiment of the present disclosure will be described with reference to Figures 16 and 17. The semiconductor module B includes a plurality of semiconductor devices A10.

[0091] 16 and 17, in the semiconductor module B, the multiple semiconductor devices A10 are arranged in the third direction y. The heat dissipation members 81 of the multiple semiconductor devices A10 are integrated. At the same time, the sealing resins 60 of the multiple semiconductor devices A10 are also integrated. For convenience of explanation, the sealing resins 60 of the integrated multiple semiconductor devices A10 are referred to as a sealing body 82. The sealing body 82 is in contact with the heat dissipation members 81.

[0092] 16 and 17, the sealing body 82 has two openings 821. Each of the two openings 821 opens from the side opposite to the side on which the heat dissipation member 81 is located, with the base material 10 of each of the multiple semiconductor devices A10 as a reference in the first direction z. When viewed in the first direction z, each of the two openings 821 is located between the base material 10 of each of two adjacent semiconductor devices A10 among the multiple semiconductor devices A10. In the semiconductor module B, each of the two openings 821 penetrates in the first direction z. The heat dissipation member 81 is exposed from each of the two openings 821.

[0093] In the semiconductor module B, the heat dissipation member 81 has a flat plate shape. In addition, the heat dissipation member 81 may be provided with fins or the like for improving heat dissipation on the side opposite to the side on which the base materials 10 of the plurality of semiconductor devices A10 are located in the first direction z.

[0094] Next, the effects of the semiconductor device A10 will be described.

[0095] The semiconductor device A10 includes a base material 10 including a first conductive layer 13, a first semiconductor element 31, a first power terminal 34, and a sealing resin 60. The first power terminal 34 is exposed from a first surface 631 of the sealing resin 60 and is surrounded by the sealing resin 60 as viewed in the first direction z. The sealing resin 60 has a first restricting surface 641 rising from the first surface 631. The first restricting surface 641 faces the side of the first power terminal 34 relative to the first semiconductor element 31 in the second direction x. With this configuration, when conductively joining an external connection member 71 to the first power terminal 34, as shown in FIG. 13 , the external connection member 71 is brought into contact with the first restricting surface 641, which facilitates positioning of the external connection member 71 relative to the first power terminal 34 in the second direction x. Therefore, with this configuration, the semiconductor device A10 can more easily position the external connection member 71 relative to the first power terminal 34.

[0096] The semiconductor device A10 further includes a first signal terminal 41 that is electrically connected to the first semiconductor element 31. A portion of the first signal terminal 41 protrudes from the second surface 632 of the sealing resin 60. The first restriction surface 641 includes a portion that is located on the opposite side of the first surface 631 from the second surface 632 in the first direction z. This configuration increases the creepage distance (the distance along the surface of the sealing resin 60) of the sealing resin 60 from the first power terminal 34 to the first signal terminal 41. This increases the dielectric strength of the semiconductor device A10.

[0097] The sealing resin 60 has a first recess 65 recessed from the second surface 632. The first recess 65 is located between the first signal terminal 41 and the first restriction surface 641 in the first direction z. This configuration increases the creepage distance of the sealing resin 60 from the first power terminal 34 to the first signal terminal 41. This further improves the dielectric strength of the semiconductor device A10.

[0098] The semiconductor device A10 further includes a second semiconductor element 32 electrically connected to the first semiconductor element 31 and a second power terminal 35 electrically connected to the second semiconductor element 32. The sealing resin 60 has a second restricting surface 642 rising from the first surface 631. The second restricting surface 642 faces the side where the first power terminal 34 is located relative to the second power terminal 35 in the third direction y, and is located between the first power terminal 34 and the second power terminal 35 in the third direction y. With this configuration, when conductively joining the external connection member 71 to the first power terminal 34, the external connection member 71 can be easily positioned relative to the first power terminal 34 in the third direction y by bringing the external connection member 71 into contact with the second restricting surface 642, as shown in FIG.

[0099] The sealing resin 60 has a second recess 66 recessed in the first direction z from the side where the first surface 631 is located. The second recess 66 is located between the second restriction surface 642 and the second power terminal 35 in the third direction y. This configuration increases the creepage distance of the sealing resin 60 from the first power terminal 34 to the second power terminal 35. This more reliably prevents leakage current from the first power terminal 34 to the second power terminal 35.

[0100] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 18 to 20. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 18 shows the first conductive member 37, the second conductive member 38, the sealing resin 60, and the heat dissipation member 81 in a transparent view. In Figure 18, the first conductive member 37, the second conductive member 38, the sealing resin 60, and the heat dissipation member 81 are each shown by imaginary lines.

[0101] In the semiconductor device A20, the configuration of the base material 10 is different from that of the semiconductor device A10.

[0102] 18 and 20, the second insulating layer 12 is connected to one side of the first insulating layer 11 in the second direction x. As shown in Figures 19 and 20, the second heat dissipation layer 17 is connected to one side of the first heat dissipation layer 16 in the second direction x.

[0103] Next, the effects of the semiconductor device A20 will be described.

[0104] The semiconductor device A20 includes a base material 10 including a first conductive layer 13, a first semiconductor element 31, a first power terminal 34, and a sealing resin 60. The first power terminal 34 is exposed from a first surface 631 of the sealing resin 60 and is surrounded by the sealing resin 60 when viewed in the first direction z. The sealing resin 60 has a first restricting surface 641 rising from the first surface 631. The first restricting surface 641 faces the side where the first power terminal 34 is located relative to the first semiconductor element 31 in the second direction x. Therefore, this configuration makes it easier to position the external connection member 71 relative to the first power terminal 34 in the semiconductor device A20 as well. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0105] In the semiconductor device A20, the second insulating layer 12 is connected to the first insulating layer 11. The second heat dissipation layer 17 is connected to the first heat dissipation layer 16. This configuration makes the distribution of heat generated from each of the first semiconductor element 31 and the second semiconductor element 32 and conducted to each of the first heat dissipation layer 16 and the second heat dissipation layer 17 more uniform. This improves the heat dissipation performance of the semiconductor device A20.

[0106] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 21 to 23. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and duplicated descriptions will be omitted. Here, Figures 21, 22, and 23 correspond to Figures 13, 14, and 15, respectively, which show the semiconductor device A10.

[0107] In the semiconductor device A30, the configurations of the first power terminal 34, the second power terminal 35, and the third power terminal 36 are different from those of the semiconductor device A10.

[0108] 21 and 22, a portion of each of the first power terminal 34 and the second power terminal 35 protrudes in the first direction z from the first surface 631 of the sealing resin 60. As shown in Fig. 23, a portion of the third power terminal 36 protrudes in the first direction z from the third surface 633 of the sealing resin 60.

[0109] Next, the effects of the semiconductor device A30 will be described.

[0110] The semiconductor device A30 includes a base material 10 including a first conductive layer 13, a first semiconductor element 31, a first power terminal 34, and a sealing resin 60. The first power terminal 34 is exposed from a first surface 631 of the sealing resin 60 and is surrounded by the sealing resin 60 when viewed in the first direction z. The sealing resin 60 has a first restricting surface 641 rising from the first surface 631. The first restricting surface 641 faces the side where the first power terminal 34 is located relative to the first semiconductor element 31 in the second direction x. Therefore, this configuration makes it easier to position the external connection member 71 relative to the first power terminal 34 in the semiconductor device A30 as well. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0111] In the semiconductor device A30, a portion of the first power terminal 34 protrudes from the first surface 631 of the sealing resin 60. This configuration ensures that the external connection member 71 is in more reliable contact with the first end surface 34A of the first power terminal 34 when conductively joining the external connection member 71 to the first power terminal 34. This prevents a decrease in the current flowing from the external connection member 71 to the first power terminal 34.

[0112] [Fourth embodiment] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 24 and 25. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 25 corresponds to Figure 6, which shows the semiconductor device A10.

[0113] In the semiconductor device A40, the configuration of the sealing resin 60 is different from that of the semiconductor device A10.

[0114] 24 and 25, the sealing resin 60 has a groove 69. The groove 69 is recessed from the top surface 61. In the second direction x, the groove 69 is located between the second surface 632 and the fourth surface 634. The groove 69 extends in the third direction y.

[0115] Next, the effects of the semiconductor device A40 will be described.

[0116] The semiconductor device A40 includes a base material 10 including a first conductive layer 13, a first semiconductor element 31, a first power terminal 34, and a sealing resin 60. The first power terminal 34 is exposed from a first surface 631 of the sealing resin 60 and is surrounded by the sealing resin 60 when viewed in the first direction z. The sealing resin 60 has a first restricting surface 641 rising from the first surface 631. The first restricting surface 641 faces the side where the first power terminal 34 is located relative to the first semiconductor element 31 in the second direction x. Therefore, this configuration makes it easier to position the external connection member 71 relative to the first power terminal 34 in the semiconductor device A40 as well. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0117] In the semiconductor device A40, the sealing resin 60 has a groove 69 recessed from the top surface 61. The groove 69 is located between the second surface 632 and the fourth surface 634 in the second direction x and extends in the third direction y. This configuration increases the creepage distance of the sealing resin 60 from the first signal terminal 41 to the second signal terminal 42 and the creepage distance of the sealing resin 60 from the first power terminal 34 to the third power terminal 36. This further improves the dielectric strength of the semiconductor device A40.

[0118] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0119] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] a substrate (10) including a first conductive layer (13); a first semiconductor element (31) bonded to one side of the first conductive layer in the first direction (z); a first power terminal (34) electrically connected to the first conductive layer and the first semiconductor element; a sealing resin (60) that covers the first semiconductor element, the sealing resin has a first surface (631) facing one side in the first direction, the first power terminal is exposed from the first surface and is surrounded by the sealing resin when viewed in the first direction; The sealing resin has a first restriction surface (641) rising from the first surface, The semiconductor device (A10) is configured such that the first restriction surface faces a side where the first power terminal is located with the first semiconductor element as a reference in a second direction (x) perpendicular to the first direction. [Appendix 2] The semiconductor device further includes a first signal terminal (41) that is electrically connected to the first semiconductor element (31), the sealing resin (60) has a second surface (632) facing the same side as the first surface (631) in the first direction (z); the second surface is located on the opposite side of the first surface with respect to the first restriction surface (641) in the second direction (x), The semiconductor device (A10) according to Appendix 1, wherein the first signal terminal is exposed from the second surface. [Appendix 3] The semiconductor device (A10) according to Appendix 2, wherein a portion of the first signal terminal (41) protrudes from the second surface (632). [Appendix 4] A semiconductor device (A10) described in Appendix 3, wherein the first control surface (641) includes a portion located on the opposite side of the first surface (632) in the first direction (z) relative to the second surface (632). [Appendix 5] The sealing resin (60) has a first recess (65) recessed from the second surface (632), The semiconductor device (A10) according to Appendix 4, wherein the first recess is located between the first signal terminal (41) and the first restriction surface (641) in the second direction (x). [Appendix 6] the sealing resin (60) has a first accommodating portion (632A) that opens from the second surface (632) and is spaced from the first recess (65); The semiconductor device (A10) according to Appendix 5, wherein the first signal terminal (41) overlaps the first housing portion when viewed in the first direction (z). [Appendix 7] The semiconductor device further includes a second semiconductor element (32) that is electrically connected to the first semiconductor element (31) and is covered with the sealing resin (60), the substrate (10) includes a second conductive layer (14) spaced apart from the first conductive layer (13) in the second direction (x), the first semiconductor element and the first power terminal (34) are conductively bonded to the first conductive layer; The semiconductor device (A10) according to Appendix 5, wherein the second semiconductor element is conductively joined to the second conductive layer. [Appendix 8] The semiconductor device further includes a second power terminal (35) that is electrically connected to the second semiconductor element (32), the second power terminal is spaced from the first power terminal (34) in a third direction (y) perpendicular to each of the first direction (z) and the second direction (x); The semiconductor device (A10) according to appendix 7, wherein the second power terminal is exposed from the first surface (631) and is surrounded by the sealing resin (60) when viewed in the first direction. [Appendix 9] The sealing resin (60) has a second restricting surface (642) rising from the first surface (631), A semiconductor device (A10) described in Appendix 8, wherein the second control surface faces the side where the first power terminal (34) is located relative to the second power terminal (35) in the third direction (y), and is located between the first power terminal and the second power terminal in the third direction. [Appendix 10] the sealing resin (60) has a second recess (66) recessed in the first direction (z) from a side where the first surface (631) is located, The semiconductor device (A10) according to Appendix 9, wherein the second recess is located between the second restriction surface (642) and the second power terminal (35) in the third direction (y). [Appendix 11] The semiconductor device (A10) according to appendix 10, wherein the second recess (66) is connected to the first recess (65). [Appendix 12] a third power terminal (36) conductively connected to the second conductive layer (14); the sealing resin (60) has a third surface (633) facing the same side as the first surface (631) in the first direction (z), the third surface is located on the opposite side of the first surface with respect to the second surface (632) in the second direction (x), The semiconductor device (A10) according to any one of appendices 9 to 11, wherein the third power terminal is exposed from the third surface and is surrounded by the sealing resin when viewed in the first direction. [Appendix 13] The sealing resin (60) has a third restriction surface (643) rising from the third surface (633), The semiconductor device (A10) according to Appendix 12, wherein the third regulation surface faces the side where the third power terminal (36) is located with the second semiconductor element (32) as a reference in the second direction (x). [Appendix 14] Further provided is a second signal terminal (42) that is electrically connected to the second semiconductor element (32), the sealing resin (60) has a fourth surface (634) facing the same side as the first surface (631) in the first direction (z), the fourth surface is located on the opposite side of the third surface with respect to the third restriction surface (643) in the second direction (x), The semiconductor device (A10) according to Appendix 13, wherein a portion of the second signal terminal protrudes from the fourth surface. [Appendix 15] the sealing resin (60) has a top surface (61) facing the same side as the first surface (631) in the first direction (z), and a groove portion (69) recessed from the top surface, the top surface is located between the second surface (632) and the fourth surface (634) in the second direction (x), The semiconductor device (A10) according to appendix 14, wherein the groove portion extends in the third direction (y). [Appendix 16] The semiconductor device (A30) according to Appendix 12, wherein a portion of each of the first power terminal (34) and the second power terminal (35) protrudes from the first surface (631). [Appendix 17] The semiconductor device (A10) according to any one of appendices 1 to 11, further comprising an external connection member (71) conductively joined to the first power terminal (34). [Appendix 18] a heat dissipation member (81); A plurality of semiconductor devices (A10), each having the same configuration as the semiconductor device described in Supplementary Note 1, The semiconductor module (B) has the base material (10) of each of the plurality of semiconductor devices joined to one side of the heat dissipation member in the first direction (z). [Appendix 19] The sealing resin (60) of each of the plurality of semiconductor devices (A10) is integrated to form a sealing body (82), the sealing body has an opening (821) that opens from the opposite side to the side on which the heat dissipation member (81) is located, with respect to the base material (10) of each of the plurality of semiconductor devices in the first direction (z), The semiconductor module (B) according to appendix 18, wherein the opening is located between the base materials of each of two adjacent semiconductor devices among the plurality of semiconductor devices when viewed in the first direction. [Appendix 20] The opening (821) penetrates in the first direction (z), 20. The semiconductor module (B) according to claim 19, wherein the heat dissipation member (81) is exposed from the opening. [Appendix 21] A semiconductor device (A10) described in Appendix 14, wherein the third control surface (643) includes a portion located on the opposite side of the third surface (633) in the first direction (z) with respect to the fourth surface (634). [Appendix 22] the sealing resin (60) has a third recess (67) recessed from the fourth surface (634), The semiconductor device (A10) according to Appendix 21, wherein the third recess is located between the second signal terminal (42) and the third restriction surface (643) in the second direction (x). [Appendix 23] the sealing resin (60) has a second accommodating portion (634A) that opens from the fourth surface (634) and is spaced from the third recess (67); The semiconductor device (A10) according to Appendix 22, wherein the second signal terminal (42) overlaps the second housing portion when viewed in the first direction (z). [Appendix 24] The semiconductor device (A30) according to appendix 16, wherein a portion of the third power terminal (36) protrudes from the third surface (633). [Appendix 25] the first conductive layer (13) includes a first layer (131) and a second layer (132) conductively bonded to one side of the first layer in the first direction (z), the first power terminal (34) is conductively bonded to the first layer; The semiconductor device (A10) according to appendix 12, wherein the first semiconductor element (31) is conductively bonded to the second layer. [Appendix 26] The semiconductor device (A10) according to Appendix 25, wherein the dimension of the second layer (132) in the first direction (z) is greater than the dimension of the first layer (131) in the first direction. [Appendix 27] The base material (10) includes a first insulating layer (11) located on the opposite side of the first semiconductor element (31) with respect to the first conductive layer (13) in the first direction (z), and a second insulating layer (12) located on the opposite side of the second semiconductor element (32) with respect to the second conductive layer (14) in the first direction, The first layer (131) is bonded to the first insulating layer, The semiconductor device (A10) according to Appendix 26, wherein the second conductive layer is bonded to the second insulating layer. [Appendix 28] The base material (10) includes a first heat dissipation layer (16) located on the opposite side of the first conductive layer (13) with respect to the first insulating layer (11) in the first direction (z), and a second heat dissipation layer (17) located on the opposite side of the second conductive layer (14) with respect to the second insulating layer (12) in the first direction, the first heat dissipation layer is bonded to the first insulating layer; the second heat dissipation layer is bonded to the second insulating layer; the sealing resin (60) has a bottom surface (62) facing the opposite side to the first surface (631) in the first direction, The semiconductor device (A10) according to Appendix 27, wherein the first heat dissipation layer and the second heat dissipation layer are exposed from the bottom surface. [Appendix 29] The second insulating layer (12) is spaced apart from the first insulating layer (11), The semiconductor device (A10) according to Appendix 28, wherein the second heat dissipation layer (17) is spaced apart from the first heat dissipation layer (16). [Appendix 30] The second insulating layer (12) is connected to the first insulating layer (11), The semiconductor device (A20) according to Appendix 28, wherein the second heat dissipation layer (17) is connected to the first heat dissipation layer (16). [Explanation of symbols]

[0120] A10 to A40: Semiconductor device B: Semiconductor module 10: Base material 11, 12: First insulating layer, second insulating layer 13: First conductive layer 13A: First mounting surface 131,132: 1st layer, 2nd layer 14: Second conductive layer 14A: Second mounting surface 141,142: 3rd layer, 4th layer 15: Third conductive layer 16,17: 1st heat dissipation layer, 2nd heat dissipation layer 21: First signal wiring 211: 1st base layer 212: 1st metal layer 213~216: 1st wiring layer, 3rd wiring layer, 5th wiring layer, 7th wiring layer 22: Second signal wiring 221:Second base layer 222: Second metal layer 223~226: 2nd wiring layer, 4th wiring layer, 6th wiring layer, 8th wiring layer 29: Sleeve 31: First semiconductor element 311,312: 1st electrode, 2nd electrode 313: First gate electrode 314: First detection electrode 32: Second semiconductor element 321,322: 3rd electrode, 4th electrode 323: Second gate electrode 324: Second detection electrode 33: Thermistor 34: 1st power terminal 34A: 1st end surface 34B, 34C: 1st circumferential surface, 2nd circumferential surface 341: First engagement part 342: 1st overhang 35: 2nd power terminal 35A: 2nd end surface 351: Second engagement portion 36: 3rd power terminal 36A: 3rd end surface 361: Third engagement part 37, 38: First conductive member, second conductive member 39: Bonding layer 41~48: 1st signal terminal ~ 8th signal terminal 51-56: 1st wire to 6th wire 60: Sealing resin 61:Top surface 62: Bottom 631~634: 1st page ~ 4th page 632A, 634A: First storage section, second storage section 641-644: 1st regulation surface to 4th regulation surface 65, 66, 67: First recess, second recess, third recess 68: Base 681: Seat 69: Groove 71: External connection member 72: Fastening member 81: Heat dissipation material 82: Sealing body 821: Opening 83: Bonding layer z,x,y: 1st direction, 2nd direction, 3rd direction

Claims

1. a substrate including a first conductive layer; a first semiconductor element bonded to one side of the first conductive layer in a first direction; a first power terminal electrically connected to the first conductive layer and the first semiconductor element; a sealing resin that covers the first semiconductor element, the sealing resin has a first surface facing one side in the first direction, the first power terminal is exposed from the first surface and is surrounded by the sealing resin when viewed in the first direction, the sealing resin has a first restriction surface rising from the first surface, The semiconductor device, wherein the first restriction surface faces a side where the first power terminal is located relative to the first semiconductor element in a second direction perpendicular to the first direction.

2. a first signal terminal electrically connected to the first semiconductor element; the sealing resin has a second surface facing the same side as the first surface in the first direction; the second surface is located on the opposite side of the first surface with respect to the first restriction surface in the second direction, The semiconductor device according to claim 1 , wherein the first signal terminal is exposed from the second surface.

3. The semiconductor device according to claim 2 , wherein a portion of said first signal terminal protrudes from said second surface.

4. The semiconductor device according to claim 3 , wherein the first restriction surface includes a portion located on the opposite side of the first surface with respect to the second surface in the first direction.

5. the sealing resin has a first recess recessed from the second surface, The semiconductor device according to claim 4 , wherein the first recess is located between the first signal terminal and the first restriction surface in the second direction.

6. the sealing resin has a first accommodating portion that is open from the second surface and is spaced from the first recess, The semiconductor device according to claim 5 , wherein the first signal terminal overlaps the first housing portion when viewed in the first direction.

7. a second semiconductor element that is electrically connected to the first semiconductor element and is covered with the sealing resin; the substrate includes a second conductive layer spaced from the first conductive layer in the second direction; the first semiconductor element and the first power terminal are conductively bonded to the first conductive layer; The semiconductor device according to claim 5 , wherein the second semiconductor element is conductively joined to the second conductive layer.

8. a second power terminal electrically connected to the second semiconductor element; the second power terminal is spaced apart from the first power terminal in a third direction perpendicular to each of the first direction and the second direction; The semiconductor device according to claim 7 , wherein the second power terminal is exposed from the first surface and is surrounded by the sealing resin when viewed in the first direction.

9. the sealing resin has a second restricting surface rising from the first surface, 9. The semiconductor device according to claim 8, wherein the second restriction surface faces the side where the first power terminal is located relative to the second power terminal in the third direction, and is located between the first power terminal and the second power terminal in the third direction.

10. the sealing resin has a second recess recessed in the first direction from a side where the first surface is located in the first direction, The semiconductor device according to claim 9 , wherein the second recess is located between the second restriction surface and the second power terminal in the third direction.

11. The semiconductor device according to claim 10 , wherein the second recess is connected to the first recess.

12. a third power terminal conductively coupled to the second conductive layer; the sealing resin has a third surface facing the same side as the first surface in the first direction; the third surface is located on the opposite side of the second surface from the first surface in the second direction, 12. The semiconductor device according to claim 9, wherein the third power terminal is exposed from the third surface and is surrounded by the sealing resin when viewed in the first direction.

13. the sealing resin has a third restriction surface rising from the third surface, The semiconductor device according to claim 12 , wherein the third restriction surface faces a side where the third power terminal is located with the second semiconductor element as a reference in the second direction.

14. a second signal terminal electrically connected to the second semiconductor element; the sealing resin has a fourth surface facing the same side as the first surface in the first direction; the fourth surface is located on the opposite side of the third surface with respect to the third restriction surface in the second direction, The semiconductor device according to claim 13 , wherein a portion of said second signal terminal protrudes from said fourth surface.

15. the sealing resin has a top surface facing the same side as the first surface in the first direction and a groove portion recessed from the top surface, the top surface is located between the second surface and the fourth surface in the second direction, The semiconductor device according to claim 14 , wherein the groove extends in the third direction.

16. The semiconductor device according to claim 12 , wherein a portion of each of the first power terminal and the second power terminal protrudes from the first surface.

17. The semiconductor device according to claim 1 , further comprising an external connection member conductively joined to said first power terminal.

18. A heat dissipation member; and a plurality of semiconductor devices each having the same configuration as the semiconductor device according to claim 1; The base material of each of the plurality of semiconductor devices is joined to one side of the heat dissipation member in the first direction.

19. a sealing body is formed by integrating the sealing resins of the plurality of semiconductor devices, the sealing body has an opening that opens from an opposite side to a side on which the heat dissipation member is located with respect to the base material of each of the plurality of semiconductor devices in the first direction, The semiconductor module according to claim 18 , wherein the opening is located between the base materials of each of two adjacent semiconductor devices among the plurality of semiconductor devices when viewed in the first direction.

20. The opening penetrates in the first direction, The semiconductor module according to claim 19 , wherein the heat dissipation member is exposed from the opening.

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