Semiconductor device

Abstract

To provide a semiconductor device capable of reducing thermal stress acting on an insulating substrate.SOLUTION: A semiconductor device includes a substrate 50, 60, a semiconductor element 40, and a resin molding 30. The insulating base material 51, 61 of the substrate 50, 60 has an exposed surface 511, 611 exposed from a patterned surface metal body 52, 62. The semiconductor device includes a brittle layer 101 laminated on at least a part of the exposed surface 511, 611 and interposed between the insulating base material 51, 61 and the resin molding 30, the brittle layer 101 having a lower yield point than the insulating base material 51, 61.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a substrate having wiring arranged on the surface of an insulating layer (insulating base material) and a heat dissipation layer arranged on the back surface of the insulating layer, a semiconductor element connected to the wiring, and a resin molded body that encapsulates the substrate and the semiconductor element. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 119226 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a part of the insulating substrate is exposed from the wiring. For example, the insulating substrate is exposed between the wiring connected to the upper arm IGBT and the wiring connected to the lower arm IGBT. When the insulating substrate is made of resin, the resin molded body adheres closely to the insulating substrate, thereby ensuring an insulation distance through solid insulation.

[0005] In molding a resin molded body, a curing process such as heating is required to complete the reaction of unreacted portions. The resin molded body is completely hardened by the curing process, and the linear expansion coefficient of the resin molded body after the curing process is smaller than that before the curing process. Before the curing process, the linear expansion coefficient of the resin molded body is larger than that of the insulating substrate containing the wiring and resin. Therefore, when the resin temperature drops before the curing process, i.e., when the resin molded body shrinks, thermal stress may concentrate at the triple points of the insulating substrate, wiring, and resin molded body. Further improvements are required in semiconductor devices in terms of the above and other aspects not mentioned.

[0006] One object of the present disclosure is to provide a semiconductor device that can reduce thermal stress acting on an insulating substrate. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the disclosure includes: a substrate (50, 60) having an insulating base material (51, 61) containing a resin, a front surface metal body (52, 62) arranged on the front surface of the insulating base material and patterned, and a rear surface metal body (53, 63) arranged on the rear surface of the insulating base material; a semiconductor element (40) having a first main electrode (41) and a second main electrode (42) provided on a surface opposite to the first main electrode in the plate thickness direction, the semiconductor element (40) being electrically connected to the surface metal body; a resin molding (30) that seals the substrate and the semiconductor element; The insulating substrate has an exposed surface (511, 611) exposed from the surface metal body, The insulating substrate is provided with a brittle layer (101) laminated on at least a part of the exposed surface, interposed between the insulating substrate and the resin molded body, and having a lower yield point than the insulating substrate.

[0008] According to the disclosed semiconductor device, the fragile layer undergoes large deformation beyond the yield point, that is, plastic deformation, thereby reducing the thermal stress acting on the insulating substrate.

[0009] A semiconductor device according to one aspect of the disclosure includes: a substrate (50, 60) having an insulating base material (51, 61) containing a resin, a front surface metal body (52, 62) arranged on the front surface of the insulating base material and patterned, and a rear surface metal body (53, 63) arranged on the rear surface of the insulating base material; a semiconductor element (40) having a first main electrode (41) and a second main electrode (42) provided on a surface opposite to the first main electrode in the plate thickness direction, the semiconductor element (40) being electrically connected to the surface metal body; a resin molding (30) that seals the substrate and the semiconductor element; The insulating substrate has an exposed surface (511, 611) exposed from the surface metal body, The insulating substrate includes an intervening layer (101) that includes any one of polyamideimide, polyamide, and polyimide, and is laminated to at least a portion of the exposed surface and disposed between the insulating substrate and the resin molded body.

[0010] According to the disclosed semiconductor device, the intervening layer undergoes plastic deformation, thereby reducing the thermal stress acting on the insulating base material.

[0011] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims are intended to exemplarily indicate the corresponding parts of the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram showing a power conversion circuit and a drive system to which the semiconductor device according to the first embodiment is applied; [Figure 2] FIG. 1 is a perspective view showing a semiconductor device. [Figure 3] 1 is a three-dimensional cross-sectional view of a semiconductor device; [Figure 4] FIG. 1 is a cross-sectional view of a semiconductor device. [Figure 5] FIG. 2 is a plan view showing the substrate on the drain electrode side. [Figure 6] FIG. 2 is a plan view showing the substrate on the source electrode side. [Figure 7] FIG. 4 is an enlarged cross-sectional view of region VII shown in FIG. [Figure 8] FIG. 10 is a diagram showing the relationship between stress and strain for a brittle layer and an insulating substrate. [Figure 9] FIG. 2 is a cross-sectional view showing a state in which resin is filled during molding of the resin molded body. [Figure 10] FIG. 10 is an enlarged cross-sectional view of an X region shown in FIG. [Figure 11] FIG. 2 is a cross-sectional view showing shrinkage before curing treatment during molding of a resin molded body. [Figure 12] FIG. 12 is an enlarged cross-sectional view of region XII shown in FIG. [Figure 13] FIG. 10 is a cross-sectional view showing a reference example. [Figure 14] FIG. 10 is a cross-sectional view showing a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0014] (First embodiment) The semiconductor device of this embodiment is applied to, for example, a mobile body using a rotating electric machine as a drive source. Examples of the mobile body include electric vehicles such as battery electric vehicles (BEV), hybrid electric vehicles (HEV), and plug-in hybrid electric vehicles (PHEV), electric flying bodies such as drones and electric vertical take-off and landing aircraft (eVTOL), ships, construction machinery, and agricultural machinery. BEV is an abbreviation for Battery Electric Vehicle. HEV is an abbreviation for Hybrid Electric Vehicle. eVTOL is an abbreviation for electronic Vertical Take-Off and Landing aircraft. An example of application to a vehicle will be described below.

[0015] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion circuit 4.

[0016] The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. The secondary battery may be, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion circuit 4 converts power between the DC power supply 2 and the motor generator 3.

[0017] <Power conversion circuit> 1 shows an example of a power conversion circuit 4. The power conversion circuit 4 shown in FIG.

[0018] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0019] The inverter 6 is a DC-AC conversion circuit. In accordance with switching control by the control circuit, the inverter 6 converts a DC voltage into a three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0020] The inverter 6 is configured to include upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. Hereinafter, the upper arm 9H and the lower arm 9L may be simply referred to as arms 9H and 9L.

[0021] The connection point between the upper arm 9H and the lower arm 9L, i.e., the midpoint of the upper / lower arm circuit 9, is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms 9H, 9L. Each arm 9H, 9L is configured with a switching element. The number of switching elements constituting each arm 9H, 9L is not particularly limited. It may be one, or multiple (for example, two). In the case of multiple switching elements, the multiple switching elements connected in parallel to each other are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0022] The illustrated switching element is an n-channel MOSFET 11. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0023] A freewheeling diode 12 is connected in antiparallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11 or an external diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0024] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0025] The power conversion circuit 4 may include a converter. The converter is a DC-DC conversion circuit configured to be able to convert a DC voltage into a DC voltage of a different value, for example. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion circuit 4 may also include a filter capacitor. The filter capacitor is provided between the DC power supply 2 and the converter.

[0026] The power conversion circuit 4 may include a snubber circuit. The snubber circuit is connected in parallel to the upper and lower arm circuits 9. The snubber circuit reduces the inductance of the upper and lower arm circuits 9. The snubber circuit absorbs a transient high voltage, known as a switching surge, that occurs when switching elements (MOSFETs 11) that constitute the upper and lower arm circuits 9. This enables the inverter 6 to perform high-speed switching.

[0027] The power conversion circuit 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0028] The power conversion circuit 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0029] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0030] <Semiconductor device> FIG. 2 is a perspective view showing an example of a semiconductor device. FIG. 3 is a three-dimensional cross-sectional view of the semiconductor device. FIG. 3 shows a cross-section along line III-III in FIG. 2. FIG. 4 is a two-dimensional cross-sectional view corresponding to FIG. 3. FIG. 5 is a plan view showing the substrate on the drain electrode side. FIG. 6 is a plan view showing the substrate on the source electrode side. FIGS. 5 and 6 show a surface metal body. FIGS. 5 and 6 also show a semiconductor element, a conductive spacer, a joint portion, a P terminal, an N terminal, and an O terminal.

[0031] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. The X direction, Y direction, and Z direction are mutually perpendicular. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view.

[0032] The semiconductor device 20 constitutes the upper and lower arm circuits 9, i.e., the inverter 6. The illustrated semiconductor device 20 constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 20 may also be referred to as a semiconductor module, a power module, or the like. As shown in FIGS. 2 to 6 , the semiconductor device 20 includes a resin molded body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, a joint portion 75, and an external connection terminal 80.

[0033] The resin molded body 30 encapsulates some of the other elements that make up the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the resin molded body 30. The resin molded body 30 is formed using a resin material. The illustrated resin molded body 30 is molded using an epoxy resin by a transfer molding method. Such a resin molded body 30 may be referred to as a molded resin, an encapsulating resin body, or the like.

[0034] The resin molded body 30 has a generally rectangular shape in plan view. The resin molded body 30 has one surface 301, a back surface 302, and side surfaces 303, 304, 305, and 306 as surfaces forming its outer contour. The back surface 302 is the surface opposite to the one surface 301 in the Z direction. The one surface 301 and the back surface 302 are, for example, flat surfaces. The side surface 304 is the surface opposite to the side surface 303 in the Y direction. The side surface 306 is the surface opposite to the side surface 305 in the X direction.

[0035] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

[0036] The illustrated semiconductor element 40 includes the n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides of the semiconductor element 40 in the thickness direction, i.e., in the Z direction. The semiconductor element 40 has, as main electrodes, a drain electrode 41 on one side and a source electrode 42 on the back side. When the diode 12 is a parasitic diode, the source electrode 42 also serves as an anode electrode, and the drain electrode 41 also serves as a cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 41 is a main electrode on the high-potential side, and the source electrode 42 is a main electrode on the low-potential side.

[0037] The semiconductor element 40 has a generally rectangular shape in plan view. The semiconductor element 40 has a pad 43 formed on the back surface at a position different from the source electrode 42. The source electrode 42 and the pad 43 are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 41 is formed on almost the entire surface. The source electrode 42 is formed on a portion of the back surface of the semiconductor element 40. The pad 43 is an electrode for signals. The pad 43 includes a pad for a gate electrode. The illustrated pad 43 is formed at the end opposite the region where the source electrode 42 is formed in the Y direction.

[0038] The semiconductor device 20 includes a plurality of semiconductor elements 40. The plurality of semiconductor elements 40 may include a plurality of types of semiconductor elements with different specifications. As in the illustrated semiconductor device 20, all of the semiconductor elements 40 may have a common configuration. The plurality of semiconductor elements 40 include a semiconductor element 40H that constitutes an upper arm 9H and a semiconductor element 40L that constitutes a lower arm 9L. The semiconductor element 40H may be referred to as an upper arm element, and the semiconductor element 40L may be referred to as a lower arm element.

[0039] The semiconductor elements 40H, 40L are aligned in the Y direction. The semiconductor elements 40H, 40L are arranged at approximately the same position as each other in the Z direction. The drain electrodes 41 of the semiconductor elements 40H, 40L face the substrate 50. The source electrodes 42 of the semiconductor elements 40H, 40L face the substrate 60. If the number of switching elements constituting each arm 9H, 9L is, for example, two, the semiconductor device 20 includes two semiconductor elements 40H, 40L. The two semiconductor elements 40H are aligned in the X direction. Similarly, the two semiconductor elements 40L are aligned in the X direction.

[0040] The semiconductor element 40H is disposed so that the pad 43 is located on the side surface 303 side relative to the source electrode 42. The semiconductor element 40L is disposed so that the pad 43 is located on the side surface 304 side relative to the source electrode 42.

[0041] The substrates 50 and 60 are arranged to sandwich the multiple semiconductor elements 40 in the Z direction. The substrates 50 and 60 are arranged so that at least a portion of each substrate faces each other in the Z direction. The substrates 50 and 60 contain all of the multiple semiconductor elements 40 in a planar view. The substrate 50 is arranged on the drain electrode 41 side. The substrate 60 is arranged on the source electrode 42 side. The substrate 50 is electrically connected to the drain electrode 41 and provides a wiring function. The substrate 60 is electrically connected to the source electrode 42 and provides a wiring function. The substrates 50 and 60 provide a heat dissipation function that dissipates heat generated by the semiconductor elements 40.

[0042] The substrate 50 includes an insulating substrate 51, a front metal body 52, and a back metal body 53. The substrate 60 includes an insulating substrate 61, a front metal body 62, and a back metal body 63. The insulating substrates 51, 61 are resin substrates containing resin as a material. Exemplary insulating substrates 51, 61 contain epoxy resin as a material. The insulating substrate 51 electrically separates the front metal body 52 and the back metal body 53. The insulating substrate 61 electrically separates the front metal body 62 and the back metal body 63.

[0043] The front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 are provided as metal plates or metal foils. The front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 are made of a metal with good electrical and thermal conductivity, such as Cu or Al. The front surface metal bodies 52, 62 are patterned. The front surface metal bodies 52, 62 may have a plating film of Ni, Au, or the like on the metal surface. The front surface metal body 52 has a P wiring 521 and a relay wiring 522. The P wiring 521 and the relay wiring 522 are electrically separated by a predetermined gap (spacing). This gap is filled with a resin molded body 30.

[0044] The P wiring 521 is connected to the P terminal 81 and the drain electrode 41 of the semiconductor element 40H. The P wiring 521 electrically connects the P terminal 81 and the drain electrode 41 of the semiconductor element 40H. The relay wiring 522 is connected to the drain electrode 41 of the semiconductor element 40L, the joint portion 75, and the O terminal 83. The relay wiring 522 electrically connects the O terminal 83 and the drain electrode 41 of the semiconductor element 40L. The illustrated P wiring 521 has a substantially rectangular shape in plan view. The relay wiring 522 has a substantially rectangular shape in plan view. The P wiring 521 and the relay wiring 522 are arranged side by side in the Y direction.

[0045] The P terminal 81 is connected to the P wiring 521 near the end on the side surface 303 side. The O terminal 83 is connected to the relay wiring 522 near the end on the side surface 304 side. The drain electrode 41 of the semiconductor element 40H is connected to the P wiring 521 at a position closer to the relay wiring 522 than the joint of the P terminal 81. The drain electrode 41 of the semiconductor element 40L is connected to the relay wiring 522 at a position closer to the P wiring 521 than the joint of the O terminal 83. The joint portion 75 is connected to the relay wiring 522 at a position closer to the P wiring 521 than the semiconductor element 40L.

[0046] The surface metal body 62 has an N wiring 621 and a relay wiring 622. The N wiring 621 and the relay wiring 622 are electrically separated by a predetermined gap (spacing). This gap is filled with a resin molding 30. The N wiring 621 is connected to the N terminal 82 and the source electrode 42 of the semiconductor element 40L. The N wiring 621 electrically connects the N terminal 82 and the source electrode 42 of the semiconductor element 40L. The relay wiring 622 is connected to the source electrode 42 of the semiconductor element 40H and the joint part 75. The relay wiring 622 electrically connects the source electrode 42 of the semiconductor element 40H and the drain electrode 41 of the semiconductor element 40L via the joint part 75.

[0047] The illustrated N wiring 621 has a substantially U-shape in plan view. The N wiring 621 has a base extending in the X direction and a pair of extension portions that are connected to the base and extend in the Y direction from both ends of the base. The relay wiring 622 is disposed between the pair of extension portions of the N wiring 621. The relay wiring 622 has the same or similar shape as a baseball home base in a plan view. The base of the N wiring 621 and the relay wiring 622 are aligned in the Y direction. The extension portions of the N wiring 621 and the relay wiring 622 are aligned in the X direction.

[0048] The source electrode 42 of the semiconductor element 40L is connected to the base of the N wiring 621. The N terminal 82 is connected to an extended portion of the N wiring 621. The semiconductor element 40L is connected to the N wiring 621 near the end portion on the side surface 304 side. The N terminal 82 is connected to the N wiring 621 near the end portion on the side surface 303 side. The source electrode 42 of the semiconductor element 40H is connected to the relay wiring 622. The joint portion 75 is connected to the relay wiring 622 at a position closer to the base of the N wiring 621 than the semiconductor element 40H.

[0049] The back surface metal bodies 53, 63 are electrically separated from the front surface metal bodies 52, 62 by the insulating base materials 51, 61. The illustrated back surface metal bodies 53, 63 are so-called solid conductors arranged over almost the entire back surface of the insulating base materials 51, 61. The back surface metal body 53 is exposed from one surface 301 of the resin molded body 30, and the back surface metal body 63 is exposed from the back surface 302. The back surface metal body 53 is exposed substantially flush with the one surface 301. The back surface metal body 63 is exposed substantially flush with the back surface 302.

[0050] The conductive spacer 70 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the substrate 60. The conductive spacer 70 ensures a height required for electrically connecting the corresponding signal terminal 84 to the pad 43 of the semiconductor element 40, for example. The conductive spacer 70 is located midway along the electrical and thermal conduction path between the source electrode 42 of the semiconductor element 40 and the substrate 60, providing wiring and heat dissipation functions. The conductive spacer 70 includes a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a generally rectangular columnar body having approximately the same size as the source electrode 42 in a planar view.

[0051] The conductive spacers 70 may also be referred to as terminals, terminal blocks, metal blocks, etc. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the semiconductor device 20 includes two conductive spacers 70. One of the conductive spacers 70 electrically connects the source electrode 42 of the semiconductor element 40H to the relay wiring 622. The other conductive spacer 70 electrically connects the source electrode 42 of the semiconductor element 40L to the N wiring 621.

[0052] The joint portion 75 electrically connects the relay wirings 522, 622. In other words, the joint portion 75 electrically connects the upper arm 9H and the lower arm 9L. The joint portion 75 is provided between the semiconductor element 40H and the semiconductor element 40L. The joint portion 75 is disposed in the overlapping region of the relay wirings 522, 622 in a plan view. The illustrated joint portion 75 is a metal columnar body provided separately from the surface metal bodies 52, 62. The joint portion 75 extends in the Z direction. One end of the joint portion 75 is connected to the relay wiring 522, and the other end is connected to the relay wiring 622.

[0053] The joint portion 75 may be integrally connected to the surface metal bodies 52, 62. In other words, the joint portion 75 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. A part of the joint portion 75 may be provided as part of the substrate 50, and another part of the joint portion 75 may be provided as part of the substrate 60.

[0054] The external connection terminals 80 are terminals for electrically connecting the semiconductor device 20 to an external device. The external connection terminals 80 are formed using a metal material with good conductivity, such as Cu. The external connection terminals 80 are, for example, a plate material. The external connection terminals 80 are sometimes referred to as leads. The external connection terminals 80 include a P terminal 81, an N terminal 82, an O terminal 83, and a signal terminal 84. The P terminal 81, the N terminal 82, and the O terminal 83 are sometimes referred to as main terminals because they are electrically connected to main electrodes of the semiconductor element 40. The P terminal 81 and the N terminal 82 are sometimes referred to as power supply terminals.

[0055] The P terminal 81 is connected to the P wiring 521 near one end in the Y direction. A portion of the P terminal 81 is covered by the resin molding 30, and another portion protrudes outside the resin molding 30. The joint portion of the P terminal 81 with the P wiring 521 is covered by the resin molding 30. The illustrated P terminal 81 extends approximately in the Y direction. The P terminal 81 protrudes from the side surface 303. The semiconductor device 20 has two P terminals 81.

[0056] The N terminal 82 is connected to an extending portion of the N wiring 621. A portion of the N terminal 82 is covered by the resin molded body 30, and another portion protrudes outside the resin molded body 30. The junction portion of the N terminal 82 with the N wiring 621 is covered by the resin molded body 30. The illustrated N terminal 82 extends generally in the Y direction, the same direction as the P terminal 81. The N terminal 82 protrudes from the side surface 303. The semiconductor device 20 has two N terminals 82 individually connected to extending portions of the N wiring 621.

[0057] The O terminal 83 is connected to the relay wiring 522 near one end in the Y direction. A portion of the O terminal 83 is covered by the resin molded body 30, and another portion protrudes outside the resin molded body 30. The joint portion of the O terminal 83 with the relay wiring 522 is covered by the resin molded body 30. The illustrated O terminal 83 extends generally in the Y direction, in the opposite direction to the P terminal 81 and the N terminal 82. The O terminal 83 protrudes from the side surface 304.

[0058] The signal terminals 84 are electrically connected to the pads 43 of the corresponding semiconductor elements 40. The signal terminals 84 include a signal terminal connected to the pads 43 of the semiconductor element 40H and a signal terminal connected to the pads 43 of the semiconductor element 40L. The illustrated signal terminals 84 are connected to the corresponding pads 43 via bonding wires (not shown). The signal terminals 84 extend generally in the Y direction in plan view. A portion of the signal terminals 84, including the connection portion with the pads 43, is covered by the resin molded body 30, and another portion protrudes from the resin molded body 30.

[0059] The signal terminal 84 connected to the pad 43 of the semiconductor element 40H protrudes from the side surface 303 to the outside of the resin molded body 30. The P terminal 81, the N terminal 82, and the signal terminal 84 on the upper arm 9H side are aligned in the X direction. In the X direction, the N terminal 82, the P terminal 81, the signal terminal 84, the P terminal 81, and the N terminal 82 are arranged in this order. The signal terminal 84 connected to the pad 43 of the semiconductor element 40L protrudes from the side surface 304 to the outside of the resin molded body 30. The O terminal 83 and the signal terminal 84 on the lower arm 9L are aligned in the X direction. In the X direction, the O terminal 83, the signal terminal 84, and the O terminal 83 are arranged in this order.

[0060] The semiconductor device 20 includes a bonding material 90. The bonding material 90 may be solder or a sintered material. The drain electrode 41 of the semiconductor element 40 is connected to the surface metal body 52 via the bonding material 90. The source electrode 42 of the semiconductor element 40 is connected to the conductive spacer 70 via the bonding material 90. The conductive spacer 70 is connected to the surface metal body 62 via the bonding material 90. The joint portion 75 is connected to the surface metal bodies 52, 62 via the bonding material 90. The multiple bonding materials 90 may be made of a common material, or the material of some of the bonding materials 90 may be different from the material of the other bonding materials 90.

[0061] The P terminal 81, the N terminal 82, and the O terminal 83 may be connected to the corresponding surface metal bodies 52, 62 by the above-mentioned bonding material 90. The P terminal 81, the N terminal 82, and the O terminal 83 may be solid-state bonded to the corresponding surface metal bodies 52, 62. Examples of solid-state bonding include ultrasonic bonding, room-temperature bonding, friction stir bonding, diffusion bonding, and friction welding.

[0062] As described above, in the semiconductor device 20, the resin molded body 30 encapsulates the plurality of semiconductor elements 40 that constitute one phase of the upper and lower arm circuits 9. The resin molded body 30 integrally encapsulates the plurality of semiconductor elements 40, a portion of the substrate 50, a portion of the substrate 60, the plurality of conductive spacers 70, the joint portion 75, and a portion of the external connection terminals 80. The resin molded body 30 encapsulates the insulating base materials 51, 61 and the surface metal bodies 52, 62 of the substrates 50, 60.

[0063] The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface metal body 53 is exposed from the resin molded body 30, approximately flush with one surface 301. The back surface metal body 63 is exposed from the resin molded body 30, approximately flush with the back surface 302. The exposed structure of the back surface metal bodies 53 and 63 can improve heat dissipation.

[0064] <Triple point, brittle layer, roughening area> The fragile layer is also shown in Figures 5 and 6. Figure 7 is an enlarged view of region VII indicated by the dashed-dotted line in Figure 3. Figure 8 is a diagram showing the relationship between stress and strain for the fragile layer and the insulating substrate. In Figure 8, the fragile layer is indicated by a solid line, and the insulating substrate by a dashed-dotted line. For convenience, the roughened portion is omitted from Figures 2 to 6.

[0065] As shown in Figures 4, 5, and 7, the insulating base material 51 has an exposed surface 511 exposed from the surface metal body 52. ​​The exposed surface 511 has an inter-wire exposed portion 5111 and a peripheral exposed portion 5112. The inter-wire exposed portion 5111 is a portion exposed by a gap between adjacent wires. The inter-wire exposed portion 5111 is exposed by a gap between the P wiring 521 and the relay wiring 522. The peripheral exposed portion 5112 is a portion exposed from the surface metal body 52 at the peripheral edge of the insulating base material 51. The peripheral exposed portion 5112 is provided along the peripheral edge of the insulating base material 51.

[0066] As shown in Figures 4, 6, and 7, the insulating base material 61 has an exposed surface 611 exposed from the front surface metal body 62. The exposed surface 611 has an inter-wiring exposed portion 6111 and a peripheral exposed portion 6112. The inter-wiring exposed portion 6111 is a portion exposed by a gap between adjacent wirings. The inter-wiring exposed portion 6111 is exposed by a gap between the N wiring 621 and the relay wiring 622. The peripheral exposed portion 6112 is a portion exposed from the front surface metal body 62 at the peripheral edge of the insulating base material 61. The peripheral exposed portion 6112 is provided along the peripheral edge of the insulating base material 61.

[0067] 7, the semiconductor device 20 has a triple point 100 where the resin molded body 30, the insulating base material 61, and the surface metal body 62 overlap. The triple point 100 is formed by the insulating base material 61 having an exposed surface 611. The triple point 100 includes, in an inter-wiring exposed portion 6111, a triple point 100 between the resin molded body 30, the insulating base material 61, and the N wiring 621, and a triple point 100 between the resin molded body 30, the insulating base material 61, and the relay wiring 622. The triple point 100 includes, in an outer periphery exposed portion 6112, a triple point 100 between the resin molded body 30, the insulating base material 61, and the surface metal body 62 (N wiring 621).

[0068] Although not shown, the semiconductor device 20 has a triple point 100 where the resin molded body 30, the insulating base material 51, and the surface metal body 52 overlap. The triple point 100 includes the triple point 100 of the resin molded body 30, the insulating base material 51, and the P wiring 521 in the inter-wire exposed portion 5111, and the triple point 100 of the resin molded body 30, the insulating base material 51, and the relay wiring 522 in the outer periphery exposed portion 5112.

[0069] In a configuration including the triple junction 100 described above, thermal stress concentrates at the triple junction 100. The semiconductor device 20 further includes a fragile layer 101 to reduce the thermal stress acting on the triple junction 100. The fragile layer 101 is laminated on at least a portion of the exposed surfaces 511, 611 of the insulating base materials 51, 61, and is interposed between the insulating base materials 51, 61 and the resin molded body 30. The illustrated fragile layer 101 is disposed in the exposed portions 5111, 6111 between the wirings.

[0070] The fragile layer 101 is a layer that is more fragile than the insulating substrates 51 and 61. As shown in FIG. 8 , the yield stress YS1 of the fragile layer 101 is smaller than the yield stress YS2 of the insulating substrates 51 and 61. In other words, the yield point of the fragile layer 101 is lower than the yield points of the insulating substrates 51 and 61. In addition, the Young's modulus YM1 of the illustrated fragile layer 101 is smaller than the Young's modulus YM2 of the insulating substrate 61. The fragile layer 101 is formed using a material that has a lower yield point than the insulating substrates 51 and 61 and a lower Young's modulus than the insulating substrate 61. The fragile layer 101 is configured to include, for example, any one of polyamideimide, polyamide, and polyimide.

[0071] The glass transition point (Tg) of the fragile layer 101 is preferably higher than the glass transition point of the resin molded body 30. This allows the resin molded body 30 to be formed with the fragile layer 101 in a completely cured state. Therefore, the resin molded body 30 is formed in an incompletely cured state, and a decrease in the bulk strength of the fragile layer 101 due to shrinkage of the resin molded body 30 before the curing treatment can be suppressed.

[0072] The semiconductor device 20 further includes a low-adhesion portion and a high-adhesion portion having a higher adhesion force to the resin molded body 30 than the low-adhesion portion. The illustrated semiconductor device 20 includes roughened portions 54, 64 as the high-adhesion portions and non-roughened portions 55, 65 as the low-adhesion portions. The substrate 50 includes a roughened portion 54 and a non-roughened portion 55. The roughened portion 54 is a roughened portion of the upper surface of the surface metal body 52. ​​The non-roughened portion 55 is a portion of the upper surface of the surface metal body 52 that is not roughened, i.e., the portion excluding the roughened portion 54. The substrate 60 includes a roughened portion 64 and a non-roughened portion 65. The roughened portion 64 is a roughened portion of the upper surface of the surface metal body 62. The non-roughened portion 65 is a portion of the upper surface of the surface metal body 52 that is not roughened, i.e., the portion excluding the roughened portion 64. For example, the portions where the bonding material 90 is disposed are the non-roughened portions 55 and 65 .

[0073] The roughened portions 54, 64 can be formed by laser irradiation, blasting, blackening treatment, roughening plating, or the like. The illustrated roughened portions 54, 64 are roughened by laser irradiation. The roughened portions 54, 64 are obtained by irradiating a plating film formed on the surface of the surface metal body 52, 62 with a pulsed laser to form an uneven oxide film derived from the main metal constituting the plating film and having fine irregularities on the surface. As shown in FIG. 7, a similar roughened portion 71 is also provided on the side surface of the conductive spacer 70.

[0074] The roughened portion 54 is provided so as to overlap at least a portion of the inter-wiring exposed portion 6111 in a plan view in the Z direction. The roughened portion 54 is provided at a position facing the inter-wiring exposed portion 6111. Although not shown in the figure, the roughened portion 64 is provided so as to overlap at least a portion of the inter-wiring exposed portion 5111 in a plan view. The roughened portion 64 is provided at a position facing the inter-wiring exposed portion 5111. The fragile layer 101 is provided so as to face the roughened portions 54, 64 in the Z direction. The roughened portion 64 is also formed on the outer periphery of the patterned surface metal bodies 52, 62.

[0075] <Effect of vulnerable groups> Fig. 9 is a cross-sectional view showing a state in which resin is filled during molding of a resin molded body. Fig. 9 shows the state before shrinkage. Fig. 10 is an enlarged view of area X shown in Fig. 9. Fig. 11 is a cross-sectional view showing the shrinkage state before curing treatment during molding of a resin molded body. Fig. 12 is an enlarged view of area XII shown in Fig. 11. Both Fig. 9 and Fig. 11 show the state before curing treatment.

[0076] In molding the resin molded body 30, a curing process such as heating is required to complete the reaction of unreacted portions. The resin molded body 30 is completely hardened by the curing process, and the linear expansion coefficient of the resin molded body 30 after the curing process is smaller than that before the curing process. Before the curing process, the linear expansion coefficient of the resin molded body 30 is larger than that of the surface metal bodies 52, 62 (wiring) and the insulating base materials 51, 61 containing resin.

[0077] In the exemplary semiconductor device 20, the linear expansion coefficient of the resin molded body 30 after the curing treatment is 14×10 -6 / K, and the linear expansion coefficient of the resin molded body 30 before curing is 20×10 -6 / K. The linear expansion coefficient of the insulating base materials 51 and 61 is about 14×10 -6 / K, and the linear expansion coefficient of the surface metal bodies 52, 62 is 16.5×10 -6 / K.

[0078] The fragile layer 101 is formed by applying any one of polyamideimide, polyamide, and polyimide to the exposed surfaces 511, 611 of the insulating base materials 51, 61 before forming the resin molded body 30. The illustrated fragile layer 101 is formed on the inter-wiring exposed portions 5111, 6111. Then, with the fragile layer 101 formed, resin is injected into a cavity of a mold (not shown) and pressure is maintained, whereby the resin reaches every corner of the cavity as shown in FIGS. 9 and 10 . The fragile layer 101 is interposed between the resin molded body 30 and the inter-wiring exposed portions 5111, 6111 of the insulating base materials 51, 61.

[0079] As described above, before the curing process, the linear expansion coefficient of the resin molded body 30 is greater than that of the surface metal bodies 52, 62 and the insulating base materials 51, 61 containing resin. Therefore, when the temperature of the resin molded body 30 decreases after pressure holding but before the curing process, the resin molded body 30 shrinks (thermal shrinkage) in the direction of the arrows shown in FIG. 11 . Thermal stress tends to concentrate at the triple junction 100. In particular, the roughened portions 54, 64 are provided on the surfaces facing the inter-wiring exposed portions 5111, 6111. In other words, the adhesion with the resin molded body 30 is enhanced. Therefore, the tensile force due to resin shrinkage increases on the opposing side of the roughened portions 54, 64, and thermal stress tends to concentrate more at the triple junction 100.

[0080] When the resin molded body 30 shrinks, the fragile layer 101, which has a smaller Young's modulus than the insulating base materials 51 and 61, elastically deforms. The fragile layer 101 deforms significantly beyond its yield point. That is, the fragile layer 101 deforms significantly in the Z direction as shown in FIG. 12. The fragile layer 101 relieves the tensile force that accompanies the shrinkage of the resin.

[0081] Fig. 13 is a cross-sectional view showing a reference example. Fig. 13 corresponds to Fig. 12. In the semiconductor device 20R of the reference example, the fragile layer 101 is not provided on the inter-wiring exposed portion 6111. The other configurations are the same as those of the semiconductor device 20. In the configuration shown in the reference example, when the resin molded body 30 shrinks in the direction of the arrows shown in Fig. 13, thermal stress concentrates at the triple point 100. This may cause cracks, for example, to occur in the insulating base materials 51 and 61.

[0082] <Summary of the First Embodiment> The semiconductor device 20 of this embodiment includes a substrate 50, 60, a semiconductor element 40, and a resin molded body 30. The insulating base material 51, 61 of the substrate 50, 60 has an exposed surface 511, 611. The semiconductor device 20 includes a brittle layer 101 that is laminated on at least a portion of the exposed surface 511, 611 and is interposed between the insulating base material 51, 61 and the resin molded body 30, and has a lower yield point than the insulating base material 51, 61. Therefore, when the resin molded body 30 shrinks before a curing process, the brittle layer 101 deforms significantly beyond the yield point, i.e., plastically deforms. This reduces the thermal stress acting on the insulating base material 51, 61.

[0083] As shown in the example, the Young's modulus of the fragile layer 101 may be smaller than that of the insulating substrates 51, 61. Because the fragile layer 101 is softer than the insulating substrates 51, 61, thermal stress can be reduced by elastic deformation of the fragile layer 101 when the resin molded body 30 shrinks before curing. By providing the fragile layer 101 with a lower yield point and a smaller Young's modulus than the insulating substrates 51, 61, it is possible to deform in the elastic region and the plastic region, effectively reducing thermal stress acting on the insulating substrates 51, 61. Note that the Young's modulus of the fragile layer 101 may be greater than or equal to that of the insulating substrates 51, 61.

[0084] As illustrated, in a configuration in which the surface metal bodies 52, 62 have a first wiring and a second wiring arranged adjacent to the first wiring with a predetermined gap therebetween, the fragile layer 101 may be laminated on the inter-wiring exposed portions 5111, 6111 exposed by the gap. In the illustrated semiconductor device 20, for example, the P wiring 521 and the N wiring 621 correspond to the first wiring, and the relay wirings 522, 622 correspond to the second wiring.

[0085] In the exposed portions 5111, 6111 between the wires, a triple junction 100 is formed between the first wire, the insulating base material 51, 61, and the resin molded body 30, and a triple junction 100 is formed between the second wire, the insulating base material 51, 61, and the resin molded body 30. In addition, since the wires are located on both sides, stress tends to concentrate. However, by providing the fragile layer 101, it is possible to reduce the thermal stress acting on the insulating base material 51, 61 in the exposed portions 5111, 6111 between the wires.

[0086] As illustrated, the substrate may include a first substrate and a second substrate arranged to sandwich the semiconductor element 40. The first substrate may have an exposed portion between the wirings, and the second substrate may have a low-adhesion portion and a high-adhesion portion on the surface facing the first substrate. The high-adhesion portion is arranged to overlap the exposed portion between the wirings in a plan view, and has a stronger adhesion to the resin molded body than the low-adhesion portion. In the illustrated semiconductor device 20, one of the substrates 50, 60 corresponds to the first substrate, and the other corresponds to the second substrate.

[0087] As described above, if a high-adhesion portion exists on the opposing surface of the inter-wiring exposed portion, the tensile force acting on the inter-wiring exposed portion increases. However, by providing the fragile layer 101, the deformation of the fragile layer 101 can reduce the thermal stress acting on the insulating base materials 51 and 61. This can improve the insulation reliability in the semiconductor device 20 with a double-sided heat dissipation structure.

[0088] As illustrated, the high adhesion portions may be roughened portions 54, 64, and the low adhesion portions may be non-roughened portions 55, 65. In the portions where the roughened portions 54, 64 are provided, the adhesive strength with the resin molded body 30 can be increased.

[0089] As illustrated, the fragile layer 101 may contain any of polyamideimide, polyamide, and polyimide. The fragile layer 101 containing these resins has a lower yield point than the insulating base materials 51 and 61 containing epoxy resin. The fragile layer 101 also has a smaller Young's modulus than the insulating base materials 51 and 61. Therefore, the above-mentioned effects can be achieved.

[0090] The semiconductor device 20 of this embodiment includes a substrate 50, 60, a semiconductor element 40, and a resin molded body 30. The insulating base material 51, 61 of the substrate 50, 60 has an exposed surface 511, 611. The semiconductor device 20 includes an intervening layer that includes any one of polyamideimide, polyamide, and polyimide and is laminated on at least a portion of the exposed surface 511, 611 and is interposed between the insulating base material 51, 61 and the resin molded body 30. When the resin molded body 30 shrinks before a curing treatment, the intervening layer deforms significantly beyond its yield point, i.e., plastically deforms. This reduces the thermal stress acting on the insulating base material 51, 61.

[0091] <Modification> The high adhesion portion is not limited to the roughened portions 54 and 64. For example, the high adhesion portion may be a portion coated with a material that has better adhesion to the resin molded body 30 than the insulating base materials 51 and 61.

[0092] Although an example in which the high adhesion portions (roughened portions 54, 64) are provided has been shown, the present invention is not limited to this, and a configuration without the high adhesion portions may also be used.

[0093] Although an example in which the fragile layer 101 is provided on the inter-wiring exposed portions 5111, 6111 has been shown, the present invention is not limited to this. The fragile layer 101 may also be provided on the outer peripheral exposed portions 5112, 6112. For example, as shown in Fig. 14, the fragile layer 101 may be provided on both the inter-wiring exposed portions 5111, 6111 and the outer peripheral exposed portions 5112, 6112. The fragile layer 101 may also be provided on other surfaces that come into contact with the resin molded body 30.

[0094] Although an example in which semiconductor device 20 includes two substrates 50, 60 has been shown, this is not limiting. Semiconductor device 20 may also include only one substrate. For example, a configuration may be adopted in which a substrate is disposed on the drain electrode 41 side, drain electrode 41 is connected to a first wiring on the substrate, and source electrode 42 is connected to a second wiring on the substrate by a metal plate such as a clip or a bonding wire. By providing fragile layer 101 on the exposed portion between the first wiring and the second wiring, when resin molded body 30 shrinks before a curing process, fragile layer 101 deforms significantly beyond its yield point, thereby reducing the thermal stress acting on the insulating base material.

[0095] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0096] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0097] When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly on, coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, no intervening elements or layers are present. Other terms used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. That is, reference to A and / or B means at least one of A and B.

[0098] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0099] Although an example of a 2-in-1 package that provides upper and lower arm circuits 9 for one phase has been shown as the semiconductor device 20, the semiconductor device 20 is not limited to this. For example, the semiconductor device 20 may be a 1-in-1 package that provides one arm, or a 6-in-1 package.

[0100] (Disclosure of technical ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be written in a multiple dependent form, with the subsequent clause referring to the preceding clause as an alternative. Furthermore, some clauses may be written in a multiple dependent form, referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0101] <Technical philosophy 1> a substrate (50, 60) having an insulating base material (51, 61) containing a resin, a patterned front surface metal body (52, 62) disposed on the front surface of the insulating base material, and a back surface metal body (53, 63) disposed on the back surface of the insulating base material; a semiconductor element (40) having a first main electrode (41) and a second main electrode (42) provided on the surface opposite to the first main electrode in the plate thickness direction, and electrically connected to the surface metal body; a resin molding (30) that seals the substrate and the semiconductor element, The insulating substrate has an exposed surface (511, 611) exposed from the surface metal body, The semiconductor device comprises a brittle layer (101) laminated on at least a part of the exposed surface, interposed between the insulating base material and the resin molded body, and having a yield point lower than that of the insulating base material.

[0102] <Technical philosophy 2> The semiconductor device according to Technical Idea 1, wherein the Young's modulus of the fragile layer is smaller than the Young's modulus of the insulating base material.

[0103] <Technical philosophy 3> The surface metal body has a first wiring (521, 621) and a second wiring (522, 622) arranged adjacent to the first wiring with a predetermined gap therebetween, The semiconductor device according to Technical Idea 1 or 2, wherein the fragile layer is laminated on an exposed portion (5111, 6111) between wirings that is exposed by the gap, among the exposed surfaces.

[0104] <Technical philosophy 4> the substrate includes a first substrate and a second substrate disposed so as to sandwich the semiconductor element between the first substrate and the second substrate in the plate thickness direction; the first substrate has the exposed portion between the wirings, The semiconductor device described in Technical Idea 3, wherein the second substrate has a low adhesion portion (55, 65) on the surface facing the first substrate, and a high adhesion portion (54, 64) that is arranged to overlap the inter-wiring exposed portion in a planar view in the thickness direction and has a higher adhesion force to the resin molding than the low adhesion portion.

[0105] <Technical philosophy 5> The semiconductor device according to Technical Concept 4, wherein the high adhesion portion is a roughened portion and the low adhesion portion is a non-roughened portion.

[0106] <Technical philosophy 6> The semiconductor device according to any one of Technical Concepts 1 to 5, wherein the fragile layer includes any one of polyamideimide, polyamide, and polyimide. [Explanation of symbols]

[0107] 1... drive system, 2... DC power supply, 3... motor generator, 3a... winding, 4... power conversion circuit, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11... MOSFET, 12... diode, 20... semiconductor device, 30... resin molded body, 301... one surface, 302... back surface, 303, 304, 305, 306... side surface, 40, 40H, 40L... semiconductor element, 41... drain electrode, 42... source electrode, 43... pad 50,60...substrate, 51,61...insulating base material, 511,611...exposed surface, 5111,6111...exposed portion between wirings, 5112,6112...exposed outer periphery, 52,62...surface metal body, 521...P wiring, 621...N wiring, 522,622...relay wiring, 53,63...back metal body, 54,64...roughened portion, 55,65...non-roughened portion, 70...conductive spacer, 71...roughened portion, 75...joint portion, 80...external connection terminal, 81...P terminal, 82...N terminal, 83...O terminal, 84...signal terminal, 90...bonding material, 100...triple point, 101...fragile layer

Claims

1. a substrate (50, 60) having an insulating base material (51, 61) containing a resin, a patterned front surface metal body (52, 62) disposed on the front surface of the insulating base material, and a rear surface metal body (53, 63) disposed on the rear surface of the insulating base material; a semiconductor element (40) having a first main electrode (41) and a second main electrode (42) provided on a surface opposite to the first main electrode in the plate thickness direction, the semiconductor element (40) being electrically connected to the surface metal body; a resin molding (30) that seals the substrate and the semiconductor element, The insulating substrate has an exposed surface (511, 611) exposed from the surface metal body, The semiconductor device comprises a brittle layer (101) laminated on at least a part of the exposed surface, interposed between the insulating substrate and the resin molded body, and having a yield point lower than that of the insulating substrate.

2. The semiconductor device according to claim 1 , wherein the Young's modulus of the fragile layer is smaller than the Young's modulus of the insulating base material.

3. The surface metal body has a first wiring (521, 621) and a second wiring (522, 622) arranged adjacent to the first wiring with a predetermined gap therebetween, 3. The semiconductor device according to claim 1, wherein the brittle layer is laminated on an exposed portion between wirings (5111, 6111) of the exposed surface that is exposed by the gap.

4. the substrate includes a first substrate and a second substrate disposed so as to sandwich the semiconductor element between the first substrate and the second substrate in the plate thickness direction; the first substrate has the exposed portion between the wirings, 4. The semiconductor device according to claim 3, wherein the second substrate has a low-adhesion portion (55, 65) on the surface facing the first substrate, and a high-adhesion portion (54, 64) that is arranged to overlap the inter-wiring exposed portion in a planar view in the thickness direction and has a higher adhesion force to the resin molding than the low-adhesion portion.

5. The semiconductor device according to claim 4 , wherein the high adhesion portion is a roughened portion, and the low adhesion portion is a non-roughened portion.

6. 3. The semiconductor device according to claim 1, wherein the fragile layer includes any one of polyamideimide, polyamide, and polyimide.

7. a substrate (50, 60) having an insulating base material (51, 61) containing a resin, a patterned front surface metal body (52, 62) disposed on the front surface of the insulating base material, and a rear surface metal body (53, 63) disposed on the rear surface of the insulating base material; a semiconductor element (40) having a first main electrode (41) and a second main electrode (42) provided on a surface opposite to the first main electrode in the plate thickness direction, the semiconductor element (40) being electrically connected to the surface metal body; a resin molding (30) that seals the substrate and the semiconductor element, The insulating substrate has an exposed surface (511, 611) exposed from the surface metal body, The semiconductor device comprises an intervening layer (101) including any one of polyamideimide, polyamide, and polyimide, laminated to at least a portion of the exposed surface, and disposed between the insulating substrate and the resin molded body.

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