Method for modular memory device

Abstract

To provide a computing system and method for a modular memory device for improving memory pool management and an architecture.SOLUTION: A method receives a first request for generating a first logical memory space by a first control circuit of a memory device controller, allocates a first memory unit to the first logical memory space on the basis of the determination that the first memory unit is usable within a first physical address range of a first memory zone, sends a memory donation request to a second control circuit of the memory device controller on the basis of the determination that a second memory unit of the first memory zone is used, and allocates a third memory unit to the first logical memory space and to the memory space on the basis of the determination that the third memory unit of a second memory zone is usable.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to systems and methods for memory pool management in computing systems, and more particularly to modular memory pool management and architectures. [Background technology]

[0002] In the computer field, a computing system may include one or more hosts and one or more memory devices coupled (e.g., communicatively coupled) to the hosts. These computing systems have become increasingly popular, in part, as they allow many different users to share the system's computing resources. Memory requirements increase as the number of users of such systems increases and as the number and complexity of applications running on these systems increases.

[0003] This background is intended to provide context only and is not an admission that the above-referenced embodiments or concepts are prior art. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,846,002 [Patent Document 2] U.S. Patent No. 11,429,518 [Patent Document 3] U.S. Patent No. 11,733,902 [Patent Document 4] US Patent Application Publication No. 2020 / 0371692 [Patent Document 5] US Patent Application Publication No. 2020 / 0401328 [Patent Document 6] US Patent Application Publication No. 2022 / 0188034 [Non-patent literature]

[0005] [Non-Patent Document 1] Niagara:Multi-Headed CXL Memory Pool Appliance,March 7,2024,retrieved at https: / / sktechsummit.com / assets / images / file / exhibition / semiconductor / S_4,1page. [Non-patent document 2] LEE,HOKYOON,Niagara: CXL Memory Disaggregation for HPC and AI Workloads,March 7,2024,retrieved at https: / / sc23.supercomputing.org / proceedings / exhibitors_forum / exhibitor_forum_pages / exforum119.html,16pages. Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in view of the above-mentioned prior art, and an object of the present invention is to provide a system and method for a modular memory device. [Means for solving the problem]

[0007] Aspects of some embodiments of the present invention relate to computing systems and provide improved memory pool management and architecture.

[0008] In order to achieve the above object, one aspect of the present invention provides a method for memory pool management, comprising: a step of receiving a first request to create a first logical memory space by a first control circuit of a memory device controller, the first control circuit being associated with a first memory zone, and allocating the first memory unit to the first logical memory space based on the first control circuit determining that a first memory unit is available in a first physical address range of the first memory zone; and a step of sending a memory donation request by the first control circuit to a second control circuit of the memory device controller based on the first control circuit determining that a second memory unit of the first memory zone is used, the second control circuit being associated with a second memory zone, and allocating the third memory unit to the first logical memory space based on the second control circuit determining that a third memory unit of the second memory zone is available.

[0009] Determining that the first memory unit is available may include reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone, and determining that the third memory unit is available may include reading, by a memory map manager of the second control circuit, a second memory map associated with the second memory zone.

[0010] Determining that the second memory unit is in use may include reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone.

[0011] The first request to create the first logical memory space is associated with a performance target.

[0012] The method further includes determining, by the first control circuitry, that the first memory unit includes features associated with providing the performance target, and determining, by the second control circuitry, that the third memory unit includes features associated with providing the performance target.

[0013] The first memory unit may include a first memory type and the third memory unit may include a second memory type different from the first memory type.

[0014] The first control circuit may include a first controller core and a second controller core, and the first request to generate the first logical memory space may be processed by the first controller core, and the second request to generate the second logical memory space may be processed by the second controller core.

[0015] The step of allocating the first memory unit to the first logical memory space may include updating, by a first controller core of the first control circuit, a first memory map of the first control circuit to characteristics of the first memory unit.

[0016] The step of allocating the third memory unit to the first logical memory space may include updating, by a second controller core of the second control circuit, a second memory map of the second control circuit to characteristics of the third memory unit.

[0017] The third memory unit may correspond to a second physical address range separate from the first physical address range.

[0018] The method further includes receiving, by the first control circuitry, a read request for a data location associated with the first logical memory space; determining, by the first control circuitry, that the data location is located outside the first memory zone; communicating, by the first control circuitry, the read request to the second control circuitry; and reading, by a memory controller of the second control circuitry, data associated with the read request from the second memory zone.

[0019] The method further includes receiving, by the first control circuitry, a write request for a data location associated with the first logical memory space; determining, by the first control circuitry, that the data location is located outside the first memory zone; communicating, by the first control circuitry, the write request to the second control circuitry; and writing, by a memory controller of the second control circuitry, data associated with the write request to the second memory zone.

[0020] According to some other embodiments of the present invention made to achieve the above-mentioned object, a system is provided comprising: a memory device controller including a first control circuit and a second control circuit; a first memory zone including a first memory unit associated with the first control circuit and a second memory unit associated with the first control circuit; and a second memory zone including a third memory unit associated with the second control circuit.

[0021] The third memory unit may correspond to a second physical address range that is distinct from a first physical address range that corresponds to the first memory unit.

[0022] The first memory unit may include a first memory type, and the third memory unit may include a second memory type different from the first memory type.

[0023] The first control circuit may include a first crossbar circuit coupling a first control core of the first control circuit to a first memory controller associated with accessing the first memory unit and a second memory controller associated with accessing the second memory unit, and the second control circuit may include a second crossbar circuit coupling a third control core of the second control circuit to a third memory controller associated with accessing the third memory unit.

[0024] The memory device controller may be configured to receive, at the first control circuit, a first request to create a first logical memory space; allocate, by the first control circuit, the first memory unit to the first logical memory space based on the first control circuit determining that the first memory unit is available; send, by the first control circuit, a memory donation request to the second control circuit based on the first control circuit determining that the second memory unit is in use; and allocate, by the second control circuit, the third memory unit to the first logical memory space based on the second control circuit determining that the third memory unit is available.

[0025] Determining that the first memory unit is available for use may include reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone, and determining that the third memory unit is available for use may include reading, by a memory map manager of the second control circuit, a second memory map associated with the second memory zone.

[0026] The first control circuit may include a first controller core and a second controller core, and the first request to generate the first logical memory space may be processed by the first controller core, and the second request to generate the second logical memory space may be fulfilled by the second controller core.

[0027] According to some other embodiments of the present invention, there is provided an apparatus including a processing circuit associated with a first control circuit and a second control circuit, and a computer-readable medium storing instructions. When executed by the processing circuit, the instructions may cause the processing circuit to receive a request to create a first logical memory space in a first control circuit associated with a first memory zone, allocate the first memory unit to the first logical memory space based on determining that a first memory unit is available in a first physical address range of the first memory zone, send a memory donation request from the first control circuit to a second control circuit associated with a second memory zone based on determining that a second memory unit in the first memory zone is in use, and allocate a third memory unit to the first logical memory space based on determining that a third memory unit in the second memory zone is available. The third memory unit may correspond to a second physical address range separate from the first physical address range. [Effects of the Invention]

[0028] In accordance with the present invention, a system and method for a modular memory device can be provided.

[0029] In accordance with the present invention, a modular memory device includes a plurality of memory zones each controlled by a plurality of control circuits. The modular memory device is capable of selecting available memory units in each of the plurality of memory zones. A system and method for generating memory space based on the selected memory units is provided, thereby enabling the modular memory device to generate memory space with increased capacity and bandwidth. [Brief explanation of the drawings]

[0030] [Figure 1]FIG. 1 is a block diagram illustrating a system for memory pool management according to some embodiments of the present invention. [Figure 2] FIG. 2 is a block diagram illustrating the configuration of a memory device controller of a system for memory pool management according to some embodiments of the present invention. [Figure 3A] FIG. 2 is a block diagram illustrating a memory management module according to some embodiments of the present invention. [Figure 3B] FIG. 2 is a block diagram illustrating a memory space identifier according to some embodiments of the present invention. [Figure 3C] FIG. 1 illustrates a method of using a memory controller according to some embodiments of the present invention. [Figure 3D] 1 illustrates a 0th memory map according to some embodiments of the present invention. The 0th memory map may correspond to a 0th memory zone. [Figure 3E] 1 illustrates a first memory map according to some embodiments of the present invention. The 0th memory map may correspond to the first memory zone. [Figure 3F] 1 illustrates a second memory map according to some embodiments of the present invention, which may correspond to a second memory zone. [Figure 3G] FIG. 4 illustrates the relationship between memory segments, memory spaces, and memory zones associated with the maps of FIGS. 3D, 3E, and 3F. [Figure 4] FIG. 2 illustrates a distributed linear memory space associated with contiguous memory zones, according to some embodiments of the present invention. [Figure 5] 4 is a flowchart illustrating the operation of a method for creating logical memory space according to some embodiments of the present invention. [Figure 6] 1 is a flowchart illustrating the operation of a method for fulfilling a load request according to some embodiments of the present invention. [Figure 7] 1 is a flowchart illustrating the operation of a method for fulfilling a store request according to some embodiments of the present invention. [Figure 8] 1 is a flowchart illustrating the operation of a method for memory pool management according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0031] Non-limiting, non-exclusive embodiments of the present invention are hereinafter described with reference to the drawings, in which like reference symbols refer to like parts in the various drawings unless clearly indicated otherwise.

[0032] Those skilled in the art will appreciate that components in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, some components, layers, and regions of the figures may be exaggerated relative to other components, layers, and regions to improve clarity and aid in understanding of the various embodiments. Furthermore, components and portions that are common and easy to understand, but not relevant to the description of the embodiments, are not shown to facilitate a more unobtrusive view of the various embodiments of the present invention and for clarity of the description.

[0033] Aspects of the present invention and methods for realizing the same may be more easily understood with reference to one or more embodiments or drawings in the detailed description. The embodiments described below may be implemented in various different forms and are not limited to the embodiments described herein. These embodiments are examples provided so that the present invention will be thorough and complete and will fully convey the aspects of the present invention to those skilled in the art. Therefore, procedures, components, or techniques unnecessary for those skilled in the art to fully understand the aspects or technical features of the present invention may be omitted.

[0034] Unless otherwise indicated, the same reference numbers, letters, or combinations thereof, designate like components throughout the written description and drawings, and therefore, descriptions thereof will not be repeated.

[0035] In describing the present invention, for purposes of explanation, numerous specific details are set forth to provide an understanding of the various embodiments, but it will be apparent that such various embodiments may be practiced without such specific details or one or more identical configurations.

[0036] As used herein, terms such as "0th," "1st," "2nd," and "3rd" are used to describe various elements, components, regions, layers, and / or sections, but such elements, components, regions, layers, and / or sections are not limited by such terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section may be referred to as a second element, component, region, or section without departing from the concept or scope of the present invention.

[0037] When an element or component is referred to as being "on," "coupled," or "connected" to another element or component, this means that it is directly on, connected, or connected to the other element or component, or there may be one or more intermediate elements or components present. However, "directly coupled / directly coupled" means that one component is directly connected or connected to the other component without any intervening components. At the same time, expressions such as "between" and "immediately between," or "adjacent" and "directly adjacent" that describe the relationship between components should be interpreted in the same manner. Furthermore, when an element or component is referred to as being "between" two elements or components, it may be the only element or component between the two elements or components, or there may be one or more intermediate elements or components present.

[0038] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the invention. As used herein, singular forms such as "a" and "an" are intended to include the plural unless the context clearly dictates otherwise. In describing the invention, the terms "includes," "including," "have," "having," "comprises," and "comprising" are used to embody the presence of stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. As used herein, the terms "or" and "and / or" each include all possible combinations of one or more listed and associated components.

[0039] For purposes of the present invention, when providing a list of elements, expressions such as "at least one" modify the entire list of elements, and not the individual elements of the list. For example, "at least one of X, Y, or Z," "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, and ZZ).

[0040] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation, not terms of degree, and are intended to account for inherent variations in measured or calculated values ​​that may be recognized by one of ordinary skill in the art. As used herein, "about" or "approximately" means inclusive of the stated value and within a tolerance of error from the particular value that would be determined by one of ordinary skill in the art given the measurement and the error associated with measuring the particular quantity (e.g., limitations of the measurement system). For example, "about" means within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value. Additionally, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention."

[0041] When one or more embodiments are implemented differently, the order of certain steps may be performed differently than described. For example, two steps described in succession may be performed in the reverse order of that described, or may be performed simultaneously.

[0042] Any component or combination of components (e.g., any system diagram included herein) may be used to perform one or more of the operations of any flowchart included herein. Furthermore, (i) these operations are merely exemplary and may include various additional operations not explicitly addressed, and (ii) the temporal order of operations may vary.

[0043] The electronic or electrical devices according to the embodiments of the present invention described herein, and / or any other related devices or components, may be realized by using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed from a single integrated circuit (IC) chip or separate IC chips. Furthermore, the various components of these devices may be realized on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or a single substrate.

[0044] Furthermore, the various components of such devices may be processes or threads running on one or more processors of one or more computing devices, executing computer program instructions, or interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory implemented in the computing device, for example, using standard memory devices such as random access memory (RAM). The computer program instructions may also be stored on a non-transitory computer-readable medium, for example, a CD-ROM, a flash drive, or similar. However, those skilled in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices, without departing from the concept or scope of embodiments of the present invention.

[0045] Any functionality described herein, including any functionality that may be implemented in a host, device, and / or the like, or combinations thereof, may be realized in hardware, software, firmware, or any combination thereof. For example, these may include hardware and / or software combinatorial logic, sequential logic, timers, counters, registers, state machines, volatile memory such as dynamic RAM (DRAM) and / or static RAM (SRAM), non-volatile memory including flash memory, cross-grid non-volatile memory, bulk resistive change memory, phase change memory (PCM), and / or the like, and / or permanent memory such as complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), central processing units (CPUs) including complex instruction set computer (CISC) processors and / or reduced instruction set computer (RISC) processors, graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), and / or the like, that execute instructions stored in any type of memory. In some embodiments, one or more components may be implemented in a system on a chip (SoC).

[0046] Any computing device disclosed herein may be implemented in any form factor, such as 3.5-inch, 2.5-inch, 1.8-inch, M.2, Enterprise and Data Center Standard Form Factor (EDSFF), NF1, and / or the like, and using any connector configuration, such as Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), U.2, and / or the like. Any computing device disclosed herein may be implemented in whole or in part in, or in conjunction with, a server chassis, a server rack, a data room, a data center, an edge data center, a mobile data center, and / or combinations thereof.

[0047] Any of the devices disclosed herein may be implemented with a storage device implemented with any type of non-transitory storage device based on solid-state media, magnetic media, optical media, and / or the like. For example, in some embodiments, a storage device (e.g., a computational storage device) may be implemented with an SSD based on NAND (not-AND) flash memory, cross-grid non-volatile memory, bulk resistive change memory, PCM, and / or the like, or any combination thereof.

[0048] Any communication linkages and / or interfaces disclosed herein may be implemented using any type of interface and / or protocol, with one or more interconnections, one or more networks, a network of networks (e.g., the Internet), and / or the like, or any combination thereof. Examples include Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe-over-fabric (NVMe-oF), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), FibreChannel, InfiniBand, SATA, SCSI, SAS, Internet Wide Area RDMA Protocol (iWARP) and / or coherent protocols such as Compute Express Link (CXL), CXL.mem, CXL.cache, CXL.IO, and / or the like, Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), and / or the like, Advanced eXtensible Interface (AXI), and / or the like. The communication may include any generation of wireless networks including LTE, 2G, 3G, 4G, 5G, 6G, and / or the like, any generation of Wi-Fi, Bluetooth, near-field communication (NFC), and / or the like, or any combination thereof.

[0049] In some embodiments, the software stack may include a communications layer that may implement one or more communications interfaces, protocols, and / or the like, such as PCIe, NVMe, CXL, Ethernet, NVMe-oF, TCP / IP, and / or the like, to allow the host and / or applications running on the host to communicate with computing or storage devices.

[0050] Unless otherwise clearly indicated, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the concepts of the present invention belong. Terms as defined in commonly used dictionaries should further be interpreted to have a meaning consistent with the meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] As mentioned above, in the field of computers, a computing system may include one or more hosts and one or more memory devices coupled (e.g., communicatively coupled) to the hosts. The memory devices may be located within the hosts or may be located remotely from the hosts. The memory devices are used by applications running on the hosts. One or more hosts may generate memory space for use by one or more applications. Different hosts may use memory differently. For example, some hosts may require a particular capacity, particular performance, particular reliability, and / or particular availability.

[0052] Aspects of some embodiments of the present invention provide improvements to memory pool management through a modular cooperative memory architecture and corresponding mapping (eg, memory allocation) scheme.

[0053] A memory pooling solution may be integrated into a data center architecture. Aspects according to embodiments of the present invention provide a data center architecture to overcome the latency issues of some memory pooling systems.

[0054] Aspects according to some embodiments of the present invention provide memory devices with very large memory capacity, high aggregate bandwidth, and / or dynamic memory provisioning. Memory devices according to some embodiments of the present invention can overcome some of the performance issues of some memory box solutions by providing very low latency to meet some CPU latency specifications (e.g., those with latencies between 150 nanoseconds (ns) and 200 nanoseconds (ns)).

[0055] In some embodiments, the system for memory pool management includes a switchless memory box architecture.

[0056] In some embodiments, a system for memory pool management includes an improved memory controller architecture.

[0057] Aspects of some embodiments of the present invention provide a scalable architecture that supports hundreds of terabytes (TB) of memory capacity and low latency (e.g., 200 ns or less) that CPUs (e.g., existing CPUs) can handle.

[0058] Aspects of some embodiments of the present invention provide a memory device with a large memory pool having increased capacity, greater bandwidth, and improved reliability, availability, and serviceability (RAS). The memory device supports a variety of memory types and interfaces. Aspects of some embodiments of the present invention provide methods for managing the memory pool and presenting the memory pool to a host.

[0059] FIG. 1 is a block diagram illustrating a system for memory pool management according to some embodiments of the present invention.

[0060] Referring to FIG. 1, system 1 includes a memory device MD. Memory device MD is accessed by multiple hosts 100 (e.g., first host 100a through nth host 100n). In some embodiments, hosts 100 are accessed through adapters 102 (e.g., host adapters). In some embodiments, adapters 102 support CXL, CCIX, and / or similar coherence protocols. For example, adapters 102 support any suitable interconnect technology having cache coherence management features. In some embodiments, adapters 102 support double data rate (DDR), low power double data rate (LPDDR), and / or similar non-coherent memory protocols. Adapters 102 have low latency (e.g., 10 ns to 20 ns per adapter). In some embodiments, hosts 100 access memory device MD through a cache coherence protocol (e.g., CXL 2.0). If the adapter 102 has compute express link (CXL) multiple logical device (MLD) functionality or if the host 100 has multiple adapters 102, the host 100 creates multiple logical memory spaces SP (e.g., logical memory devices) from the memory device MD. In some embodiments, the operating system (OS) of a given host 100 recognizes each of the memory spaces (SP) (e.g., each logical device) as a separate non-uniform memory access (NUMA) node. In some embodiments, a process (e.g., an application on the host 100) of a given host 100 creates memory objects from one logical device or across multiple logical devices. In response to a request r from a given host 100, the memory device MD creates (e.g., dynamically creates) a given memory space SP having user-specified capacity, performance, and / or reliability.

[0061] As described in more detail below, the memory device MD includes a memory device controller 200 having a modular cooperative architecture. In some embodiments, the memory device controller 200 operates at the chassis level. For example, the memory device controller 200 provides one or more hosts 100 with access to one or more memory zones MZ across memory locations (e.g., memory regions MR within a memory component (e.g., memory circuit)). In other words, the modular cooperative architecture allows flexibility in allocating memory units MU to memory space SP at various levels, including the chassis level and the component level.

[0062] As used herein, a "memory region MR" refers to an address space (e.g., linear address space) of a memory controller within a memory zone MZ. For example, a given memory zone MZ includes one or more memory regions (e.g., one or more linear address spaces), where the one or more memory regions are managed by the memory controller of the given memory zone MZ. As used herein, a "memory unit (MU)" refers to a logically allocatable portion of a memory region MR. A memory unit MU includes various sizes and / or types. For example, a memory unit MU refers to an LBA, a 1 kB page, a 2 kB page, a 4 kB page, a big page, a block, a die, a chip (e.g., a memory chip), and / or the like. The size of a memory unit MU is configured by software. As used herein, a "memory segment (SEG)" refers to a chunk of memory allocated for a logical device from a given memory region MR. For example, a given memory segment SEG may include one or more portions of a given memory unit in a given memory zone MZ allocated to a given memory space SP, and / or may include one or more memory units MU (e.g., logical memory units) in a given memory zone MZ. For example, the third memory space SP3 includes memory segments SEG in the third memory zone MZ3 and the fourth memory zone MZ4. The fourth memory zone MZ4 includes a memory region MR. The memory region MR includes one or more memory units MU. The memory segment SEG in the fourth memory zone MZ4 includes one or more memory units MU of the memory region MR of the fourth memory zone MZ4. The first memory zone MZ1, the second memory zone MZ2, and the third memory zone MZ3 may similarly include one or more memory regions MR, one or more memory units MU, and one or more memory segments SEG associated with one or more memory spaces SP (e.g., the first memory space SP1, the second memory space SP2, and the third memory space SP3).

[0063] The memory device controller 200 includes multiple control circuits (CC) (e.g., control modules). For example, the memory device controller 200 includes first to fourth control circuits CC1 to CC4. The control circuits CC are the smallest units for configuring a memory device MD. Each control circuit CC is associated with managing a memory zone MZ (e.g., MZ1 to MZ4) of a corresponding memory pool 300. Each control circuit CC is coupled to one or more hosts 100 via a host interface IF (e.g., the host interface IF includes one or more ports). In some embodiments, the host interface IF includes a CXL port. However, the present invention is not limited thereto. For example, the host interface IF may include any appropriate port known to those skilled in the art. Each control circuit CC is coupled to the control circuits CC of one or more other memory device controllers 200 via interconnects ICT. In some embodiments, the interconnect ICT is an AXI (advanced extensible interface) or ARM (advanced RISC machine) on-chip interconnect and / or similar non-coherent interconnect. In some embodiments, the interconnect ICT may include an ARM CMN-700 (coherent mesh network-700) and / or similar coherent interconnect. In some embodiments, the interconnect ICT may include one or more of PCIe, UCIe (universal chiplet interconnect express), Marvell MoChi, and / or the like. In some embodiments, the interconnect ICT is a non-coherent interconnect that interfaces with a network (e.g., an external network coupled to the host interface IF) that provides coherence information (e.g., through a coherence network such as CXL). In some embodiments, the coherence information is not used (e.g., ignored) by system 1.

[0064] Each of the control circuits CC is coupled to a corresponding memory zone MZ to provide modularity for the memory device MD. The modularity aspect of the memory device MD enables scalability and heterogeneity by allowing the addition of control circuits CC associated with memory zones MZ that have different or similar functionality from other memory zones MZ. For example, one or more memory zones MZ (e.g., MZ1-MZ4) may have similar or different capacities, speeds, architectures, and / or similar functionality. The mapping and routing schemes provided by the multiple control circuits CC, described in more detail below, enable cooperative memory pooling for flexibility in the creation of memory space SP.

[0065] FIG. 2 is a block diagram illustrating components of a memory device controller 200 of a system for memory pool management according to some embodiments of the present invention.

[0066] Referring to FIG. 2 , the memory device MD includes a memory device controller 200 and a memory pool 300. The memory device controller 200 includes a group of control circuits CC coupled by an interconnect ICT (e.g., an on-chip interconnect). In some embodiments, the control circuits CC are the smallest unit for configuring the memory device controller 200. The number of control circuits CC varies depending on the target memory capacity and / or target performance. The control circuits CC include a processor core cluster (e.g., a controller core group of a controller core C), ports (e.g., ports of a host interface IF), memory controllers X, and a memory management module MMM including a memory map M (e.g., a memory map table managed by the memory management module MMM). The controller cores C (e.g., C1 to Cn) (also referred to as control cores) of a given controller core group share the memory controllers X (e.g., X1 to Xn) of the corresponding control circuit CC. Each of the memory controllers X manages a portion of the memory of a given memory zone MZ. In some embodiments, controller cores C of a given control circuit CC access any memory controller X of their corresponding control circuit CC through a crossbar (CB) with the same overhead. For example, the crossbar CB is a switch (e.g., a lightweight, optimized switch) with very low latency that provides each of the controller cores C of a given control circuit CC with access (e.g., equal access) to each of the memory controllers X. A given controller core C responds to a given host 100 through a port of the host interface IF to which the controller core C is dedicated. The number of controller cores C, the number of ports, and the number of memory controllers X of a core cluster of a control circuit CC can vary and are not limited to the numbers shown in FIG. 2 .

[0067] As will be described in detail below with reference to FIGS. 5, 6, and 7, the memory device controller 200 processes various requests from the host 100 coupled to one or more corresponding host interfaces IF. FIG. 5 shows an operation for creating a logical memory space SP. FIG. 6 shows an operation for performing a load request. FIG. 7 shows an operation for performing a store request. For example, the first host 100 sends a creation request r1a to the first control circuit CC1 to create a memory space SP. Any appropriate controller core C of the first control circuit CC1 processes the creation request r1a. For example, the first controller core C1 processes the creation request r1a. The first controller core C1 determines whether the first memory unit MU1 of the first memory zone MZ1 is available (e.g., not used by another memory space SP).

[0068] The first controller core C1 checks the first memory zone MZ1 before checking the adjacent memory zone MZ because the first memory zone MZ1 is the local zone (also referred to as the home zone) of the creation request r1a. For example, the home zone can provide the shortest path and latency between a given host 100 and its memory space SP, so that a given host 100 can be adapted to use memory units MU from the home zone before using memory units of an adjacent memory zone MZ. The first control circuit CC1 allocates the first memory unit MU1 to the memory space SP. For example, the first control circuit CC1 allocates the first memory unit MU1 as a portion of the memory space SP (e.g., a memory segment SEG). The first memory unit MU1 is located at a physical address within a range (e.g., a contiguous range) of physical addresses of the first memory zone MZ1. To determine whether the first memory unit MU1 is available, the first controller core C1 can check the first memory map M1 of the first control circuit CC1.

[0069] In some embodiments, memory units MU are allocated to a given memory space SP to meet a performance target. The performance target is associated with (e.g., specified in) the generation request r1a. For example, the performance target includes (e.g., points to) a latency-related characteristic (e.g., minimum latency), and a first memory unit MU1 is selected from the first memory zone MZ1 based on the first memory unit MU1's contribution to meeting the performance target. For example, the first memory unit MU1 may contribute to (e.g., provide) lower latency because it is physically adjacent to the first control circuit CC1 and / or includes (e.g., is) physical memory that is a relatively fast type of memory.

[0070] The first memory unit MU1 alone may be insufficient to satisfy the creation request r1a. The first controller core C1 determines that the first memory zone MZ1 does not have enough available memory to satisfy the creation request r1a. For example, the first controller core C1 determines whether the second memory unit MU2 will be used (e.g., whether it is unavailable) (see r1b). The first controller core C1 determines whether the second memory unit MU2 will be used based on checking the first memory map M1. The first controller core C1 sends a donation request r1c (e.g., a memory donation request) to one or more adjacent control circuits CC to find additional memory units MU to satisfy the creation request r1a. For example, the first controller core C1 of the second control circuit CC2 processes the donation request r1c and determines that the third memory unit MU3 is available. The second control circuit CC2 allocates the third memory unit MU3 to the memory space SP. For example, the second control circuit CC2 allocates the third memory unit MU3 as part of the memory space SP (e.g., a memory segment SEG). Based on the use of the memory management module MMM, each of the controller groups of the controller core C can know how much memory is available in the corresponding memory zone MZ in order to cooperate with other control circuits CC in donating memory to meet memory requests.

[0071] The third memory unit MU3 is located at a physical address within a range (e.g., a contiguous range) of physical addresses of the second memory zone MZ2. Because the first memory unit MU1 and the third memory unit MU3 are located in different memory zones MZ, they are non-contiguous with each other. For example, the third memory unit MU3 is located in a physical address range (e.g., a given memory zone MZ) that is distinct from the physical address range (e.g., a given memory region MR) of the first memory unit MU1. The memory units MU of adjacent (e.g., separated, discontiguous, and / or distant) memory zones MZ are non-contiguous, but the memory units MU within each memory zone MZ are contiguous. In some embodiments, two or more memory zones MZ have different memory unit types from each other. For example, two or more memory zones MZ may have different interface types, different latencies, and / or different other characteristics. Thus, the memory device MD allows for a heterogeneous memory space SP, even though each of the memory zones MZ includes homogeneous memory units MU within the same memory zone MZ. Thus, the memory device MD can allow flexibility in allocating the memory space SP to reach a performance target. For example, each of the controller groups of the controller core C can have knowledge of the characteristics of its local memory zone MZ and cooperate with other control circuits CC to provide heterogeneous memory. In some embodiments, the control circuits CC determine whether the corresponding memory units MU include one or more characteristics (e.g., performance characteristics) to reach a performance target. For example, the performance characteristics may include one or more of latency (e.g., average latency, minimum latency, maximum latency, latency quality of service (QoS) and / or the like), throughput (e.g., input / output (IO) operations, tokens per second and / or the like), bandwidth (e.g., gigabytes per second (GB / s) and / or the like), and / or the like.

[0072] For example, with further reference to FIG. 2 , in some embodiments, the memory pool 300 includes multiple memory zones MZ. While each of the memory zones MZ may be independently configured in terms of form factor, interface, topology, etc., the memory within the memory zones MZ is homogenous in terms of form factor and interface. For example, the memory zones MZ may accommodate various types of RAM, such as graphics double data rate (GDDR) or high bandwidth memory (HBM), and video RAM (VRAM). Furthermore, the memory zones MZ support internal memory interfaces such as DDR, synchronous dynamic random access memory (SDRAM), RDRAM (Rambus DRAM), GDDR, HBM, CXL, and others. Thus, the memory device MD may have a combination of different memory types and interfaces. In some embodiments, a given memory zone MZ may include non-volatile random access memory technologies, such as ferroelectric random access memory (FeRAM) or magnetoresistive random access memory (MRAM).

[0073] In some embodiments, a memory device MD may have a memory zone MZ based on 4-channel DDR5 SDRAM, a memory zone MZ based on 8-channel DDR4 SDRAM, a memory zone MZ based on 12 GDDR chips, and a memory zone MZ based on 6 HBM chips. Thus, to handle the diversity of memory types, the corresponding control circuit CC should have a specific memory controller X associated with the memory type and interface.

[0074] Each controller core C fulfills a different request from the host 100 (see FIG. 1). For example, while the first controller core C1 fulfills a first request (e.g., r1a) from the first host 100, the nth controller core Cn fulfills a second request (e.g., r2a) from the second host 100. Furthermore, the controller core C of the second control circuit CC2 fulfills a third request (e.g., r3a) from the third host 100 while the first controller core C1 and the nth controller core Cn fulfill the first request (e.g., r1a) and the second request (e.g., r2a), respectively.

[0075] 3A-3G (collectively, FIG. 3) are diagrams illustrating methods of configuring a memory according to some embodiments of the present invention.

[0076] Each memory map M maintains memory space information (e.g., logical device information) managed by a corresponding control circuit CC (see FIG. 2). As described above, a memory space SP is generated within a local memory zone MZ or between a local memory zone and a remote memory zone MZ. A memory device MD basically represents one linear address space (e.g., one logical memory space) (see FIG. 4). If multiple memory spaces SP are generated, each memory space SP generates one continuous linear address space (e.g., a logically continuous linear address space) from a basic address space. For example, the basic address space corresponds to the linear memory space (LMS) of the memory device MD. The memory map M is used by the corresponding control circuit CC to discover and track (e.g., manage) memory segments SEG throughout the memory device MD.

[0077] When a given host 100 creates a memory object (e.g., memory space and / or associated data), the control circuit CC for the given host 100 registers the memory object, along with capacity, performance, and RAS information, in a memory map M of the control circuit CC. When the host 100 requests a read or write associated with a memory address, the controller core C of the control circuit CC tests the request against the memory map M to determine whether the host 100 is allowed to access the memory address. If it is determined that the host 100 can access the memory address, the controller core C communicates the request to the memory controller X of the target memory zone MZ.

[0078] FIG. 3A is a block diagram illustrating a memory management module MMM according to some embodiments of the present invention.

[0079] 3A, each memory management module MMM of the memory device controller 200 manages a memory map M (e.g., a memory map table) of a corresponding control circuit CC (see FIG. 2). In some embodiments, based on receiving a creation request, a given memory management module MMM receives a device linear address DLA from the corresponding control circuit CC and / or an adjacent control circuit CC, which is associated with a memory segment SEG that the control circuit CC allocates to the memory space SP for the creation request (e.g., r1a). Based on the received device linear address DLA, the memory management module MMM records address information A (see FIGS. 3D-3F) in the memory map M (e.g., corresponding to one of M0-M2) and generates a memory space identifier ID (e.g., a logical memory device identifier) ​​based on the received device linear address DLA.

[0080] FIG. 3B is a block diagram illustrating a method for generating a memory space identifier ID according to some embodiments of the present invention.

[0081] Referring to FIG. 3B , in some embodiments, the device linear address DLA provided to the memory management module MMM includes (or is used to determine) a memory zone MZ, a sector (S), and address information A. In some embodiments, the address information A includes a start address SA and / or an end address EA associated with a given memory segment SEG corresponding to the memory zone MZ. The memory segment SEG corresponds to an address (e.g., a physical address) within the given memory zone MZ. For example, in some embodiments, if the start address SA corresponds to memory address 0 and the memory segment SEG has a length of 4 kB (e.g., 4 k pages), the end address EA is 4 kB. The memory space identifier ID is any identifier assigned to one or more memory segments SEG suitable for indicating that the memory segments SEG are associated with the same memory space SP. For example, the memory space identifier ID may be a number that increases from a previously created memory space SP. For example, a previously created memory space SP may have an identifier of 4, and a more recently created memory space SP may have an identifier of 5.

[0082] FIG. 3C is a block diagram illustrating how memory controller X may be used in accordance with some embodiments of the present invention.

[0083] 3C, in some embodiments, address information A is provided to a corresponding memory controller X (e.g., X1-Xn) to access a corresponding memory unit MU (see FIG. 2). In some embodiments, a controller core C determines which memory controller X manages the address of a given memory zone MZ associated with address information A. For example, the controller core C points to a memory map M of a control circuit CC associated with the memory zone MZ.

[0084] FIG. 3D is a diagram illustrating a 0th memory map M0 associated with a 0th memory zone MZ0 according to some embodiments of the present invention.

[0085] FIG. 3E is a diagram illustrating a first memory map M1 associated with a first memory zone MZ1 according to some embodiments of the present invention.

[0086] FIG. 3F is a diagram illustrating a second memory map M2 associated with a second memory zone MZ2 according to some embodiments of the present invention.

[0087] FIG. 3G is a diagram illustrating the relationship between memory segments SEG, memory spaces SP, and memory zones MZ associated with the maps of FIGS. 3D, 3E, and 3F, according to some embodiments of the present invention.

[0088] 3D , a given memory map M (e.g., M0) includes information for locating memory segments SEG associated with one or more memory spaces SP. For example, each memory map M includes a memory space identifier ID (e.g., a logical memory device identifier) ​​(corresponding to a particular memory space SP), information indicating a corresponding memory zone MZ (e.g., a memory zone identifier), information indicating a corresponding memory segment SEG of the memory zone MZ, and corresponding address information A (e.g., a start address SA and an end address EA). In some embodiments, each memory map M includes information related to determining performance characteristics (e.g., latency information and the like) associated with a given memory space SP.

[0089] Each memory map M indicates, for which memory space identifier ID, whether the corresponding control circuit CC is used as a local (or home) control circuit CC (e.g., a local or home control module). For example, a given control circuit CC is used as a home control circuit CC for a memory space SP created based on a request r (e.g., a creation request) provided in the given control circuit CC. In FIGS. 3D, 3E, and 3F, the memory space identifier ID is displayed in shading to indicate which control circuit CC corresponding to which memory space identifier ID is used as a local (or home) control circuit CC. In some embodiments, the memory space identifier ID (e.g., logical memory device identifier) ​​of a given memory map M associated with a local control circuit CC is defined as a column in the table of the memory map M. In FIG. 3D, rows R1-R5 indicate that the control circuit CC (e.g., the 0th control circuit CC0) including the 0th memory map M0 is used as the home control circuit CC for memory space identifier IDs ID0, ID1, and ID2. Each of the memory space identifiers IDs, ID0, ID1, ID2, ID3, ID4, and ID5, corresponds to SP0, SP1, SP2, SP3, SP4, and SP5 in FIG. 3G. Rows that are not shaded (e.g., R6 in FIG. 3D) indicate that the control circuit CC corresponding to the memory space identifier ID is used as a donation (or remote) control circuit CC. In some embodiments, the memory space identifier ID for a given memory map M associated with a remote control circuit CC is defined by a column in the table for the memory map M. For example, the 0th control circuit CC0 includes the 0th memory map M0 and is used as the donation control circuit CC for memory space identifier ID5 (e.g., SP5 in FIG. 3G). Memory space identifier ID5 is the local memory space SP of the second control circuit CC2 that includes the second memory map M2 (see FIG. 3F).

[0090] FIG. 3E is a diagram illustrating a first memory map M1 corresponding to a first memory zone MZ1 according to some embodiments of the present invention.

[0091] 3E, the information in the first memory map M1 for locating memory segments SEG associated with one or more memory spaces SP provides an example for the first control circuit CC1 associated with the first memory map M1 being used as the home control circuit CC for a different memory space SP from the zeroth control circuit CC0 associated with the zeroth memory map M0. For example, the shaded portions of rows R3-R5 indicate that the first control circuit CC1 is used as the home control circuit CC for memory space identifiers ID3 and ID4.

[0092] FIG. 3F is a diagram illustrating a memory map M2 corresponding to the second memory zone MZ2 according to some embodiments of the present invention.

[0093] 3F, the information in the second memory map M2 for locating memory segments SEG associated with one or more memory spaces SP provides an example for the second control circuit CC2 associated with the second memory map M2 being used as a home control circuit CC for the memory space SP that is different from both the zeroth control circuit CC0 and the first control circuit CC1 associated with the zeroth memory map M0 and the first memory map M1, respectively. For example, the shaded portions of rows R3-R5 indicate that the second control circuit CC2 is used as the home control circuit CC for the memory space identifier ID5.

[0094] Referring to FIG. 3G, the zeroth control circuit CC0 is used as the home control circuit CC for three logical devices—the zeroth memory space SP0, the first memory space SP1, and the second memory space SP2. The zeroth memory space SP0 includes the zeroth segment SEG0 of the zeroth memory zone MZ0, which corresponds to the start address SA of A and the end address EA of B. The first memory space SP1 spans two memory zones MZ—the first memory zone MZ1 and the second memory zone MZ2. The zeroth memory zone MZ0 is the requester (e.g., requesting) zone. The first memory zone MZ1 and the second memory zone MZ2 are donors. For example, the first memory zone MZ1 donates the zeroth segment SEG0 of the first memory zone MZ1, which corresponds to the start address SA of C and the end address EA of D. The second memory zone MZ2 donates the zeroth segment SEG0, which corresponds to the start address SA of E and the end address EA of F. The second memory space SP2 spans two memory zones, the 0th memory zone MZ0 and the 1st memory zone MZ1. The 0th memory zone MZ0 provides the second memory space SP2 with the first segment SEG1 of the 0th memory zone MZ0, which corresponds to the start address SA of G and the end address EA of H. The 1st memory zone MZ1 provides the second memory space SP2 with the first segment SEG1 of the 1st memory zone MZ1, which corresponds to the start address SA of I and the end address EA of J.

[0095] The first control circuit CC1 is used as a home control circuit CC for two logic devices—a third memory space SP3 and a fourth memory space SP4. The third memory space SP3 includes a second segment SEG2 of the first memory zone MZ1, corresponding to a start address SA of K and an end address EA of L. The fourth memory space SP4 lies between the first memory zone MZ1 and the second memory zone MZ2. The fourth memory space SP4 includes a third segment SEG3 of the first memory zone MZ1, corresponding to a start address SA of M and an end address EA of N. The fourth memory space SP4 further includes a first segment SEG1 of the second memory zone MZ2, corresponding to a start address SA of O and an end address EA of P.

[0096] The second control circuit CC2 is used as the home control circuit CC for one logical device—the fifth memory space SP5. The fifth memory space SP5 spans three memory zones MZ—the zeroth memory zone MZ0, the first memory zone MZ1, and the second memory zone MZ2. The fifth memory space SP5 includes the second segment SEG2 of the second memory zone MZ2, which corresponds to the start address SA of Q and the end address EA of R. The zeroth memory zone MZ0 donates the second segment SEG2 of the zeroth memory zone MZ0, which corresponds to the start address SA of S and the end address EA of T, to the fifth memory space SP5. The first memory zone MZ1 donates the fourth segment SEG4 of the first memory zone MZ1, which corresponds to the start address SA of U and the end address EA of V, to the fifth memory space SP5.

[0097] FIG. 4 is a diagram illustrating a scattered memory space associated with a contiguous memory region MR according to some embodiments of the present invention.

[0098] 4, in some embodiments, from a physical perspective, each memory zone MZ includes multiple channels, and each channel includes multiple memory chips. However, the present invention is not limited thereto, and the memory zone MZ may include any suitable memory type and / or architecture known to those skilled in the art.

[0099] Each memory zone MZ is viewed as a linear address space (e.g., a non-contiguous linear address space). As described above, the linear address space within a given memory zone MZ is referred to as a memory region MR. Each memory zone MZ includes one or more memory regions MR. A memory space SP (e.g., a logical device) is generated from one or more memory regions MR.

[0100] For example, a memory device MD is accessed by two hosts 100 (e.g., a first host 100a and a second host 100b). Each host 100 generates one memory space SP (e.g., SPa and SPb) from the memory device MD. The operating system of each host 100 recognizes three NUMA nodes. The three NUMA nodes include a first NUMA node for DDR memory of a given host 100 that is local to a CPU associated with the given host 100 (e.g., the first host 100a) in the server, a second NUMA node for DDR memory of another host 100 (e.g., the second host 100b) that is local to a CPU of another host 100 in the server, and a third NUMA node for a memory space SP (e.g., a CXL logical device) generated from the memory device MD.

[0101] In some embodiments, four memory devices MD are linked by an on-chip interconnect and combined to create a larger memory device (e.g., a super memory device) including four memory pools 300. Each control circuit CC includes one or more core clusters of one or more controller cores (control cores) C, one or more host interfaces IF including one or more ports (e.g., CXL 2.0 ports), one or more memory controllers X (e.g., DDR5 memory controllers), and one or more memory maps M. Each memory space SP is at least partially generated in its local memory zone MZ and registered in its memory map M. Each memory pool 300 includes four memory zones MZ. One or more (e.g., all) of the memory zones MZ are homogenous. Each memory zone MZ has four interleaved DDR5 SDRAM dual in-line memory modules (DIMMs). In such an embodiment, there is only one memory region MR within a memory zone MZ. However, the present invention is not limited to this, and each memory zone MZ may include one or more memory regions MR.

[0102] Referring again to FIG. 4, memory device MD (see FIG. 1) includes a linear memory space (e.g., a "giant" linear address space) that is visible to hosts 100 (e.g., first host 100a and second host 100b). In some embodiments, the entire memory device MD includes 128 terabytes (TB) and is therefore referred to as a giant LMS. The linear memory space of memory device MD includes multiple memory zones MZ (e.g., MZ0-MZn) that are local to memory device MD. For example, each memory zone MZ provides 32 TB of the total 128 TB. Each memory zone MZ includes its own linear memory space. For example, each memory zone MZ includes a linear address space associated with a corresponding control circuit CC. Each memory zone MZ has a different base address from the other memory zones MZ. Each memory zone MZ includes one or more memory regions MR (e.g., MR1, MR2, MR3, and MR4). For example, each memory region MR includes 8 TB of the total 32 TB. For example, each memory region MR includes a linear address space associated with a corresponding memory controller X. Memory regions MR of different memory zones MZ have the same address. A memory segment SEG is a chunk of memory and may be allocated for memory space SP from a given memory region MR. For example, a first memory region MR1 is described as including four memory segments, including SEG0, SEG1, SEG2, and SEG3. Memory segments SEG0 and SEG2 are allocated to the first host 100a. Memory segments SEG1 and SEG3 are allocated to the second host 100b. In some embodiments, the memory regions MR correspond to channels and ranks of memory chips on a DIMM. For example, a given memory region MR is a logical region corresponding to channels and ranks of memory chips on a DIMM. Because the memory zones MZ cooperatively contribute to the memory unit MU to satisfy a given production request, the memory within each of the memory zones MZ is scattered (e.g., non-contiguous), yet the memory region MR of the memory zones MZ is contiguous.

[0103] As explained in the legend at the bottom of Figure 4, memory segments SEG for the first host 100a are illustrated as blocks with diagonal lines. Memory segments SEG for the second host 100b are illustrated as blocks with horizontal lines. Portions of available memory (e.g., empty or unused memory portions) are shown without hatching patterns. In some embodiments, the physical memory addresses associated with a memory region MR of a given memory zone MZ (e.g., MZ0) comprise a linear address space, but the memory segments SEG assigned to a given memory space SP are interspersed.

[0104] FIG. 5 is a flowchart illustrating the operation of a method for generating a logical memory space SP according to some embodiments of the present invention.

[0105] As described above, the memory device controller 200 (see Figures 1 and 2) allocates memory segments SEG for requested memory space SP (e.g., logical memory space) based on requests r received from one or more hosts 100 at the host interface IF.

[0106] 5, the method 5000 includes one or more operations described below. A controller core C (e.g., a home controller core) of a first control circuit CC1 (e.g., a home control circuit) receives a creation request r1a from the host 100 via a port of the host interface IF of the first control circuit CC1 (operation 5001). For example, the home controller core C may be a controller core C dedicated to (e.g., assigned to process) the port that received the creation request r1a. The control circuit CC that received the creation request r1a is also referred to as a home control circuit CC. The first controller core C1 determines whether the first memory zone MZ1 (used as the home zone) can create the requested memory space SP as a whole (operation 5002). For example, the first controller core C1 determines whether the first memory zone MZ1 has enough units to satisfy the creation request r1a. If the first memory zone MZ1 has enough available memory units MU to satisfy the creation request (Y), the home control circuit CC (e.g., through the path of the first controller core C1) allocates available memory portions (e.g., empty or unused memory portions) of the first memory zone MZ1 as memory segments SEG to the memory space SP by updating the memory map M of the first control circuit CC1 to register (e.g., record) the memory segments SEG and their characteristics (operation 5003). The first controller core C1 first attempts to allocate memory units MU from its local memory zone MZ (e.g., the home zone) because the local memory zone MZ (e.g., the first memory zone MZ1) provides the shortest path (e.g., lowest latency) between the host 100 and the memory units MU. If the first memory zone MZ1 does not have enough available memory units MU to satisfy the creation request (N), the first controller core C1 determines whether the memory space SP should be created in cooperation with one or more other memory zones MZ (operation 5004).For example, the first memory zone MZ1 may not have enough available memory because the memory units MU are used by other memory spaces SP and / or do not have enough capacity for the requested memory space SP.

[0107] The controller core C of the home zone requests support from one or more remote (e.g., one or more neighboring) controller cores C of other memory zones MZ by sending a request r (e.g., a memory availability request) through the interconnect ICT (operation 5005). The one or more remote controller cores C send availability information to the home controller core C (e.g., the first controller core C1, which is the requesting controller core C) (operation 5006). Based on the availability information from the one or more remote controller cores C, the home controller core C determines whether there is sufficient available memory to complete the creation request r1a (operation 5007). If there is not enough available memory to complete (e.g., satisfy) the creation request r1a (N), the home controller core C returns an error to the requesting host 100 (operation 5008). If there is sufficient available memory to complete the creation request r1a (Y), the home controller core C determines which remote controller cores C will participate as donors by sending donation requests (e.g., memory donation requests) (e.g., r1c) to remote controller cores C that have available memory (operation 5009).

[0108] The controller core to be used (e.g., a selected donor controller core) (e.g., one or more controller cores C among the second control circuit CC2, the third control circuit CC3, and the fourth control circuit CC4) registers the memory segments SEG (and their characteristics) in their corresponding memory map M for the requested memory space SP. The home controller core (e.g., the first controller core C1) updates its corresponding memory map M by registering those memory segments SEG (and their characteristics) and the memory segments SEG (and their characteristics) from all other donor memory zones MZ (operation 5003). The home controller core C determines whether all memory segments SEG were successfully created (e.g., successfully registered or successfully reserved) (operation 5011). For example, all memory zones MZ send a confirmation (e.g., a notification) when their respective donated memory segments SEG are registered in their corresponding memory map M. If all memory segments SEG are successfully created (Y), the home controller core C commits the registration of the memory segments SEG to all associated memory zones MZ (operation 5012). For example, the home controller core C updates its home memory map M with the memory segments SEG from the home memory zone MZ and the memory segments SEG from any donor memory zones MZ. The home controller core C returns address information A (e.g., start address SA) of the memory space SP to the requesting host 100 via a corresponding port of the host 100 in the host interface IF (operation 5013). If all memory segments are not successfully created (N), the home controller core C returns all registrations to the associated memory zones MZ (operation 5014).

[0109] Therefore, the home controller core C (in cooperation with the donor controller core C) can create a memory space SP using multiple memory segments SEG provisioned from different memory zones MZ. All memory segments SEG are registered in the local memory map M of the home controller core C, while remote (e.g., adjacent) control circuits CC0 register the memory segments they provide to their local memory maps M. Once the memory space SP is created, the host 100 accesses the corresponding memory using a load operation (e.g., a read operation) and a store operation (e.g., a write operation).

[0110] FIG. 6 is a flowchart illustrating the operation of a method for fulfilling a load request according to some embodiments of the present invention.

[0111] 6, method 6000 includes one or more of the following operations: A first control circuit (e.g., first control circuit CC1) receives a request r (e.g., a load request, also referred to as a read request) from host 100 via a port of a host interface IF of first control circuit CC1 (6001). For example, home controller C is dedicated (assigned) to be used for the request received on the port associated with the load request. Home controller core C determines whether the address for the load request (e.g., associated with the load request) belongs to a memory zone of the home controller core (e.g., home memory zone MZ) based on checking a local memory map M (operation 6002). If the address is included in the local memory zone of the home controller core (Y), home controller core C sends a memory load request to memory controller X of home memory zone MZ (e.g., first memory zone MZ1), and the memory controller manages the address (operation 6003). For example, the home controller core converts an address of the memory space SP associated with the load request into a device linear address (e.g., a linear address associated with the memory device MD as a whole). For example, the device linear address corresponds to the linear address of the entire memory device MD, which includes two or more memory spaces SP, such that addresses in one memory space SP differ from their corresponding addresses in relation to all other addresses in the memory device MD. The memory controller X (e.g., the local memory controller X) loads data for the load request from the local memory zone MZ and returns the data to the home controller core C (operation 6004). The home controller core C returns the loaded data to the requesting host 100 via a port of the host interface IF circuit of the first control circuit CC1 (operation 6005).

[0112] If the address does not belong to the home controller core's local memory zone MZ (N), the home controller core C sends (e.g., transmits) a load request to a remote (e.g., adjacent) controller core C of a remote memory zone (e.g., second memory zone MZ2) that manages the address through the interconnect ICT (operation 6006). The remote controller core C loads data associated with the address from its memory zone MZ (e.g., via the remote memory controller X) and returns the data to the home controller core C through the interconnect ICT (operation 6007). The home controller core C determines whether the remote load performed by one or more remote controller cores C is completed. If the remote load is completed (Y), the home controller core C returns the loaded data to the requesting host 100 through a port of the host interface IF of the first control circuit CC1 (operation 6005). If the remote load is not completed (e.g., if a time threshold has passed), the home controller core C returns an error to the requesting host 100 (operation 6009).

[0113] FIG. 7 is a flowchart illustrating method operations for fulfilling a store request according to some embodiments of the present invention.

[0114] 7, method 7000 includes one or more of the following operations: A controller core C (e.g., home controller core C) of the first control circuit CC1 receives a store request (e.g., a write request) from the host 100 via a port of the host interface IF of the first control circuit CC1 (operation 7001). For example, the home controller C is dedicated (e.g., assigned) to be used for the received request at the port associated with the store request. The home controller core C determines whether the address of the store request (e.g., associated with the store request) belongs to the local memory zone MZ (e.g., home memory zone MZ) of the home controller core C based on checking the local memory map M (operation 7002). If the address belongs to the local memory zone MZ of the home controller core (e.g., the address is valid in the memory space) (Y), the home controller core C sends the memory store request to the memory controller X of the home memory zone MZ, which manages the address (operation 7003). For example, the home controller core C converts the address of the memory space SP to a device linear address. The memory controller X (e.g., local memory controller X) stores the data for the store request in the local memory zone MZ (operation 7004). The home controller core C returns a confirmation (e.g., a notification) to the requesting host 100 via a port of the host interface IF based on the completion of the store operation (operation 7005).

[0115] If the address does not belong to the local memory zone MZ of the home controller core C (N), the home controller core C sends (e.g., transmits) a store request to the remote controller core C of the remote memory zone MZ that manages the address via the interconnect ICT (operation 7006). The remote controller core C stores the data associated with the address in its memory zone MZ (operation 7007). The remote controller core C sends a confirmation that the store operation has been completed (operation 7008). The home controller core C and the remote controller core C assume that the write order has been preserved so that the data is returned in the appropriate order to the requesting host 100 (operation 7009). The home controller core C returns a confirmation to the requesting host 100 indicating that the store operation has been completed via a port of the host interface IF (operation 7005).

[0116] FIG. 8 is a flowchart illustrating the operation of a method for memory pool management according to some embodiments of the present invention.

[0117] 8, method 8000 includes one or more of the following operations: A first control circuit CC1 (see FIG. 2) receives a first request r1a (e.g., a first generation request) to generate a memory space SP (e.g., a logical memory space) (Operation 8001). The first control circuit CC1 is associated with (e.g., communicatively coupled to) a first memory zone MZ1. Based on determining that a first memory unit MU1 (e.g., a first logical memory unit) of the first memory zone MZ1 is available, the first control circuit CC1 allocates the first memory unit MU1 (e.g., a first logical memory unit) to the memory space SP (Operation 8002). In response to determining that a second memory unit MU2 of the first memory zone MZ1 is being used, the first control circuit CC1 sends a first donation request r1c (e.g., a memory donation request) to a second control circuit CC2 associated with a second memory zone MZ2 (Operation 8003). The second memory zone MZ2 includes the physical addresses of the first memory zone MZ1 and non-contiguous physical addresses. The second memory zone MZ2 includes a memory unit type different from (or the same as) the memory unit type of the first memory zone MZ1. Based on determining that the third memory unit MU3 of the second memory zone MZ2 is available, the second control circuit CC2 allocates the third memory unit MU2 to the memory space SP (operation 8004).

[0118] Thus, aspects of some embodiments of the present invention can provide improved memory pool management by providing a collaborative modular design that flexibly meets the demands for large memory space with reduced latency in a scalable system.

[0119] Exemplary embodiments of the present invention extend to, but are not limited to, the following statements.

[0120] Statement 1. An example method includes receiving, by first control circuitry of a memory device controller, a first request to create a first logical memory space, the first control circuitry being associated with a first memory zone, and allocating, by the first control circuitry, the first memory unit to the first logical memory space based on the first control circuitry determining that a first memory unit is available in a first physical address range of the first memory zone; and sending, by the first control circuitry, a memory donation request to second control circuitry of the memory device controller based on the first control circuitry determining that a second memory unit of the first memory zone is in use, the second control circuitry being associated with a second memory zone, and allocating, by the second control circuitry, the third memory unit to the first logical memory space based on the second control circuitry determining that a third memory unit of the second memory zone is available.

[0121] Statement 2. An example method includes the method of statement 1, wherein determining that the first memory unit is available includes reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone, and determining that the third memory unit is available includes reading, by a memory map manager of the second control circuit, a second memory map associated with the second memory zone.

[0122] Statement 3. Example methods include any of statements 1 and 2, wherein determining that the second memory unit is in use includes reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone.

[0123] Statement 4. Exemplary methods include any of statements 1-3, wherein the first request that generates the first logical space is associated with a performance target.

[0124] Statement 5. An example method includes any of statements 1-4, wherein the first request to create the first logical memory space is associated with a performance target.

[0125] Statement 6. An example method includes any of statements 1-5 and further includes determining, by the first control circuitry, that the first memory unit includes features associated with providing the performance target, and determining, by the second control circuitry, that the third memory unit includes features associated with providing the performance target.

[0126] Statement 7. Example methods include any of statements 1-6, wherein the first control circuitry includes a first control core and a second control core, the first request to generate the first logical memory space is processed by the first control core, and the second request to generate the second logical memory space is processed by the second control core.

[0127] Statement 8. Exemplary methods include any of statements 1 to 7, wherein allocating the first memory unit to the first logical memory space includes updating, by a first control core of the first control circuit, a first memory map of the first control circuit with characteristics of the first memory unit.

[0128] Statement 9. Exemplary methods include any of statements 1 to 8, wherein allocating the third memory unit to the first logical memory space includes updating, by a second control core of the second control circuit, a second memory map of the second control circuit with characteristics of the third memory unit.

[0129] Statement 10. Example methods include any of statements 1-9, wherein the third memory unit corresponds to a second physical address range separate from the first physical address range.

[0130] Statement 11. An example method includes any of the methods of Statements 1-10 and further includes receiving, by the first control circuitry, a read request for a data location associated with the first logical memory space; determining, by the first control circuitry, that the data location is located outside the first memory zone; communicating, by the first control circuitry, the read request to the second control circuitry; and reading, by a memory controller of the second control circuitry, data associated with the read request from the second memory zone.

[0131] Statement 12. An example method includes any of the methods of Statements 1-11, and further includes receiving, by the first control circuitry, a write request for a data location associated with the first logical memory space; determining, by the first control circuitry, that the data location is located outside the first memory zone; communicating, by the first control circuitry, the write request to the second control circuitry; and writing, by a memory controller of the second control circuitry, data associated with the write request to the second memory zone.

[0132] Statement 13. An example system for performing any of the methods of statements 1 to 12 includes a memory device controller including a first control circuit and a second control circuit, a first memory zone including a first memory unit associated with the first circuit and a second memory unit associated with the first control circuit, and a second memory zone including a third memory unit associated with the second control circuit.

[0133] Statement 14. An example apparatus for performing any of the methods of Statements 1 to 12 includes a processing circuit associated with a first control circuit and a second control circuit, and a computer-readable medium storing instructions that, when executed by the processing circuit, cause the processing circuit to perform any of the methods of Statements 1 to 12.

[0134] While embodiments of the present invention have been particularly shown and described with reference to the embodiments set forth herein, those skilled in the art will recognize that various changes in form and detail may be made therein without departing from the concept and scope of the invention. [Explanation of symbols]

[0135] 1 System 100 hosts 102 Adapter 200 Memory Device Controller 300 memory pool ICT Interconnect IF Host Interface MD memory device MMM Memory Management Module MR memory area MU Memory Unit MZ Memory Zone SEG memory segment SP memory space

Claims

1. 1. A method for memory pool management, comprising: receiving, by a first control circuit of a memory device controller, a first request to create a first logical memory space, the first control circuit being associated with a first memory zone; allocating, by the first control circuitry, the first memory unit to the first logical memory space based on the first control circuitry determining that a first memory unit is available in a first physical address range of the first memory zone; sending a memory donation request by the first control circuitry to a second control circuitry of the memory device controller based on the first control circuitry determining that a second memory unit in the first memory zone is in use, the second control circuitry being associated with the second memory zone; and allocating, by the second control circuitry, the third memory unit in the second memory zone to the first logical memory space based on the second control circuitry determining that the third memory unit is available.

2. Determining that the first memory unit is available includes reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone; 2. The method of claim 1, wherein determining that the third memory unit is available includes reading, by a memory map manager of the second control circuit, a second memory map associated with the second memory zone.

3. 2. The method of claim 1, wherein determining that the second memory unit is in use includes reading, by a memory map manager of the first control circuit, a first memory map associated with the first memory zone.

4. 2. The method of claim 1, wherein the first request to create the first logical memory space is associated with a performance target.

5. determining, by the first control circuitry, that the first memory unit includes features related to providing the performance target; 5. The method of claim 4, further comprising: determining, by the second control circuitry, that the third memory unit includes features related to providing the performance target.

6. the first memory unit includes a first memory type; 2. The method of claim 1, wherein the third memory unit comprises a second memory type different from the first memory type.

7. the first control circuit includes a first controller core and a second controller core; the first request to create the first logical memory space is processed by the first controller core; 2. The method of claim 1, wherein a second request to create a second logical memory space is processed by the second controller core.

8. 2. The method of claim 1, wherein allocating the first memory unit to the first logical memory space includes updating a first memory map of the first control circuit with characteristics of the first memory unit by a first controller core of the first control circuit.

9. 2. The method of claim 1, wherein allocating the third memory unit to the first logical memory space includes updating, by a second controller core of the second control circuit, a second memory map of the second control circuit with characteristics of the third memory unit.

10. 2. The method of claim 1, wherein the third memory unit corresponds to a second physical address range separate from the first physical address range.

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