Semiconductor element

Abstract

To provide a semiconductor element capable of making improvement of a breakdown voltage and reduction of ON resistance compatible.SOLUTION: A semiconductor element 1 includes a substrate 10, a main drift layer 11, a current dispersion layer 20, a sub drift layer 12, a second conductivity type block layer 30, a second conductivity type body layer 31, and a first conductivity type impurity high concentration containing layer 13. A groove 30a is formed in the second conductivity type block layer 30, and a gate trench T is formed in a groove shape reaching at least the sub drift layer 12 from the first conductivity type impurity high concentration containing layer 13. A gate insulating film 14 is disposed in a film shape along a bottom face and a side face of the gate trench T, a gate electrode is disposed via the gate insulating film, and a bottom part Ta of the gate trench T is positioned closer to the first conductivity type impurity high concentration containing layer 13 than a bottom face of the second conductivity type block layer 30.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices. [Background technology]

[0002] In semiconductor devices with gate trench structures, in the off-state when the gate voltage is below the threshold, leakage current tends to occur due to electric field concentration at the bottom of the gate trench, resulting in low breakdown voltage. Therefore, the configurations disclosed in Patent Documents 1 and 2 aim to improve breakdown voltage by providing a p-block layer between the p-body layer and the n-drift layer to mitigate electric field concentration at the bottom of the gate trench and suppress current leakage. Furthermore, in the configuration disclosed in Patent Document 1, an n-current spreading layer is provided from the gate trench to below the p-block layer, which sufficiently spreads current to the n-drift layer, thereby facilitating a large current flow in the on-state when the gate voltage is above the threshold, thereby reducing on-resistance. Furthermore, in the configuration disclosed in Patent Document 2, an n-current spreading layer is provided in the region excluding the region below the p-block layer, thereby reducing on-resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2020-512682 [Patent Document 2] Japanese Patent Application Publication No. 2019-054174 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration disclosed in Patent Document 1, the electric field strength increases at the corners of the bottom of the gate trench and at the corners of the p-block layer on the trench side, leading to an increase in leakage current and a decrease in breakdown voltage. Furthermore, in the configuration disclosed in Patent Document 2, the n-current spreading layer is not provided below the p-block layer, so the effect of reducing on-resistance is insufficient. Therefore, there is room for improvement in semiconductor devices with gate trench structures in order to achieve both an increase in breakdown voltage and a decrease in on-resistance.

[0005] The present invention has been made in view of the above background, and aims to provide a semiconductor element that can achieve both an improvement in breakdown voltage and a reduction in on-resistance. [Means for solving the problem]

[0006] One aspect of the present invention is a substrate that is a semiconductor containing a first conductivity type impurity; a main drift layer provided on the substrate and containing a first conductivity type impurity at a lower concentration than the substrate; a current spreading layer provided on the main drift layer, the current spreading layer including a first conductivity type impurity at a concentration lower than that of the substrate and higher than that of the main drift layer; a sub-drift layer provided on the current spreading layer and containing a first conductivity type impurity at a lower concentration than the current spreading layer; a second-conductivity-type block layer including a second-conductivity-type impurity and provided in contact with the sub-drift layer and having a groove formed therein; a second-conductivity-type body layer provided on the sub-drift layer and the second-conductivity-type block layer, the second-conductivity-type body layer including a second-conductivity-type impurity at a concentration equal to or lower than that of the second-conductivity-type block layer; a first conductivity type impurity high concentration layer provided on the second conductivity type body layer and containing first conductivity type impurities at a concentration higher than that of the current spreading layer; a gate trench formed in a groove shape extending from the first conductivity type high concentration impurity containing layer to at least the sub-drift layer; a gate insulating film provided in a film shape along the bottom surface and side surfaces of the gate trench; a gate electrode provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film; The bottom of the gate trench is located in the semiconductor element closer to the first conductivity type high concentration impurity layer than the bottom surface of the second conductivity type block layer. [Effects of the Invention]

[0007] In the above-described embodiment, a sub-drift layer is provided on a current spreading layer formed on a main drift layer, and a second-conductivity-type block layer having a groove is provided in contact with the sub-drift layer. The gate trench is formed as a groove that reaches at least the sub-drift layer, and the bottom of the gate trench is positioned closer to the first-conductivity-type high-concentration impurity layer than the bottom surface of the second-conductivity-type block layer. This ensures a wide current flow path in the current spreading layer, allowing more current to flow more easily in the on-state and reducing on-resistance. Furthermore, with this configuration, the second-conductivity-type block layer can prevent the electric field strength from increasing at the corners of the bottom of the gate trench and the corners of the second-conductivity-type block layer on the trench side, thereby reducing leakage current and improving breakdown voltage. This allows for both improved breakdown voltage and reduced on-resistance.

[0008] As described above, in the above aspect, it is possible to provide a semiconductor element that can achieve both an improvement in breakdown voltage and a reduction in on-resistance. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor element according to Embodiment 1, taken along a plane perpendicular to the main surface of a substrate. [Figure 2] 1A and 1B are diagrams showing examples of planar patterns of trenches. [Figure 3] FIG. 10 is a diagram showing another example of a planar pattern of a trench. [Figure 4] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 12] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element in a first modified embodiment, the cross-sectional view being perpendicular to the main surface of the substrate. [Figure 14] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element in a second modified embodiment, the cross-sectional view being perpendicular to the main surface of the substrate. [Figure 15] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor element in a third modified embodiment, the cross-sectional view being perpendicular to the main surface of the substrate. [Figure 16] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element according to a second embodiment, taken along a plane perpendicular to the main surface of the substrate. [Figure 17] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor element according to the second embodiment. [Figure 18] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor element according to the second embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element in Modification 4, taken along a plane perpendicular to the main surface of the substrate. [Figure 20] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element in Modification 4, taken along a plane perpendicular to the main surface of the substrate. DETAILED DESCRIPTION OF THE INVENTION

[0010] The current spreading layer may include a first current spreading layer in contact with the main drift layer and a second current spreading layer covering a wall surface of the groove in the second-conductivity-type block layer, and the sub-drift layer may include a first sub-drift layer in contact with the first current spreading layer and the second-conductivity-type block layer, and a second sub-drift layer in contact with the second current spreading layer and the gate insulating film. In this case, the second current spreading layer can further reduce the on-resistance, and the first and second sub-drift layers and the first and second current spreading layers can further suppress the occurrence of leakage current, thereby improving the breakdown voltage.

[0011] The second current spreading layer may be configured so as not to contact the corners of the gate trench, which can prevent the electric field strength at the corners of the bottom of the gate trench from becoming high, thereby improving the breakdown voltage.

[0012] The first current spreading layer and the second current spreading layer may be configured to be in contact with each other, which promotes the current spreading effect and further reduces the on-resistance.

[0013] The second sub-drift layer may be in contact with the entire lower surface of the second conductivity type body layer, and the second current spreading layer may be in contact with the entire lower surface of the second sub-drift layer, which promotes current spreading and further reduces on-resistance.

[0014] The first sub-drift layer may be interposed between the first current spreading layer and the second current spreading layer. In this case, even if the first current spreading layer and the second current spreading layer are separated from each other, it is possible to obtain a reduction in on-resistance and to suppress the occurrence of leakage current, thereby improving the breakdown voltage.

[0015] A part of the second current spreading layer may be configured to penetrate into the first current spreading layer, which increases the contact area between the first current spreading layer and the second current spreading layer, thereby promoting the current spreading effect and further reducing the on-resistance, and also suppressing the occurrence of leakage current and improving the breakdown voltage.

[0016] a bottom of the gate trench extends into the groove of the second conductivity type block layer; The second sub-drift layer is interposed between the bottom of the gate trench and the second current spreading layer, which can suppress the occurrence of leakage current and improve the breakdown voltage.

[0017] The bottom of the gate trench may have a portion that extends into the groove of the second-conductivity-type block layer and a portion that is located inside the second-conductivity-type block layer, and the corners of the bottom of the gate trench may not be in contact with the second current spreading layer. In this case, it is possible to suppress the occurrence of leakage current and improve the breakdown voltage.

[0018] The entire bottom of the gate trench may be located inside the second-conductivity-type block layer, and the corners of the bottom of the gate trench may not be in contact with the second current spreading layer. In this case, the occurrence of leakage current may be suppressed, and the breakdown voltage may be improved.

[0019] (Embodiment 1) 1. Structure of semiconductor elements 1 is a cross-sectional view showing the configuration of a semiconductor element according to embodiment 1, taken perpendicular to the main surface of a substrate. The semiconductor element according to embodiment 1 is a MOSFET having a gate trench structure. In addition, the semiconductor element according to embodiment 1 has a structure in which regular hexagonal unit cells are arranged in a honeycomb pattern in a plan view, and the unit cells are connected in parallel.

[0020] 1, the semiconductor device of the first embodiment includes a substrate 10, a main drift layer 11, a sub-drift layer 12, a current spreading layer 20, a second-conductivity-type block layer 30, a second-conductivity-type body layer 31, a first-conductivity-type heavily doped layer 13, a gate trench T, a recess R, a gate insulating film 14, a gate electrode GM, a source electrode SM, and a drain electrode DM. The gate trench T, the gate insulating film 14, and the gate electrode GM form a gate trench structure. All of the gate trench structures are MIS structures.

[0021] The substrate 10 is a semiconductor containing first conductivity type impurities, and in this embodiment, is a Si-doped n-type semiconductor having a c-plane as its principal surface. + The substrate 10 is made of GaN. The Si concentration is 5×10 17 ~5×10 20 / cm 3 In this embodiment, it can be set to 2×10 18 / cm 3 The thickness of the substrate 10 can be set to 100 to 500 μm, and is set to 300 μm in this embodiment. The material of the substrate 10 may be other than GaN, and any material can be used as long as it is conductive and can grow a nitride semiconductor. For example, Si, SiC, ZnO, etc. can be used. However, it is preferable to use a nitride semiconductor, particularly GaN as in embodiment 1.

[0022] The main drift layer 11 is provided on the substrate 10 and contains a first conductivity type impurity at a lower concentration than the substrate 10. In this embodiment, the main drift layer 11 is a Si-doped n - The Si concentration of the main drift layer 11 is 3×10 15 ~3×10 16 / cm 3 In this embodiment, it can be set to 1×10 16 / cm 3 The thickness of the main drift layer 11 can be set to 0.5 to 20 μm, and is set to 10 μm in this embodiment.

[0023] The current spreading layer 20 is provided on the main drift layer 11, and contains a first conductivity type impurity at a concentration lower than that of the substrate 10 and higher than that of the main drift layer 11. In this embodiment, the current spreading layer 20 includes a first current spreading layer 21 and a second current spreading layer 22.

[0024] The first current spreading layer 21 is formed over the entire upper surface of the main drift layer 11 and is in contact with the main drift layer 11. The first current spreading layer 21 is made of Si-doped n - The first current spreading layer 21 is made of GaN. The Si concentration of the first current spreading layer 21 is 1×10 16 ~1×10 18 / cm 3 In this embodiment, it can be set to 5×10 16 / cm 3 The thickness of the first current spreading layer 21 can be set to 0.1 to 1.0 μm, and is set to 0.5 μm in this embodiment.

[0025] The second current spreading layer 22 covers the wall surfaces of the grooves 30a in the second conductivity-type block layer 30, which will be described later. In this embodiment, the grooves 30a penetrate a part of the first sub-drift layer 121 and reach the upper surface of the first current spreading layer 21, so that the bottom surface of the second current spreading layer 22 is in contact with the first current spreading layer 21. Furthermore, in this embodiment, the second current spreading layer 22 is not in contact with the corners Tb of the gate trench T.

[0026] The second current spreading layer 22 is a Si-doped n - The Si concentration of the second current spreading layer 22 is equal to or higher than that of the first current spreading layer 21, and is 1×10 16 ~5×10 18 / cm 3 In this embodiment, it can be set to 1×10 17 / cm 3 The thickness of the second current spreading layer 22 can be set to 0.1 to 0.6 μm, and is set to 0.3 μm in this embodiment.

[0027] The sub-drift layer 12 is provided on the current spreading layer 20 and contains a first conductivity type impurity at a lower concentration than the current spreading layer 20. In this embodiment, the sub-drift layer 12 includes a first sub-drift layer 121 and a second sub-drift layer 122.

[0028] The first sub-drift layer 121 is in contact with the first current spreading layer 21 and the second conductivity type block layer 30 described later, and in this embodiment, is formed between the first current spreading layer 21 and the second conductivity type block layer 30. In this embodiment, the first sub-drift layer 121 is formed of Si-doped n - The Si concentration of the first sub-drift layer 121 is lower than the Si concentration of the first current spreading layer 21, and is 3×10 15 ~3×10 16 / cm 3 In this embodiment, it can be set to 1×10 16 / cm 3 The thickness of the first sub-drift layer 121 can be set to 0.1 to 1.0 μm, and is set to 0.2 μm in this embodiment.

[0029] The second sub-drift layer 122 is formed so as to be in contact with the second current spreading layer 22 and a gate insulating film 14 (described later), and in this embodiment, is formed between the second current spreading layer 22 and the gate insulating film 14 in the groove 30a of the second conductivity type block layer 30 (described later). As a result, all corners Tb of the bottom Ta of the gate trench T are located in the second sub-drift layer 122. In this embodiment, the second sub-drift layer 122 is formed of Si-doped n - The Si concentration of the second sub-drift layer 122 is lower than the Si concentration of the second current spreading layer 22, and is 3×10 15 ~3×10 16 / cm 3 In this embodiment, it can be set to 1×10 16 / cm 3 The thickness of the second sub-drift layer 122 can be set to 0.1 to 1.5 μm, and is set to 1.0 μm in this embodiment.

[0030] The second-conductivity-type block layer 30 contains second-conductivity-type impurities and is provided in contact with the sub-drift layer 12. In this embodiment, the second-conductivity-type block layer 30 is made of Mg-doped p-GaN and is also referred to as a p-block layer 30. The Mg concentration of the p-block layer 30 is 5×10 17 ~5×10 19 / cm 3 In this embodiment, the 19 / cm 3 The thickness of the p-blocking layer 30 can be set to 0.3 to 1.0 μm, and is set to 0.5 μm in this embodiment.

[0031] A groove 30a is formed in the second conductivity type block layer (p block layer) 30. In this embodiment, the groove 30a includes a bottom region of a gate trench T, which will be described later, inside. In this embodiment, the groove 30a penetrates a part of the first sub-drift layer 121 provided directly below the p block layer 30 and reaches the upper surface of the first current spreading layer 21. As a result, a corner 301 of the p block layer 30 is located on the wall surface of the groove 30a.

[0032] The second-conductivity-type body layer 31 is provided on the sub-drift layer 12 and the p-block layer 30. The second-conductivity-type body layer 31 contains second-conductivity-type impurities at the same concentration as the p-block layer 30 or at a lower concentration than the p-block layer. In this embodiment, the second-conductivity-type body layer 31 is made of Mg-doped p-GaN and is also referred to as the p-body layer 31. The Mg concentration of the p-body layer 31 is 1×10 17 ~4×10 19 / cm 3 In this embodiment, it can be set to 5×10 18 / cm 3 The thickness of the p body layer 31 can be set to 0.2 to 1.0 μm, and is set to 0.4 μm in this embodiment.

[0033] The first conductivity type impurity high concentration layer 13 is provided on the p body layer 31. The first conductivity type impurity high concentration layer 13 contains a first conductivity type impurity at a higher concentration than the current spreading layer 20. In this embodiment, the first conductivity type impurity high concentration layer 13 is a Si-doped n + The n-type layer 13 is made of GaN and is also called an n-type layer 13. The Si concentration of the n-type layer 13 is 5×10 17 ~1×10 19 / cm 3 In this embodiment, the 18 / cm 3 The thickness of the n-type layer 13 can be set to 0.1 to 0.6 μm, and is set to 0.2 μm in this embodiment.

[0034] The gate trench T has a groove shape that extends from the first-conductivity-type high-concentration impurity layer 13 to the sub-drift layer 12. In this embodiment, the second sub-drift layer 122 is exposed at the bottom surface of the gate trench T. The second sub-drift layer 122, the p-body layer 31, and the n-type layer 13 are exposed at the side surface of the gate trench T, in this order from the bottom side. The p-body layer 31 exposed at the side surface of the gate trench T functions as a channel. The bottom Ta of the gate trench T is in contact with the sub-drift layer 12 and is located closer to the n-type layer 13 than the bottom surface 302 of the p-block layer 30.

[0035] The width of the gate trench T can be set to 0.5 to 3 μm, and is set to 1.5 μm in this embodiment. The cell pitch can be set to 3 to 10 μm, and is set to 6 μm in this embodiment. The trench width can be set to 0.5 to 3 μm, and is set to 2 μm in this embodiment. The trench angle is not limited, and is perpendicular to the substrate 10 in this embodiment.

[0036] The recess R is a recess that penetrates the n-type layer 13 and has a depth that reaches the p-body layer 31. The recess R is provided to bring the source electrode SM into contact with the p-body layer 31.

[0037] The gate insulating film 14 is provided continuously in the form of a film along the bottom, side, and top surface (on the n-type layer 13 near the gate trench T) of the gate trench T. The gate insulating film 14 is made of a material such as SiO, SiN, SiON, or AlO, and has a thickness of, for example, 50 nm.

[0038] The gate electrode GM is provided in a continuous film shape along the bottom, side and top surfaces of the gate trench T via the gate insulating film 14. The material of the gate electrode GM is TiN or the like.

[0039] The source electrode SM is provided continuously on the p-body layer 31 exposed at the bottom surface of the recess R and on the n-type layer 13. The material of the source electrode SM is, for example, Ti / Al, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0040] The gate trenches T and the source electrodes SM are each provided in a predetermined region on the surface of the n-type layer 13. In this embodiment, the planar pattern of the gate trenches T and the source electrodes SM is a stripe pattern in which the gate trenches T and the source electrodes SM are alternately arranged in parallel, as shown in FIG. 2. The p-blocking layer 30 is provided along the source electrodes SM. FIG. 1 corresponds to a cross section in the X direction in FIG. 2. Alternatively, as shown in FIG. 3, the p-blocking layer 30 may be provided so as to intersect with the gate trenches T and source electrodes SM arranged in a stripe pattern.

[0041] The drain electrode DM is provided over the entire rear surface of the substrate 10. The material of the drain electrode DM is, for example, Ti / Al, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0042] 2. Manufacturing method of semiconductor element Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.

[0043] 4, main drift layer 11, first current spreading layer 21, first sub-drift layer 121, and p-blocking layer 30 are stacked on substrate 10 in this order from the substrate 10 side. Each layer is formed by a vapor phase growth method such as MOCVD, HVPE, MBE, or sputtering so that Si as the first conductivity type impurity or Mg as the second conductivity type impurity has a predetermined doping concentration.

[0044] Next, as shown in FIG. 5, a mask pattern 32 is formed on the p-blocking layer 30. The mask pattern 32 can be formed of resist or an SiO2 film. Thereafter, etching is performed to remove the p-blocking layer 30 and the first sub-drift layer 121 until the first current spreading layer 21 is exposed. As shown in FIG. 6, the etching leaves the area covered by the mask pattern 32 and removes the area not covered by the mask pattern 32, forming the groove 30a. The etching can be performed by dry etching such as RIE. After etching, the mask pattern 32 is removed.

[0045] 7, the second current spreading layer 22 and the second sub-drift layer 122 are formed in this order on the p-blocking layer 30 and the grooves 30a. Each layer is formed by a vapor phase growth method such as MOCVD, HVPE, MBE, or sputtering so that the first conductivity type impurity Si has a predetermined doping concentration. As a result, the grooves 30a are filled with the second current spreading layer 22 and the second sub-drift layer 122.

[0046] 8, the second current spreading layer 22 and the second sub-drift layer 122 are etched back until the second current spreading layer 22 on the p-blocking layer 30 disappears and the p-blocking layer 30 is exposed. The second current spreading layer 22 and the second sub-drift layer 122 can be removed by dry etching such as ICE or RIE, wet etching such as PEC, or polishing.

[0047] 9, p body layer 31 and n-type layer 13 (layer containing a high concentration of first conductivity type impurities) are formed in this order on p block layer 30 and groove 30a. Each layer is formed by a vapor phase growth method such as MOCVD, HVPE, MBE, or sputtering so that Si as the first conductivity type impurity or Mg as the second conductivity type impurity has a predetermined doping concentration.

[0048] 10 , a predetermined region of the n-type layer 13 is dry-etched until the p-body layer 31 is exposed to form a recess R, and predetermined regions above the grooves 30a in the n-type layer 13, the p-body layer 31, and the second sub-drift layer 122 are dry-etched to form a gate trench T. In a region of the gate trench T below the p-body layer 31, the wall surfaces and bottom of the gate trench T are formed in the second sub-drift layer 122.

[0049] Next, as shown in FIG. 11, a gate insulating film 14 is formed over the entire upper surface of the device. The gate insulating film 14 is formed by a method such as ALD or CVD. To form the gate electrode GM on the gate insulating film 14, first, a uniform metal layer having the same stacked structure as the gate electrode GM is formed on the gate insulating film 14, and the uniform metal layer and the gate insulating film 14 are partially removed by etching using a resist or the like. This forms the gate electrode GM and the gate insulating film 14 as shown in FIG. 12. Next, as shown in FIG. 1, a source electrode SM is formed continuously over the wall surfaces of the recess R and the surface of the n-type layer 13 in the vicinity of the recess R, and a drain electrode DM is formed on the back surface of the substrate 10. The source electrode SM and the drain electrode DM are formed by vapor deposition or the like.

[0050] 3. Effects According to the semiconductor device 1 of this embodiment, the sub-drift layer 12 is provided on the current spreading layer 20 formed on the main drift layer 11, and the p-blocking layer 30 having the groove 30a is provided in contact with the sub-drift layer 12. The gate trench T is formed as a groove that reaches at least the sub-drift layer 12, and the bottom Ta of the gate trench T is positioned closer to the n-type layer 13 than the bottom surface 302 of the p-blocking layer 30. This ensures a wide current flow path in the current spreading layer 20, allowing more current to flow more easily in the on-state and reducing the on-resistance. Furthermore, with this configuration, the p-blocking layer 30 can prevent the electric field intensity from increasing at the corners of the bottom Ta of the gate trench T and the corners 301 of the p-blocking layer 30 on the trench side, thereby reducing the flow of leakage current and improving the breakdown voltage. This allows for both an improved breakdown voltage and a reduced on-resistance.

[0051] Furthermore, in the first embodiment, the current spreading layer 20 includes a first current spreading layer 21 in contact with the main drift layer 11 and a second current spreading layer 22 covering the wall surfaces of the grooves 30a in the p block layer 30. The sub-drift layer 12 includes a first sub-drift layer 121 in contact with the first current spreading layer 21 and the p block layer 30, and a second sub-drift layer 122 in contact with the second current spreading layer 22 and the gate insulating film 14. As a result, the second current spreading layer 22 further reduces the on-resistance, and the first sub-drift layer 121, the second sub-drift layer 122, the first current spreading layer 21, and the second current spreading layer 22 further suppress the occurrence of leakage current, thereby improving the breakdown voltage.

[0052] Furthermore, in the first embodiment, the second current spreading layer 22 is not in contact with the corners Tb of the bottom Ta of the gate trench T. This makes it possible to prevent the electric field strength at the corners Tb of the bottom Ta of the gate trench T from increasing, thereby improving the breakdown voltage.

[0053] In addition, in the first embodiment, the first current spreading layer 21 and the second current spreading layer 22 are in contact with each other, which promotes the current spreading effect and further reduces the on-resistance.

[0054] In addition, in the first embodiment, the bottom Ta of the gate trench T extends into the groove 30a of the p-blocking layer 30, and the second sub-drift layer 122 is interposed between the bottom Ta of the gate trench T and the second current spreading layer 22. This makes it possible to suppress the occurrence of leakage current and improve the breakdown voltage.

[0055] In the first embodiment, all of the corners Tb of the bottom Ta of the gate trench T are located in the second sub-drift layer 122. Alternatively, as in modified form 1 shown in Fig. 13, the bottom Ta of the gate trench T may include a portion Tb2 that enters the groove 30a of the p block layer 30 and a portion Tb1 that is located inside the p block layer 30, and the corners Tb1, Tb2 of the bottom Ta of the gate trench T are not in contact with the second current spreading layer 22. In modified form 1, as in the first embodiment, it is possible to suppress the occurrence of leakage current and improve the breakdown voltage.

[0056] In the first embodiment, the bottom of the second current spreading layer 22 is in contact with the first current spreading layer 21. Alternatively, as in modified form 2 shown in Fig. 14, a first sub-drift layer 121 may be interposed between the first current spreading layer 21 and the second current spreading layer 22. Even if the first current spreading layer 21 and the second current spreading layer 22 are separated from each other as in modified form 2, it is possible to obtain the effect of reducing the on-resistance, and to suppress the occurrence of leakage current and improve the breakdown voltage.

[0057] 15, a part of the second current spreading layer 22 may penetrate into the first current spreading layer 21. According to the third modified embodiment, the contact area between the first current spreading layer 21 and the second current spreading layer 22 increases, which promotes the current spreading effect and further reduces the on-resistance, and also suppresses the occurrence of leakage current and improves the breakdown voltage.

[0058] As described above, in the first embodiment and the first to third modifications, it is possible to provide a semiconductor element 1 that can achieve both an improvement in breakdown voltage and a reduction in on-resistance.

[0059] (Embodiment 2) 1, in the above-described first embodiment, the second current spreading layer 22 and the second sub-drift layer 122 are provided only in the grooves 30a of the p block layer 30. However, instead of this, in the semiconductor device 1 of the second embodiment, the second current spreading layer 22 and the second sub-drift layer 122 are provided in the grooves 30a of the p block layer 30 and over the entire upper surface 303 of the p block layer 30, as shown in Fig. 16. Note that, as in the case of the first embodiment, the entire bottom Ta of the gate trench T is located in the second sub-drift layer 122.

[0060] The method for manufacturing the semiconductor device 1 of the second embodiment is similar to that of the first embodiment in that, after forming the second sub-drift layer 122 as shown in Fig. 7, the second current spreading layer 22 and the second sub-drift layer 122 are not removed, and the p-body layer 31 and the n-type layer 13 are subsequently formed in this order on the second sub-drift layer 122 as shown in Fig. 17. Each layer is formed by a vapor phase growth method such as MOCVD, HVPE, MBE, or sputtering so that the first conductivity type impurity Si or the second conductivity type impurity Mg has a predetermined doping concentration. The second current spreading layer 22 to the n-type layer 13 can be epitaxially grown at once by MOCVD, which has the advantage of reducing the number of processes.

[0061] 18 , a predetermined region of n-type layer 13 is dry-etched until p-body layer 31 is exposed, thereby forming recess R, and a predetermined region above groove 30a is dry-etched to expose n-type layer 13, p-body layer 31, and second sub-drift layer 122 until second current spreading layer 22 is exposed, thereby forming gate trench T. As a result, groove 30a is filled with second current spreading layer 22.

[0062] Thereafter, as in the case of the first embodiment, the gate insulating film 14 and the gate electrode GM are formed, the source electrode SM is formed continuously on the wall surfaces of the recess R and on the surface of the n-type layer 13 in the vicinity of the recess R, and the drain electrode DM is formed on the rear surface of the substrate 10 (see FIG. 16). The source electrode SM and the drain electrode DM are formed by vapor deposition or the like.

[0063] According to the second embodiment, the second sub-drift layer 122 is in contact with the entire lower surface of the p-body layer 31, and the second current spreading layer 22 is in contact with the entire lower surface of the second sub-drift layer 122. This promotes the current spreading effect, and can further reduce the on-resistance.

[0064] Note that the same effects as those of the embodiment 1 are achieved in the embodiment 2. Furthermore, in the embodiment 2, if the p block layer 30 and the p body layer 31 are connected to each other and set to the same potential, the p block layer 30 can further suppress an increase in the electric field intensity at the corners of the bottom Ta of the gate trench T and at the corners 301 of the p block layer 30 on the trench side, thereby achieving a further improvement in the breakdown voltage.

[0065] In the second embodiment, the entire bottom Ta of the gate trench T is located in the second sub-drift layer 122. Alternatively, as in modified form 4 shown in Fig. 19, the bottom Ta of the gate trench T includes a portion Tb2 that enters the groove 30a of the p block layer 30 and a portion Tb1 that is located inside the p block layer 30, and the corners Tb1 and Tb2 of the bottom Ta of the gate trench T are not in contact with the second current spreading layer 22. In modified form 1, as in the second embodiment, it is possible to suppress the occurrence of leakage current and improve the breakdown voltage.

[0066] 20 , a configuration can be adopted in which the entire bottom Ta of the gate trench T is located inside the p-blocking layer 30, and corners Tb1 and Tb2 of the bottom Ta of the gate trench T are not in contact with the second current spreading layer 22. In the fifth modification, as in the second embodiment, it is possible to suppress the occurrence of leakage current and improve the breakdown voltage.

[0067] Furthermore, in the first and second embodiments and the first to fifth modifications, the first conductivity type impurities are n-type and the second conductivity type impurities are p-type, but this may be reversed so that the first conductivity type impurities are p-type and the second conductivity type impurities are n-type. [Explanation of symbols]

[0068] 1: Semiconductor element 10: Circuit board 11: Main drift layer 12: Sub-drift layer 121: First secondary drift layer 122: Second secondary drift layer 13: First conductivity type impurity high concentration layer (n-type layer) 14: Gate insulating film 20: Current distribution layer 21: First current distribution layer 22:Second current distribution layer 30: second conductive type block layer (p block layer) 30a: Groove 301: Corner 302: Bottom 303:Top surface 31: second conductive type body layer (p body layer) 32: Mask pattern DM: drain electrode GM: gate electrode R: Recess SM: Source electrode T: Gate trench

Claims

1. a substrate that is a semiconductor containing a first conductivity type impurity; a main drift layer provided on the substrate and containing a first conductivity type impurity at a concentration lower than that of the substrate; a current spreading layer provided on the main drift layer, the current spreading layer including a first conductivity type impurity at a concentration lower than that of the substrate and higher than that of the main drift layer; a sub-drift layer provided on the current spreading layer and containing a first conductivity type impurity at a lower concentration than the current spreading layer; a second-conductivity-type block layer including a second-conductivity-type impurity and provided in contact with the sub-drift layer and having a groove formed therein; a second-conductivity-type body layer provided on the sub-drift layer and the second-conductivity-type block layer, the second-conductivity-type body layer including a second-conductivity-type impurity at a concentration equal to or lower than that of the second-conductivity-type block layer; a first conductivity type impurity high concentration layer provided on the second conductivity type body layer and containing first conductivity type impurities at a concentration higher than that of the current spreading layer; a gate trench formed in a groove shape extending from the first conductivity type high concentration impurity doped layer to at least the sub-drift layer; a gate insulating film provided in a film shape along the bottom surface and side surfaces of the gate trench; a gate electrode provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film; a bottom of the gate trench is located closer to the first conductivity type high concentration impurity containing layer than a bottom surface of the second conductivity type block layer.

2. the current spreading layer includes a first current spreading layer in contact with the main drift layer and a second current spreading layer covering a wall surface of the groove in the second conductivity type block layer; 2. The semiconductor device according to claim 1, wherein the sub-drift layer comprises a first sub-drift layer in contact with the first current spreading layer and the second conductivity type block layer, and a second sub-drift layer in contact with the second current spreading layer and the gate insulating film.

3. The semiconductor device according to claim 2 , wherein the second current spreading layer is disposed so as not to contact corners of the bottom of the gate trench.

4. The semiconductor device of claim 3 , wherein the first current spreading layer and the second current spreading layer are in contact with each other.

5. the second sub-drift layer is in contact with the entire lower surface of the second conductivity type body layer, The semiconductor device according to claim 2 , wherein the second current spreading layer is in contact with the entire lower surface of the second sub-drift layer.

6. 4. The semiconductor device according to claim 3, wherein the first sub-drift layer is interposed between the first current spreading layer and the second current spreading layer.

7. The semiconductor device of claim 3 , wherein a portion of the second current spreading layer penetrates into the first current spreading layer.

8. a bottom of the gate trench extends into the groove of the second conductivity type block layer; The semiconductor device according to claim 2 , wherein the second sub-drift layer is interposed between the bottom of the gate trench and the second current spreading layer.

9. 3. The semiconductor device of claim 2, wherein a bottom of the gate trench includes a portion that extends into the groove of the second conductivity type block layer and a portion that is located inside the second conductivity type block layer, and wherein corners of the bottom of the gate trench are not in contact with the second current spreading layer.

10. 3. The semiconductor device of claim 2, wherein the entire bottom of the gate trench is located inside the second conductivity type block layer, and corners of the bottom of the gate trench are not in contact with the second current spreading layer.

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