Method of manufacturing semiconductor device and semiconductor device

Abstract

To prevent a lamination defect in an SiC semiconductor device from expanding during current application.SOLUTION: A method of manufacturing a semiconductor device 10 comprises irradiating the semiconductor device 10 with helium ions to form a point defect in a buffer layer 14, where the semiconductor device comprises a substrate 12 made of silicon carbide, the buffer layer 14 of a first conductivity type on a first surface 12a of the substrate 12, and a drift layer 16 of the first conductivity type which is on the buffer layer 14 and has lower impurity concentration than the buffer layer 14. The maximum density of the point defect formed in the buffer layer 14 by the irradiation with the helium ions is 2×1016 / cm3 or larger, and the density of a point defect formed in the drift layer 16 by the irradiation with the helium ions is 2×1017 / cm3 or smaller.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is attracting attention as a material for use in next-generation power semiconductor devices. For example, an epitaxial layer is formed on a SiC substrate, and a transistor structure is formed within the epitaxial layer. It is known that in SiC semiconductor devices, injected carriers are trapped in stacking faults in the epitaxial layer when a current is applied, reducing the stacking fault energy and leading to the expansion of stacking faults. The expansion of stacking faults is considered a problem because it leads to an increase in forward voltage.

[0003] To suppress the expansion of stacking faults, the drift layer is irradiated with helium ions and then annealed to reduce the Z-type charge transport due to C vacancies. 1 / 2 A technique has been proposed in which centers are introduced to promote the recombination of injected carriers before they are trapped by stacking faults. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-080035 Summary of the Invention [Problem to be solved by the invention]

[0005] When attempting to suppress the expansion of stacking faults by generating lifetime killers, it is necessary to generate lifetime killers over a wide area in the depth direction to promote sufficient carrier recombination, which requires increasing the thickness of the buffer layer or irradiating a wide area in the depth direction with helium ions, leading to increased manufacturing costs.

[0006] An exemplary object of an embodiment of the present invention is to provide a technique for suppressing the expansion of stacking faults in a SiC semiconductor device when a current is applied. [Means for solving the problem]

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes irradiating a semiconductor device including a silicon carbide substrate, a buffer layer of a first conductivity type on a first surface of the substrate, and a drift layer of the first conductivity type on the buffer layer and having a lower impurity concentration than the buffer layer, with helium ions to form point defects in the buffer layer. The density of point defects formed in the buffer layer by the helium ion irradiation is 2×10 16 / cm 3 The density of point defects formed in the drift layer by helium ion irradiation is 2 × 10 17 / cm 3 The following is the result.

[0008] Another aspect of the present invention is a semiconductor device. The device includes a substrate made of silicon carbide, a buffer layer of a first conductivity type provided on a first surface of the substrate, and a drift layer of the first conductivity type provided on the buffer layer and having a lower impurity concentration than the buffer layer. The density of point defects formed in the buffer layer is 2×10 16 / cm 3 The density of point defects formed in the drift layer is 2 × 10 17 / cm 3 The following is the result.

[0009] Any combination of the above components or mutual substitution of the components or expressions of the present invention between methods, devices, systems, etc. are also valid aspects of the present invention. [Effects of the Invention]

[0010] According to an embodiment of the present invention, it is possible to suppress the expansion of stacking faults in a SiC semiconductor device when a current is applied. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to an embodiment. [Figure 2] 1 is a graph showing an example of a density distribution of point defects formed by irradiation with helium ions. [Figure 3] 1 is a table showing the densities of point defects formed by helium ion irradiation in comparative examples and examples. [Figure 4] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 9] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 10 is a graph showing an example of a density distribution of point defects formed by irradiation with helium ions according to a modified example. [Figure 11] 10 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments for carrying out the present invention will be described in detail. Note that the configurations described below are examples and do not limit the scope of the present invention in any way. Furthermore, in the description of the drawings, the same elements are given the same reference numerals, and duplicate explanations will be omitted as appropriate. Furthermore, in the drawings referred to in the following description, the size and thickness of each component are for the convenience of explanation and do not necessarily represent the actual dimensions or ratios.

[0013] An outline of the present embodiment will be described. The present embodiment relates to a SiC semiconductor device including a substrate made of silicon carbide (SiC), a buffer layer of a first conductivity type provided on a first surface of the substrate, and a drift layer of the first conductivity type provided on the buffer layer and having a lower impurity concentration than the buffer layer. In such a SiC semiconductor device, a problem is that stacking faults present near the interface between the substrate and the buffer layer expand when a current is applied, leading to an increase in forward voltage.

[0014] In this embodiment, helium ions are irradiated near the interface between the substrate and the buffer layer to form point defects, which are then pinned to partial dislocations that border the stacking faults, thereby suppressing the expansion of the stacking faults when a current is applied. By pinning the point defects to partial dislocations, it is possible to suppress the reduction in stacking fault energy that would otherwise be caused by the trapped injected carriers in the stacking faults.

[0015] According to the findings of the present inventors, the density of point defects formed in the buffer layer is 2×10 16 / cm 3 By irradiating helium ions to a density of 2×10 or more, a sufficient number of point defects can be fixed to the partial dislocations that surround the stacking faults near the interface between the substrate and the buffer layer, thereby suppressing the expansion of stacking faults. 17 / cm 3 By irradiating helium ions as follows, it is possible to suppress the deterioration of the electrical characteristics of the semiconductor device.

[0016] 1 is a cross-sectional view schematically illustrating an example of the configuration of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is a SiC semiconductor device and a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor device 10 includes a substrate 12, a buffer layer 14, a drift layer 16, a base region 18, a source region 20, a base contact region 22, a gate insulating film 24, a gate electrode 26, an interlayer insulating film 28, a source electrode 30, and a drain electrode 32.

[0017] The substrate 12 is a SiC substrate made of silicon carbide (SiC) of a first conductivity type (e.g., n-type) or a second conductivity type (e.g., p-type). The substrate 12 is, for example, an n-type SiC substrate, and is doped with, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the first conductivity type or the second conductivity type of the substrate 12 is 1.0×10 18 / cm 3 For example, 2.0 × 10 18 / cm 3 Over 5.0 x 10 19 / cm 3 The substrate 12 has a first surface 12a and a second surface 12b opposite to the first surface 12a. The first surface 12a is, for example, a (0001) Si surface.

[0018] The buffer layer 14 is a first conductivity type SiC semiconductor layer epitaxially grown on the first surface 12a of the substrate 12. The buffer layer 14 is, for example, an n-type SiC layer, and is doped with, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the first conductivity type in the buffer layer 14 is lower than the impurity concentration of the first conductivity type or the second conductivity type in the substrate 12, and higher than the impurity concentration of the first conductivity type in the drift layer 16. The impurity concentration of the first conductivity type in the buffer layer 14 is, for example, 1.0×10 16 / cm 3 Over 1.0 x 10 18 / cm 3 The thickness of the buffer layer 14 is not less than 1.0 μm and not more than 5.0 μm, for example not less than 1.5 μm and not more than 3.0 μm, for example 2.0 μm.

[0019] The drift layer 16 is a first conductivity type SiC semiconductor layer epitaxially grown on the buffer layer 14. The drift layer 16 is, for example, an n-type SiC layer, and is doped with, for example, nitrogen (N) as an n-type impurity. The first conductivity type impurity concentration of the drift layer 16 is lower than the first conductivity type impurity concentration of the buffer layer 14. The first conductivity type impurity concentration of the drift layer 16 is, for example, 1.0×10 15 / cm 3 Over 1.0 x 10 17 / cm 3The thickness of the drift layer 16 is greater than the thickness of the buffer layer 14. The thickness of the drift layer 16 is 5.0 μm or more and 50 μm or less, for example, 7.5 μm or more and 15 μm or less, for example, 10 μm.

[0020] The base region 18 is a second conductivity type SiC semiconductor region provided on the drift layer 16. The base region 18 is, for example, p-type and is doped with, for example, aluminum (Al) as a p-type impurity. The base region 18 is formed, for example, by irradiating the drift layer 16 with impurity ions of the second conductivity type. The impurity concentration of the second conductivity type in the base region 18 is higher than the impurity concentration of the first conductivity type in the drift layer 16. The impurity concentration of the second conductivity type in the base region 18 is, for example, 1.0×10 16 / cm 3 Over 1.0 x 10 18 / cm 3 The following is the result.

[0021] The source region 20 is a first conductivity type SiC semiconductor region provided on the base region 18. The source region 20 is provided adjacent to the gate insulating film 24. The source region 20 is, for example, n-type, and is doped with, for example, nitrogen (N) as an n-type impurity. The source region 20 is formed, for example, by irradiating the drift layer 16 with impurity ions of the first conductivity type. The impurity concentration of the first conductivity type in the source region 20 is higher than that in the drift layer 16. The impurity concentration of the first conductivity type in the source region 20 is 1.0×10 18 / cm 3 For example, 2.0 × 10 18 / cm 3 Over 5.0 x 10 19 / cm 3 The following is the result.

[0022] The base contact region 22 is a second conductivity type SiC semiconductor region provided on the base region 18. The base contact region 22 is provided away from the gate insulating film 24. The base contact region 22 is, for example, p-type, and is doped with, for example, aluminum (Al) as a p-type impurity. The base contact region 22 is formed, for example, by irradiating the drift layer 16 with impurity ions of the second conductivity type. The second conductivity type impurity concentration of the base contact region 22 is higher than the second conductivity type impurity concentration of the base region 18. The second conductivity type impurity concentration of the base contact region 22 is, for example, 1.0×10 17 / cm 3 Over 1.0 x 10 19 / cm 3 The following is the result.

[0023] The gate insulating film 24 is provided on the inner wall surface of the gate trench 34. The gate insulating film 24 is provided so as to be adjacent to the drift layer 16, the base region 18, and the source region 20. The gate trench 34 is formed so as to be dug down from the upper surface 20a of the source region 20 toward the substrate 12. The gate trench 34 is formed so as to penetrate through the source region 20 and the base region 18 and reach the top of the drift layer 16. The gate insulating film 24 is formed of an oxide material, for example, SiO2.

[0024] The gate electrode 26 is provided so as to fill the inside of the gate insulating film 24 (gate trench 34). The gate electrode 26 is made of polycrystalline silicon doped with n-type impurities such as phosphorus (P) or nitrogen (N).

[0025] The interlayer insulating film 28 is provided on the gate insulating film 24 and the gate electrode 26. The interlayer insulating film 28 is made of any insulating material.

[0026] The source electrode 30 is provided on the source region 20, the base contact region 22, and the interlayer insulating film 28. The source electrode 30 is in contact with the upper surface 20a of the source region 20 and the upper surface 22a of the base contact region 22. The source electrode 30 is formed of a metal material such as chromium (Cr) or nickel (Ni). The source electrode 30 may be formed of a metal multilayer film in which multiple metal layers made of different metal materials are stacked. The source electrode 30 is a surface metal electrode layer formed on the surface of the semiconductor device 10.

[0027] The drain electrode 32 is provided on the second surface 12b of the substrate 12. The drain electrode 32 is in contact with the second surface 12b of the substrate 12. The drain electrode 32 is formed of a metal material such as chromium (Cr) or nickel (Ni). The drain electrode 32 may be formed of a metal multilayer film in which multiple metal layers made of different metal materials are stacked. The drain electrode 32 is a back surface metal electrode layer formed on the back surface of the semiconductor device 10.

[0028] In the manufacturing process of the semiconductor device 10, the semiconductor device 10 is irradiated with helium ions, and point defects are formed in the vicinity of the buffer layer 14. The density of the point defects formed in the buffer layer 14 is preferably large enough to suppress the expansion of stacking faults. The density of the point defects formed in the buffer layer 14 is preferably 2×10 16 / cm 3 For example, 5 x 10 16 / cm 3 That's it, 1×10 17 / cm 3 or more than 1×10 18 / cm 3 On the other hand, it is preferable that the density of point defects formed in the drift layer 16 is small enough to avoid a deterioration in the electrical characteristics of the semiconductor device 10. The density of point defects formed in the drift layer 16 is preferably 2×10 17 / cm 3 For example, 1 x 10 17 / cm 3 Below, 5 x 10 16 / cm 3 or less or 2×10 16 / cm 3 The following is the result.

[0029] Fig. 2 is a graph showing an example of the density distribution of point defects formed by helium ion irradiation. Fig. 2 shows the distribution of point defects formed by helium ion irradiation with an irradiation energy of 3.6 MeV and a dose of 1.6 × 10 12 / cm 2 2, the peak of the point defect density distribution is located at the first surface 12a, which is the interface between the substrate 12 and the buffer layer 14. The point defect density in the buffer layer 14 is 1.4×10 18 / cm 3 is the 2×10 16 / cm 3 On the other hand, the density of point defects in the drift layer 16 is 5.0×10 16 / cm 3 is the 2×10 required to avoid degradation of device functionality. 17 / cm 3 The following is the result.

[0030] The presence or absence of stacking fault expansion can be confirmed by X-ray topography or photoluminescence. First, the positions of stacking faults present in the semiconductor device 10 before current application are confirmed by X-ray topography or photoluminescence, and then whether or not the stacking faults have expanded after current application can be observed by X-ray topography or photoluminescence. Note that instead of generating injected carriers by current application, carriers can also be generated by irradiating with ultraviolet light, and the presence or absence of stacking fault expansion can be confirmed.

[0031] 3 is a table showing the density of point defects formed by helium ion irradiation in the comparative example and the example. As in FIG. 2, FIG. 3 shows the density of point defects formed by helium ion irradiation in the direction from the drift layer 16 to the buffer layer 14 when the helium ion irradiation energy is 3.6 MeV and the helium ion irradiation dose is 1.6×10 10 / cm 2 ~1.6×10 13 / cm 2The maximum density of point defects in the buffer layer 14 is 2×10 16 / cm 3 On the other hand, in Comparative Example 1, where the maximum density of point defects in the buffer layer 14 is less than 2×10 16 / cm 3 In the above-described Examples 1, 2, and Comparative Example 2, the expansion of stacking faults was not confirmed, and it was therefore found that the expansion of stacking faults could be suppressed. 17 / cm 3 In Comparative Example 2, where the maximum density of point defects in the drift layer 16 exceeds 2×10, a decrease in the electrical characteristics (for example, IV characteristics) of the semiconductor device 10 was confirmed. 17 / cm 3 In the following Comparative Example 1, Example 1, and Example 2, no degradation of the electrical characteristics (e.g., IV characteristics) of the semiconductor device 10 was observed. Typical examples of degradation of the electrical characteristics of the semiconductor device 10 include a forward voltage drop due to an increase in resistance value and a degradation of the IV characteristics, but may also include degradation of various other electrical characteristics.

[0032] 2 and 3, the peak of the density distribution of point defects formed by the irradiation of helium ions is located at the interface between the substrate 12 and the buffer layer 14, i.e., at the first surface 12a. However, the peak of the density distribution of point defects may be shifted toward the substrate 12 or toward the buffer layer 14. However, it is preferable that the peak of the density distribution of point defects is not located in the drift layer 16. By locating the peak of the density distribution of point defects at the interface between the substrate 12 and the buffer layer 14 (i.e., the first surface 12a) or in the vicinity thereof (for example, within the substrate 12 located within 2 μm on the substrate 12 side from the interface between the substrate 12 and the buffer layer 14, or within the buffer layer 14 located within 2 μm on the buffer layer 14 side from the interface between the substrate 12 and the buffer layer 14), a high defect density can be formed at the interface between the substrate 12 and the buffer layer 14 while suppressing the irradiation dose of helium ions, and the expansion of stacking faults can be suitably suppressed.

[0033] According to this embodiment, helium ions are irradiated in a direction from drift layer 16 toward buffer layer 14. In this case, compared to an irradiation method in which helium ions are irradiated in a direction from substrate 12 toward buffer layer 14, there is no need to irradiate helium ions so that they pass through thick substrate 12, and therefore the irradiation energy of the helium ions can be reduced to several MeV. As a result, helium ions can be irradiated onto the interface between substrate 12 and buffer layer 14 using a small electrostatic accelerator.

[0034] The density of point defects formed in the buffer layer 14 may be subsequently reduced by an annealing process included in the manufacturing process of the semiconductor device 10. For example, when an annealing process is performed after helium ion irradiation, the annealing process may diffuse or repair the point defects, thereby reducing the density of point defects. In this case, point defects pinned to partial dislocations that border stacking faults remain pinned even after the annealing process. In other words, point defects that diffuse or repair due to the annealing process are not pinned to partial dislocations that border stacking faults, and are therefore considered not to contribute to suppressing the expansion of stacking faults. According to this embodiment, the maximum density of point defects in the buffer layer 14 when the semiconductor device 10 is completed is 2×10 16 / cm 3 Even if the concentration is less than 1000 ppm, the maximum density of point defects formed in the buffer layer 14 after helium ion irradiation is 2×10 16 / cm 3 If the annealing treatment is not performed after the helium ion irradiation, the maximum density of point defects formed in the buffer layer 14 of the semiconductor device 10 is 2×10 16 / cm 3 The above state may be maintained.

[0035] Next, a description will be given of a method for manufacturing the semiconductor device 10. Figures 4 to 8 are cross-sectional views that schematically show the manufacturing process of the semiconductor device 10.

[0036] 4, a buffer layer 14 is formed on the first surface 12a of the substrate 12, and a drift layer 16 is formed on the buffer layer 14. The buffer layer 14 and the drift layer 16 can be formed using any epitaxial growth method such as chemical vapor deposition (CVD). The growth temperature of the buffer layer 14 and the drift layer 16 is, for example, 1500°C or higher and 1700°C or lower.

[0037] Next, as shown in FIG. 4 , helium ions 50 are irradiated from above the drift layer 16 to form point defects in the buffer layer 14. The irradiation of the helium ions 50 can be performed using any ion irradiation device. For example, the helium ions 50 can be irradiated using a cyclotron-type or Van de Graaff-type ion irradiation device. The helium ions 50 may be irradiated from the second surface 12b (back surface) of the substrate 12.

[0038] 5, second impurity ions 52, which are impurities of the second conductivity type, are irradiated from above the drift layer 16 to form the base region 18 and the base contact region 22. The second impurity ions 52 are, for example, aluminum ions. The base region 18 can be formed by irradiating the entire surface of the drift layer 16 with the second impurity ions 52. The base contact region 22 can be formed by irradiating the second impurity ions 52 while masking the region other than the region that will become the base contact region 22.

[0039] 6, first impurity ions 54, which are impurities of the first conductivity type, are irradiated from above the drift layer 16 to form the source region 20. The first impurity ions 54 are, for example, nitrogen ions. The source region 20 can be formed by irradiating the first impurity ions 54 while masking the region other than the region that will become the source region 20 (for example, the base contact region 22).

[0040] Next, an annealing treatment is performed at a first temperature to activate the impurities of the first or second conductivity type implanted into the base region 18, the source region 20, and the base contact region 22. The first temperature is 1500°C or higher, for example, 1600°C or higher and 1800°C or lower. By performing the annealing treatment at the first temperature, point defects that are not anchored to partial dislocations that border extended defects are diffused or recovered, and the maximum density of point defects formed in the buffer layer 14 is reduced to 2×10 16 / cm 3 It may be reduced to less than

[0041] 7, the gate trench 34 is formed. For example, the gate trench 34 can be formed by forming a mask in an area other than the area where the gate trench 34 is to be formed, and dry etching the source region 20, the base region 18, and the drift layer 16 in the opening area of ​​the mask.

[0042] Next, the gate insulating film 24 is formed on the inner wall surface of the gate trench 34. The gate insulating film 24 can be formed, for example, by thermally oxidizing the inner wall surface of the gate trench 34 at a temperature of about 700°C to 1000°C. Next, the gate electrode 26 is formed inside the gate insulating film 24. The gate electrode 26 can be formed using any technique such as CVD.

[0043] 8, an interlayer insulating film 28 is formed on the source region 20, the base contact region 22, the gate insulating film 24, and the gate electrode 26. The interlayer insulating film 28 can be formed using any technique, such as CVD. Subsequently, a drain electrode 32 (rear surface metal electrode layer) is formed on the second surface 12b of the substrate 12. The drain electrode 32 can be formed using any film formation technique, such as sputtering or vapor deposition.

[0044] After the drain electrode 32 is formed, the drain electrode 32 is annealed at a second temperature to bring the drain electrode 32 into ohmic contact with the second surface 12b of the substrate 12. The second temperature is 450°C or higher, for example, 600°C or higher and 800°C or lower.

[0045] 8, a portion of the interlayer insulating film 28 is removed to expose the upper surface 20a of the source region 20 and the upper surface 22a of the base contact region 22. Subsequently, the source electrode 30 (surface metal electrode layer) shown in FIG. 1 is formed. The source electrode 30 can be formed using any film formation technique such as sputtering or vapor deposition.

[0046] After the source electrode 30 is formed, the source electrode 30 is annealed at a third temperature to bring the source electrode 30 into ohmic contact with the source region 20 and the base contact region 22. The third temperature is 300°C or higher, for example, 350°C or higher and 500°C or lower.

[0047] Through the above steps, the semiconductor device 10 shown in FIG. 1 is completed.

[0048] 9 is a flowchart showing an example of a manufacturing method of the semiconductor device 10 according to the embodiment. First, a buffer layer 14 and a drift layer 16 of a first conductivity type are formed on a substrate 12 (S10). Next, helium ions 50 are irradiated to form point defects in the buffer layer 14 (S12). Second conductivity type impurity ions 52 are irradiated to form a base region 18 and a base contact region 22 (S14), and first conductivity type impurity ions 54 are irradiated to form a source region 20 (S16).

[0049] Next, the semiconductor device 10 is annealed at a first temperature of 1500°C or higher (S18) to activate the impurities in the base region 18, the source region 20, and the base contact region 22. Next, a gate trench 34 is formed, and a gate insulating film 24 and a gate electrode 26 are formed in the gate trench 34 (S20). Next, an interlayer insulating film 28 is formed on the gate electrode 26 (S22).

[0050] Next, a backside metal electrode layer (drain electrode 32) is formed on the second surface 12b of the substrate 12 and annealed at a second temperature of 450°C or higher (S24). Next, a portion of the interlayer insulating film 28 is removed (S26), and a frontside metal electrode layer (source electrode 30) is formed on the interlayer insulating film 28 and annealed at a third temperature of 300°C or higher (S28).

[0051] According to this embodiment, the density of point defects formed in the buffer layer 14 by irradiation with helium ions 50 is set to 2×10 16 / cm 3 By doing so, it is possible to suppress the expansion of stacking faults. In particular, it is possible to suppress the upward expansion of stacking faults present in the substrate 12 and the buffer layer 14, and to prevent the stacking faults from reaching the base region 18, the source region 20, and the base contact region 22. This makes it possible to suppress performance degradation of the semiconductor device 10 during use with power applied.

[0052] According to this embodiment, the density of point defects formed in the drift layer 16 by irradiation with helium ions 50 is set to 2×10 17 / cm 3 By setting the following, it is possible to suppress the deterioration of the electrical characteristics of the semiconductor device 10.

[0053] 9, the order of steps S12 to S16 may be reversed. For example, irradiation with second impurity ions 52 in S14 may be followed by irradiation with helium ions 50 in S12, or irradiation with first impurity ions 54 in S16 may be followed by irradiation with helium ions 50 in S12. Furthermore, irradiation with first impurity ions 54 in S16 may be followed by irradiation with second impurity ions 52 in S14.

[0054] 9, irradiation with helium ions 50 in S12 may be performed after annealing at the first temperature in S18. In this case, annealing at the second temperature in S24 can repair lattice defects caused by the irradiation with helium ions 50. The irradiation step with helium ions 50 in S12 may be performed between S18 and S20, between S20 and S22, or between S22 and S24.

[0055] 9, the irradiation of helium ions 50 in S12 may be performed after the annealing treatment at the second temperature in S24. In this case, the irradiation step of helium ions 50 in S12 may be performed between S24 and S26, or between S26 and S28. In this case, the third temperature of the annealing treatment in S28 is low, so that the recovery and diffusion of point defects formed in the buffer layer 14 are suppressed. In this case, when the semiconductor device 10 is completed, the maximum density of point defects in the buffer layer 14 is 2×10 16 / cm 3 The above state may be maintained.

[0056] 9, the order of steps S22 to S28 may be reversed. For example, the interlayer insulating film 28 may be formed in S22 after the back surface metal electrode layer (drain electrode 32) is formed in S24. Alternatively, the step of forming the back surface metal electrode layer (drain electrode 32) in S24 may be performed after the step S26 or after the step S28.

[0057] 10 is a graph showing an example of the density distribution of point defects formed by helium ion irradiation according to a modified example. Fig. 10 shows the case where helium ions are irradiated from the second surface 12b of the substrate 12, that is, the case where helium ions are irradiated in the direction from the substrate 12 toward the buffer layer 14. In Fig. 10, the irradiation energy of the helium ions is 23.1 MeV, and the dose is 1.0 × 10 13 / cm 2 It states that:

[0058] 10, the peak of the point defect density distribution is located approximately 2 μm toward the substrate 12 from the interface between the substrate 12 and the buffer layer 14. The maximum density of point defects in the buffer layer 14 is 3.5×10 17 / cm 3 is the 2×10 16 / cm 3 On the other hand, the density of point defects in the drift layer 16 is 8.0×10 16 / cm 3 is the 2×10 required to avoid degradation of device functionality. 17 / cm3 The following is the result.

[0059] According to this modification, damage to buffer layer 14 can be suppressed and an increase in forward voltage can be suppressed compared to an irradiation method in which helium ions are irradiated in a direction from drift layer 16 toward buffer layer 14 so that they pass through buffer layer 14. Furthermore, since the peak of the point defect density distribution is located within substrate 12, the point defect density in drift layer 16 can be suppressed and deterioration of device function can be more suitably suppressed.

[0060] 11 is a flowchart showing an example of a manufacturing method for semiconductor device 10 according to a modified example. Steps S10 to S22 are similar to those in the flowchart shown in FIG. 9, but differ in that the step of irradiating helium ions 50 in S12 is not included. After step S22, second surface 12b of substrate 12 is polished to reduce the thickness of substrate 12 (S30). For example, the thickness of substrate 12 is changed from approximately 300 μm to 400 μm (e.g., 350 μm) before polishing to approximately 100 μm to 250 μm (e.g., 150 μm to 200 μm) after polishing.

[0061] Next, helium ions 50 are irradiated from the second surface 12b of the substrate 12 to form point defects in the buffer layer 14 (S32). Next, the second surface 12b of the substrate 12 is polished to remove contamination from the second surface 12b of the substrate 12 (S34). The amount (thickness) of the substrate 12 polished in the step S34 may be smaller than the amount (thickness) of the substrate 12 polished in the step S30. The amount (thickness) of the substrate 12 polished in the step S34 may be, for example, 10 μm or less, 5 μm or less, or 1 μm or less. Thereafter, steps S24 to S28 are performed, as in the flowchart shown in FIG. 9. In this way, by irradiating the substrate 12 with helium ions 50 after reducing its thickness, the irradiation energy of the helium ions 50 can be reduced. In the modified example of FIG. 11, as in the flowchart of FIG. 9, the order of the steps may be appropriately changed.

[0062] In the above-described embodiment, the semiconductor device 10 is a MOSFET. However, this embodiment can also be applied to SiC semiconductor devices other than MOSFETs, as long as they have a stacked structure of a substrate, a buffer layer, and a drift layer. For example, the semiconductor device 10 may be a transistor such as a junction field-effect transistor (JFET), a bipolar transistor (BJT), or an insulated gate bipolar transistor (IGBT), or may be a diode such as a Schottky barrier diode or a PIN diode.

[0063] The present invention has been described above based on examples. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that various design changes and modifications are possible, and that such modifications are also within the scope of the present invention. [Explanation of symbols]

[0064] 10...semiconductor device, 12...substrate, 12a...first surface, 12b...second surface, 14...buffer layer, 16...drift layer, 50...helium ions.

Claims

1. irradiating a semiconductor device including a substrate made of silicon carbide, a buffer layer of a first conductivity type on a first surface of the substrate, and a drift layer of the first conductivity type on the buffer layer and having an impurity concentration lower than that of the buffer layer, with helium ions to form point defects in the buffer layer; The density of point defects formed in the buffer layer by the irradiation of helium ions is 2×10 １６ / cm ３ That's all, The density of point defects formed in the drift layer by the irradiation of helium ions is 2×10 １７ / cm ３ Below is the A method for manufacturing a semiconductor device.

2. a peak of a density distribution of point defects formed in the semiconductor device by the irradiation of helium ions is located in the buffer layer; The method for manufacturing a semiconductor device according to claim 1 .

3. a peak of a density distribution of point defects formed in the semiconductor device by the irradiation of helium ions is located within the substrate; The method for manufacturing a semiconductor device according to claim 1 .

4. the helium ions are irradiated in a direction from the drift layer toward the buffer layer. The method for manufacturing a semiconductor device according to claim 1 .

5. the helium ions are irradiated in a direction from the substrate toward the buffer layer; The method for manufacturing a semiconductor device according to claim 1 .

6. further comprising polishing a second surface of the substrate opposite the first surface to reduce the thickness of the substrate; The helium ions are irradiated after reducing the thickness of the substrate. The method for manufacturing a semiconductor device according to claim 5 .

7. a substrate made of silicon carbide; a buffer layer of a first conductivity type provided on a first surface of the substrate; a drift layer of the first conductivity type provided on the buffer layer and having a lower impurity concentration than the buffer layer, The density of point defects formed in the buffer layer is 2×10 １６ / cm ３ That's all, The density of point defects formed in the drift layer is 2×10 １７ / cm ３ Below is the Semiconductor device.

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