Amplifier circuit

Abstract

To provide an amplifier circuit capable of miniaturization and widening bandwidth.SOLUTION: An amplification circuit includes: a first distributor for distributing an input signal to a first signal and a second signal; a first amplifier for amplifying the first signal; a second amplifier for amplifying the second signal; a combiner for combining the first signal and the second signal, and outputting the combined signal as an output signal; and a CRLH line, connected to at least either a first line connecting the first distributor and the first amplifier or a second line connecting the first distributor and the second amplifier, for adjusting a phase of at least the first signal flowing the first line or the second signal flowing the second line.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit. [Background technology]

[0002] 2. Description of the Related Art A load modulated balanced amplifier (LMBA) is known as an amplifier circuit for amplifying high frequency signals such as microwaves (for example, see Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Broadband RF-Input Continuous-Mode Load-Modulated Balanced Power Amplifier With Input Phase Adjustment” Jingzhou Pang et.al. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES Vol.66,No.10 October,2020,pp.4466-4478 Summary of the Invention [Problem to be solved by the invention]

[0004] An amplifier circuit combines multiple signals and outputs them. Adjusting the phase of the combined signal improves efficiency and other characteristics. If the signal phase deviates from the optimum value, the characteristics will deteriorate. A phase adjustment line is provided to adjust the phase.

[0005] However, there is a demand for amplifier circuits with a wider operating band. Therefore, there is also a demand for phase adjustment lines to optimize the phase over a wide band. When a transmission line is used as the phase adjustment line, the line length increases. As a result, the amplifier circuit becomes larger. When the transmission line is made smaller, it becomes difficult to adjust the phase over a wide band. The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide an amplifier circuit that can be made smaller and have a wider band. [Means for solving the problem]

[0006] One embodiment of the present disclosure is an amplifier circuit including a first divider that divides an input signal into a first signal and a second signal, a first amplifier that amplifies the first signal, a second amplifier that amplifies the second signal, a combiner that combines the first signal and the second signal and outputs the combined signal as an output signal, and a CRLH line that is connected to at least one of a first line that connects the first divider and the first amplifier and a second line that connects the first divider and the second amplifier, and that adjusts the phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide an amplifier circuit that can be made smaller and have a wider bandwidth. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 1A is a circuit diagram illustrating an amplifier circuit according to the first embodiment. [Figure 1B] FIG. 1B is a diagram illustrating an FET. [Figure 2A] FIG. 2A is a diagram illustrating phase dispersion. [Figure 2B] FIG. 2B is a diagram illustrating the phase of a signal. [Figure 2C] FIG. 2C is a diagram illustrating the phase of a signal. [Figure 3]FIG. 3 is a circuit diagram illustrating an amplifier circuit according to the second embodiment. [Figure 4] FIG. 4 is a circuit diagram illustrating an amplifier circuit according to the third embodiment. [Figure 5] FIG. 5 is a circuit diagram illustrating an amplifier circuit according to a comparative example. [Figure 6A] FIG. 6A is a diagram illustrating the phase. [Figure 6B] FIG. 6B is a diagram illustrating the drain efficiency. [Figure 6C] FIG. 6C is a plan view illustrating an example of a transmission line. [Figure 6D] FIG. 6D is a plan view illustrating one CRLH line. [Figure 7] FIG. 7 is a circuit diagram illustrating an amplifier circuit according to the fourth embodiment. [Figure 8] FIG. 8 is a circuit diagram illustrating an amplifier circuit according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is an amplifier circuit including a first divider that divides an input signal into a first signal and a second signal, a first amplifier that amplifies the first signal, a second amplifier that amplifies the second signal, a combiner that combines the first signal and the second signal and outputs the combined signal as an output signal, and a CRLH line connected to at least one of a first line connecting the first divider and the first amplifier and a second line connecting the first divider and the second amplifier, and that adjusts the phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line. The CRLH line enables signal phase adjustment over a wide band. Furthermore, the line length does not need to be long. This allows for a smaller amplifier circuit and a wider bandwidth. (2) In the above (1), the combiner may be a load modulation circuit that modulates the load of the second amplifier, and the amplifier circuit may be a load modulation balanced amplifier. This makes it possible to reduce the size and broaden the bandwidth of the load modulation balanced amplifier. (3) In the above (2), a second divider may be provided on the second line, the second divider divides the second signal into a third signal and a fourth signal, the second amplifier includes a third amplifier and a fourth amplifier, the third amplifier amplifies the third signal, and the fourth amplifier amplifies the fourth signal, and the CRLH line may be connected to at least one of the first line and the second line between the first divider and the second divider. This allows the load modulation balanced amplifier to be made smaller and have a wider bandwidth. (4) In the above (3), the combiner may have a first terminal, a second terminal, a third terminal, and a fourth terminal, the third signal amplified by the third amplifier may be input to the first terminal, the fourth signal amplified by the fourth amplifier may be input to the second terminal, the first signal amplified by the first amplifier may be input to the third terminal, and the output signal may be output from the fourth terminal. The CRLH line makes the phase of the signals when combined in the combiner closer to the optimum. The amplifier circuit can be made wider bandwidth. (5) In the above (3) or (4), a plurality of the CRLH lines may be provided, and the plurality of CRLH lines may be connected to at least one of the first line and the second line between the first divider and the second divider. This enables miniaturization and broadbanding of the amplifier circuit. (6) In the above (5), the number of the plurality of CRLH lines may be three or more, which allows the amplifier circuit to be made smaller and have a wider bandwidth. (7) In any of (1) to (6) above, the CRLH line may have a first inductor, a first capacitor, a second inductor, and a second capacitor, and when the CRLH line is provided on the first line, the first inductor and the first capacitor may be connected in series to the first line, and the second inductor and the second capacitor may be connected in shunt between the first capacitor and the first amplifier, and when the CRLH line is provided on the second line, the first inductor and the first capacitor may be connected in series to the second line, and the second inductor and the second capacitor may be connected in shunt between the first capacitor and the second amplifier. Because the first capacitor has a DC blocking function, the amplifier circuit can be made smaller. (8) In the above (7), the second inductor may be connected to a bias power supply, and when the CRLH line is provided on the first line, the bias power supply may supply a bias voltage to the first amplifier, and when the CRLH line is provided on the second line, the bias power supply may supply a bias voltage to the second amplifier. Since there is no need to provide a separate bias circuit, the amplifier circuit can be made smaller. (9) In any of the above (1) to (8), the CRLH line may include two CRLH lines, that is, a first CRLH line and a second CRLH line, and the first line may be provided with the first CRLH line and the second line may be provided with the second CRLH line. The phases of the first signal and the second signal can be adjusted. [Details of the embodiments of the present disclosure] Specific examples of amplifier circuits according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0010] First Embodiment 1A is a circuit diagram illustrating an amplifier circuit 100 according to a first embodiment. The amplifier circuit 100 amplifies a signal Si input from an input terminal Tin and outputs an output signal So from an output terminal Tout. The signal So is a high-frequency signal. The frequency of the high-frequency signal is, for example, not less than 0.5 GHz and not more than 10 GHz.

[0011] A divider 10 (first divider) is connected to an input terminal Tin. An amplifier 11 (first amplifier) ​​is connected to one output terminal of the divider 10. An amplifier 13 (second amplifier) ​​is connected to the other output terminal of the divider 10.

[0012] The amplifiers 11 and 13 are, for example, field effect transistors (FETs). The FETs are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). FIG. 1B is a diagram illustrating an example of a FET. As shown in FIG. 1B, in the amplifiers 11 and 13, the sources of the FETs are grounded and a bias voltage is applied to the gates. A high-frequency signal is input to the gates and output from the drains. Each of the amplifiers 11 and 13 may have multiple stages of FETs.

[0013] The amplifier 11 is connected to one input terminal of the combiner 17. The amplifier 13 is connected to the other input terminal of the combiner 17. The output terminal of the combiner 17 is connected to the output terminal Tout.

[0014] The line between the divider 10 and the amplifier 11 is referred to as a line 12 (first line), and the line between the divider 10 and the amplifier 13 is referred to as a line 14 (second line).

[0015] A bias circuit 16 is provided on the line 12. The bias circuit 16 has a bias power supply Vgc, an inductor La, a capacitor Ca, and a capacitor Cb. The capacitor Ca is connected in series between the divider 10 and the amplifier 11. One end of the inductor La is connected between the capacitor Ca and the amplifier 11. The bias power supply Vgc is connected to the other end of the inductor La. One end of the capacitor Cb is connected between the inductor La and the bias power supply Vgc. The other end of the capacitor Cb is grounded. The bias power supply Vgc is a DC power supply. A bias voltage is supplied to the amplifier 11 from the bias circuit 16.

[0016] A CRLH (Composite Right / Left-Handed Transmission Line) 18 is provided on the line 14. The CRLH line 18 has an inductor L1 (first inductor), an inductor L2 (second inductor), a capacitor C1 (first capacitor), and a capacitor C2 (second capacitor). As will be described later, the capacitors and inductors in the CRLH line 18 are, for example, chip components.

[0017] An inductor L1 and a capacitor C1 are connected in series, in this order, between the divider 10 and the amplifier 13. An inductor L2 and a capacitor C2 are shunt-connected between the capacitor C1 and the amplifier 13. One end of the capacitor C2 is connected between the capacitor C1 and the amplifier 13. The other end of the capacitor C2 is grounded.

[0018] One end of inductor L2 is connected to a position on the line between capacitor C1 and amplifier 13, closer to the divider 10 than the position where capacitor C2 is connected. A bias power supply Vgb is connected to the other end of inductor L2. The bias power supply Vgb is a DC power supply and supplies a bias voltage to the amplifier 13. One end of capacitor C3 is connected between inductor L2 and bias power supply Vgb. The other end of capacitor C3 is grounded. Capacitor C3 grounds the bias power supply Vgb in a high-frequency sense, making it difficult for high-frequency signals to flow to the bias power supply Vgb. The bias power supply Vgb of the CRLH line 18 supplies a bias voltage to the amplifier 13.

[0019] The capacitances of the capacitors C1 and C2 are denoted as C1 and C2. The inductances of the inductors L1 and L2 are denoted as L1 and L2. The characteristic impedance Z0 of the CRLH line 18 is expressed by the following equation 1.

number

[0020] A signal Si is input from an input terminal Tin. A distributor 10 divides the signal Si into a signal Si1 (first signal) and a signal Si2 (second signal). The signal Si1 propagates through a line 12, is amplified by an amplifier 11, and is input to a combiner 17. The signal Si2 propagates through a line 14, passes through a CRLH line 18, is amplified by an amplifier 13, and is input to the combiner 17. The CRLH line 18 adjusts the phase of the signal Si2. The combiner 17 combines the signals Si1 and Si2 and outputs the combined signal as a signal So to an output terminal Tout.

[0021] By bringing the signal phase closer to the optimum value when combined in the combiner 17, characteristics such as efficiency improve. However, in high-frequency circuits, signal phase delay can be a problem. When the phase deviates from the optimum value, characteristics such as efficiency deteriorate. The optimum phase when combined differs depending on the frequency. To widen the operating band of the amplifier circuit 100, the phase of the combined signal is optimized over a wide band.

[0022] FIG. 2A is a diagram illustrating phase dispersion. The horizontal axis represents the phase of the signal when it passes through the line. The vertical axis represents the frequency of the signal. In FIG. 2A, the dashed line represents the phase dispersion of the right-handed line. The dotted line represents the phase dispersion of the left-handed line. The solid line represents the phase dispersion of CRLH line 18. The phase dispersion of the right-handed line is linear. The phase dispersion of the left-handed line is nonlinear. The phase dispersion of CRLH line 18 is a combination of the characteristics of the right-handed line and the characteristics of the left-handed line, and has both nonlinear and linear parts.

[0023] In a right-handed transmission line, the phase dispersion is linear, so it is difficult to optimize the signal delay for each frequency. To change the gradient of the phase dispersion, the transmission line can be made longer. However, this increases the size of the circuit.

[0024] 2B and 2C are diagrams illustrating the phase of a signal. FIG. 2B is an example of a right-handed line. FIG. 2C is an example of a CRLH line 18. The horizontal axis of FIGS. 2B and 2C represents the frequency of the signal. The vertical axis represents the phase of the signal after passing through the line. The phase of the signal is illustrated at frequencies from 0 GHz to 16 GHz.

[0025] In the example of FIG. 2B, the phase change is linear across the entire frequency band in the figure. It is difficult to optimize the signal phase for each frequency. In the example of FIG. 2C, frequencies higher than approximately 9 GHz are in the linear portion, where the phase changes linearly. Frequencies lower than approximately 9 GHz are in the nonlinear portion, where the phase change is nonlinear. By changing the capacitance and inductance in the CRLH line 18, the slope of the linear portion can be adjusted, and the curve of the nonlinear portion can be adjusted. The phase can be optimized across the frequency band.

[0026] According to the first embodiment, the CRLH line 18 is provided on the line 14 connecting the divider 10 and the amplifier 13. As shown in FIG. 2A , the phase dispersion of the CRLH line 18 includes a nonlinear portion, allowing for a high degree of freedom in phase design. By setting appropriate values ​​for the capacitance, inductance, and other parameters of the CRLH line 18, desired phase characteristics can be obtained over a wide bandwidth. By adjusting the signal phase using the CRLH line 18, the phase of the combined signal can be brought closer to the optimum over a wide bandwidth. Furthermore, the line length of the CRLH line 18 does not need to be increased in order to optimize the phase. This allows for a smaller amplifier circuit 100. This allows for a smaller amplifier circuit 100 and a wider bandwidth.

[0027] The operating band of the amplifier circuit 100 is, for example, 0.5 GHz or more, 1 GHz or more, 1.5 GHz or more, or 2 GHz or more. In these bands, the phase of the combined signal should be brought close to the optimum value.

[0028] It is sufficient to provide the CRLH line 18 on at least one of the line 12 and the line 14. As in the example of FIG. 1A, the CRLH line 18 may be provided on the line 14. As in the example of FIG. 8 described below, the CRLH line 18 may be provided on both the line 12 and the line 14.

[0029] Parasitic components are also taken into consideration in the design of CRLH line 18. For example, a left-handed line having capacitor C1 and inductor L2 is designed, and CRLH line 18 is designed with the parasitic components occurring in the left-handed line as inductor L1 and capacitor C2.

[0030] The CRLH line 18 includes a capacitor C1, a capacitor C2, an inductor L1, and an inductor L2. The capacitor C1 is connected in series to the line 14 between the divider 10 and the amplifier 13, and blocks DC signals. This eliminates the need to provide a separate capacitor for DC blocking on the line 14. This allows the amplifier circuit 100 to be made smaller.

[0031] A bias power supply Vgb is connected to the inductor L2 of the CRLH line 18. A bias voltage is supplied from the bias power supply Vgb to the amplifier 13. Since there is no need to provide a separate bias circuit for the line 14, the amplifier circuit 100 can be made smaller. The order of connections in the CRLH line 18 may be changed so that the capacitor C1 is located near the divider 10 and the inductor L1 is located near the amplifier 13.

[0032] Second Embodiment (LMBA) 3 is a circuit diagram illustrating an amplifier circuit 200 according to the second embodiment. The amplifier circuit 200 is a load modulated balanced amplifier (LMBA). Description of the same configuration as in the first embodiment will be omitted. The amplifier circuit 200 is used in, for example, a base station for mobile communications.

[0033] The amplifier circuit 200 includes a divider 10 (first divider), an amplifier 11 (first amplifier), a matching circuit 20, a CRLH line 18, a divider 22 (second divider), an amplifier 13a (third amplifier), an amplifier 13b (fourth amplifier), and a load modulation circuit 24 (combiner). The amplifier 11, the amplifier 13a, and the amplifier 13b are connected in parallel between an input terminal Tin and an output terminal Tout.

[0034] The amplifier 11 is a control amplifier. The amplifier 11 is connected to one output terminal of the distributor 10. The line between the distributor 10 and the amplifier 11 is referred to as a line 12 (first line). The line 12 is provided with a bias circuit 16-1. The bias circuit 16-1 supplies bias power to the amplifier 11.

[0035] The amplifiers 13a and 13b are balanced amplifiers. A line 14 (second line) extends from the divider 10 to the amplifiers 13a and 13b. A CRLH line 18 and a divider 22 are provided on the line 14.

[0036] The divider 22 is, for example, a hybrid coupler and has terminals 22a, 22b, 22c, and 22d. Terminals 22a and 22d are diagonal terminals. Terminals 22b and 22c are diagonal terminals. Terminal 22a of the divider 22 is connected to the output terminal of the divider 10. A CRLH line 18 is connected between the divider 10 and terminal 22a of the divider 22. The CRLH line 18 in the second embodiment has capacitors C1 and C2, and inductors L1 and L2, but does not have a bias power supply or capacitor C3. Terminal 22b of the divider 22 is terminated by a reference load Ro. An amplifier 13a is connected to terminal 22c. An amplifier 13b is connected to terminal 22d.

[0037] A bias circuit 16-2 is connected between terminal 22c of the divider 22 and amplifier 13a. A bias circuit 16-3 is connected between terminal 22d and amplifier 13b. Bias circuit 16-2 supplies bias power to amplifier 13a. Bias circuit 16-3 supplies bias power to amplifier 13b. In FIG. 3, bias circuits 16-1, 16-2, and 16-3 are illustrated as blocks. Each of these bias circuits has the same configuration as bias circuit 16 in FIG. 1.

[0038] The load modulation circuit 24 is, for example, a hybrid coupler, and has a terminal 24a (first terminal), a terminal 24b (second terminal), a terminal 24c (third terminal), and a terminal 24d (fourth terminal). The terminals 24a and 24d are diagonal terminals. The terminals 24b and 24c are diagonal terminals. The amplifier 13a is connected to the terminal 24a. The amplifier 13b is connected to the terminal 24b.

[0039] The amplifier 11 is connected to the terminal 24c. A matching circuit 20 is provided between the amplifier 11 and the terminal 24c. The matching circuit 20 matches the impedance seen from the amplifier 11 at the matching circuit 20 with the impedance seen from the matching circuit 20 at the load modulation circuit 24. The output terminal Tout is connected to the terminal 24d. The output terminal Tout is grounded via a load resistance RL. The load resistance RL is, for example, 50 Ω.

[0040] A signal Si is input from an input terminal Tin. A divider 10 divides the signal Si into a signal Si1 (first signal) and a signal Si2 (second signal). The signal Si1 propagates through a line 12 and is amplified by an amplifier 11. The amplified signal Si1 passes through a matching circuit 20 and is output to a terminal 24c of a load modulation circuit 24.

[0041] The signal Si2 passes through the CRLH line 18 and is output to the terminal 22a of the divider 22. The divider 22 divides the signal Si2 into a signal Si2a (third signal) and a signal Si2b (fourth signal). The phase of the signal Si2b lags behind the phase of the signal Si2a by 90°.

[0042] The signal Si2a is output from the terminal 22c and is amplified by the amplifier 13a. The amplified signal Si2a is output to the terminal 24a of the load modulation circuit 24. The signal Si2b is output from the terminal 22d and is amplified by the amplifier 13b. The amplified signal Si2b is output to the terminal 24b of the load modulation circuit 24. The output signal So is output from the terminal 24d of the load modulation circuit 24 to the output terminal Tout.

[0043] Amplifier 11 operates in class AB or class B. Amplifiers 13a and 13b operate in class C. When the power of input signal Si is small, amplifier 11 mainly amplifies input signal Si. When the power of input signal Si is large, amplifier 11, amplifier 13a, and amplifier 13b amplify the peaks of input signal Si. As a result, amplifier 11, amplifier 13a, and amplifier 13b amplify input signal Si.

[0044] When the power of the input signal Si is low and the amplifiers 13a and 13b are not operating, the signal Si1 input to the load modulation circuit 24 from the terminal 24c is split into two signals Si1a and distributed to the terminals 24a and 24b. The phase of the signal Si1a propagating from the terminal 24c to the terminal 24b lags behind the phase of the signal Si1a propagating to the terminal 24a by 90°. The signal Si1a is reflected at the terminals 24a and 24b. The phase of the signal Si1a reflected at the terminal 24a lags behind the phase of the signal Si1a reflected at the terminal 24b by 90°. The phases of the two signals Si1a are aligned at the terminal 24d. The two signals Si1a are combined at the terminal 24d. The combined signal is output to the output terminal Tout as the output signal So. The reflection coefficient of the load modulation circuit 24 seen from the amplifiers 13a and 13b is greater than 1, and the load impedance of the amplifiers 13a and 13b is substantially high.

[0045] When the power of the input signal Si is high and the amplifiers 13a and 13b are operating, the phase of the signal Si2b amplified by the amplifier 13b lags behind the phase of the signal Si2a amplified by the amplifier 13a by 90°. The CRLH line 18 adjusts the phase of the signal Si2. At the terminal 24a of the load modulation circuit 24, the signals Si1a and Si2a are aligned in phase. At the terminal 24b, the signals Si1a+Si2a combined at the terminal 24a and the signal Si1a+Si2b combined at the terminal 24b are combined at the terminal 24d. The combined signal at the terminal 24d is output as the output signal So.

[0046] In this case, the reflection coefficient of load modulation circuit 24 as seen from amplifiers 13a and 13b is less than 1, and decreases as the amplitudes of signals Si2a and Si2b increase. As a result, the load impedance of amplifiers 13a and 13b is effectively reduced. Load modulation circuit 24 modulates the load impedance as seen from amplifiers 13a and 13b depending on the amplitudes of signals Si2a and Si2b.

[0047] As an example different from the above-described operation example, amplifiers 13a and 13b may operate in class AB or class B. Amplifier 11 may operate in class C. When the power of input power Si is small, amplifiers 13a and 13b mainly amplify input signal Si. When the power of input signal Si is large, amplifiers 11, 13a, and 13b amplify the peaks of input signal Si. As a result, amplifiers 11, 13a, and 13b amplify input signal Si.

[0048] Harmonic processing circuits may be provided between amplifier 11 and matching circuit 20, between amplifier 13a and load modulation circuit 24, and between amplifier 13b and load modulation circuit 24. The harmonic processing circuits suppress harmonic components such as double wave components in the signal.

[0049] According to the second embodiment, the amplifier circuit 200 is an LMBA and operates over a wide bandwidth. The amount of phase delay of a high-frequency signal varies depending on the frequency. To achieve a wider bandwidth, the signal phase can be optimized for each frequency. As shown in FIG. 3, the amplifier circuit 200 has a CRLH line 18. As shown in FIG. 2A, the phase dispersion of the CRLH line 18 includes a nonlinear portion, providing a high degree of freedom in phase design. The CRLH line 18 can be used to optimize the phase over a wide bandwidth. The line length of the CRLH line 18 does not need to be long. The amplifier circuit 200 can be made smaller and have a wider bandwidth.

[0050] The amplifier circuit 200 is an LMBA and is used, for example, in a mobile communication base station. The LMBA can widen the operating band compared to a Doherty amplifier circuit. According to the second embodiment, the LMBA can further widen the operating band by adjusting the phase over a wide band.

[0051] In the example of FIG. 3, a CRLH line 18 is provided on the line 14 between the divider 10 and the divider 22. The CRLH line 18 adjusts the phase of the signal Si2. The phase-adjusted signal Si2 is divided by the divider 22. The divided signals Si2a and Si2b are combined. In a wide band, the phase of the combined signal can be made closer to the optimum. In a wide band, the characteristics of the amplifier circuit 200, such as drain efficiency, are improved.

[0052] As shown in Fig. 3, a CRLH line 18 is provided in a stage preceding the amplifiers 13a and 13b. The signal before amplification propagates through the CRLH line 18, and the phase is adjusted. The phase-adjusted signal is amplified. The amplified signal is not lost by the CRLH line 18.

[0053] The amplifier circuit 200 has a load modulation circuit 24. A signal Si2a is input to a terminal 24a of the load modulation circuit 24. A signal Si2b is input to a terminal 24b. A signal Si1 is input to a terminal 24c. The load modulation circuit 24 combines the signals and outputs an output signal So. The CRLH line 18 allows the combined signal phase to approach an optimum in a wide band. The bandwidth of the amplifier circuit 200 can be widened.

[0054] The CRLH line 18 includes a capacitor C1, a capacitor C2, an inductor L1, and an inductor L2. The capacitor C1 is connected in series to the line 14 between the divider 10 and the divider 22, and blocks DC signals. This eliminates the need to provide a separate capacitor for DC blocking on the line 14. This allows the amplifier circuit 200 to be miniaturized.

[0055] <Third embodiment> FIG. 4 is a circuit diagram illustrating an amplifier circuit 300 according to the third embodiment. The amplifier circuit 300 has three CRLH lines. In FIG. 4, the CRLH line of one cell is illustrated as one block. Descriptions of the same configuration as in the first or second embodiment will be omitted.

[0056] As shown in Fig. 4, the line 14 is provided with CRLH lines 18-1, 18-2, and 18-3 in order from the side closest to the divider 10. Each CRLH line has a series-connected inductor L1 and capacitor C1, and a shunt-connected inductor L2 and capacitor C2, similar to the CRLH line 18 in Fig. 2. The three CRLH lines are designed so that the phase is optimized.

[0057] (Comparative Example) 5 is a circuit diagram illustrating an amplifier circuit 110 according to a comparative example. The amplifier circuit 110 does not have a CRLH line, but has a transmission line 19. The transmission line 19 is, for example, a microstrip line, and is provided on the line 14.

[0058] FIG. 6A is a diagram illustrating phase, where the signal phase for each frequency is calculated in the comparative example and the third embodiment. The horizontal axis represents the signal frequency. The vertical axis represents the signal phase after passing through the line. The dashed line represents the comparative example. The phase delay amount in transmission line 19 of the comparative example is approximately 130°. The solid line represents the third embodiment. In each of the CRLH lines, L1 = 0.7 nH, L2 = 1.4 nH, C1 = 0.56 pF, and C2 = 0.28 pF. The characteristic impedance of each CRLH line is 50 Ω. The dots in FIG. 6A represent the optimal phase when the signal frequencies are 3.2 GHz, 3.7 GHz, and 4.2 GHz.

[0059] In the comparative example, the phase of a 3.7 GHz signal can be optimized. However, the phase deviates from the optimum value at frequencies lower and higher than 3.7 GHz. The farther the frequency is from 3.7 GHz, the greater the deviation from the optimum phase. By setting the phase delay amount of the transmission line 19 to 490°, the phase can be optimized across the band from 3.2 GHz to 4.2 GHz. However, the transmission line 19 becomes longer, and the amplifier circuit 110 becomes larger.

[0060] As shown in Fig. 6A, in the third embodiment, by using three CRLH lines, the signal phase can be optimized over the band from 3.2 GHz to 4.2 GHz. The three-cell CRLH line is shorter than the 490° transmission line 19. Therefore, the amplifier circuit 300 can be made smaller.

[0061] FIG. 6B is a diagram illustrating drain efficiency. The horizontal axis represents the power Pout of the signal amplified by amplifier 13a and amplifier 13b. The vertical axis represents the drain efficiency DE of the amplifier. The signal frequency ranges from 3.2 GHz to 4.2 GHz. Circles and solid lines represent an example of a frequency of 3.2 GHz. Diamonds and dotted lines represent an example of a frequency of 3.4 GHz. Triangles and dashed lines represent an example of a frequency of 3.6 GHz. Squares and dashed lines represent an example of a frequency of 3.8 GHz. Double circles and dashed lines represent an example of a frequency of 4.0 GHz. An asterisk and solid line represent an example of a frequency of 4.2 GHz.

[0062] At all frequencies, the drain efficiency increases as the power increases. By optimizing the signal phase in the range of 3.2 GHz to 4.2 GHz as shown in Figure 6A, the drain efficiency improves as shown in Figure 6B. According to the third embodiment, it is possible to achieve both improved drain efficiency and a smaller amplifier circuit 300.

[0063] FIG. 6C is a plan view illustrating transmission line 19. Wiring pattern 32 is provided on the surface of substrate 30. Substrate 30 includes, for example, a dielectric. A ground pattern (not shown) is provided on the back surface of substrate 30 at a position overlapping wiring pattern 32. Substrate 30, wiring pattern 32, and ground pattern form transmission line 19 (microstrip line). The length of transmission line 19 is X1. If the phase delay amount is 130°, length X1 is 23 mm. However, adjusting the phase is difficult. If the phase delay amount is 490°, length X1 is 71 mm. The transmission line 19 becomes longer, and the amplifier circuit 110 becomes larger.

[0064] FIG. 6D is a plan view illustrating one CRLH line 18. A wiring pattern 34, multiple wiring patterns 35, and multiple chip components 36 are provided on a substrate 30. In the example of FIG. 6D, the chip components 36 are shaded. The wiring pattern 34, together with a ground pattern (not shown), forms a microstrip line. This microstrip line corresponds, for example, to the line 14 in FIG. 5. The multiple wiring patterns 35 are spaced apart from each other and from the wiring pattern 34. Chip components 36 are connected to the multiple wiring patterns 35. The chip components 36 and parasitic components correspond to the inductors or capacitors of the CRLH line 18. The length X2 of the CRLH line 18 is, for example, 13 mm. The total length of the three CRLH lines is approximately 39 mm.

[0065] According to the third embodiment, three CRLH lines are provided on the line 14 of the amplifier circuit 300. As shown in FIG. 6A, the phase can be optimized over a wide band of, for example, about 1 GHz. For example, three CRLH lines can be provided instead of the transmission line 19 with a delay of 490°. Compared to the example in which the transmission line 19 is provided, the amplifier circuit 300 can be made more compact.

[0066] The number of CRLH lines provided on the line 14 may be two, three or more, four or more, or five or more. The phase can be adjusted over a wide band of 1 GHz or more.

[0067] <Fourth embodiment> 7 is a circuit diagram illustrating an amplifier circuit 400 according to the fourth embodiment. A CRLH line 18 is provided on the line 12. No CRLH line is provided on the line 14.

[0068] According to the fourth embodiment, the CRLH line 18 is provided on the line 12, so the phase of the signal Si1 is adjusted. The phase of the signal when combined can be made closer to the optimum in a wide band. The amplifier circuit 400 can be made smaller and have a wider band.

[0069] A plurality of CRLH lines may be provided on the line 12. For example, by providing three CRLH lines on the line 12, it is possible to bring the phase close to the optimum value in the 1 GHz band as shown in FIG.

[0070] A capacitor C1 is provided on the line 12. The capacitor C1 has a DC blocking function. There is no need to provide a separate capacitor for DC blocking on the line 12. The amplifier circuit 400 can be made smaller.

[0071] A bias power supply Vgc is connected to the inductor L2 of the CRLH line 18. The bias power supply Vgc supplies a bias voltage to the amplifier 11. Since there is no need to provide a separate bias circuit for the line 12, the amplifier circuit 400 can be made smaller.

[0072] Fifth Embodiment 8 is a circuit diagram illustrating an amplifier circuit 500 according to a fifth embodiment. The amplifier circuit 500 has a CRLH line 18a (first CRLH line) and a CRLH line 18b (second CRLH line). The CRLH line 18a is provided on the line 12.

[0073] The CRLH line 18a includes a capacitor C1a, a capacitor C2a, a capacitor C3a, an inductor L1a, and an inductor L2a. A bias power supply Vgc is connected to the inductor L2a. The CRLH line 18b includes a capacitor C1b, a capacitor C2b, an inductor L1b, and an inductor L2b.

[0074] According to the fifth embodiment, the CRLH line 18a is provided on the line 12, so the phase of the signal Si1 is adjusted. The CRLH line 18b is provided on the line 14, so the phase of the signal Si2 is adjusted. The phase of the signals when combined can be made closer to the optimum in a wide band. The amplifier circuit 500 can be made smaller and have a wider band.

[0075] As shown in the second to fifth embodiments, a CRLH line is provided on at least one of the line 12 and the line 14. In the example of Fig. 8, a CRLH line is provided on both the line 12 and the line 14. This allows the amplifier circuit 500 to be miniaturized as follows.

[0076] Capacitor C1a of CRLH line 18a is connected in series to line 12 and functions as a DC block. CRLH line 18a has a bias power supply Vgc. A bias voltage is supplied to amplifier 11 from bias power supply Vgc of CRLH line 18a. It is not necessary to provide a capacitor for DC blocking and a bias circuit on line 12 separate from CRLH line 18a. Capacitor C1b of CRLH line 18b is connected in series to line 14 and functions as a DC block. It is not necessary to provide a capacitor for DC blocking on line 14 separate from capacitor C1b. The amplifier circuit 500 can be made smaller.

[0077] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0078] 10, 22 distributor 11, 13, 13a, 13b Amplifiers 12, 14 tracks 16, 16-1, 16-2, 16-3 bias circuit 17 Synthesizer 18, 18-1, 18-2, 18-3 CRLH tracks 19 Transmission Lines 20 Matching circuit 22a, 22b, 22c, 22d, 24a, 24b, 24c, 24d ends 24 Load modulation circuit 30 boards 32, 34, 35 Wiring patterns 36 Chip parts 100, 110, 200, 300, 400, 500 Amplification circuit

Claims

1. a first divider that divides an input signal into a first signal and a second signal; a first amplifier for amplifying the first signal; a second amplifier for amplifying the second signal; a combiner that combines the first signal and the second signal and outputs the combined signal as an output signal; a CRLH line connected to at least one of a first line connecting the first divider and the first amplifier and a second line connecting the first divider and the second amplifier, and adjusting the phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line.

2. the combiner is a load modulation circuit that modulates the load of the second amplifier; 2. The amplifier circuit of claim 1, wherein the amplifier circuit is a load modulation balanced amplifier.

3. a second divider provided on the second line, the second divider divides the second signal into a third signal and a fourth signal; the second amplifier includes a third amplifier and a fourth amplifier; the third amplifier amplifies the third signal; the fourth amplifier amplifies the fourth signal; 3. The amplifier circuit according to claim 2, wherein the CRLH line is connected to at least one of the first line and the second line between the first divider and the second divider.

4. the combiner has a first end, a second end, a third end, and a fourth end; the third signal amplified by the third amplifier is input to the first terminal; the fourth signal amplified by the fourth amplifier is input to the second terminal; the first signal amplified by the first amplifier is input to the third terminal; The amplifier circuit according to claim 3 , wherein the output signal is output from the fourth terminal.

5. A plurality of the CRLH lines are provided, 5. The amplifier circuit according to claim 3, wherein the plurality of CRLH lines are connected to at least one of the first line and the second line between the first divider and the second divider.

6. 6. The amplifier circuit according to claim 5, wherein the number of the plurality of CRLH lines is three or more.

7. the CRLH line includes a first inductor, a first capacitor, a second inductor, and a second capacitor; When the CRLH line is provided on the first line, the first inductor and the first capacitor are connected in series to the first line, and the second inductor and the second capacitor are connected in shunt between the first capacitor and the first amplifier; 3. The amplifier circuit according to claim 1, wherein, when the CRLH line is provided on the second line, the first inductor and the first capacitor are connected in series to the second line, and the second inductor and the second capacitor are connected in shunt between the first capacitor and the second amplifier.

8. the second inductor is connected to a bias power supply; When the CRLH line is provided on the first line, the bias power supply supplies a bias voltage to the first amplifier; 8. The amplifier circuit according to claim 7, wherein the bias power supply supplies a bias voltage to the second amplifier when the CRLH line is provided on the second line.

9. The CRLH line includes two CRLH lines, a first CRLH line and a second CRLH line, the first CRLH line is provided on the first line, 3. The amplifier circuit according to claim 1, wherein the second line is provided with the second CRLH line.

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