Memory device

Abstract

To provide a memory device capable of executing efficient reading operations.SOLUTION: A memory device of an embodiment includes a plurality of memory cells, a word line, and a controller. Each of the plurality of memory cells stores 5 bit data including first to fifth bit data according to a threshold voltage. The plurality of memory cells stores first to fifth pages including the first to fifth bit data, respectively. The word line is connected to the plurality of memory cells. The controller executes reading operations for reading data from the plurality of memory cells by applying the reading voltage to the word line. The number of times the controller applies different read voltages to the word lines in the respective reading operations of the first to fifth pages is 7, 6, 6, 6, and 6, respectively.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4892307 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a memory device capable of executing an efficient read operation. [Means for solving the problem]

[0005] The memory device of the embodiment includes a plurality of memory cells, word lines, and a controller. Each of the plurality of memory cells stores 5-bit data including first, second, third, fourth, and fifth bit data according to a threshold voltage. The plurality of memory cells store a first page, a second page, a third page, a fourth page, and a fifth page, each including the first, second, third, fourth, and fifth bit data, respectively. The word lines are connected to the plurality of memory cells. The controller performs a read operation. The threshold voltages of the memory cells are included in one of different 0th to 31st states. Different 5-bit data are assigned to each of the 0th to 31st states. First to 31st read voltages are set in order from lowest to highest corresponding to adjacent states among the 0th to 31st states. In a first page read operation, the controller performs six read operations by applying the 7th read voltage, the 15th read voltage, the 18th read voltage, the 22nd read voltage, the 25th read voltage, and the 29th read voltage to the word line, respectively. In a second page read operation, the controller performs six read operations by applying the 4th read voltage, the 8th read voltage, the 13th read voltage, the 21st read voltage, the 27th read voltage, and the 31st read voltage to the word line, respectively. In a third page read operation, the controller performs six read operations by applying the 3rd read voltage, the 9th read voltage, the 12th read voltage, the 16th read voltage, the 20th read voltage, and the 26th read voltage to the word line, respectively. In a fourth page read operation, the controller performs seven read operations by applying the 2nd read voltage, the 6th read voltage, the 10th read voltage, the 14th read voltage, the 19th read voltage, the 23rd read voltage, and the 28th read voltage to the word line, respectively. In the read operation of the fifth page, the controller performs six reads by applying the first read voltage, the fifth read voltage, the eleventh read voltage, the seventeenth read voltage, the twenty-fourth read voltage, and the thirtieth read voltage to the word line, respectively. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the hardware configuration of a memory controller according to the first embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the hardware configuration of the memory device according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. [Figure 5] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in the memory device according to the first embodiment. [Figure 6] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the memory device according to the first embodiment. [Figure 7] FIG. 2 is a schematic diagram showing an example of threshold voltage distributions of memory cell transistors in the memory device according to the first embodiment. [Figure 8] 4 is a table showing data allocation and read voltage settings used in the memory device according to the first embodiment. [Figure 9] 6 is a timing chart showing an example of a first page read in the memory system according to the first embodiment. [Figure 10] 10 is a timing chart showing an example of second page reading in the memory system according to the first embodiment. [Figure 11] 10 is a timing chart showing an example of a third page read in the memory system according to the first embodiment. [Figure 12] 10 is a timing chart showing an example of a fourth page read in the memory system according to the first embodiment. [Figure 13] 10 is a timing chart showing an example of a fifth page read in the memory system according to the first embodiment. [Figure 14]10 is a table showing data allocation and read voltage settings of a first modified example. [Figure 15] FIG. 10 is a waveform diagram showing an example of a voltage applied to a selected word line in a read operation of a first modified example. [Figure 16] 10 is a table showing data allocation and read voltage settings in a second modified example. [Figure 17] FIG. 10 is a waveform diagram showing an example of a voltage applied to a selected word line in a read operation of a second modified example. [Figure 18] 13 is a table showing data allocation and read voltage settings of a third modified example. [Figure 19] FIG. 11 is a waveform diagram showing an example of a voltage applied to a selected word line in a read operation of a third modified example. [Figure 20] 13 is a table showing data allocation and read voltage settings of a fourth modified example. [Figure 21] FIG. 13 is a waveform diagram showing an example of a voltage applied to a selected word line in a read operation according to a fourth modified example. [Figure 22] 13 is a table showing data allocation and read voltage settings in the fifth modified example. [Figure 23] FIG. 13 is a waveform diagram showing an example of a voltage applied to a selected word line in a read operation of a fifth modified example. [Figure 24] 13 is a table showing data allocation and read voltage settings according to a sixth modified example. [Figure 25] 13 is a table showing data allocation and read voltage settings according to the seventh modified example. [Figure 26] 13 is a table showing data allocation and read voltage settings according to the eighth modified example. [Figure 27] 13 is a table showing data allocation and read voltage settings according to a ninth modified example. [Figure 28] 20 is a table showing data allocation and read voltage settings according to a tenth modified example. [Figure 29] 23 is a table showing data allocation and read voltage settings according to the eleventh modification. [Figure 30]23 is a table showing data allocation and read voltage settings according to a twelfth modified example. [Figure 31] 23 is a table showing data allocation and read voltage settings according to a thirteenth modified example. [Figure 32] 23 is a table showing data allocation and read voltage settings of the fourteenth modification example. [Figure 33] 23 is a table showing data allocation and read voltage settings according to a fifteenth modification. [Figure 34] 23 is a table showing data allocation and read voltage settings according to the sixteenth modification. [Figure 35] 22 is a table showing data allocation and read voltage settings according to the seventeenth modification. [Figure 36] 22 is a table showing data allocation and read voltage settings according to the eighteenth modification. [Figure 37] 23 is a table showing data allocation and read voltage settings according to a nineteenth modification. [Figure 38] 19 is a table showing data allocation and read voltage settings of the twentieth modification. [Figure 39] 22 is a table showing data allocation and read voltage settings of the 21st modified example. [Figure 40] 22 is a table showing data allocation and read voltage settings according to the twenty-second modified example. [Figure 41] 23 is a table showing data allocation and read voltage settings according to the 23rd modified example. [Figure 42] 23 is a table showing data allocation and read voltage settings of the 24th modified example. [Figure 43] 23 is a table showing data allocation and read voltage settings according to the 25th modified example. [Figure 44] 23 is a table showing data allocation and read voltage settings according to the 26th modified example. [Figure 45] 23 is a table showing data allocation and read voltage settings according to the 27th modified example. [Figure 46] 22 is a table showing data allocation and read voltage settings according to the 28th modified example. [Figure 47] 23 is a table showing data allocation and read voltage settings according to the 29th modified example. [Figure 48] 13 is a table showing data allocation and read voltage settings of the 30th modified example. [Figure 49] 13 is a table showing data allocation and read voltage settings of the thirty-first modified example. [Figure 50] 13 is a table showing data allocation and read voltage settings of the thirty-second modified example. [Figure 51] 13 is a table showing data allocation and read voltage settings of the thirty-third modified example. [Figure 52] 13 is a table showing data allocation and read voltage settings of the thirty-fourth modified example. [Figure 53] 13 is a table showing data allocation and read voltage settings of the thirty-fifth modified example. [Figure 54] 13 is a table showing data allocation and read voltage settings according to the thirty-sixth modified example. [Figure 55] 13 is a table showing data allocation and read voltage settings according to the thirty-seventh modified example. [Figure 56] 13 is a table showing data allocation and read voltage settings according to the 38th modified example. [Figure 57] 13 is a table showing data allocation and read voltage settings according to the thirty-ninth modified example. [Figure 58] 13 is a table showing data allocation and read voltage settings of the 40th modified example. [Figure 59] 13 is a table showing data allocation and read voltage settings of the 41st modified example. [Figure 60] 13 is a table showing data allocation and read voltage settings of the 42nd modified example. [Figure 61] 13 is a table showing data allocation and read voltage settings according to the 43rd modified example. [Figure 62] 13 is a table showing data allocation and read voltage settings of the 44th modified example. [Figure 63]13 is a table showing data allocation and read voltage settings of the 45th modified example. [Figure 64] 13 is a table showing data allocation and read voltage settings according to the 46th modified example. [Figure 65] 13 is a table showing data allocation and read voltage settings according to the 47th modified example. [Figure 66] 13 is a table showing data allocation and read voltage settings according to the 48th modified example. [Figure 67] 13 is a table showing data allocation and read voltage settings according to the 49th modification. [Figure 68] 13 is a table showing data allocation and read voltage settings of the 50th modified example. [Figure 69] 13 is a table showing data allocation and read voltage settings of the 51st modified example. [Figure 70] 13 is a table showing data allocation and read voltage settings of the 52nd modified example. [Figure 71] 13 is a table showing data allocation and read voltage settings of the 53rd modified example. [Figure 72] 10 is a timing chart showing an example of a first page read in the memory system according to the second embodiment. [Figure 73] 10 is a timing chart showing an example of sequential reading in a memory system according to a third embodiment. [Figure 74] FIG. 10 is a plan view showing an example of a circuit layout of a memory device according to a comparative example. [Figure 75] FIG. 10 is a plan view showing an example of a circuit layout of a memory device according to a fourth embodiment. [Figure 76] FIG. 13 is a plan view showing an example of a circuit layout of a memory device according to a modified example of the fourth embodiment. [Figure 77] FIG. 10 is a schematic diagram showing a first configuration example of a sense amplifier module in a memory device according to a fourth embodiment. [Figure 78] FIG. 10 is a schematic diagram showing a second configuration example of a sense amplifier module in a memory device according to the fourth embodiment. [Figure 79]FIG. 13 is a plan view showing an example of a circuit layout of a memory device according to a fifth embodiment. [Figure 80] FIG. 13 is a schematic diagram showing a first configuration example of a sense amplifier set and a latch set in a memory device according to a fifth embodiment. [Figure 81] FIG. 13 is a schematic diagram showing a second configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. [Figure 82] FIG. 13 is a schematic diagram showing a third configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. [Figure 83] FIG. 13 is a schematic diagram showing a fourth configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions, ratios, etc. of each drawing are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are assigned the same reference numerals. The numbers following the letters that make up the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same letters and have similar configurations.

[0008] [1] First embodiment The first embodiment will be described below.

[0009] [1-1] Configuration [1-1-1] Configuration of Information Processing System 1 1 is a block diagram showing an example of the configuration of an information processing system 1 according to the first embodiment. As shown in FIG. 1, the information processing system 1 includes, for example, a host device HD and a memory system MS. The host device HD is an electronic device such as a personal computer, a mobile information terminal, or a server. The memory system MS is a storage medium such as a memory card or an SSD (solid state drive). The memory system MS includes, for example, a memory controller 10 and a memory device 20.

[0010] The memory controller 10 is a semiconductor integrated circuit configured as, for example, an SoC (System On a Chip). The memory controller 10 is connected to a host device HD via a host bus HB. The memory controller 10 is connected to a memory device 20 via a memory bus MB. The memory controller 10 controls the memory device 20 based on commands received from the host device HD. For example, the memory controller 10 controls the memory device 20 to perform read operations, write operations, erase operations, etc.

[0011] The memory device 20 is a semiconductor memory device that stores data in a nonvolatile manner. The memory device 20 is, for example, a NAND flash memory. In a NAND flash memory, the unit of data read and write is called a "page." The memory device 20 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. Each memory cell transistor MT is associated with one bit line BL and one word line WL. A column address is assigned to each bit line BL. A page address is assigned to each word line WL.

[0012] [1-1-2] Hardware configuration of memory controller 10 2 is a block diagram showing an example of a hardware configuration of a memory controller 10 according to the first embodiment. As shown in Fig. 2, the memory controller 10 includes, for example, a host interface (host I / F) 11, a memory interface (memory I / F) 12, a CPU (Central Processing Unit) 13, an ECC (Error Correction Code) circuit 14, a ROM (Read Only Memory) 15, a RAM (Random Access Memory) 16, and a buffer memory 17.

[0013] The host I / F 11 is a hardware interface that complies with the interface standard between the host device HD and the memory controller 10. The host I / F 11 is connected to the host device HD via a host bus HB. The host I / F 11 is, for example, a SATA (Serial Advanced Technology Attachment), PCIe TM Supports interface standards such as PCI Express.

[0014] The memory I / F 12 is a hardware interface that complies with an interface standard between the memory controller 10 and the memory device 20. The memory I / F 12 is connected to the memory device 20 via a memory bus MB. The memory I / F 12 supports, for example, the NAND interface standard.

[0015] The CPU 13 is a processor that controls the overall operation of the memory controller 10. The CPU 13 instructs the memory device 20 to write data via the memory I / F 12 in accordance with a write request received via the host I / F 11. The CPU 13 instructs the memory device 20 to read data via the memory I / F 12 in accordance with a read request received via the host I / F 11.

[0016] The ECC circuit 14 is a circuit that performs ECC processing. The ECC processing includes encoding and decoding of data. The ECC circuit 14 encodes data to be written to the memory device 20 and decodes data read from the memory device 20.

[0017] The ROM 15 is a non-volatile memory. The ROM 15 stores programs such as firmware. The ROM 15 is, for example, an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory) The operation of the memory controller 10 is realized by the CPU 13 executing firmware stored in the ROM 15 or the like.

[0018] The RAM 16 is a volatile memory and is used as a working area for the CPU 13. The RAM 16 is a dynamic random access memory (DRAM) or a static random access memory (SRAM), for example.

[0019] The buffer memory 17 is, for example, a volatile memory. The buffer memory 17 temporarily stores data received via the host I / F 11, data received via the memory I / F 12, etc. The buffer memory 17 is, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0020] [1-1-3] Hardware configuration of memory device 20 3 is a block diagram showing an example of a hardware configuration of a memory device 20 according to the first embodiment. As shown in Fig. 3, the memory device 20 includes, for example, an input / output circuit 201, a logic controller 202, a register circuit 203, a sequencer 204, a ready / busy controller 205, a driver circuit 206, a memory cell array 207, a row decoder module 208, and a sense amplifier module 209. Signals transmitted or received via the memory bus MB include, for example, input / output signals I / O0 to I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a ready / busy signal RBn.

[0021] The input / output circuit 201 is an interface circuit that controls transmission and reception of input / output signals I / O0 to I / O7. The input / output signals I / O include data DAT, status information STS, address information ADD, command CMD, etc. The input / output circuit 201 can transfer (input or output) the data DAT to and from the sense amplifier module 209. The input / output circuit 201 can transfer (output) the status information STS transferred from the register circuit 203 to the memory controller 10. The input / output circuit 201 can transfer each of the address information ADD and command CMD transferred from the memory controller 10 to the register circuit 203.

[0022] The logic controller 202 is a controller that controls each of the input / output circuit 201 and the sequencer 204 based on control signals CEn, CLE, ALE, WEn, REn, and WPn input from the memory controller 10. The logic controller 202 enables the memory device 20 based on the control signal CEn. The logic controller 202 notifies the input / output circuit 201 that the input / output signal I / O received by the memory device 20 is a command CMD and address information ADD based on the control signals CLE and ALE. The logic controller 202 instructs the input / output circuit 201 to input the input / output signal I / O based on the control signal WEn, and instructs the input / output circuit 201 to output the input / output signal I / O based on the control signal REn. The logic controller 202 puts the memory device 20 into a protected state when power is turned on or off based on the control signal WPn.

[0023] The register circuit 203 is a circuit that temporarily stores status information STS, address information ADD, and commands CMD. The status information STS stored in the register circuit 203 is updated under the control of the sequencer 204 and transferred to the input / output circuit 201. The address information ADD includes a block address, a page address, a column address, etc. The commands CMD include instructions related to various operations of the memory device MD.

[0024] The sequencer 204 is a controller that controls the overall operation of the memory device 20. The sequencer 204 executes read operations, write operations, erase operations, etc. based on the command CMD and address information ADD stored in the register circuit 203.

[0025] The ready-busy controller 205 is a controller that generates a ready-busy signal RBn under the control of the sequencer 204. The ready-busy signal RBn is a signal that notifies the memory controller 10 whether the memory device 20 is in a ready state or a busy state. The "ready state" is a state in which the memory device 20 accepts commands from the memory controller 10, and is notified by a ready-busy signal RBn at an "H" level. The "busy state" is a state in which the memory device 20 does not accept commands from the memory controller 10, and is notified by a ready-busy signal RBn at an "L" level.

[0026] The driver circuit 206 is a circuit that generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 206 supplies the generated voltages to the row decoder module 208, the sense amplifier module 209, and the like.

[0027] The memory cell array 207 is a collection of multiple memory cell transistors MT. The memory cell array 207 includes multiple blocks BLK0 to BLKn (n is an integer equal to or greater than 1). A block address is assigned to each block BLK. Each block BLK includes multiple pages. A block BLK is used, for example, as a unit for erasing data. The memory cell array 207 is provided with multiple bit lines BL0 to BLm (m is an integer equal to or greater than 1) and multiple word lines WL.

[0028] The row decoder module 208 is a circuit used to select a block BLK to be operated and to transfer voltages to wiring such as word lines WL. The row decoder module 208 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively.

[0029] The sense amplifier module 209 is a circuit used for transferring voltages to each bit line BL and reading data. The sense amplifier module 209 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively.

[0030] [1-1-4] Circuit configuration of memory device 20 (Circuit configuration of memory cell array 207) 4 is a circuit diagram showing an example of the circuit configuration of the memory cell array 207 included in the memory device 20 according to the first embodiment. Fig. 4 shows the circuit configuration of one block BLK. As shown in Fig. 4, the block BLK includes, for example, string units SU0 to SU4, word lines WL0 to WL7, select gate lines SGD0 to SGD4, select gate line SGS, and source line SL.

[0031] Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS of each string unit SU are connected to bit lines BL0 to BLm, respectively. Each NAND string NS includes memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT has a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the string unit SU.

[0032] The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to the drain of the memory cell transistor MT7. The memory cell transistors MT0 to MT7 are connected in series. The source of the memory cell transistor MT0 is connected to the drain of the select transistor ST2. The source of the select transistor ST2 is connected to a source line SL. The source line SL is shared by, for example, multiple blocks BLK. The word lines WL0 to WL7 are connected to the memory cell transistors MT0 to MT7 of each NAND string NS, respectively. The select gate lines SGD0 to SGD4 are connected to the gates of the multiple select transistors ST1 included in the string units SU0 to SU4, respectively. The select gate line SGS is connected to the gate of the select transistor ST2 of each NAND string NS.

[0033] In this specification, a set of memory cell transistors MT included in the same string unit SU and connected to the same word line WL is referred to as a "cell unit CU." In the memory device 20, each memory cell transistor MT stores 5 bits of data. That is, each cell unit CU can store 5 pages of data. Note that the circuit configuration of the memory cell array 207 may be other circuit configurations. The number of string units SU included in each block BLK and the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be freely designed.

[0034] (Circuit configuration of row decoder module 208) 5 is a circuit diagram showing an example of the circuit configuration of the row decoder module 208 included in the memory device 20 according to the first embodiment. FIG. 5 shows the connection relationship between the row decoder module 208 and each of the driver circuit 206 and the memory cell array 207, and a detailed circuit configuration of the row decoder RD0 among the row decoders RD0 to RDn. As shown in FIG. 5, each row decoder RD is connected to the driver circuit 206 via signal lines CG0 to CG11, SGDD0 to SGDD4, SGSD, USGD, and USGS. Each row decoder RD is connected to the associated block BLK via word lines WL0 to WL7 and select gate lines SGS and SGD0 to SGD4.

[0035] The following describes the connections between each element of the row decoder RD and the driver circuit 206 and the block BLK0, taking the row decoder RD0 as a representative. The row decoder RD0 includes transistors TR0 to TR19, transfer gate lines TG and bTG, and a block decoder BD. Each of the transistors TR0 to TR19 is a high-voltage N-type MOS transistor.

[0036] The drain and source of transistor TR0 are connected to signal line SGSD and select gate line SGS, respectively. The drains of transistors TR1 to TR8 are connected to signal lines CG0 to CG7, respectively. The sources of transistors TR1 to TR8 are connected to word lines WL0 to WL7, respectively. The drains of transistors TR9 to TR13 are connected to signal lines SGDD0 to SGDD4, respectively. The sources of transistors TR9 to TR13 are connected to select gate lines SGD0 to SGD4, respectively. The drain and source of transistor TR14 are connected to signal line USGS and select gate line SGS, respectively. The drains of transistors TR15 to TR19 are connected to signal line USGD, respectively. The sources of transistors TR15 to TR19 are connected to select gate lines SGD0 to SGD4, respectively. The gates of transistors TR0 to TR13 are connected to transfer gate line TG, respectively. The gates of transistors TR14 to TR19 are connected to transfer gate line bTG, respectively.

[0037] The block decoder BD is a decoder that decodes a block address. The block decoder BD applies a predetermined voltage to each of the transfer gate lines TG and bTG based on the decoded block address. Specifically, the block decoder BD corresponding to the selected block BLK applies "H" level and "L" level voltages to the transfer gate lines TG and bTG, respectively. The block decoder BD corresponding to the unselected block BLK applies "L" level and "H" level voltages to the transfer gate lines TG and bTG, respectively. As a result, the voltages of the signal lines CG0 to CG7 are transferred to the word lines WL0 to WL7 of the selected block BLK, respectively, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are transferred to the select gate lines SGD0 to SGD4 and SGS of the selected block BLK, respectively, and the voltages of the signal lines USGD and USGS are transferred to the select gate lines SGD and SGS of the unselected blocks BLK, respectively.

[0038] The row decoder module 208 may have other circuit configurations. For example, the number of transistors TR included in the row decoder module 208 may be changed depending on the number of wirings provided in each block BLK. The signal line CG may be called a "global word line" because it is shared among multiple blocks BLK. The word line WL may be called a "local word line" because it is provided for each block. The signal lines SGDD and SGSD may be called "global transfer gate lines" because they are shared among multiple blocks BLK. The select gate lines SGD and SGS may be called "local transfer gate lines" because they are provided for each block.

[0039] (Circuit configuration of the sense amplifier module 209) 6 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module 209 included in the memory device 20 according to the first embodiment. FIG. 6 shows the circuit configuration of one sense amplifier unit SAU. As shown in FIG. 6, the sense amplifier unit SAU includes a sense amplifier unit SA, a bit line connection unit BLHU, latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL, and a bus LBUS. The sense amplifier unit SA and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL are configured to be able to transmit and receive data via the bus LBUS.

[0040] The sense amplifier unit SA is a circuit used to determine data based on the voltage of the bit line BL and to apply a voltage to the bit line BL. When a control signal STB is asserted during a read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the voltage of the associated bit line BL. Each of the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL is a circuit capable of temporarily holding data. The latch circuit XDL is used for inputting and outputting data DAT between the sense amplifier unit SAU and the input / output circuit 201. The latch circuit XDL can also be used as a cache memory. The memory device MD can be in a ready state if at least the latch circuit XDL is free.

[0041] The sense amplifier section SA includes transistors T0 to T7, a capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU includes a transistor T8. The latch circuit SDL includes inverters IV0 and IV1, transistors T10 and T11, and nodes SINV and SLAT. The transistor T0 is a P-type MOS transistor. Each of the transistors T1 to T8, T10, and T11 is an N-type MOS transistor. The transistor T8 is an N-type MOS transistor with a higher withstand voltage than the N-type transistors in the sense amplifier section SA.

[0042] The gate of transistor T0 is connected to node SINV. The source of transistor T0 is connected to the power supply line. The drain of transistor T0 is connected to node ND1. Node ND1 is connected to the drains of transistors T1 and T2. The sources of transistors T1 and T2 are connected to nodes ND2 and SEN, respectively. Nodes ND2 and SEN are connected to the source and drain of transistor T3, respectively. Node ND2 is connected to the drains of transistors T4 and T5. The source of transistor T5 is connected to node SRC. The gate of transistor T5 is connected to node SINV. Node SEN is connected to the gate of transistor T6 and one electrode of capacitor CP. The source of transistor T6 is grounded. The drain and source of transistor T7 are connected to bus LBUS and the drain of transistor T6, respectively. The drain of transistor T8 is connected to the source of transistor T4. The source of transistor T8 is connected to the associated bit line BL.

[0043] For example, a power supply voltage VDD is applied to the source of transistor T0. For example, a ground voltage VSS is applied to node SRC. Control signals BLX, HLL, XXL, BLC, and STB are input to the gates of transistors T1, T2, T3, T4, and T7, respectively. A control signal BLS is input to the gate of transistor T8. A clock signal CLK is input to the other electrode of capacitor CP.

[0044] The input node of inverter IV0 is connected to node SLAT. The output node of inverter IV0 is connected to node SINV. The input node of inverter IV1 is connected to node SINV. The output node of inverter IV1 is connected to node SLAT. One end of transistor T10 is connected to node SINV. The other end of transistor T10 is connected to bus LBUS. A control signal STI is input to the gate of transistor T10. One end of transistor T11 is connected to node SLAT. The other end of transistor T11 is connected to bus LBUS. A control signal STL is input to the gate of transistor T11. Latch circuit SDL holds data at node SLAT and holds inverted data of the data held at node SLAT at node SINV.

[0045] The circuit configurations of the latch circuits ADL, BDL, CDL, DDL, EDL, and XDL are similar to that of the latch circuit SDL. For example, the latch circuit ADL holds data at a node ALAT and its inverted data at a node AINV. A control signal ATI is input to the gate of the transistor T10 of the latch circuit ADL, and a control signal ATL is input to the gate of the transistor T11 of the latch circuit ADL. The latch circuit BDL holds data at a node BLAT and its inverted data at a node BINV. A control signal BTI is input to the gate of the transistor T10 of the latch circuit BDL, and a control signal BTL is input to the gate of the transistor T11 of the latch circuit BDL. The latch circuits CDL, DDL, and EDL are similar, so their explanations are omitted.

[0046] The control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, and the clock signal CLK are each generated by, for example, the sequencer 204. The sense amplifier module 209 may have other circuit configurations. For example, each sense amplifier unit SAU may include eight or more latch circuits. The sense amplifier unit SAU may have an arithmetic circuit capable of performing simple logical operations. In this specification, asserting a control signal corresponds to temporarily changing a low-level voltage to a high-level voltage. If the transistor T6 is a P-type transistor, asserting the control signal STB corresponds to temporarily changing a high-level voltage to a low-level voltage. The sense amplifier module 209 can determine (determine) the data stored in the memory cell transistor MT by appropriately performing arithmetic processing using the latch circuit during a read operation of each page.

[0047] [1-1-5] Threshold voltage distribution of memory cell transistor MT 7 is a schematic diagram showing an example of the threshold voltage distribution of memory cell transistors MT in a memory device 20 according to the first embodiment. "NMTs" on the vertical axis indicates the number of memory cell transistors MT. "Vth" on the horizontal axis indicates the threshold voltage of the memory cell transistors MT. As shown in FIG. 7, the threshold voltage distribution of the memory cell transistors MT in the memory device 20 can form states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31, in order from lowest threshold voltage.

[0048] Furthermore, in the memory device 20, read voltages R1 to R31 and a read pass voltage VREAD are set for states S0 to S31. Specifically, read voltage R1 is set between states S0 and S1, read voltage R2 is set between states S1 and S2, read voltage R3 is set between states S2 and S3, read voltage R4 is set between states S3 and S4, ..., read voltage R30 is set between states S29 and S30, and read voltage R30 is set between states S30 and S31. The read pass voltage VREAD is set to a voltage higher than state S31, which has the highest threshold voltage among states S0 to S31. A memory cell transistor MT, to whose gate a read pass voltage VREAD is applied, is turned on regardless of the data to be stored.

[0049] 7 may include a negative voltage. The set of read voltages R1 to R31 may be a combination of a negative voltage, 0V, and a positive voltage. That is, in the set of read voltages R1 to R31, some read voltages may be negative voltages and the other read voltages may be 0V or positive read voltages. For example, each of read voltages R1 to R4 may be a negative voltage, read voltage R5 may be 0V, and each of read voltages R6 to R31 may be a positive voltage. The set of read voltages R1 to R31 may include a negative voltage and a positive voltage without including 0V.

[0050] Each of the states S0 to S31 is assigned one of the data sets D0 to D31. The data sets D0 to D31 correspond to 32 sets of different 5-bit data. Each of the data sets D0 to D31 includes first to fifth bits of data. The specific data contents of each of the data sets D0 to D31 are listed below.

[0051] (Example) Data set: "1st bit data / 2nd bit data / 3rd bit data / 4th bit data / 5th bit data" D0: "00000" D1: "00001" D2: “00010” D3: “00011” D4: “00100” D5: “00101” D6: “00110” D7: “00111” D8: “01000” D9: “01001” D10: “01010” D11: “01011” D12: “01100” D13: “01101” D14: “01110” D15: “01111” D16: "10000" D17: "10001" D18: "10010" D19: "10011" D20: "10100" D21: “10101” D22: “10110” D23: “10111” D24: "11000" D25: “11001” D26: “11010” D27: “11011” D28: “11100” D29: “11101” D30: “11110” D31: “11111”

[0052] [1-1-6] Data allocation 8 is a table showing data allocation and read voltage settings used in the memory device 20 according to the first embodiment. The memory device 20 according to the first embodiment uses a data allocation in which one cell unit CU stores five pages of data, i.e., a 5-bit / cell coding. The data allocation and read voltage settings of the first embodiment will be described below with reference to FIG. 8.

[0053] Note that the "state ID" described in the drawings referenced in this specification corresponds to the number attached to the reference symbol "S" indicating a state. The "data set ID" described in the drawings referenced in this specification corresponds to the number attached to the reference symbol "D" indicating a data set. The "first page (first page data PG1)" corresponds to the group of first bit data stored in the cell unit CU. The "second page (second page data PG2)" corresponds to the group of second bit data stored in the cell unit CU. The "third page (third page data PG3)" corresponds to the group of third bit data stored in the cell unit CU. The "fourth page (fourth page data PG4)" corresponds to the group of fourth bit data stored in the cell unit CU. The "fifth page (fifth page data PG5)" corresponds to the group of fifth bit data stored in the cell unit CU. Hereinafter, read operations targeting the first to fifth pages will be referred to as first to fifth page reads, respectively.

[0054] In the data allocation of the first embodiment, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D9, D1, D3, D19, D23, D21, D20, D4, D12, D14, D10, D2, D0, D16, D17, D25, D29, D13, D5, D7, D6, D22, D18, D26, D27, D11 and D15, respectively.

[0055] In the data allocation of the first embodiment, the read voltages used in the first page read are R4, R8, R12, R18, R22, R26, and R30. In the data allocation of the first embodiment, the read voltages used in the second page read are R6, R13, R16, R20, R23, and R28. In the data allocation of the first embodiment, the read voltages used in the third page read are R3, R9, R15, R21, R27, and R31. In the data allocation of the first embodiment, the read voltages used in the fourth page read are R2, R7, R10, R14, R17, and R24. In the data allocation of the first embodiment, the read voltages used in the fifth page read are R1, R5, R11, R19, R25, and R29.

[0056] In the first page read, data is determined after seven reads. In each of the second, third, fourth, and fifth page reads, data is determined after six reads. This type of data allocation is called, for example, "7-6-6-6-6 coding." In the data allocation of the first embodiment, the difference between the maximum and minimum values ​​of the number of reads set to determine data between pages is "1." Also, in the data allocation of the first embodiment, the interval between the read voltages in each page is a minimum of "3" and a maximum of "8."

[0057] In this specification, the "number of reads" in a read operation for each page corresponds to the number of times the control signal STB is asserted. In other words, the "number of reads" corresponds to the number of times a threshold voltage determination is performed using a certain read voltage. Performing a data determination according to a certain read voltage while that read voltage is applied may simply be referred to as "reading." The "read voltage interval" corresponds to the number of read voltages that are not used between adjacent read voltages among the multiple read voltages used in a read operation for a certain page. In other words, the "read voltage interval" corresponds to the number of states between adjacent read voltages in a read operation for each page. For example, the interval between read voltages R4 and R8 in a first page read is "4 (equivalent to four states)" because four states S4 to S7 are located between read voltages R4 and R8. The interval between read voltages R12 and R18 in a first page read is "6 (equivalent to six states)" because six states S12 to S17 are located between read voltages R12 and R18.

[0058] [1-2] Operation The operation of the memory system MS according to the first embodiment will be described below. Hereinafter, the selected word line WL will be referred to as the "selected word line WLsel." The sequencer 204 applies a voltage to the selected word line WLsel, which corresponds to the driver circuit 206 applying a voltage via the row decoder module 208 based on the control of the sequencer 204. The address information ADD and command CMD received by the memory device 20 are transferred to the register circuit 203. "tR" in the drawing indicates the period (time) during which the memory device 20 is in a busy state based on an instruction from the memory controller 10.

[0059] The details of each of the first to fifth page reads in the first embodiment will be described below. In this specification, a case where the voltage of the source line SL is constant in each of the first to fifth page reads is illustrated. Furthermore, the drawings referred to below illustrate a case where the voltage of the selected word line WLsel at the start and end of the read operation is the ground voltage VSS. However, the present invention is not limited to this, and the voltage of the selected word line WLsel at the start and end of the read operation may be a negative voltage.

[0060] [1-2-1] First page read 9 is a timing chart showing an example of a first page read in the memory system MS according to the first embodiment. Fig. 9 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the first page read of the first embodiment. The first page read of the first embodiment will be described below with reference to Fig. 9.

[0061] When executing a first page read, the memory controller 10 transmits, for example, command "01h", command "00h", address "ADD", and command "30h" to the memory device 20 in this order. Command "01h" is a command that specifies an operation that selects the first page. Command "00h" is a command that specifies a read operation. Address "ADD" includes the address of the word line WL to be read. Command "30h" is a command that instructs the start of a read operation.

[0062] When the memory device 20 receives the command "30h," the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies read voltages R4, R8, R12, R18, R22, R26, and R30 to the selected word line WLsel in this order. The sequencer 204 also asserts a control signal STB while each of the read voltages R4, R8, R12, R18, R22, R26, and R30 is being applied. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the first bit data read from the memory cell transistor MT connected to the selected word line WLsel and stores the determination result in the latch circuit XDL.

[0063] When the determination result of the first bit data is stored in the latch circuit XDL, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the transition of the memory device 20 from a busy state to a ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (first page data PG1) stored in each latch circuit XDL of the sense amplifier module 209. For example, the memory controller 10 can cause the memory device 20 to sequentially output the data DAT by toggling the control signal REn. Upon receiving the first page data PG1, the memory controller 10 transfers the first page data PG1 to, for example, the host device HD, and ends the first page read.

[0064] [1-2-2] Read the second page 10 is a timing chart showing an example of a second page read in the memory system MS according to the first embodiment. Fig. 10 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the second page read in the first embodiment. The second page read in the first embodiment will be described below with reference to Fig. 10.

[0065] When executing a second page read, the memory controller 10 transmits, for example, a command “02h”, a command “00h”, an address “ADD”, and a command “30h” in this order to the memory device 20. The command “02h” is a command that specifies an operation that selects the second page.

[0066] When the memory device 20 receives the command "30h," the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies read voltages R6, R13, R16, R20, R23, and R28 to the selected word line WLsel in this order. The sequencer 204 also asserts a control signal STB while each of the read voltages R6, R13, R16, R20, R23, and R28 is being applied. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the second bit data read from the memory cell transistor MT connected to the selected word line WLsel, and stores the determination result in the latch circuit XDL.

[0067] When the determination result of the second bit data is stored in the latch circuit XDL, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the transition of the memory device 20 from a busy state to a ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (second page data PG2) stored in each latch circuit XDL of the sense amplifier module 209. When the memory controller 10 receives the second page data PG2, it transfers the second page data PG2 to, for example, the host device HD, and ends the second page read.

[0068] [1-2-3] Read the third page 11 is a timing chart showing an example of a third page read in the memory system MS according to the first embodiment. Fig. 11 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the third page read of the first embodiment. The third page read of the first embodiment will be described below with reference to Fig. 11.

[0069] When executing a third page read, the memory controller 10 transmits, for example, a command “03h”, a command “00h”, an address “ADD”, and a command “30h” in this order to the memory device 20. The command “03h” is a command that specifies an operation that selects the third page.

[0070] When the memory device 20 receives the command "30h," the sequencer 204 transitions the memory device 20 from a ready state to a busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies read voltages R3, R9, R15, R21, R27, and R31 to the selected word line WLsel in this order. The sequencer 204 also asserts a control signal STB while each of the read voltages R3, R9, R15, R21, R27, and R31 is being applied. Under the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the third bit data read from the memory cell transistor MT connected to the selected word line WLsel, and stores the determination result in the latch circuit XDL.

[0071] When the determination result of the third bit data is stored in the latch circuit XDL, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the transition of the memory device 20 from a busy state to a ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (third page data PG3) stored in each latch circuit XDL of the sense amplifier module 209. When the memory controller 10 receives the third page data PG3, it transfers the third page data PG3 to, for example, the host device HD, and ends the third page read.

[0072] [1-2-4] Read the fourth page 12 is a timing chart showing an example of a fourth page read in the memory device according to the first embodiment. Fig. 12 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the fourth page read in the first embodiment. The fourth page read in the first embodiment will be described below with reference to Fig. 12.

[0073] When executing a fourth page read, the memory controller 10 transmits, for example, a command “04h”, a command “00h”, an address “ADD”, and a command “30h” in this order to the memory device 20. The command “04h” is a command that specifies an operation that selects the fourth page.

[0074] When the memory device 20 receives the command "30h," the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies read voltages R2, R7, R10, R14, R17, and R24 to the selected word line WLsel in this order. The sequencer 204 also asserts a control signal STB while each of the read voltages R2, R7, R10, R14, R17, and R24 is being applied. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the fourth bit data read from the memory cell transistor MT connected to the selected word line WLsel, and stores the determination result in the latch circuit XDL.

[0075] When the determination result of the fourth bit data is stored in the latch circuit XDL, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the transition of the memory device 20 from a busy state to a ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (fourth page data PG4) stored in each latch circuit XDL of the sense amplifier module 209. When the memory controller 10 receives the fourth page data PG4, it transfers the fourth page data PG4 to, for example, the host device HD, and ends the fourth page read.

[0076] [1-2-5] Page 5 read 13 is a timing chart showing an example of a fifth page read in the memory device according to the first embodiment. Fig. 13 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the fifth page read in the first embodiment. The fifth page read in the first embodiment will be described below with reference to Fig. 13.

[0077] When executing a fifth page read, the memory controller 10 transmits, for example, a command “02h”, a command “00h”, an address “ADD”, and a command “30h” in this order to the memory device 20. The command “05h” is a command that specifies an operation in which the fifth page is selected.

[0078] When the memory device 20 receives the command "30h," the sequencer 204 transitions the memory device 20 from a ready state to a busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies read voltages R1, R5, R11, R19, R25, and R29 to the selected word line WLsel in this order. The sequencer 204 also asserts a control signal STB while each of the read voltages R1, R5, R11, R19, R25, and R29 is being applied. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the fifth bit data read from the memory cell transistor MT connected to the selected word line WLsel and stores the determination result in the latch circuit XDL.

[0079] When the determination result of the fifth bit data is stored in the latch circuit XDL, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the transition of the memory device 20 from a busy state to a ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (fifth page data PG5) stored in each latch circuit XDL of the sense amplifier module 209. When the memory controller 10 receives the fifth page data PG5, it transfers the fifth page data PG5 to, for example, the host device HD, and ends the fifth page read.

[0080] [1-3] Effects of the first embodiment The memory device 20 according to the first embodiment described above can perform an efficient read operation. The effects of the first embodiment will be described in detail below.

[0081] In memory-specific data allocation, the 5-bit data assigned to a state is set to differ by only one bit from the 5-bit data assigned to an adjacent state. Memory-specific coding with 5 bits per cell has over 10 million possibilities when page allocation is not taken into account. Even when page allocation is taken into account, coding with 5 bits per cell has about 100,000 possibilities.

[0082] For efficient allocation of read voltages, it is preferable that the number of reads per page is averaged and that the interval between read voltages per page is averaged. The average number of reads per page can average the probability of occurrence of defects per page. The average interval between read voltages per page can reduce read noise and average the setup time of the read voltage. Furthermore, averaging the setup time can shorten the time for the read operation per page, thereby improving the latency of the read operation of the memory device 20.

[0083] When applied to 5 bits per cell, it is ideal that the number of reads is (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6), and the minimum interval between read voltages for each page is 4 and the maximum interval is as small as possible. The reason why the minimum interval between optimal read voltages is 4 is that there are 31 read voltages in the coding of 5 bits per cell, and the result of dividing 31 by the maximum number of reads, 7, is close to 4. However, there is no data assignment in which the number of reads is (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6), and the minimum interval between read voltages for each page is 4.

[0084] Furthermore, data determination using the lowest read voltage R1 tends to have a higher probability of defects due to the widening of the upper tail of the lowest state S0. Data determination using the highest read voltage R31 tends to have a higher probability of defects due to the widening of the lower tail of the highest state S31. A page that has been read seven times tends to have a higher probability of defects than a page that has been read six times. For this reason, in a memory, it is preferable that the interval between read voltages is set evenly for a page that has been read seven times, and that the lowest or highest read voltage of the 31 types of read voltages is not used.

[0085] In contrast, data allocation in the memory device 20 according to the first embodiment is set to conditions close to ideal conditions. Specifically, in the data allocation according to the first embodiment, the number of reads is (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6), and the interval between read voltages in each page is a minimum of 3 and a maximum of 8. In the first page, which has 7 reads, the lowest read voltage is R4 and the highest read voltage is R30. That is, in the first page read according to the first embodiment, the lowest read voltage R4 is set three states away from R1, and the highest read voltage R30 is set one state away from R31.

[0086] As a result, the memory device 20 according to the first embodiment can average the number of reads per page and average the probability of occurrence of defects per page. By averaging the probability of occurrence of defects, the memory device 20 can suppress the occurrence of retries of read operations and improve latency. By limiting the interval between read voltages to a minimum of "3" and a maximum of "8", the memory device 20 can approximately average the setup time of the read voltage per page. Therefore, the memory device 20 can shorten the time for a read operation. Therefore, the memory device 20 according to the first embodiment can perform an efficient read operation.

[0087] [1-4] Modification of the first embodiment There are other data allocations that allow for efficient read operations similar to those in Embodiment 1. Below, first to seventeenth modifications will be described as data allocations in the modifications of Embodiment 1.

[0088] (First Modification) 14 is a table showing data allocation and read voltage settings in Modification 1. The data allocation and read voltage settings in Modification 1 will be described below with reference to FIG.

[0089] In the data allocation of the first modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D23, D7, D5, D1, D9, D25, D27, D26, D10, D14, D6, D4, D20, D21 and D29, respectively.

[0090] In the data allocation of the first modification, the read voltages used in the first page read are R7, R15, R18, R22, R25, and R29. In the data allocation of the first modification, the read voltages used in the second page read are R4, R8, R13, R21, R27, and R31. In the data allocation of the first modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, and R26. In the data allocation of the first modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R19, R23, and R28. In the data allocation of the first modification, the read voltages used in the fifth page read are R1, R5, R11, R17, R24, and R30.

[0091] 15 is a waveform diagram showing an example of a voltage (read waveform) applied to the selected word line WLsel in a read operation of the first modified example. In each of the first to fifth page reads of the first modified example, the sequencer 204 can read desired page data from the cell unit CU by applying a read voltage to the selected word line WLsel as shown in FIG. 15. The operations are the same between the first embodiment and the first modified example, except that the type of read voltage applied to the selected word line WLsel in each page read is different.

[0092] (Second Modification) 16 is a table showing data allocation and read voltage settings in Modification 2. The data allocation and read voltage settings in Modification 2 will be described below with reference to FIG.

[0093] In the data allocation of the second modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D8, D9, D1, D5, D7, D23, D19, D18, D26, D10, D14, D12, D4, D0, D16, D17, D25, D27, D11, D3, D2, D6, D22, D20, D21, D29, D13 and D15, respectively.

[0094] In the data allocation of the second modification, the read voltages used in the first page read are R4, R9, R13, R18, R22, R26, and R30. In the data allocation of the second modification, the read voltages used in the second page read are R6, R12, R16, R20, R23, and R29. In the data allocation of the second modification, the read voltages used in the third page read are R3, R7, R10, R14, R17, and R25. In the data allocation of the second modification, the read voltages used in the fourth page read are R2, R8, R15, R21, R27, and R31. In the data allocation of the second modification, the read voltages used in the fifth page read are R1, R5, R11, R19, R24, and R28.

[0095] 17 is a waveform diagram showing an example of a voltage (read waveform) applied to the selected word line WLsel in a read operation of the second modified example. In each of the first to fifth page reads of the second modified example, the sequencer 204 can read desired page data from the cell unit CU by applying a read voltage to the selected word line WLsel as shown in FIG. 17. The operations of the first embodiment and the second modified example are the same except that the type of read voltage applied to the selected word line WLsel in each page read is different.

[0096] (Third Modification) 18 is a table showing data allocation and read voltage settings in Modification Example 3. The data allocation and read voltage settings in Modification Example 3 will be described below with reference to FIG.

[0097] In the data allocation of the third modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D23, D7, D15, D13, D12, D4, D0, D2, D18, D26, D27, D11, D3, D1, D5, D21, D20, D22, D6, D14, D10, D8, D9, D25 and D29, respectively.

[0098] In the data allocation of the third modification, the read voltages used in the first page read are R8, R15, R18, R22, R25, and R30. In the data allocation of the third modification, the read voltages used in the second page read are R4, R9, R12, R16, R19, and R26. In the data allocation of the third modification, the read voltages used in the third page read are R3, R7, R13, R21, R27, and R31. In the data allocation of the third modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R20, R24, and R28. In the data allocation of the third modification, the read voltages used in the fifth page read are R1, R5, R11, R17, R23, and R29.

[0099] 19 is a waveform diagram showing an example of a voltage (read waveform) applied to the selected word line WLsel in a read operation of the third modified example. In each of the first to fifth page reads of the third modified example, the sequencer 204 can read desired page data from the cell unit CU by applying a read voltage to the selected word line WLsel as shown in FIG. 19. The operations of the first embodiment and the third modified example are the same except that the type of read voltage applied to the selected word line WLsel in each page read is different.

[0100] (Fourth Modification) 20 is a table showing data allocation and read voltage settings in Modification Example 4. The data allocation and read voltage settings in Modification Example 4 will be described below with reference to FIG.

[0101] In the data allocation of the fourth modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D25, D17, D19, D23, D7, D15, D14, D12, D4, D0, D16, D18, D26, D27, D11, D3, D1, D5, D21, D20, D22, D6, D2, D10, D8, D9, D13 and D29, respectively.

[0102] In the data allocation of the fourth modification, the read voltages used in the first page read are R8, R14, R18, R22, R25, and R31. In the data allocation of the fourth modification, the read voltages used in the second page read are R5, R9, R12, R16, R19, and R27. In the data allocation of the fourth modification, the read voltages used in the third page read are R3, R7, R13, R21, R26, and R30. In the data allocation of the fourth modification, the read voltages used in the fourth page read are R2, R6, R11, R15, R20, R24, and R28. In the data allocation of the fourth modification, the read voltages used in the fifth page read are R1, R4, R10, R17, R23, and R29.

[0103] 21 is a waveform diagram showing an example of a voltage (read waveform) applied to the selected word line WLsel in a read operation of the fourth modified example. In each of the first to fifth page reads of the fourth modified example, the sequencer 204 can read desired page data from the cell unit CU by applying a read voltage to the selected word line WLsel as shown in FIG. 21. The operations of the first embodiment and the fourth modified example are the same except that the type of read voltage applied to the selected word line WLsel in each page read is different.

[0104] (Fifth Modification) 22 is a table showing data allocation and read voltage settings in Modification 5. The data allocation and read voltage settings in Modification 5 will be described below with reference to FIG.

[0105] In the data allocation of the fifth modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D8, D0, D2, D3, D19, D23, D22, D20, D4, D12, D13, D9, D1, D17, D16, D18, D26, D10, D14, D6, D7, D5, D21, D29, D25, D27, D11 and D15, respectively.

[0106] In the data allocation of the fifth modification, the read voltages used in the first page read are R4, R8, R12, R17, R21, R26, and R30. In the data allocation of the fifth modification, the read voltages used in the second page read are R5, R13, R16, R20, R23, and R27. In the data allocation of the fifth modification, the read voltages used in the third page read are R3, R9, R15, R22, R28, and R31. In the data allocation of the fifth modification, the read voltages used in the fourth page read are R2, R6, R11, R19, R25, and R29. In the data allocation of the fifth modification, the read voltages used in the fifth page read are R1, R7, R10, R14, R18, and R24.

[0107] 23 is a waveform diagram showing an example of a voltage (read waveform) applied to the selected word line WLsel in a read operation of the fifth modified example. In each of the first to fifth page reads of the fifth modified example, the sequencer 204 can read desired page data from the cell unit CU by applying a read voltage to the selected word line WLsel as shown in FIG. 23. The operations of the first embodiment and the fifth modified example are the same except that the type of read voltage applied to the selected word line WLsel in each page read is different.

[0108] (Sixth Modification) 24 is a table showing data allocation and read voltage settings in Modification Example 6. The data allocation and read voltage settings in Modification Example 6 will be described below with reference to FIG.

[0109] In the data allocation of the sixth modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D20, D4, D5, D1, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21 and D29, respectively.

[0110] In the data allocation of the sixth modification, the read voltages used in the first page read are R7, R15, R18, R22, R25, and R29. In the data allocation of the sixth modification, the read voltages used in the second page read are R4, R8, R13, R21, R27, and R31. In the data allocation of the sixth modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, and R26. In the data allocation of the sixth modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the sixth modification, the read voltages used in the fifth page read are R1, R5, R11, R19, R24, and R28.

[0111] (Seventh Modification) 25 is a table showing data allocation and read voltage settings in Modification Example 7. The data allocation and read voltage settings in Modification Example 7 will be described below with reference to FIG.

[0112] In the data allocation of the seventh modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D10, D26, D18, D22, D20, D4, D0, D2, D3, D19, D27, D25, D9, D8, D12, D14, D6, D7, D23, D21 and D29, respectively.

[0113] In the data allocation of the seventh modification, the read voltages used in the first page read are R6, R12, R16, R20, R23, and R29. In the data allocation of the seventh modification, the read voltages used in the second page read are R4, R8, R13, R21, R27, and R31. In the data allocation of the seventh modification, the read voltages used in the third page read are R3, R7, R10, R14, R17, and R25. In the data allocation of the seventh modification, the read voltages used in the fourth page read are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the seventh modification, the read voltages used in the fifth page read are R1, R5, R11, R19, R24, and R28.

[0114] (Eighth Modification) 26 is a table showing data allocation and read voltage settings in Modification Example 8. The data allocation and read voltage settings in Modification Example 8 will be described below with reference to FIG.

[0115] In the data allocation of the eighth modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D3, D19, D18, D22, D20, D4, D12, D14, D10, D26, D27, D25, D9, D8, D0, D2, D6, D7, D23, D21 and D29, respectively.

[0116] In the data allocation of the eighth modification, the read voltages used in the first page read are R6, R12, R16, R20, R23, and R29. In the data allocation of the eighth modification, the read voltages used in the second page read are R4, R8, R11, R17, R25, and R31. In the data allocation of the eighth modification, the read voltages used in the third page read are R3, R7, R10, R14, R19, and R27. In the data allocation of the eighth modification, the read voltages used in the fourth page read are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the eighth modification, the read voltages used in the fifth page read are R1, R5, R13, R21, R24, and R28.

[0117] (Ninth Modification) 27 is a table showing data allocation and read voltage settings in Modification 9. The data allocation and read voltage settings in Modification 9 will be described below with reference to FIG.

[0118] In the data allocation of the ninth modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D5, D1, D0, D2, D18, D22, D20, D4, D12, D8, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21 and D29, respectively.

[0119] In the data allocation of the ninth modification, the read voltages used in the first page read are R7, R15, R18, R22, R25, and R29. In the data allocation of the ninth modification, the read voltages used in the second page read are R4, R8, R11, R19, R27, and R31. In the data allocation of the ninth modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, and R26. In the data allocation of the ninth modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the ninth modification, the read voltages used in the fifth page read are R1, R5, R13, R21, R24, and R28.

[0120] (Tenth Modification) 28 is a table showing data allocation and read voltage settings in Modification 10. The data allocation and read voltage settings in Modification 10 will be described below with reference to FIG.

[0121] In the data allocation of the tenth modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D3, D19, D18, D22, D20, D4, D0, D2, D10, D26, D27, D25, D9, D8, D12, D14, D6, D7, D23, D21 and D29, respectively.

[0122] In the data allocation of the tenth modification, the read voltages used in the first page read are R6, R12, R16, R20, R23, and R29. In the data allocation of the tenth modification, the read voltages used in the second page read are R4, R8, R11, R19, R27, and R31. In the data allocation of the tenth modification, the read voltages used in the third page read are R3, R7, R10, R14, R17, and R25. In the data allocation of the tenth modification, the read voltages used in the fourth page read are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the tenth modification, the read voltages used in the fifth page read are R1, R5, R13, R21, R24, and R28.

[0123] (Eleventh Modification) 29 is a table showing data allocation and read voltage settings in Modification 11. Data allocation and read voltage settings in Modification 11 will be described below with reference to FIG.

[0124] In the data allocation of the 11th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D5, D1, D17, D19, D18, D22, D20, D4, D12, D8, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21 and D29, respectively.

[0125] In the data allocation of the eleventh modification, the read voltages used in the first page read are R5, R13, R18, R22, R25, and R29. In the data allocation of the eleventh modification, the read voltages used in the second page read are R4, R8, R11, R19, R27, and R31. In the data allocation of the eleventh modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, and R26. In the data allocation of the eleventh modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the eleventh modification, the read voltages used in the fifth page read are R1, R7, R15, R21, R24, and R28.

[0126] (12th Modification) 30 is a table showing data allocation and read voltage settings in Modification 12. The data allocation and read voltage settings in Modification 12 will be described below with reference to FIG.

[0127] In the data allocation of the 12th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D23, D7, D5, D1, D9, D25, D29, D21, D20, D4, D6, D14, D10, D26 and D27, respectively.

[0128] In the data allocation of the twelfth modification, the read voltages used in the first page read are R7, R15, R18, R22, R26, and R30. In the data allocation of the twelfth modification, the read voltages used in the second page read are R4, R8, R13, R21, R24, and R28. In the data allocation of the twelfth modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the twelfth modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R19, and R27. In the data allocation of the twelfth modification, the read voltages used in the fifth page read are R1, R5, R11, R17, R25, and R31.

[0129] (13th Modification) 31 is a table showing data allocation and read voltage settings in Modification Example 13. The data allocation and read voltage settings in Modification Example 13 will be described below with reference to FIG.

[0130] In the data allocation of the 13th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D5, D1, D17, D19, D18, D22, D20, D4, D12, D8, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26 and D27, respectively.

[0131] In the data allocation of the thirteenth modification, the read voltages used in the first page read are R5, R13, R18, R22, R26, and R30. In the data allocation of the thirteenth modification, the read voltages used in the second page read are R4, R8, R11, R19, R24, and R28. In the data allocation of the thirteenth modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the thirteenth modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R17, and R25. In the data allocation of the thirteenth modification, the read voltages used in the fifth page read are R1, R7, R15, R21, R27, and R31.

[0132] (14th Modification) 32 is a table showing data allocation and read voltage settings in Modification 14. The data allocation and read voltage settings in Modification 14 will be described below with reference to FIG.

[0133] In the data allocation of the 14th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D20, D4, D5, D1, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26 and D27, respectively.

[0134] In the data allocation of the fourteenth modification, the read voltages used in the first page read are R7, R15, R18, R22, R26, and R30. In the data allocation of the fourteenth modification, the read voltages used in the second page read are R4, R8, R13, R21, R24, and R28. In the data allocation of the fourteenth modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the fourteenth modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R17, and R25. In the data allocation of the fourteenth modification, the read voltages used in the fifth page read are R1, R5, R11, R19, R27, and R31.

[0135] (15th Modification) 33 is a table showing data allocation and read voltage settings in Modification Example 15. The data allocation and read voltage settings in Modification Example 15 will be described below with reference to FIG.

[0136] In the data allocation of the 15th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D5, D1, D0, D2, D18, D22, D20, D4, D12, D8, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26 and D27, respectively.

[0137] In the data allocation of the fifteenth modification, the read voltages used in the first page read are R7, R15, R18, R22, R26, and R30. In the data allocation of the fifteenth modification, the read voltages used in the second page read are R4, R8, R11, R19, R24, and R28. In the data allocation of the fifteenth modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the fifteenth modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R17, and R25. In the data allocation of the fifteenth modification, the read voltages used in the fifth page read are R1, R5, R13, R21, R27, and R31.

[0138] (16th Modification) 34 is a table showing data allocation and read voltage settings in Modification Example 16. Data allocation and read voltage settings in Modification Example 16 will be described below with reference to FIG.

[0139] In the data allocation of the 16th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D10, D14, D6, D22, D20, D21, D29, D13, D12, D4, D0, D16, D17, D19, D23, D7, D5, D1, D9, D25, D27, D26, D18, D2, D3, D11 and D15, respectively.

[0140] In the data allocation of the 16th modification, the read voltages used in the first page read are R4, R8, R12, R16, R20, R24, and R28. In the data allocation of the 16th modification, the read voltages used in the second page read are R7, R11, R14, R23, R27, and R30. In the data allocation of the 16th modification, the read voltages used in the third page read are R3, R6, R15, R19, R22, and R31. In the data allocation of the 16th modification, the read voltages used in the fourth page read are R2, R5, R9, R18, R21, and R25. In the data allocation of the 16th modification, the read voltages used in the fifth page read are R1, R10, R13, R17, R26, and R29.

[0141] (17th Modification) 35 is a table showing data allocation and read voltage settings in Modification Example 17. Data allocation and read voltage settings in Modification Example 17 will be described below with reference to FIG.

[0142] In the data allocation of the 17th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D9, D1, D5, D21, D29, D25, D27, D11, D3, D2, D0, D16, D17, D19, D23, D7, D6, D14, D10, D26, D18, D22, D20, D4, D12, D13 and D15, respectively.

[0143] In the data allocation of the seventeenth modification, the read voltages used in the first page read are R4, R8, R12, R16, R20, R24, and R28. In the data allocation of the seventeenth modification, the read voltages used in the second page read are R6, R9, R13, R22, R25, and R29. In the data allocation of the seventeenth modification, the read voltages used in the third page read are R3, R7, R10, R19, R23, and R26. In the data allocation of the seventeenth modification, the read voltages used in the fourth page read are R2, R11, R15, R18, R27, and R31. In the data allocation of the seventeenth modification, the read voltages used in the fifth page read are R1, R5, R15, R17, R21, and R30.

[0144] (18th Modification) 36 is a table showing data allocation and read voltage settings in Modification Example 18. Data allocation and read voltage settings in Modification Example 18 will be described below with reference to FIG.

[0145] In the data allocation of the 18th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D10, D14, D6, D22, D18, D26, D27, D11, D3, D2, D0, D16, D17, D19, D23, D7, D5, D1, D9, D25, D29, D21, D20, D4, D12, D13 and D15, respectively.

[0146] In the data allocation of the 18th modification, the read voltages used in the first page read are R8, R12, R16, R20, R24, and R28. In the data allocation of the 18th modification, the read voltages used in the second page read are R4, R7, R10, R13, R23, R26, and R29. In the data allocation of the 18th modification, the read voltages used in the third page read are R3, R6, R9, R19, R22, and R25. In the data allocation of the 18th modification, the read voltages used in the fourth page read are R2, R5, R15, R18, R21, and R31. In the data allocation of the 18th modification, the read voltages used in the fifth page read are R1, R11, R14, R17, R27, and R30.

[0147] (19th Modification) 37 is a table showing data allocation and read voltage settings in Modification Example 19. Data allocation and read voltage settings in Modification Example 19 will be described below with reference to FIG.

[0148] In the data allocation of the 19th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D27, D11, D3, D2, D0, D16, D20, D22, D6, D14, D10, D26, D18, D19, D23, D7, D5, D4, D12, D8, D9, D1, D17, D21, D29, D13 and D15, respectively.

[0149] In the data allocation of the 19th modification, the read voltages used in the first page read are R6, R10, R13, R16, R20, R27, and R30. In the data allocation of the 19th modification, the read voltages used in the second page read are R7, R14, R17, R23, R26, and R29. In the data allocation of the 19th modification, the read voltages used in the third page read are R3, R11, R15, R19, R24, and R28. In the data allocation of the 19th modification, the read voltages used in the fourth page read are R2, R5, R9, R12, R21, and R31. In the data allocation of the 19th modification, the read voltages used in the fifth page read are R1, R4, R8, R18, R22, and R25.

[0150] (20th Modification) 38 is a table showing data allocation and read voltage settings in Modification Example 20. Data allocation and read voltage settings in Modification Example 20 will be described below with reference to FIG.

[0151] In the data allocation of the 20th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D21, D20, D22, D6, D2, D3, D1, D5, D4, D12, D14, D10, D26, D18, D16, D0, D8, D9, D11, D27, D19, D23, D7, D15, D13 and D29, respectively.

[0152] In the data allocation of the 20th modification, the read voltages used in the first page read are R9, R18, R21, R25, R28, and R31. In the data allocation of the 20th modification, the read voltages used in the second page read are R5, R15, R19, R22, R26, and R29. In the data allocation of the 20th modification, the read voltages used in the third page read are R3, R6, R10, R13, R17, and R27. In the data allocation of the 20th modification, the read voltages used in the fourth page read are R2, R8, R12, R16, R20, R24, and R30. In the data allocation of the 20th modification, the read voltages used in the fifth page read are R1, R4, R7, R11, R14, and R23.

[0153] (21st Modification) 39 is a table showing data allocation and read voltage settings in Modification Example 21. Data allocation and read voltage settings in Modification Example 21 will be described below with reference to FIG.

[0154] In the data allocation of the 21st modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D10, D14, D6, D22, D18, D26, D27, D25, D9, D1, D5, D7, D23, D19, D17, D16, D0, D2, D3, D11, D15, D13, D12, D4, D20, D21 and D29, respectively.

[0155] In the data allocation of the 21st modification, the read voltages used in the first page read are R4, R8, R13, R17, R21, and R29. In the data allocation of the 21st modification, the read voltages used in the second page read are R7, R10, R14, R24, R28, and R31. In the data allocation of the 21st modification, the read voltages used in the third page read are R3, R6, R9, R15, R18, and R25. In the data allocation of the 21st modification, the read voltages used in the fourth page read are R2, R5, R12, R16, R19, R22, and R26. In the data allocation of the 21st modification, the read voltages used in the fifth page read are R1, R11, R20, R23, R27, and R30.

[0156] (22nd Modification) 40 is a table showing data allocation and read voltage settings in Modification Example 22. Data allocation and read voltage settings in Modification Example 22 will be described below with reference to FIG.

[0157] In the data allocation of the 22nd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D27, D11, D3, D2, D0, D16, D20, D21, D29, D13, D9, D1, D17, D19, D23, D7, D5, D4, D12, D8, D10, D26, D18, D22, D6, D14 and D15, respectively.

[0158] In the data allocation of the 22nd modification, the read voltages used in the first page read are R6, R10, R14, R17, R20, R26, and R29. In the data allocation of the 22nd modification, the read voltages used in the second page read are R7, R13, R16, R23, R27, and R30. In the data allocation of the 22nd modification, the read voltages used in the third page read are R3, R11, R15, R19, R24, and R28. In the data allocation of the 22nd modification, the read voltages used in the fourth page read are R2, R5, R9, R18, R21, and R25. In the data allocation of the 22nd modification, the read voltages used in the fifth page read are R1, R4, R8, R12, R22, and R31.

[0159] (23rd Modification) 41 is a table showing data allocation and read voltage settings in Modification Example 23. The data allocation and read voltage settings in Modification Example 23 will be described below with reference to FIG.

[0160] In the data allocation of the 23rd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D19, D18, D26, D10, D14, D12, D4, D5, D1, D3, D2, D6, D22, D20, D16, D0, D8, D9, D13, D29, D21, D23, D7, D15, D11 and D27, respectively.

[0161] In the data allocation of the 23rd modification, the read voltages used in the first page read are R9, R18, R21, R25, R28, and R31. In the data allocation of the 23rd modification, the read voltages used in the second page read are R5, R8, R12, R22, R26, and R29. In the data allocation of the 23rd modification, the read voltages used in the third page read are R3, R10, R14, R17, R20, R24, and R30. In the data allocation of the 23rd modification, the read voltages used in the fourth page read are R2, R6, R11, R15, R19, and R27. In the data allocation of the 23rd modification, the read voltages used in the fifth page read are R1, R4, R7, R13, R16, and R23.

[0162] (24th Modification) 42 is a table showing data allocation and read voltage settings in Modification Example 24. The data allocation and read voltage settings in Modification Example 24 will be described below with reference to FIG.

[0163] In the data allocation of the 24th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D21, D20, D22, D6, D2, D3, D1, D9, D8, D10, D26, D18, D16, D0, D4, D12, D14, D15, D11, D27, D19, D23, D7, D5, D13 and D29, respectively.

[0164] In the data allocation of the 24th modification, the read voltages used in the first page read are R9, R16, R19, R25, R28, and R31. In the data allocation of the 24th modification, the read voltages used in the second page read are R5, R13, R17, R21, R26, and R30. In the data allocation of the 24th modification, the read voltages used in the third page read are R3, R6, R10, R20, R24, and R27. In the data allocation of the 24th modification, the read voltages used in the fourth page read are R2, R8, R12, R15, R18, R22, and R29. In the data allocation of the 24th modification, the read voltages used in the fifth page read are R1, R4, R7, R11, R14, and R23.

[0165] (25th Modification) 43 is a table showing data allocation and read voltage settings in Modification Example 25. The data allocation and read voltage settings in Modification Example 25 will be described below with reference to FIG.

[0166] In the data allocation of the 25th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D18, D22, D6, D14, D12, D13, D29, D25, D17, D1, D5, D7, D15, D11, D9, D8, D0, D4, D20, D21, D23, D19, D3, D2, D10, D26 and D27, respectively.

[0167] In the data allocation of the 25th modification, the read voltages used in the first page read are R7, R11, R14, R23, R27, and R30. In the data allocation of the 25th modification, the read voltages used in the second page read are R4, R8, R13, R17, R21, and R29. In the data allocation of the 25th modification, the read voltages used in the third page read are R3, R6, R12, R15, R18, R22, and R26. In the data allocation of the 25th modification, the read voltages used in the fourth page read are R2, R5, R9, R16, R19, and R25. In the data allocation of the 25th modification, the read voltages used in the fifth page read are R1, R10, R20, R24, R28, and R31.

[0168] (26th Modification) 44 is a table showing data allocation and read voltage settings in Modification Example 26. The data allocation and read voltage settings in Modification Example 26 will be described below with reference to FIG.

[0169] In the data allocation of the 26th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D29, D21, D20, D22, D18, D26, D10, D14, D6, D7, D23, D19, D17, D1, D5, D4, D12, D8, D9, D25 and D27, respectively.

[0170] In the data allocation of the 26th modification, the read voltages used in the first page read are R5, R11, R17, R24, and R30. In the data allocation of the 26th modification, the read voltages used in the second page read are R4, R8, R12, R16, R19, and R27. In the data allocation of the 26th modification, the read voltages used in the third page read are R3, R9, R15, R18, R22, R25, and R28. In the data allocation of the 26th modification, the read voltages used in the fourth page read are R2, R6, R10, R14, R23, and R31. In the data allocation of the 26th modification, the read voltages used in the fifth page read are R1, R7, R13, R20, R26, and R29.

[0171] (27th Modification) 45 is a table showing data allocation and read voltage settings in Modification Example 27. Data allocation and read voltage settings in Modification Example 27 will be described below with reference to FIG.

[0172] In the data allocation of the 27th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D0, D4, D20, D22, D23, D7, D5, D1, D9, D25, D27, D19, D3, D2, D6, D14, D12, D13, D29, D21, D17, D16, D18, D26, D10, D11 and D15, respectively.

[0173] In the data allocation of the 27th modification, the read voltages used in the first page read are R4, R7, R10, R14, R17, R23, and R29. In the data allocation of the 27th modification, the read voltages used in the second page read are R5, R13, R16, R20, R24, and R28. In the data allocation of the 27th modification, the read voltages used in the third page read are R3, R6, R12, R19, R25, and R31. In the data allocation of the 27th modification, the read voltages used in the fourth page read are R2, R8, R11, R15, R21, and R27. In the data allocation of the 27th modification, the read voltages used in the fifth page read are R1, R9, R18, R22, R26, and R30.

[0174] (28th Variation) 46 is a table showing data allocation and read voltage settings in Modification Example 28. Data allocation and read voltage settings in Modification Example 28 will be described below with reference to FIG.

[0175] In the data allocation of the 28th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D23, D19, D27, D25, D9, D8, D10, D26, D18, D22, D6, D14, D12, D13, D29, D21, D20, D4, D0, D2, D3, D11 and D15, respectively.

[0176] In the data allocation of the 28th modification, the read voltages used in the first page read are R6, R9, R13, R1, R19, R23, and R26. In the data allocation of the 28th modification, the read voltages used in the second page read are R4, R11, R17, R20, R24, and R30. In the data allocation of the 28th modification, the read voltages used in the third page read are R3, R7, R10, R18, R27, and R31. In the data allocation of the 28th modification, the read voltages used in the fourth page read are R2, R8, R12, R15, R21, and R28. In the data allocation of the 28th modification, the read voltages used in the fifth page read are R1, R5, R14, R22, R25, and R29.

[0177] (29th Variation) 47 is a table showing data allocation and read voltage settings in Modification Example 29. Data allocation and read voltage settings in Modification Example 29 will be described below with reference to FIG.

[0178] In the data allocation of the 29th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D10, D26, D18, D19, D23, D7, D5, D1, D17, D25 and D27, respectively.

[0179] In the data allocation of the 29th modification, the read voltages used in the first page read are R5, R14, R18, R22, R26, and R29. In the data allocation of the 29th modification, the read voltages used in the second page read are R4, R7, R11, R17, R23, and R30. In the data allocation of the 29th modification, the read voltages used in the third page read are R3, R6, R10, R13, R19, R25, and R28. In the data allocation of the 29th modification, the read voltages used in the fourth page read are R2, R8, R15, R21, R27, and R31. In the data allocation of the 29th modification, the read voltages used in the fifth page read are R1, R9, R12, R16, R20, and R24.

[0180] (30th Variation) 48 is a table showing data allocation and read voltage settings in Modification Example 30. Data allocation and read voltage settings in Modification Example 30 will be described below with reference to FIG.

[0181] In the data allocation of the 30th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D9, D13, D29, D21, D23, D19, D18, D26, D10, D14, D12, D4, D5, D1, D17, D25, D27, D11, D3, D2, D0, D16, D20, D22, D6, D7 and D15, respectively.

[0182] In the data allocation of the 30th modification, the read voltages used in the first page read are R4, R7, R13, R19, R22, R26, and R29. In the data allocation of the 30th modification, the read voltages used in the second page read are R8, R12, R16, R20, R23, and R31. In the data allocation of the 30th modification, the read voltages used in the third page read are R3, R6, R10, R14, R18, and R27. In the data allocation of the 30th modification, the read voltages used in the fourth page read are R2, R9, R15, R21, R25, and R28. In the data allocation of the 30th modification, the read voltages used in the fifth page read are R1, R5, R11, R17, R24, and R30.

[0183] (31st Modification) 49 is a table showing data allocation and read voltage settings in Modification Example 31. Data allocation and read voltage settings in Modification Example 31 will be described below with reference to FIG.

[0184] In the data allocation of the 31st modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D19, D23, D7, D5, D1, D9, D8, D12, D4, D6, D22, D18, D26, D10, D14, D15, D13, D29, D21, D20, D16, D0, D2, D3, D11 and D27, respectively.

[0185] In the data allocation of the 31st modification, the read voltages used in the first page read are R8, R16, R19, R23, R27, and R31. In the data allocation of the 31st modification, the read voltages used in the second page read are R5, R11, R14, R18, R24, and R30. In the data allocation of the 31st modification, the read voltages used in the third page read are R3, R7, R10, R13, R17, R20, and R26. In the data allocation of the 31st modification, the read voltages used in the fourth page read are R2, R6, R9, R15, R22, and R28. In the data allocation of the 31st modification, the read voltages used in the fifth page read are R1, R4, R12, R21, R25, and R29.

[0186] (32nd Variation) 50 is a table showing data allocation and read voltage settings in Modification Example 32. The data allocation and read voltage settings in Modification Example 32 will be described below with reference to FIG.

[0187] In the data allocation of the 32nd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D29, D21, D23, D19, D3, D11 and D15, respectively.

[0188] In the data allocation of the 32nd modification, the read voltages used in the first page read are R6, R12, R15, R19, R22, R25, and R29. In the data allocation of the 32nd modification, the read voltages used in the second page read are R4, R10, R17, R23, R26, and R30. In the data allocation of the 32nd modification, the read voltages used in the third page read are R3, R7, R11, R20, R28, and R31. In the data allocation of the 32nd modification, the read voltages used in the fourth page read are R2, R8, R14, R18, R21, and R27. In the data allocation of the 32nd modification, the read voltages used in the fifth page read are R1, R5, R9, R13, R16, and R24.

[0189] (33rd Variation) 51 is a table showing data allocation and read voltage settings in Modification Example 33. The data allocation and read voltage settings in Modification Example 33 will be described below with reference to FIG.

[0190] In the data allocation of the 33rd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D1, D5, D4, D20, D16, D18, D26, D10, D11, D9, D13, D29, D21, D23, D22, D6, D2, D0, D8, D12, D14, D15, D7, D3, D19 and D27, respectively.

[0191] In the data allocation of the 33rd modification, the read voltages used in the first page read are R6, R9, R13, R17, R21, and R30. In the data allocation of the 33rd modification, the read voltages used in the second page read are R5, R12, R18, R24, R28, and R31. In the data allocation of the 33rd modification, the read voltages used in the third page read are R3, R7, R10, R16, R22, R25, and R29. In the data allocation of the 33rd modification, the read voltages used in the fourth page read are R2, R11, R15, R19, R23, and R26. In the data allocation of the 33rd modification, the read voltages used in the fifth page read are R1, R4, R8, R14, R20, and R27.

[0192] (34th Variation) 52 is a table showing data allocation and read voltage settings in Modification Example 34. The data allocation and read voltage settings in Modification Example 34 will be described below with reference to FIG.

[0193] In the data allocation of the 34th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D27, D19, D3, D1, D9, D8, D12, D14, D6, D2, D0, D16, D17, D21, D23, D7, D15, D11, D10, D26, D18, D22, D20, D4, D5, D13 and D29, respectively.

[0194] In the data allocation of the 34th modification, the read voltages used in the first page read are R7, R16, R20, R24, R28, and R31. In the data allocation of the 34th modification, the read voltages used in the second page read are R6, R9, R13, R21, R25, and R30. In the data allocation of the 34th modification, the read voltages used in the third page read are R3, R11, R14, R18, R22, and R26. In the data allocation of the 34th modification, the read voltages used in the fourth page read are R2, R5, R8, R12, R15, R19, and R27. In the data allocation of the 34th modification, the read voltages used in the fifth page read are R1, R4, R10, R17, R23, and R29.

[0195] (35th Variation) 53 is a table showing data allocation and read voltage settings in Modification Example 35. The data allocation and read voltage settings in Modification Example 35 will be described below with reference to FIG.

[0196] In the data allocation of the 35th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D9, D1, D3, D2, D6, D14, D12, D13, D29, D21, D17, D16, D0, D8, D10, D26, D18, D22, D20, D4, D5, D7, D23, D19, D27, D11 and D15, respectively.

[0197] In the data allocation of the 35th modification, the read voltages used in the first page read are R5, R13, R17, R20, R24, R27, and R30. In the data allocation of the 35th modification, the read voltages used in the second page read are R6, R10, R14, R18, R21, and R29. In the data allocation of the 35th modification, the read voltages used in the third page read are R3, R9, R15, R22, R28, and R31. In the data allocation of the 35th modification, the read voltages used in the fourth page read are R2, R7, R11, R19, R23, and R26. In the data allocation of the 35th modification, the read voltages used in the fifth page read are R1, R4, R8, R12, R16, and R25.

[0198] (36th Variation) 54 is a table showing data allocation and read voltage settings in Modification Example 36. Data allocation and read voltage settings in Modification Example 36 will be described below with reference to FIG.

[0199] In the data allocation of the 36th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D27, D11, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D0, D16, D18, D26, D10, D14, D12, D4, D5, D1, D17, D19, D23, D7 and D15, respectively.

[0200] In the data allocation of the 36th modification, the read voltages used in the first page read are R6, R10, R14, R18, R21, R27, and R30. In the data allocation of the 36th modification, the read voltages used in the second page read are R7, R13, R17, R20, R24, and R31. In the data allocation of the 36th modification, the read voltages used in the third page read are R3, R9, R15, R22, R26, and R29. In the data allocation of the 36th modification, the read voltages used in the fourth page read are R2, R5, R11, R19, R23, and R28. In the data allocation of the 36th modification, the read voltages used in the fifth page read are R1, R4, R8, R12, R16, and R25.

[0201] (37th Variation) 55 is a table showing data allocation and read voltage settings in Modification Example 37. Data allocation and read voltage settings in Modification Example 37 will be described below with reference to FIG.

[0202] In the data allocation of the 37th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D18, D22, D6, D7, D15, D11, D9, D8, D0, D2, D3, D19, D23, D21, D20, D4, D12, D14, D10, D26, D27, D25, D17, D1, D5, D13 and D29, respectively.

[0203] In the data allocation of the 37th modification, the read voltages used in the first page read are R7, R16, R20, R24, R28, and R31. In the data allocation of the 37th modification, the read voltages used in the second page read are R4, R9, R13, R21, R27, and R30. In the data allocation of the 37th modification, the read voltages used in the third page read are R3, R6, R10, R17, R23, and R29. In the data allocation of the 37th modification, the read voltages used in the fourth page read are R2, R5, R11, R14, R18, R22, and R26. In the data allocation of the 37th modification, the read voltages used in the fifth page read are R1, R8, R12, R15, R19, and R25.

[0204] (38th Variation) 56 is a table showing data allocation and read voltage settings in Modification Example 38. Data allocation and read voltage settings in Modification Example 38 will be described below with reference to FIG.

[0205] In the data allocation of the 38th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D1, D3, D2, D6, D22, D20, D16, D0, D8, D9, D13, D29, D21, D23, D19, D18, D26, D10, D14, D12, D4, D5, D7, D15, D16, and D27, respectively.

[0206] In the data allocation of the 38th modification, the read voltages used in the first page read are R6, R10, R13, R17, R23, and R31. In the data allocation of the 38th modification, the read voltages used in the second page read are R5, R14, R18, R22, R26, and R29. In the data allocation of the 38th modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, R24, and R30. In the data allocation of the 38th modification, the read voltages used in the fourth page read are R2, R7, R11, R19, R25, and R28. In the data allocation of the 38th modification, the read voltages used in the fifth page read are R1, R4, R8, R15, R21, and R27.

[0207] (39th Variation) 57 is a table showing data allocation and read voltage settings in Modification Example 39. Data allocation and read voltage settings in Modification Example 39 will be described below with reference to FIG.

[0208] In the data allocation of the 39th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D27, D25, D17, D21, D20, D22, D6, D2, D3, D1, D9, D8, D10, D26, D18, D19, D23, D7, D5, D13 and D29, respectively.

[0209] In the data allocation of the 39th modification, the read voltages used in the first page read are R5, R11, R17, R24, R28, and R31. In the data allocation of the 39th modification, the read voltages used in the second page read are R4, R7, R13, R21, R25, and R30. In the data allocation of the 39th modification, the read voltages used in the third page read are R3, R6, R10, R14, R18, and R27. In the data allocation of the 39th modification, the read voltages used in the fourth page read are R2, R8, R12, R16, R20, R23, and R29. In the data allocation of the 39th modification, the read voltages used in the fifth page read are R1, R9, R15, R19, R22, and R26.

[0210] (40th Variation) 58 is a table showing data allocation and read voltage settings in Modification Example 40. Data allocation and read voltage settings in Modification Example 40 will be described below with reference to FIG.

[0211] In the data allocation of the 40th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D21, D23, D7, D6, D14, D12, D8, D0, D2, D3, D19, D27, D25, D9, D1, D5, D4, D20, D22, D18, D26, D10, D11, D15, D13 and D29, respectively.

[0212] In the data allocation of the 40th modification, the read voltages used in the first page read are R8, R16, R19, R23, R27, and R31. In the data allocation of the 40th modification, the read voltages used in the second page read are R4, R10, R13, R17, R20, and R26. In the data allocation of the 40th modification, the read voltages used in the third page read are R3, R6, R12, R21, R25, and R29. In the data allocation of the 40th modification, the read voltages used in the fourth page read are R2, R7, R11, R14, R18, R24, and R30. In the data allocation of the 40th modification, the read voltages used in the fifth page read are R1, R5, R9, R15, R22, and R28.

[0213] (41st Variation) 59 is a table showing data allocation and read voltage settings in Modification Example 41. The data allocation and read voltage settings in Modification Example 41 will be described below with reference to FIG.

[0214] In the data allocation of the 41st modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D15, D11, D3, D19, D23, D21 and D29, respectively.

[0215] In the data allocation of the 41st modification, the read voltages used in the first page read are R6, R12, R15, R19, R22, and R28. In the data allocation of the 41st modification, the read voltages used in the second page read are R4, R10, R17, R23, R27, and R31. In the data allocation of the 41st modification, the read voltages used in the third page read are R3, R7, R11, R20, R26, and R29. In the data allocation of the 41st modification, the read voltages used in the fourth page read are R2, R8, R14, R18, R21, R25, and R30. In the data allocation of the 41st modification, the read voltages used in the fifth page read are R1, R5, R9, R13, R16, and R24.

[0216] (42nd Variation) 60 is a table showing data allocation and read voltage settings in Modification Example 42. Data allocation and read voltage settings in Modification Example 42 will be described below with reference to FIG.

[0217] In the data allocation of the 42nd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D27, D19, D3, D7, D15, D14, D12, D8, D0, D2, D6, D22, D23, D21, D17, D1, D9, D11, D10, D26, D18, D16, D20, D4, D5, D13 and D29, respectively.

[0218] In the data allocation of the 42nd modification, the read voltages used in the first page read are R7, R16, R20, R24, R28, and R31. In the data allocation of the 42nd modification, the read voltages used in the second page read are R6, R9, R13, R21, R25, and R30. In the data allocation of the 42nd modification, the read voltages used in the third page read are R3, R8, R12, R15, R19, and R27. In the data allocation of the 42nd modification, the read voltages used in the fourth page read are R2, R5, R11, R14, R18, R22, and R26. In the data allocation of the 42nd modification, the read voltages used in the fifth page read are R1, R4, R10, R17, R23, and R29.

[0219] (43rd Variation) 61 is a table showing data allocation and read voltage settings in Modification Example 43. The data allocation and read voltage settings in Modification Example 43 will be described below with reference to FIG.

[0220] In the data allocation of the 43rd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D25, D17, D1, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D0, D16, D18, D26, D10, D14, D12, D4, D5, D7, D23, D19, D27, D11 and D15, respectively.

[0221] In the data allocation of the 43rd modification, the read voltages used in the first page read are R6, R10, R14, R18, R21, R27, and R30. In the data allocation of the 43rd modification, the read voltages used in the second page read are R5, R13, R17, R20, R24, and R29. In the data allocation of the 43rd modification, the read voltages used in the third page read are R3, R9, R15, R22, R28, and R31. In the data allocation of the 43rd modification, the read voltages used in the fourth page read are R2, R7, R11, R19, R23, and R26. In the data allocation of the 43rd modification, the read voltages used in the fifth page read are R1, R4, R8, R12, R16, and R25.

[0222] (44th Variation) 62 is a table showing data allocation and read voltage settings in Modification Example 44. Data allocation and read voltage settings in Modification Example 44 will be described below with reference to FIG.

[0223] In the data allocation of the 44th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D21, D5, D7, D15, D11, D10, D8, D0, D4, D20, D22, D23, D19, D3, D1, D9, D25, D27, D26, D18, D2, D6, D14, D12, D13 and D29, respectively.

[0224] In the data allocation of the 44th modification, the read voltages used in the first page read are R7, R15, R19, R22, R26, and R31. In the data allocation of the 44th modification, the read voltages used in the second page read are R4, R9, R13, R21, R25, and R28. In the data allocation of the 44th modification, the read voltages used in the third page read are R3, R6, R10, R14, R18, and R27. In the data allocation of the 44th modification, the read voltages used in the fourth page read are R2, R8, R12, R16, R20, R23, and R29. In the data allocation of the 44th modification, the read voltages used in the fifth page read are R1, R5, R11, R17, R24, and R30.

[0225] (45th Variation) 63 is a table showing data allocation and read voltage settings in Modification Example 45. Data allocation and read voltage settings in Modification Example 45 will be described below with reference to FIG.

[0226] In the data allocation of the 45th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D1, D9, D11, D15, D14, D6, D2, D3, D19, D17, D21, D20, D4, D12, D8, D10, D26, D18, D22, D23, D7, D5, D13, D29, D25 and D27, respectively.

[0227] In the data allocation of the 45th modification, the read voltages used in the first page read are R5, R14, R18, R22, R26, and R29. In the data allocation of the 45th modification, the read voltages used in the second page read are R4, R7, R11, R19, R23, and R28. In the data allocation of the 45th modification, the read voltages used in the third page read are R3, R9, R12, R16, R20, R24, and R30. In the data allocation of the 45th modification, the read voltages used in the fourth page read are R2, R8, R15, R21, R27, and R31. In the data allocation of the 45th modification, the read voltages used in the fifth page read are R1, R6, R10, R13, R17, and R25.

[0228] (46th Variation) 64 is a table showing data allocation and read voltage settings in Modification Example 46. The data allocation and read voltage settings in Modification Example 46 will be described below with reference to FIG.

[0229] In the data allocation of the 46th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D21, D23, D7, D15, D11, D10, D26, D18, D22, D20, D4, D5, D1, D3, D19, D27, D25, D9, D8, D0, D2, D6, D14, D12, D13 and D29, respectively.

[0230] In the data allocation of the 46th modification, the read voltages used in the first page read are R8, R12, R16, R20, R23, and R31. In the data allocation of the 46th modification, the read voltages used in the second page read are R4, R9, R13, R21, R25, and R28. In the data allocation of the 46th modification, the read voltages used in the third page read are R3, R6, R10, R14, R18, and R27. In the data allocation of the 46th modification, the read voltages used in the fourth page read are R2, R7, R15, R19, R22, R26, and R29. In the data allocation of the 46th modification, the read voltages used in the fifth page read are R1, R5, R11, R17, R24, and R30.

[0231] (47th Variation) 65 is a table showing data allocation and read voltage settings of Modification Example 47. Data allocation and read voltage settings of Modification Example 47 will be described below with reference to FIG.

[0232] In the data allocation of the 47th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D3, D2, D6, D22, D20, D21, D17, D1, D9, D8, D10, D26, D18, D19, D23, D7, D5, D13, D29, D25 and D27, respectively.

[0233] In the data allocation of the 47th modification, the read voltages used in the first page read are R5, R14, R18, R22, R26, and R29. In the data allocation of the 47th modification, the read voltages used in the second page read are R4, R7, R11, R19, R23, and R28. In the data allocation of the 47th modification, the read voltages used in the third page read are R3, R6, R10, R13, R17, R25, and R30. In the data allocation of the 47th modification, the read voltages used in the fourth page read are R2, R8, R15, R21, R27, and R31. In the data allocation of the 47th modification, the read voltages used in the fifth page read are R1, R9, R12, R16, R20, and R24.

[0234] (48th Variation) 66 is a table showing data allocation and read voltage settings of Modification Example 48. Data allocation and read voltage settings of Modification Example 48 will be described below with reference to FIG.

[0235] In the data allocation of the 48th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D22, D18, D26, D10, D14, D12, D4, D20, D21, D23, D19, D27, D25, D9, D8, D0, D2, D3, D11, D15, D13 and D29, respectively.

[0236] In the data allocation of the 48th modification, the read voltages used in the first page read are R6, R10, R13, R17, R23, and R31. In the data allocation of the 48th modification, the read voltages used in the second page read are R4, R12, R16, R21, R25, and R28. In the data allocation of the 48th modification, the read voltages used in the third page read are R3, R7, R11, R14, R20, and R29. In the data allocation of the 48th modification, the read voltages used in the fourth page read are R2, R8, R15, R19, R22, R26, and R30. In the data allocation of the 48th modification, the read voltages used in the fifth page read are R1, R5, R9, R18, R24, and R27.

[0237] (49th Variation) 67 is a table showing data allocation and read voltage settings in Modification Example 49. Data allocation and read voltage settings in Modification Example 49 will be described below with reference to FIG.

[0238] In the data allocation of the 49th modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D0, D2, D10, D26, D27, D25, D17, D21, D23, D7, D6, D14, D12, D8, D9, D1, D5, D4, D20, D22, D18, D19, D3, D11, D15, D13 and D29, respectively.

[0239] In the data allocation of the 49th modification, the read voltages used in the first page read are R5, R8, R14, R23, R27, and R31. In the data allocation of the 49th modification, the read voltages used in the second page read are R4, R7, R11, R16, R20, and R28. In the data allocation of the 49th modification, the read voltages used in the third page read are R3, R12, R18, R21, R25, and R29. In the data allocation of the 49th modification, the read voltages used in the fourth page read are R2, R6, R10, R13, R17, R24, and R30. In the data allocation of the 49th modification, the read voltages used in the fifth page read are R1, R9, R15, R19, R22, and R26.

[0240] (50th Variation) 68 is a table showing data allocation and read voltage settings in Modification Example 50. Data allocation and read voltage settings in Modification Example 50 will be described below with reference to FIG.

[0241] In the data allocation of the 50th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D9, D1, D5, D7, D6, D14, D10, D26, D18, D22, D20, D4, D12, D13, D29, D21, D23, D19, D3, D2, D0, D16, D17, D25, D27, D11 and D15, respectively.

[0242] In the data allocation of the 50th modification, the read voltages used in the first page read are R4, R12, R16, R19, R23, R26, and R30. In the data allocation of the 50th modification, the read voltages used in the second page read are R6, R10, R13, R17, R20, and R28. In the data allocation of the 50th modification, the read voltages used in the third page read are R3, R7, R11, R14, R22, and R31. In the data allocation of the 50th modification, the read voltages used in the fourth page read are R2, R8, R15, R21, R25, and R29. In the data allocation of the 50th modification, the read voltages used in the fifth page read are R1, R5, R9, R18, R24, and R27.

[0243] (51st Variation) 69 is a table showing data allocation and read voltage settings in Modification Example 51. Data allocation and read voltage settings in Modification Example 51 will be described below with reference to FIG.

[0244] In the data allocation of the 51st modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D0, D2, D6, D14, D12, D13, D9, D25, D27, D19, D3, D1, D5, D4, D20, D22, D23, D7, D15, D11, D10, D26, D18, D16, D17, D21 and D29, respectively.

[0245] In the data allocation of the 51st modification, the read voltages used in the first page read are R4, R12, R15, R19, R22, and R26. In the data allocation of the 51st modification, the read voltages used in the second page read are R5, R8, R14, R23, R27, and R31. In the data allocation of the 51st modification, the read voltages used in the third page read are R3, R7, R11, R17, R24, and R30. In the data allocation of the 51st modification, the read voltages used in the fourth page read are R2, R6, R9, R13, R16, R20, and R28. In the data allocation of the 51st modification, the read voltages used in the fifth page read are R1, R10, R18, R21, R25, and R29.

[0246] (52nd Variation) 70 is a table showing data allocation and read voltage settings in Modification Example 52. The data allocation and read voltage settings in Modification Example 52 will be described below with reference to FIG.

[0247] In the data allocation of the 52nd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D16, D17, D19, D23, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D15, D11, D3, D1, D5, D21 and D29, respectively.

[0248] In the data allocation of the 52nd modification, the read voltages used in the first page read are R8, R12, R15, R19, R22, and R30. In the data allocation of the 52nd modification, the read voltages used in the second page read are R4, R10, R17, R23, R27, and R31. In the data allocation of the 52nd modification, the read voltages used in the third page read are R3, R7, R11, R20, R26, and R29. In the data allocation of the 52nd modification, the read voltages used in the fourth page read are R2, R6, R14, R18, R21, R25, and R28. In the data allocation of the 52nd modification, the read voltages used in the fifth page read are R1, R5, R9, R13, R16, and R24.

[0249] (53rd Variation) 71 is a table showing data allocation and read voltage settings in Modification Example 53. Data allocation and read voltage settings in Modification Example 53 will be described below with reference to FIG.

[0250] In the data allocation of the 53rd modification, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 1 are assigned the data sets D31, D30, D28, D24, D8, D9, D13, D29, D21, D20, D22, D6, D2, D0, D16, D17, D25, D27, D11, D3, D1, D5, D4, D12, D14, D10, D26, D18, D19, D23, D7 and D15, respectively.

[0251] In the data allocation of the 53rd modification, the read voltages used in the first page read are R4, R7, R11, R14, R18, R26, and R30. In the data allocation of the 53rd modification, the read voltages used in the second page read are R8, R16, R19, R23, R27, and R31. In the data allocation of the 53rd modification, the read voltages used in the third page read are R3, R6, R12, R21, R25, and R29. In the data allocation of the 53rd modification, the read voltages used in the fourth page read are R2, R10, R13, R17, R20, and R24. In the data allocation of the 53rd modification, the read voltages used in the fifth page read are R1, R5, R9, R15, R22, and R28.

[0252] [1-5] Characteristics of each data allocation The data allocation in each of the first to fifteenth modifications is "7-6-6-6-6 coding." That is, in each of the first to fifteenth modifications, the difference between the maximum and minimum values ​​of the number of reads set to confirm data between pages is "1," as in the first embodiment. In each of the first to fifteenth modifications, the read voltage interval in each page is a minimum of "3" and a maximum of "8," as in the first embodiment. In each of the sixteenth and seventeenth modifications, the read voltage interval in each page is a minimum of "3" and a maximum of "9." In addition, in each of the sixteenth and seventeenth modifications, the read voltage interval in a page with seven reads is only "4." In each of the eighteenth to twenty-fifth modifications, the read voltage interval in each page is a minimum of "3" and a maximum of "10." In the data allocation of each of the 26th to 53rd modified examples, the interval between read voltages in each page is at least "3" and at most "9".

[0253] In addition to the conditions explained in the effect of the embodiment, the following conditions (1) to (5) are conditions that should be avoided as much as possible when considering data allocation. (1) The lowest read voltage used in the read operation of the page where the number of reads is seven is separated by only one state from the lowest read voltage R1 of the read voltages R1 to R31. (2) The highest read voltage used in the read operation of the page where the number of reads is seven is separated from the highest read voltage R31 of the read voltages R1 to R31 by only one state. (3) The minimum interval between the multiple read voltages used in the page read operation in which the number of reads is 7 is "3 (i.e., 3 states)." (4) The minimum interval between the multiple read voltages used in the page read operation using the lowest read voltage R1 or the highest read voltage R31 is “3 (i.e., 3 states)” or the maximum interval is “9 (i.e., 9 states).” (5) There is a page that uses both the lowest read voltage R1 and the highest read voltage R31 among the read voltages R1 to R31 for the read operation. In other words, the first to fifth pages include pages that use both the read voltages R1 and R31 for the read operation. (6) The minimum interval of the read voltage used in the read operation of each page is "3 (ie, 3 states)" and the maximum interval is "9 (ie, 9 states)" or more.

[0254] The priority of avoidance for each condition is (1), (2)<(3), (4)<(5)<(6). The fewer conditions (1) to (6) that are satisfied, the closer the data allocation to ideal data. Furthermore, when comparing satisfying one condition with a lower priority with satisfying one condition with a higher priority, satisfying one condition with a lower priority is closer to ideal data allocation. When considering conditions (1) to (6), the embodiment and the first to seventeenth modifications are classified into, for example, first to seventh groups.

[0255] The first group includes the embodiment and the first to fourth modifications. The data allocation of the first group satisfies one of the conditions (1) and (2) among the conditions (1) to (6). That is, the data allocation of the first group does not satisfy the other of the conditions (1) and (2) and the conditions (3), (4), (5), and (6).

[0256] The second group includes the fifth variation. The data allocation of the second group satisfies conditions (2) and (4). That is, the data allocation of the second group does not satisfy conditions (1), (3), (5), and (6).

[0257] The third group includes the sixth and seventh variants. The data allocation of the third group satisfies conditions (1), (2), and (3). That is, the data allocation of the third group does not satisfy conditions (4), (5), and (6).

[0258] The fourth group includes the eighth modification. The data allocation of the fourth group satisfies conditions (2), (3), and (4). That is, the data allocation of the fourth group does not satisfy conditions (1), (5), and (6).

[0259] The fifth group includes the ninth to eleventh modifications. The data allocation of the fifth group satisfies the conditions (1), (2), (3), and (4). That is, the data allocation of the fifth group does not satisfy the conditions (5) and (6).

[0260] The sixth group includes the twelfth to fifteenth modifications. The data allocation of the sixth group satisfies the conditions (3) and (5). That is, the data allocation of the sixth group does not satisfy the conditions (1), (2), (4), and (6).

[0261] The seventh group includes the sixteenth and seventeenth modifications. The data allocation of the seventh group satisfies the conditions (4) and (6). That is, the data allocation of the seventh group does not satisfy the conditions (1), (2), (3), and (5).

[0262] When scoring is performed using conditions (1) to (6), the read efficiency is ranked from best to worst as follows: Group 1, Group 2, Group 3, Group 4, Group 5, Group 6, and Group 7. The data allocations of the 26th to 53rd variants have read efficiency similar to that of Group 7, for example. The read efficiency of the data allocations of the 18th to 25th variants is slightly inferior to that of Group 7 because the maximum read voltage interval in each page is 10. Furthermore, the 18th, 19th, 20th, 21st, 23rd, and 24th variants do not have any pages that use both the lowest read voltage R1 and the highest read voltage R31. Therefore, the read efficiency of each of the 18th, 19th, 20th, 21st, 23rd, and 24th variations is higher than that of each of the 22nd and 25th variations, which have pages using both the lowest read voltage R1 and the highest read voltage R31. The memory device 20 can perform an efficient read operation regardless of the data allocation that belongs to any group.

[0263] Conditions (1) to (6) can be rephrased as the following conditions (1a) to (6a), respectively. Conditions (1a) to (6a) are conditions that are preferably met to the extent possible in addition to the conditions explained in the effects of the embodiment. (1a) The lowest read voltage used in the read operation of a page where the number of reads is 7 is two states or more away from the lowest read voltage R1 of the read voltages R1 to R31. (2a) The highest read voltage used in the read operation of the page for which the number of reads is 7 is two states or more away from the highest read voltage R31 of the read voltages R1 to R31. (3a) The minimum interval between the multiple read voltages used in the page read operation in which the number of reads is 7 is "4 (that is, 4 states)." (4a) The minimum interval between multiple read voltages used in a page read operation using the lowest read voltage R1 or the highest read voltage R31 is “4 (i.e., 4 states)” or the maximum interval is “8 (i.e., 8 states).” (5a) Of the read voltages R1 to R31, the lowest read voltage R1 and the highest read voltage R31 are used for read operations on different pages. In other words, the first to fifth pages do not include any pages that use both the read voltages R1 and R31 for read operations. (6a) The minimum interval of the read voltage used in the read operation of each page is "4 (ie, 4 states)" and the maximum interval is "8 (ie, 8 states)."

[0264] The priority for each condition is (1a), (2a) > (3a), (4a) > (5a) > (6a). The more conditions (1a) to (6a) that are met, the closer the data allocation is to the ideal data allocation. Furthermore, when comparing meeting one condition with a low priority with meeting one condition with a high priority, meeting one condition with a high priority is closer to the ideal data allocation.

[0265] [2] Second embodiment The configuration of the information processing system 1 according to the second embodiment is the same as that of the information processing system 1 according to the first embodiment. In the second embodiment, the memory device 20 executes a page-by-page read operation by applying a read voltage starting from the highest. The following describes the differences between the second embodiment and the first embodiment.

[0266] [2-1] Operation 72 is a timing chart showing an example of a first page read in the memory system MS according to the second embodiment. Fig. 72 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the first page read of the second embodiment. The first page read of the second embodiment will be described below with reference to Fig. 72.

[0267] When executing the first page read, the memory controller 10 transmits, for example, a command “01h”, a command “00h”, an address “ADD”, and a command “30h” in this order to the memory device 20. When the memory device 20 receives the command “30h”, the sequencer 204 transitions the memory device 20 from a ready state to a busy state based on the command and address stored in the register circuit 203.

[0268] Then, the sequencer 204 applies read voltages R30, R26, R22, R18, R12, R8, and R4 to the selected word line WLsel in this order. The sequencer 204 also asserts a control signal STB while each of the read voltages R30, R26, R22, R18, R12, R8, and R4 is being applied. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the first bit data read from the memory cell transistor MT connected to the selected word line WLsel, and stores the determination result in the latch circuit XDL.

[0269] Other operations of the first page read in the second embodiment are the same as those in the first embodiment. A read operation in which a higher read voltage is applied first is called, for example, a "reverse read." The memory device 20 according to the second embodiment can perform each of the second to fifth page reads by reverse read, similar to the first page read.

[0270] 72, the ground voltage VSS is applied to the selected word line WLsel, followed by the application of the read voltage to the selected word line WLsel. However, this is not limiting. For example, before the read voltage is applied to the selected word line WLsel, a predetermined voltage higher than the read voltage may be applied to the selected word line WLsel. The predetermined voltage value may be equal to the voltage applied to the unselected word lines WL during a read operation, or may be a voltage higher than the highest read voltage R31.

[0271] [2-2] Effects of the second embodiment As described above, the memory device MD according to the second embodiment performs a read operation in which read voltages are applied in the reverse order to that of the first embodiment. In this way, the data allocation of the first embodiment can be used regardless of the order in which the read voltages are applied. Note that the reverse read described in the second embodiment may be applied to any of the data allocations of the first to seventeenth modifications.

[0272] [3] Third embodiment The configuration of the information processing system 1 according to the third embodiment is the same as that of the information processing system 1 according to the first embodiment. In the third embodiment, the memory device 20 executes a sequential read operation (hereinafter referred to as a sequential read) of five pages of data stored in the cell unit CU. The following describes the differences between the third embodiment and the first embodiment.

[0273] [3-1] Operation Fig. 73 is a timing chart showing an example of sequential read in the memory system MS according to the third embodiment. Fig. 73 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during sequential read in the third embodiment. The sequential read in the third embodiment will be described below with reference to Fig. 73.

[0274] When executing a sequential read, the memory controller 10 transmits, for example, a command “xxh”, a command “00h”, an address “ADD”, and a command “30h” in this order to the memory device 20. The command “xxh” is a command that specifies a sequential read.

[0275] When the memory device 20 receives the command "30h," the sequencer 204 transitions the memory device 20 from a ready state to a busy state based on the command and address stored in the register circuit 203. Then, the sequencer 204 applies read voltages R1 to R31 to the selected word line WLsel in this order. Furthermore, the sequencer 204 asserts a control signal STB while each of the read voltages R1 to R31 is being applied. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (determines) the first to fifth bits of data read from the memory cell transistor MT connected to the selected word line WLsel, and stores the determination results in the latch circuits ADL, BDL, CDL, DDL, and EDL, respectively.

[0276] For example, when reading using the read voltage R24 is completed and the fourth bit data is determined, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the transition of the memory device 20 from the busy state to the ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (fourth page data PG4) stored in each latch circuit DDL of the sense amplifier module 209, and the fourth page data PG4 is output to the memory controller 10.

[0277] Furthermore, while the fourth page data PG4 is being output to the memory controller 10, reading using the read voltages R25 to R31 is completed, and the first, second, third, and fifth page data are each determined. When the memory controller 10 has completed receiving the fourth page data PG4, it instructs the memory device 20 to output data in the order in which the data was determined (PG2, PG5, PG1, and PG3, for example). When the memory controller 10 has received five pages of data, it ends the sequential read.

[0278] In this example, the case where data is output in the order in which the data is confirmed is illustrated, but the present invention is not limited to this. When there are multiple pages with confirmed data, the order in which the pages are output from the memory device 20 to the memory controller 10 can be freely designed. In the third embodiment, the case where a lower read voltage is applied first in sequential read is illustrated, but the present invention is not limited to this. The sequential read may be performed by reverse read as in the second embodiment.

[0279] [3-2] Effects of the third embodiment As described above, the memory device 20 according to the third embodiment can simultaneously read five pages of data stored in the cell unit CU. The data allocation according to the first embodiment can also be applied when sequential reading is performed. Sequential reading may be applied to any of the data allocations according to the first to seventeenth modifications. Furthermore, the memory system MS according to the third embodiment can improve the latency in sequential reading by sequentially outputting data from the memory device 20 to the memory controller 10 starting from the page where data has been confirmed.

[0280] [3-3] Modification of the third embodiment The memory device 20 can accelerate the timing of data output in sequential read by devising page allocation or using reverse read. For example, in the data allocation of the embodiment shown in FIG. 8, the first page and the second page may be swapped, and sequential read using reverse read (i.e., a read operation in which read voltages are applied in order from the highest read voltage) may be performed. In this case, the memory device 20 can output data of the first page after reading using read voltage R6, and can output data of the second page after reading using read voltage R3. This can improve the latency of the memory system MS.

[0281] [4] Fourth embodiment The fourth embodiment relates to the circuit arrangement of the memory device 20 described in the first to third embodiments. A memory device 20a according to the fourth embodiment will be described below, also using a comparative example. In the following description, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the Z direction is a direction perpendicular to the XY plane formed by the X direction and the Y direction. The XY plane corresponds to, for example, a plane parallel to the surface of a semiconductor substrate on which the memory device 20a is formed.

[0282] [4-1] Configuration of the comparative example Figure 74 is a plan view showing an example of a circuit layout of a memory device 20b according to a comparative example. The memory device 20b has a structure in which a memory cell array 207 and a sense amplifier module 209 are adjacent to each other in the Z direction. (A) of Figure 74 shows the circuit layout in a layer including the memory cell array 207 of the memory device 20b. (B) of Figure 74 shows the circuit layout in a layer including the sense amplifier module 209 of the memory device 20b.

[0283] The memory device 20b includes, for example, four plane LUNs, LUN1 to LUN4, a wiring unit 210, and a peripheral circuit 211. Plane LUN1 and LUN2 are adjacent to each other in the Y direction. Plane LUN3 and LUN4 are adjacent to each other in the Y direction. Plane LUN1 and LUN3 are adjacent to each other in the X direction. Plane LUN2 and LUN4 are adjacent to each other in the X direction. Each plane LUN shares the wiring unit 210 and the peripheral circuit 211. The wiring unit 210 is provided in a layer including the memory cell array 207. The wiring unit 210 is arranged to overlap the peripheral circuit 211 in the Z direction. The wiring unit 210 is used to connect the peripheral circuit 211 to a plurality of pads (i.e., pads used to connect the input / output circuit 201 and the like to the memory controller 10) provided in the memory device 20b. The peripheral circuit 211 is provided in a layer including the sense amplifier module 209. The peripheral circuit 211 may include an input / output circuit 201, a logic controller 202, a register circuit 203, a sequencer 204, etc. The wiring section 210 and the peripheral circuit 211 are each adjacent to a set of plane LUN1 to LUN4 in the Y direction.

[0284] Each plane LUN includes a memory cell array 207, an output area HR, a row decoder module 208, and a sense amplifier module 209. Specifically, plane LUN1 includes a memory cell array 207A, output areas HR_A1 and HR_A2, row decoder modules 208_A1 and 208_A2, and a sense amplifier module 209A. Plane LUN2 includes a memory cell array 207B, output areas HR_B1 and HR_B2, row decoder modules 208_B1 and 208_B2, and a sense amplifier module 209B. Plane LUN3 includes a memory cell array 207C, output areas HR_C1 and HR_C2, row decoder modules 208_C1 and 208_C2, and a sense amplifier module 209C. Plane LUN4 includes a memory cell array 207D, lead-out areas HR_D1 and HR_D2, row decoder modules 208_D1 and 208_D2, and a sense amplifier module 209D.

[0285] Here, focusing on plane LUN1, a specific circuit arrangement in plane LUN1 will be described. As shown in FIG. 74(A), the memory cell array 207A is sandwiched between lead-out regions HR_A1 and HR_A2 in the X direction. As shown in FIG. 74(B), the sense amplifier module 209A is sandwiched between row decoder modules 208_A1 and 208_A2 in the X direction. As shown in FIGS. 74(A) and 74(B), the memory cell array 207A is provided so as to overlap the sense amplifier module 209A in the Z direction. The lead-out regions HR_A1 and HR_A2 are provided so as to overlap the row decoder modules 208_A1 and 208_A2 in the Z direction, respectively. The memory cell array 207A is connected to the row decoder module 208_A1 via a plurality of wirings provided in the lead-out region HR_A1, and is connected to the row decoder module 208_A2 via a plurality of wirings provided in the lead-out region HR_A2. The pair of row decoder modules 208_A1 and 208_A2 constitutes, for example, the row decoder module 208 described in FIG.

[0286] The Y-direction width of each of the lead-out regions HR_A1 and HR_A2 is approximately equal to the Y-direction width of the memory cell array 207A. The Y-direction width of each of the row decoder modules 208_A1 and 208_A2 is approximately equal to the Y-direction width of each of the lead-out regions HR_A1 and HR_A2. When the 5-bit / cell coding described in the first embodiment is applied to the memory cell array 207A, for example, the Y-direction width of the sense amplifier module 209A is wider than the Y-direction width of the memory cell array 207A. This is because the sense amplifier module 209A requires many latch circuits when handling ultra-multilevel data such as 5 bits / cell. As such, if the Y-direction widths differ between the memory cell array 207A and the sense amplifier module 209A, a surplus region SP may be formed in each of the layers in which the memory cell array 207A is provided and the sense amplifier module 209A is provided. The configuration of each of the plane LUN2 to LUN4 is the same as that of the plane LUN1.

[0287] In the memory device 20b according to the comparative example described above, the area of ​​the sense amplifier module 209 is larger than the area of ​​the memory cell array 207, which may increase the chip area of ​​the memory device 20b to match the area of ​​the sense amplifier module 209. In particular, in the 5-bit / cell memory cell array 207 described in the first embodiment or the 4-bit / cell memory cell array 207, the number of latch circuits in the sense amplifier module 209 increases, which may increase the circuit area of ​​the sense amplifier module 209.

[0288] [4-2] Configuration of the fourth embodiment In contrast, the memory device 20a according to the fourth embodiment has a circuit layout that uses at least two types of memory cell arrays 207, each having a different number of bits stored in the memory cell transistor MT. For example, the memory device 20a according to the fourth embodiment uses a k-level (e.g., 4-level (2 bits / cell), where "k" is an integer equal to or greater than 1) memory cell array 207 and an l-level (e.g., 32-level (5 bits / cell), where "l" is an integer greater than "k"). Hereinafter, the "memory cell array 207 configured with memory cell transistors MT capable of storing k levels" will be referred to as a "memory cell array 207 with less than multiple levels," and the "memory cell array 207 configured with memory cell transistors MT capable of storing l levels" will be referred to as a "super multi-level memory cell array 207."

[0289] [4-2-1]Circuit layout Figure 75 is a plan view showing an example of a circuit layout of a memory device 20a according to the fourth embodiment. (A) of Figure 75 shows the circuit layout in a layer including a memory cell array 207 of the memory device 20a. (B) of Figure 75 shows the circuit layout in a layer including a sense amplifier module 209 of the memory device 20a. The circuit layout of the memory device 20a according to the fourth embodiment has a configuration in which the surplus region SP is omitted compared to the circuit layout of the memory device 20b according to the comparative example.

[0290] Specifically, in the memory device 20a, each of the memory cell arrays 207A and 207C is an ultra multi-level memory cell array 207. In the memory device 20a, each of the memory cell arrays 207B and 207D is a memory cell array 207 of multi-level or less. That is, the memory cell arrays 207A and 207B adjacent in the Y direction are a combination of an ultra multi-level memory cell array 207 and a memory cell array 207 of multi-level or less. Similarly, the memory cell arrays 207C and 207D adjacent in the Y direction are a combination of an ultra multi-level memory cell array 207 and a memory cell array 207 of multi-level or less. The following description focuses on the circuit layout of the set of planes LUN1 and LUN2.

[0291] The width in the Y direction of the sense amplifier module 209A, which is provided so as to overlap the ultra multi-level memory cell array 207A in the Z direction, is wider than that of the memory cell array 207A. On the other hand, the width in the Y direction of the sense amplifier module 209B, which is provided so as to overlap the multi-level or less memory cell array 207B in the Z direction, is narrower than that of the memory cell array 207B. The reason for this is that the number of latch circuits required for the operation of the multi-level or less memory cell array 207 is fewer than the number of latch circuits required for the operation of the ultra multi-level memory cell array 207. In the memory device 20a, the width in the Y direction of the ultra multi-level memory cell array 207A is designed to be narrower than the width in the Y direction of the multi-level or less memory cell array 207B.

[0292] As a result, the combined Y-direction width of the memory cell arrays 207A and 207B and the combined Y-direction width of the sense amplifier modules 209A and 209B can be designed to be approximately the same. That is, the pair of memory cell arrays 207A and 207B and the pair of sense amplifier modules 209A and 209B can be provided with approximately the same area and arranged to overlap in the Z direction. Similarly, the pair of draw-out regions HR_A1 and HR_B1 and the pair of row decoder modules 208_A1 and 208_B1 can be provided with approximately the same area and arranged to overlap in the Z direction. The pair of draw-out regions HR_A2 and HR_B2 and the pair of row decoder modules 208_A2 and 208_B2 can be provided with approximately the same area and arranged to overlap in the Z direction. This allows the surplus region SP to be omitted in the fourth embodiment. The circuit layout of the pair of planes LUN3 and LUN4 is similar to the circuit layout of the pair of planes LUN1 and LUN2.

[0293] Note that a portion of the peripheral circuitry may be arranged in the region of the sense amplifier module 209. That is, a portion of the peripheral circuitry may be arranged in the region of each of the sense amplifier modules 209 in Figures 74 and 75. Therefore, the relationship in area between the associated memory cell array 207 and the sense amplifier module 209 is not limited to the example shown in Figure 75.

[0294] Figure 76 is a plan view showing another example of the circuit layout of the memory device 20a according to the fourth embodiment. (A) of Figure 76 shows the circuit layout in a layer including the memory cell array 207 of the memory device 20a. (B) of Figure 76 shows the circuit layout in a layer including the sense amplifier module 209 of the memory device 20a. The circuit layout of the memory device 20a shown in Figure 76 differs from the circuit layout of the memory device 20a shown in Figure 75 in the area (size) of the sense amplifier module 209.

[0295] 76, the area of ​​the sense amplifier module 209 associated with the multi-level memory cell array 207 is larger than the area of ​​the multi-level memory cell array 207. Furthermore, the area of ​​the sense amplifier module 209 associated with the ultra multi-level memory cell array 207 is smaller than the area of ​​the ultra multi-level memory cell array 207. Even in this case, the combined Y-direction width of the memory cell arrays 207A and 207B and the combined Y-direction width of the sense amplifier modules 209A and 209B can be designed to be approximately the same. That is, even in the example shown in FIG. 76, the set of memory cell arrays 207A and 207B and the set of sense amplifier modules 209A and 209B can be provided with approximately the same area and can be arranged to overlap in the Z direction.

[0296] [4-2-2] Example of the configuration of the sense amplifier module 209 Below, in the fourth embodiment, a configuration example will be described in which the circuit configuration of one sense amplifier unit SAU included in the sense amplifier module 209 connected to the ultra-multi-value memory cell array 207 is combined with the circuit configuration of one sense amplifier unit SAU included in the sense amplifier module 209 connected to the multi-value or less memory cell array 207.

[0297] (First configuration example) FIG. 77 is a schematic diagram showing a first configuration example of a sense amplifier module 209 in a memory device 20a according to the fourth embodiment. As shown in FIG. 77, in the first configuration example of the fourth embodiment, the sense amplifier unit SAU of the sense amplifier module 209A includes a sense amplifier unit SA configured to be able to transmit and receive data via a bus LBUS1, and latch circuits SDL, ADL, BDL, CDL, and XDL. In the first configuration example of the fourth embodiment, the sense amplifier unit SAU of the sense amplifier module 209B includes a sense amplifier unit SA configured to be able to transmit and receive data via a bus LBUS2, and latch circuits SDL and XDL. Note that in this example, the number of latch circuits connected to each of the buses LBUS1 and LBUS2 can be changed as appropriate depending on the number of bits stored in the memory cell transistors MT of the associated memory cell array 207.

[0298] (Second configuration example) 78 is a schematic diagram showing a second configuration example of the sense amplifier module 209 in the memory device 20a according to the fourth embodiment. As shown in FIG. 78, the second configuration example in the fourth embodiment has a configuration in which the latch circuit SDL of the sense amplifier unit SAU of the sense amplifier module 209B is omitted from the first configuration example in the fourth embodiment. Depending on the number of bits stored in the memory cell transistor MT in the multi-level or less memory cell array 207B (for example, in the case of 1 bit), latch circuits other than the latch circuit XDL may be omitted in the sense amplifier unit SAU of the sense amplifier module 209B, as in the second configuration example in the fourth embodiment.

[0299] [4-3] Effects of the fourth embodiment As described above, the memory device 20a according to the fourth embodiment combines a plain LUN including an ultra-multilevel memory cell array 207 and a plain LUN including a memory cell array 207 with less than multilevel memory. This allows the memory device 20a according to the fourth embodiment to suppress the formation of a surplus area SP due to the difference in area between the memory cell array 207 and the sense amplifier module 209 in one plane LUN. As a result, the memory device 20a according to the fourth embodiment can reduce the chip area compared to the comparative example. In other words, the memory device 20a according to the fourth embodiment can suppress the manufacturing cost of the memory device 20a.

[0300] In the memory device 20a according to the fourth embodiment, when the memory cell arrays 207A and 207C are used as the ultra multi-level memory cell array 207 and the memory cell arrays 207B and 207D are used as the memory cell array 207 with less than multi-level data, the four planes LUN1 to LUN4 can be operated in parallel (i.e., four-plane operation). In addition, in the memory device 20a according to the fourth embodiment, when all of the memory cell arrays 207A, 207B, 207C, and 207D are used as the memory cell array 207 with less than multi-level data, the four planes LUN1 to LUN4 can be operated in parallel. On the other hand, in the memory device 20a according to the fourth embodiment, when the memory cell arrays 207A and 207C are used as the ultra multi-level memory cell array 207, the memory cell arrays 207B and 207D cannot be used as the ultra multi-level memory cell array 207.

[0301] [5] Fifth embodiment The memory device 20c according to the fifth embodiment has a configuration in which a latch circuit is shared by a plurality of memory cell arrays 207, in relation to the circuit arrangement of the memory system MS described in the first to third embodiments. The memory device 20c according to the fifth embodiment will be described below.

[0302] [5-1] Configuration of the fifth embodiment The memory device 20c according to the fifth embodiment has a configuration in which a latch circuit is shared among a plurality of plane LUNs, thereby utilizing an ultra multi-level memory cell array 207 and suppressing the area of ​​the latch circuit.

[0303] [5-1-1] Circuit layout Figure 79 is a plan view showing an example of a circuit layout of a memory device 20c according to the fifth embodiment. The memory device 20c has a structure in which a memory cell array 207 and a sense amplifier module 209 are adjacent to each other in the Z direction. (A) of Figure 79 shows the circuit layout in a layer including the memory cell array 207 of the memory device 20c. (B) of Figure 79 shows the circuit layout in a layer including the sense amplifier module 209 of the memory device 20c.

[0304] The memory device 20c includes, for example, four plane LUNs 1 to 4, a wiring section 210, and a peripheral circuit 211. The layout of the plane LUNs 1 to 4 in the fifth embodiment is the same as the layout of the plane LUNs 1 to 4 in the comparative example described in the fourth embodiment. Each plane LUN includes a memory cell array 207, a lead-out region HR, a row decoder module 208, and a sense amplifier set SAS. The sense amplifier set SAS includes at least a sense amplifier section SA. For example, two plane LUNs adjacent in the Y direction share a latch set LS. The latch set LS includes, for example, at least one latch circuit shared by multiple sense amplifier sets SAS for each row address. The pair of the sense amplifier set SAS and the latch set LS can be used in the same manner as the sense amplifier module 209 described in the first embodiment.

[0305] Specifically, plane LUN1 includes memory cell array 207A, draw-out areas HR_A1 and HR_A2, row decoder modules 208_A1 and 208_A2, and sense amplifier set SAS1. Plane LUN2 includes memory cell array 207B, draw-out areas HR_B1 and HR_B2, row decoder modules 208_B1 and 208_B2, and sense amplifier set SAS2. Plane LUN3 includes memory cell array 207C, draw-out areas HR_C1 and HR_C2, row decoder modules 208_C1 and 208_C2, and sense amplifier set SAS3. Plane LUN4 includes memory cell array 207D, draw-out areas HR_D1 and HR_D2, row decoder modules 208_D1 and 208_D2, and sense amplifier set SAS4. Sense amplifier sets SAS1 and SAS2 share latch set LS1. The sense amplifier sets SAS3 and SAS4 share the latch set LS1.

[0306] Here, a specific circuit arrangement in plane LUN1 will be described. As shown in FIG. 79(A), the memory cell array 207A is sandwiched between lead-out regions HR_A1 and HR_A2 in the X direction. As shown in FIG. 79(B), the sense amplifier module 209A is sandwiched between row decoder modules 208_A1 and 208_A2 in the X direction. As shown in FIGS. 79(A) and (B), the memory cell array 207A is provided so as to overlap with the sense amplifier set SAS1 in the Z direction. The lead-out regions HR_A1 and HR_A2 are provided so as to overlap with the row decoder modules 208_A1 and 208_A2 in the Z direction, respectively. The widths of the lead-out regions HR_A1 and HR_A2 in the Y direction are approximately equal to the width of the memory cell array 207A in the Y direction. The widths of the row decoder modules 208_A1 and 208_A2 in the Y direction are approximately equal to the widths of the lead-out regions HR_A1 and HR_A2 in the Y direction, respectively. The width in the Y direction of each of the row decoder modules 208_A1 and 208_A2 is wider than the width in the Y direction of the sense amplifier set SAS1.

[0307] Plane LUN2 has a circuit layout similar to that of plane LUN1, except that sense amplifier set SAS2 is located away from plane LUN1. Sense amplifier sets SAS1 and SAS2 sandwich latch set LS1 in the Y direction. As a result, the combined Y-direction width of memory cell arrays 207A and 207B and the combined Y-direction width of sense amplifier sets SAS1 and SAS2 and latch set LS1 can be designed to be approximately the same. That is, the set of memory cell arrays 207A and 207B and the set of sense amplifier sets SAS1 and SAS2 and latch set LS1 can be provided with approximately the same area and can be arranged overlapping in the Z direction. The circuit layout of the set of plane LUN3 and LUN4 is similar to that of the set of plane LUN1 and LUN2. Note that a portion of the peripheral circuitry may be arranged in the area of ​​sense amplifier set SAS in FIG. 79.

[0308] [5-1-2] Example of the configuration of the sense amplifier set SAS and latch set LS The following describes first to fourth configuration examples of the circuit configuration of the sense amplifier set SAS and latch set LS1 in the fifth embodiment. Note that the following description will be given taking as an example the circuit configuration included in the sense amplifier sets SAS1 and SAS2 and latch set LS1 corresponding to the pair of plane LUN1 and LU2.

[0309] (First configuration example) FIG. 80 is a schematic diagram showing a first configuration example of a sense amplifier set SAS and a latch set LS in a memory device 20c according to the fifth embodiment. As shown in FIG. 80, in the first configuration example of the fifth embodiment, the sense amplifier set SAS1 includes a sense amplifier unit SA and a latch circuit XDL configured to be able to transmit and receive data via a bus LBUS1, and the sense amplifier set SAS2 includes a sense amplifier unit SA and a latch circuit XDL configured to be able to transmit and receive data via a bus LBUS2. In the first configuration example of the fifth embodiment, the latch set LS1 includes latch circuits SDL, ADL, BDL, and CDL configured to be able to transmit and receive data via a bus SBUS, and switches SW1 and SW2. The switches SW1 and SW2 are, for example, MOS transistors. The switch SW1 is connected between LBUS1 and SBUS. The switch SW2 is connected between LBUS2 and SBUS. Control signals CS1 and CS2 are input to the gates of the switches SW1 and SW2, respectively. The switch SW1 operates based on the control signal CS1. The switch SW2 operates based on the control signal CS2. The control signals CS1 and CS2 are generated by, for example, the sequencer 204.

[0310] In a first configuration example of the fifth embodiment, the memory device 20c uses a combination of a sense amplifier set SAS1 and a latch set LS1 when handling ultra multi-level data. Specifically, when ultra multi-level data is assigned to the memory cell array 207A and multi-level data is assigned to the memory cell array 207B, the sequencer 204 controls the switch SW1 to an on state, thereby electrically connecting LBUS1 and SBUS, and performing an ultra multi-level data operation (for example, an operation described in the first to third embodiments) on the memory cell array 207A. On the other hand, when handling multi-level data, the memory device 20c uses, for example, only the sense amplifier set SAS2. Specifically, the sequencer 204 controls the switch SW2 to an off state, thereby electrically disconnecting LBUS2 and SBUS, and performing an ultra multi-level data operation.

[0311] (Second configuration example) FIG. 81 is a schematic diagram showing a second configuration example of the sense amplifier set SAS and the latch set LS in the memory device 20c according to the fifth embodiment. As shown in FIG. 81, the second configuration example in the fifth embodiment differs from the first configuration example in the fifth embodiment in that the latch circuit SDL of the latch set LS1 is omitted, and one latch circuit SDL is connected to each of the buses LBUS1 and LBUS2. The second configuration example in the fifth embodiment can perform read and write operations using only the sense amplifier set SAS when coding is used in which a read or write operation can be performed using a single latch circuit, such as 1 bit per cell. Specifically, in the second configuration example of the fifth embodiment, the memory device 20c can perform read and write operations for the plain LUN1 and LUN2 in parallel using, for example, a set of the sense amplifier set SAS1 and the latch set LS1 used in ultra-multilevel data storage and a sense amplifier set SAS2 used in multilevel data storage.

[0312] (Third configuration example) FIG. 82 is a schematic diagram showing a third configuration example of the sense amplifier set SAS and latch set LS in the memory device 20c according to the fifth embodiment. As shown in FIG. 82, the third configuration example in the fifth embodiment differs from the first configuration example in the fifth embodiment in that the latch circuits XDL of the latch sets LS1 and LS2 are omitted, and one latch circuit XDL is connected to the bus SBUS. In this way, the sense amplifier set SAS may include only the sense amplifier unit SA, and the latch circuits used in read and write operations may be collected in the latch set LS1. In this case, the memory device 20c may selectively perform an operation targeted at the plane LUN1 and an operation targeted at the plane LUN2 in the combined plane LUN1 and LUN2.

[0313] (Fourth configuration example) 83 is a schematic diagram showing a fourth configuration example of the sense amplifier set SAS and the latch set LS in the memory device 20c according to the fifth embodiment. As shown in FIG. 83, the fourth configuration example in the fifth embodiment differs from the third configuration example in the fifth embodiment in that the latch circuit SDL of the latch set LS1 is omitted and one latch circuit SDL is connected to each of the buses LBUS1 and LBUS2. In the fourth configuration example in the fifth embodiment, by providing the latch circuit SDL in the sense amplifier set SAS, it is possible to execute, for example, a 1-bit / cell operation and a super multi-level or multi-level operation in parallel.

[0314] [5-2] Effects of the fifth embodiment In the memory device 20c according to the fifth embodiment, a latch set LS is shared by multiple memory cell arrays 207 (sense amplifier sets SAS). When handling ultra-multilevel data, two plane LUNs sharing the latch set LS operate separately for each plane LUN. For example, when two plane LUNs sharing the latch set LS are executing a write operation on one plane LUN, the other plane LUN cannot be used and is in a standby state. Furthermore, when handling multilevel data (or 1 bit / cell), two plane LUNs sharing the latch set LS can operate in parallel.

[0315] In the memory device 20c, two plane LUNs sharing a latch set LS may be used, one for ultra-multilevel data and the other for multilevel data. By providing a memory cell array 207 used for multilevel data, the area required for arranging the latch circuit can be reduced. Furthermore, in the fifth embodiment, when a memory cell array 207 (a 1-bit / cell memory cell array 207) in which memory cell transistors MT store only 1-bit data is provided and a sense amplifier set SAS and a latch set LS are provided as in the first configuration example, the 1-bit / cell memory cell array 207 can perform read and write operations using the sense amplifier set SAS without using the latch set LS.

[0316] As described above, the memory device 20c according to the fifth embodiment can reduce the area of ​​the circuit that functions as the sense amplifier module 209 by sharing the latch set LS. As a result, the memory device 20a according to the fifth embodiment can reduce the chip area, and the manufacturing cost of the memory device 20c can be reduced.

[0317] The memory device 20c according to the fifth embodiment can use all of the memory cell arrays 207A, 207B, 207C, and 207D as the ultra multi-level memory cell array 207. When two plane LUNs sharing a latch set LS each have an ultra multi-level memory cell array 207, the memory device 20c executes write operations for each plane LUN. When the memory device 20c according to the fifth embodiment uses the memory cell arrays 207A and 207C as the ultra multi-level memory cell array 207 and the memory cell arrays 207B and 207D as the multi-level or lower memory cell array 207, the memory device 20c according to the fifth embodiment can operate the four plane LUNs 1 to 4 in parallel. When the memory device 20a according to the fifth embodiment uses all of the memory cell arrays 207A, 207B, 207C, and 207D as the multi-level or lower memory cell array 207, the memory device 20a according to the fifth embodiment can operate the four plane LUNs 1 to 4 in parallel.

[0318] [6] Other In the data allocation described in the above embodiment, data allocation for each page may be swapped between pages. The commands used in the above embodiment are merely examples. For example, the commands “01h” to “05h” and “xxh” may be replaced with any command. Commands specifying the page to be read, such as “01h” to “05h,” may be omitted by including page information in the address “ADD.” The address “ADD” may be transmitted in multiple cycles. In the read operation of the first embodiment, the sequencer 204 may transition the memory device 20 from a busy state to a ready state upon confirmation of the data. In this case, the memory controller 10 instructs the memory device 20 to transfer the data determination result to the latch circuit XDL, and then instructs the memory device 20 to output the confirmed page data.

[0319] In the fourth and fifth embodiments, multiple plain LUNs are operated in parallel, but this is not limited to the case where each operation starts at the same time. As long as the operations of multiple plain LUNs overlap for a certain period of time, the start times of each operation may be different. For example, when four plain LUNs (LUN1 to LUN4) are operated in parallel, they may be executed in the following order: start of LUN1 operation, start of LUN2 operation, start of LUN3 operation, start of LUN4 operation, end of LUN1 operation, end of LUN2 operation, end of LUN3 operation, and end of LUN4 operation. Furthermore, in this example, the start of LUN4 operation and the end of LUN1 operation may be executed in the reverse order.

[0320] In the fourth and fifth embodiments, the memory device 20 has four plain LUNs, but the present invention is not limited to this. Each of the fourth and fifth embodiments can be applied to a case where the memory device 20 has at least a plurality of plain LUNs. In the fourth and fifth embodiments, when the memory cell array 207 of multi-level or less and the memory cell array 207 of ultra multi-level are combined, the memory cell array 207 of multi-level or less is used, for example, as a buffer area for speeding up operation. In other words, in the fourth and fifth embodiments, the memory cell array 207 of multi-level or less and the memory cell array 207 of ultra multi-level are used in combination, thereby speeding up operation of the memory device 20.

[0321] In a read operation, the voltage applied to the selected word line WLsel is, for example, the same voltage as the voltage of the signal line CG through which the driver circuit 206 supplies voltage to the row decoder module 208. The magnitude of the voltage applied to various wirings and the period for which the voltage is applied can be roughly determined by checking the voltage of the corresponding signal line CG. When estimating the voltages of the select gate line, word line, etc. from the voltage of each signal line connected to the driver circuit 206, the voltage drop due to the transistor TR included in the row decoder RD may be taken into consideration. In this case, the voltage of each select gate line and word line will be lower than the voltage applied to the corresponding signal line by the amount of the voltage drop due to the transistor TR.

[0322] In this specification, "connection" refers to electrical connection, and does not exclude, for example, the presence of another element between them. "On state" refers to a state in which a voltage equal to or greater than the threshold voltage of the corresponding transistor ("H" level voltage) is applied to the gate of the corresponding transistor. "Off state" refers to a state in which a voltage equal to or less than the threshold voltage of the corresponding transistor ("L" level voltage) is applied to the gate of the corresponding transistor. A small current such as a leakage current may flow in a transistor in the off state. "Read voltage" may also be called a "read level." "Lowest read voltage" refers to the lowest read voltage of a specified group. "Top read voltage" refers to the highest read voltage of a specified group.

[0323] Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0324] [Appendix 1] a first memory cell array group having a first memory cell array (a is an integer equal to or greater than 1), each having memory cells that store data based on a threshold value of k values ​​(k is an integer equal to or greater than 1); a second memory cell array group having memory cells that store data based on a threshold value of l (l is an integer greater than k), and having b (b is an integer greater than or equal to 1) second memory cell arrays; A sequencer, Equipped with the sequencer simultaneously writes data of k value or less to c (c is a or less) of the first memory cell arrays and writes data of l value or less to d (d is b or less) of the second memory cell arrays; Semiconductor memory device.

[0325] [Appendix 2] a first sense amplifier unit connected to the memory cells of the first memory cell array; a second sense amplifier unit connected to the memory cells of the second memory cell array; Furthermore, the number of latch circuits included in the second sense amplifier unit is greater than the number of latch circuits included in the first sense amplifier unit; 3. The semiconductor memory device according to claim 2.

[0326] [Appendix 3] a first memory cell array group having a number a (a is an integer greater than or equal to 1) of first memory cell arrays each having memory cells selectable to store data based on a threshold value of k (k is an integer greater than or equal to 1) or l (l is an integer greater than k); a second memory cell array group having b (b is an integer greater than or equal to 1) second memory cell arrays each having memory cells selectable to store data based on a threshold value of k (k is an integer greater than or equal to 1) or l (l is an integer greater than k); A sequencer, Equipped with the sequencer simultaneously writes data of k value or less to c (c is a or less) of the first memory cell arrays and writes data of l value or less to d (d is b or less) of the second memory cell arrays; Semiconductor memory device.

[0327] [Appendix 4] a first set of sense amplifiers connected to memory cells of the first memory cell array; a second set of sense amplifiers connected to memory cells of the second memory cell array; a latch circuit connected to the first sense amplifier set and the second sense amplifier set; A sequencer, Furthermore, the sequencer drives both the first sense amplifier set and the latch circuit when writing data of l value or less into the memory cells of the first memory cell array group, and drives both the second sense amplifier set and the latch circuit when writing data of l value or less into the memory cells of the second memory cell array group; 4. The semiconductor memory device according to claim 3.

[0328] [Appendix 5] The data write to the first memory cell array and the data write to the second memory cell array start at different times. 4. The semiconductor memory device according to claim 1 or 3.

[0329] [Appendix 6] The data write to the first memory cell array and the data write to the second memory cell array start at approximately the same time. 4. The semiconductor memory device according to claim 1 or 3.

[0330] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0331] 1...information processing system, 10...memory controller, 11...host interface, 12...memory interface, 13...CPU, 14...ECC circuit, 15...ROM, 16...RAM, 17...buffer memory, 20...memory device, 101...input / output circuit, 201...input / output circuit, 202...logic controller, 203...register circuit, 204...sequencer, 205...ready / busy controller, 206...driver circuit, 207...memory cell array, 208...row decoder module, 209...sense amplifier module, BLK...block, SU...string unit, NS...NAND string, RD...row decoder, SAU...sense amplifier unit, BL...bit line, WL...word line, SGD, SGS...select gate line, SL...source line, MT...memory cell transistor, ST1, ST2...select transistor, S0 to S31...state, D0 to D31...data set, R1 to R31...read voltage, VREAD...read pass voltage

Claims

1. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the seventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, and the twenty-sixth read voltage to the word line, respectively; In the fourth page read operation, seven reads are performed in which the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the nineteenth read voltage, the twenty-third read voltage, and the twenty-eighth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the seventeenth read voltage, the twenty-fourth read voltage, and the thirtieth read voltage are applied to the word line, respectively. Memory device.

2. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, seven reads are performed in which the fourth read voltage, the ninth read voltage, the thirteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the second page, six reads are performed by applying the sixth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation of the fourth page, six reads are performed by applying the second read voltage, the eighth read voltage, the fifteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

3. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the eighth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the nineteenth read voltage, and the twenty-sixth read voltage to the word line, respectively; In the read operation of the third page, six read operations are performed in which the third read voltage, the seventh read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage are applied to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the twentieth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively; In the read operation for the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the seventeenth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage are applied to the word line, respectively. Memory device.

4. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the eighth read voltage, the fourteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fifth read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the nineteenth read voltage, and the twenty-seventh read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the seventh read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-sixth read voltage, and the thirtieth read voltage to the word line, respectively; In the fourth page read operation, seven reads are performed in which the second read voltage, the sixth read voltage, the eleventh read voltage, the fifteenth read voltage, the twentieth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively; In the read operation for the fifth page, six read operations are performed in which the first read voltage, the fourth read voltage, the tenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage are applied to the word line, respectively. Memory device.

5. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, seven reads are performed by applying the fourth read voltage, the eighth read voltage, the twelfth read voltage, the seventeenth read voltage, the twenty-first read voltage, the twenty-sixth read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fifth read voltage, the thirteenth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-seventh read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the ninth read voltage, the fifteenth read voltage, the twenty-second read voltage, the twenty-eighth read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the fourth page, six reads are performed by applying the second read voltage, the sixth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fifth read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation for the fifth page, six read operations are performed in which the first read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the eighteenth read voltage, and the twenty-fourth read voltage are applied to the word line, respectively. Memory device.

6. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the seventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, and the twenty-sixth read voltage to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

7. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the sixth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the ninth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

8. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the sixth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the eleventh read voltage, the seventeenth read voltage, the twenty-fifth read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the nineteenth read voltage, and the twenty-seventh read voltage to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the ninth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

9. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the seventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, and the twenty-sixth read voltage to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

10. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the sixth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the ninth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

11. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the fifth read voltage, the thirteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, and the twenty-sixth read voltage to the word line, respectively; In the read operation of the fourth page, seven reads are performed in which the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the thirtieth read voltage are applied to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the seventh read voltage, the fifteenth read voltage, the twenty-first read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively. Memory device.

12. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the seventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage to the word line, respectively; In the read operation of the third page, seven reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the fourth page, six reads are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the nineteenth read voltage, and the twenty-seventh read voltage to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the seventeenth read voltage, the twenty-fifth read voltage, and the thirty-first read voltage are applied to the word line, respectively. Memory device.

13. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the fifth read voltage, the thirteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage to the word line, respectively; In the read operation of the third page, seven reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the fourth page read operation, six reads are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation for the fifth page, six read operations are performed in which the first read voltage, the seventh read voltage, the fifteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage are applied to the word line, respectively. Memory device.

14. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the seventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage to the word line, respectively; In the read operation of the third page, seven reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the fourth page read operation, six reads are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation for the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-seventh read voltage, and the thirty-first read voltage are applied to the word line, respectively. Memory device.

15. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, six reads are performed by applying the seventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the second page, six reads are performed by applying the fourth read voltage, the eighth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage to the word line, respectively; In the read operation of the third page, seven reads are performed by applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-ninth read voltage to the word line, respectively; In the fourth page read operation, six reads are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation of the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage are applied to the word line, respectively. Memory device.

16. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, seven reads are performed in which the fourth read voltage, the eighth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively; In the read operation of the second page, six reads are performed by applying the seventh read voltage, the eleventh read voltage, the fourteenth read voltage, the twenty-third read voltage, the twenty-seventh read voltage, and the thirtieth read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the sixth read voltage, the fifteenth read voltage, the nineteenth read voltage, the twenty-second read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation of the fourth page, six reads are performed by applying the second read voltage, the fifth read voltage, the ninth read voltage, the eighteenth read voltage, the twenty-first read voltage, and the twenty-fifth read voltage to the word line, respectively; In the read operation of the fifth page, six reads are performed by applying the first read voltage, the tenth read voltage, the thirteenth read voltage, the seventeenth read voltage, the twenty-sixth read voltage, and the twenty-ninth read voltage to the word line, respectively. Memory device.

17. a plurality of memory cells each storing five-bit data including first to fifth bit data according to a threshold voltage, and storing first to fifth pages corresponding to the first to fifth bit data, respectively; a word line connected to the plurality of memory cells; a controller for performing a read operation; The threshold voltage of the memory cell is included in any one of 0th state to 31st state which are different from each other, 5-bit data which are different from each other are assigned to each of the 0th state to the 31st state, and first read voltage to 31st read voltage are set in order from the lowest voltage corresponding to adjacent states among the 0th state to the 31st state, The controller In the read operation of the first page, seven reads are performed in which the fourth read voltage, the eighth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage are applied to the word line, respectively; In the read operation of the second page, six reads are performed by applying the sixth read voltage, the ninth read voltage, the thirteenth read voltage, the twenty-second read voltage, the twenty-fifth read voltage, and the twenty-ninth read voltage to the word line, respectively; In the read operation of the third page, six reads are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the nineteenth read voltage, the twenty-third read voltage, and the twenty-sixth read voltage to the word line, respectively; In the read operation of the fourth page, six reads are performed by applying the second read voltage, the eleventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively; In the read operation for the fifth page, six read operations are performed in which the first read voltage, the fifth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-first read voltage, and the thirtieth read voltage are applied to the word line, respectively. Memory device.

18. each of the first read voltage and the second read voltage is a negative voltage; 18. A memory device according to any one of claims 1 to 17.

19. each of the first read voltage, the second read voltage, the third read voltage, and the fourth read voltage is a negative voltage; 18. A memory device according to any one of claims 1 to 17.

20. the controller applies read voltages in order from highest to lowest in each of the first page read operation, the second page read operation, the third page read operation, the fourth page read operation, and the fifth page read operation; 18. A memory device according to any one of claims 1 to 17.

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