Semiconductor storage device and control method thereof

Abstract

To provide a semiconductor storage device capable of improving a sense margin of a sense amplifier, even if an offset cancellation operation sequence is executed for each of a plurality of sense amplifiers of a plurality of pages, and a control method thereof.SOLUTION: A semiconductor storage device includes a control unit that executes an offset cancellation operation sequence including at least one predetermined operation of supplying a power supply voltage common to all pages to the sense amplifier, for each sense amplifier on each page. The control unit is configured to control timing of executing the offset cancellation operation sequence in each page without executing the predetermined operation on the other page other than any other page, while executing the predetermined operation on any other page of the plurality of pages, when executing the offset cancellation operation sequence on each page of the plurality of pages.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] For example, semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) are configured to read data by generating a weak potential difference between a pair of bit lines based on data stored in a memory cell and amplifying this potential difference with a sense amplifier. Here, the sense amplifier is provided with a pair of N-channel field effect transistors (nMOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)) and a pair of P-channel field effect transistors (pMOSFETs), and differences in the capabilities (characteristics) of these transistors can generate an offset voltage that reduces the sense margin.

[0003] Therefore, a semiconductor memory device configured to cancel the offset voltage is known (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Publication No. 9,202,531 Summary of the Invention [Problem to be solved by the invention]

[0005] The technology described in Patent Document 1 executes an offset cancel operation sequence including an offset cancel operation for canceling the offset voltage of the sense amplifier, a charge sharing operation for activating the word line and generating a sensing signal voltage on the bit line, a pre-sensing operation for amplifying the sensing signal voltage, and a bit line charge operation (restore operation in Patent Document 1) for transferring sensing data to a pair of bit lines.

[0006] The offset cancel operation sequence can be performed in units of pages including multiple memory cells. FIG. 1(a) shows an example of changes in the power supply voltage VBLH and the ground voltage VSS when the offset cancel operation sequence is performed on a single page (Page 1 in the example shown in the figure). In the example shown in FIG. 1(a), an offset cancel operation (OC) is performed on multiple sense amplifiers connected to multiple memory cells in Page 1 between times t1 and t2, and a charge sharing operation (CS) is performed on multiple sense amplifiers between times t2 and t3. A pre-sensing operation (PS) is performed on multiple sense amplifiers between times t3 and t4, and a bit line charge operation (BC) is performed on multiple sense amplifiers at time t4. When the offset cancel operation sequence includes the offset cancel operation (OC), the pre-sensing operation (PS), and the bit line charge operation (BC), each sense amplifier is connected to the power supply voltage VBLH and the ground voltage VSS. At this time, power supply noise occurs in the power supply voltage VBLH and the ground voltage VSS due to the current consumption of each sense amplifier.

[0007] Meanwhile, DRAMs require a memory retention operation called refresh, which periodically charges the memory cells. This refresh is generally performed in units of multiple pages. In this case, as shown in FIG. 1(b), an offset cancel operation sequence is simultaneously performed on multiple pages (four pages, page 1 to page 4, in the illustrated example). This increases power supply noise generated in the power supply voltage VBLH and ground voltage VSS common to all pages when the three operations, namely, the offset cancel operation (OC), the pre-sensing operation (PS), and the bit line charge operation (BC), are performed. Therefore, when an offset cancel operation sequence is performed on multiple pages, such as when a refresh is performed, the influence of power supply noise may reduce the sense margin of the sense amplifier.

[0008] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a semiconductor memory device and a control method thereof that can improve the sense margin of a sense amplifier even when an offset cancellation operation sequence is executed for multiple sense amplifiers for each of multiple pages. [Means for solving the problem]

[0009] In order to solve the above problem, the present invention provides a semiconductor memory device comprising: a plurality of pages, each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each memory cell; and a control unit that executes an offset cancel operation sequence for the plurality of sense amplifiers in each page, the offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to each page to the sense amplifier, wherein when executing the offset cancel operation sequence in each of the plurality of pages, the control unit is configured to control the timing of executing the offset cancel operation sequence in each page so that while the predetermined operation is being performed in any one of the plurality of pages, the predetermined operation is not performed in any other page other than the one of the plurality of pages.

[0010] According to this invention, while a predetermined operation of supplying a power supply voltage common to all pages to sense amplifiers is being performed in one of the multiple pages, the predetermined operation is controlled not to be performed in the other pages, thereby preventing the power supply voltage from being simultaneously supplied to the sense amplifiers of the multiple pages.As a result, it is possible to reduce power supply noise generated in the power supply voltage compared to, for example, a case where each sense amplifier of the multiple pages is connected to the power supply voltage, and therefore it is possible to improve the sense margin of the sense amplifiers even when an offset cancellation operation sequence is performed for each of the multiple sense amplifiers of the multiple pages.

[0011] The present invention also provides a control method for a semiconductor memory device, the semiconductor memory device comprising: a plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each memory cell; and a control unit that executes an offset cancel operation sequence for the plurality of sense amplifiers in each page, the offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to all pages to the sense amplifiers, when the control unit executes the offset cancel operation sequence in each of the plurality of pages, controlling the timing of executing the offset cancel operation sequence in each page so that the predetermined operation is not performed in any page other than the one of the plurality of pages while the predetermined operation is being performed in the one of the plurality of pages. [Effects of the Invention]

[0012] According to the semiconductor memory device and the control method thereof of the present invention, even when an offset cancel operation sequence is executed for a plurality of sense amplifiers for each of a plurality of pages, the sense margin of the sense amplifiers can be improved. [Brief explanation of the drawings]

[0013] [Figure 1]FIG. 10A is a diagram showing an example of changes in power supply voltage and ground voltage when an offset cancellation operation sequence is executed on one page in the conventional technology, and FIG. 10B is a diagram showing an example of changes in power supply voltage and ground voltage when offset cancellation operation sequences are executed simultaneously on multiple pages in the conventional technology. [Figure 2] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of a sense amplifier. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of a control unit. [Figure 5] 10 is a time chart showing an example of an operation of a sense amplifier in an offset cancel operation sequence. [Figure 6] 10A and 10B are diagrams illustrating an example of changes in power supply voltage and ground voltage when an offset cancel operation sequence is executed for multiple pages in this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Fig. 2 is a diagram showing an example of the configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in Fig. 2, the semiconductor memory device includes a plurality of pages 10 and a control unit 100. Each of the plurality of pages 10 includes a plurality of memory cells (not shown) connected to the same word line and a plurality of sense amplifiers (SA) 11 connected to each memory cell.

[0015] In this embodiment, the control unit 100 is configured to execute an offset cancel operation sequence for the plurality of sense amplifiers 11 of each page 10, the offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage VBLH common to all pages to the sense amplifiers 11. When executing the offset cancel operation sequence for each of the plurality of pages 10, the control unit 100 is also configured to control the timing of executing the offset cancel operation sequence for each page 10 so that while a predetermined operation is being performed on one of the plurality of pages 10, a predetermined operation is not performed on any page other than that page.

[0016] Here, the predetermined operation may include at least one of an offset cancel operation (OC) of the sense amplifier 11, a pre-sensing operation (PS) of the sense amplifier, and a bit line charge operation (BC). This makes it possible to control so that while any of the offset cancel operation (OC), the pre-sensing operation (PS) of the sense amplifier, and the bit line charge operation (BC) is being performed in any one of the multiple pages 10, any of the offset cancel operation (OC), the pre-sensing operation (PS) of the sense amplifier, and the bit line charge operation (BC) is not being performed in the other pages 10.

[0017] The offset cancel operation sequence may include an offset cancel operation (OC), a charge sharing operation (CS) of the sense amplifier 11 after the offset cancel operation, a pre-sensing operation (PS) after the charge sharing operation (CS), and a bit line charge operation (BC) after the pre-sensing operation (PS). This makes it possible to reduce the offset voltage of the sense amplifier 11, thereby improving the sense margin of the sense amplifier 11.

[0018] Furthermore, the control unit 100 may be configured to execute an offset cancel operation sequence for the plurality of sense amplifiers 11 of each of the plurality of pages 10 when refreshing the plurality of memory cells of each of the plurality of pages 10. This makes it possible to improve the sense margin of the sense amplifiers 11 even when the offset cancel operation sequence is executed on the plurality of pages 10 when refreshing is performed.

[0019] Furthermore, the control unit 100 may be configured to stop supplying the power supply voltage VBLH to the sense amplifiers 11 in one of the pages 10 when a predetermined operation is started in another page 10 while a predetermined operation is being performed in the other page 10. This makes it possible to prevent the power supply voltage VBLH from being supplied to the sense amplifiers 11 of one of the pages 10 while the power supply voltage VBLH is being supplied to the sense amplifiers 11 of the other page 10.

[0020] Furthermore, when a predetermined operation is started in one of the pages 10 while another page 10 is being performed, the control unit 100 may be configured to start the predetermined operation in the other page 10 after the predetermined operation in one of the pages 10 has finished. This makes it possible to prevent the power supply voltage VBLH from being supplied to the sense amplifiers 11 of one of the pages 10 while the power supply voltage VBLH is being supplied to the sense amplifiers 11 of the other page 10.

[0021] An example configuration of the sense amplifier 11 will be described with reference to FIG. 3. As shown in FIG. 3, the sense amplifier 11 includes a pair of pMOSFETs 11a connected to a node CSP on the high-voltage power supply side and a pair of nMOSFETs 11b connected to a node CSN on the low-voltage power supply side. A pair of complementary bit lines BLT and BLB (hereinafter referred to as a "pair of bit lines BLT and BLB") is connected to a node between the pair of pMOSFETs 11a and the pair of nMOSFETs 11b. Here, the pair of pMOSFETs 11a is an example of a "pair of first transistors" of the present invention, and the pair of nMOSFETs 11b is an example of a "pair of second transistors" of the present invention. In this embodiment, the sense amplifier 11 includes a circuit for executing an offset cancellation operation sequence, as described in, for example, Patent Document 1. For simplicity of explanation, MOSFETs and the like used as switches for enabling the offset cancellation operation sequence are omitted from FIG. 3.

[0022] Next, a detailed configuration example of the control unit 100 will be described with reference to Fig. 4. Note that in the example shown in Fig. 4, only one page 10 is shown to simplify the description. As shown in Fig. 4, the control unit 100 includes a first control unit 110 and a second control unit 120. Furthermore, the first control unit 110 includes a CSP control unit 111 and a CSP driver 112. Furthermore, the second control unit 120 includes a CSN control unit 121 and a CSN driver 122.

[0023] The CSP control unit 111 of the first control unit 110 includes a NOT circuit to which the voltage VGP is applied and to which the signal OC_EN_B is input. When the CSP control unit 111 receives a low-level signal OC_EN_B, it outputs a high-level signal CSP_OC_EN. The voltage of the high-level signal CSP_OC_EN is equal to the voltage VGP. The CSP driver 112 of the first control unit 110 includes an nMOSFET having a drain terminal connected to the power supply voltage VBLH, a source terminal connected to a node CSP of page 10, and a gate terminal to which the signal CSP_OC_EN is input.

[0024] The CSN control unit 121 of the second control unit 120 includes a NOT circuit to which a voltage VGN is applied and to which a signal OC_EN_B is input. When a low-level signal OC_EN_B is input, the CSN control unit 121 outputs a high-level signal CSN_OC_EN. The voltage of the high-level signal CSN_OC_EN is equal to the voltage VGN. The CSN driver 122 of the second control unit 120 includes an nMOSFET having a drain terminal connected to node CSN of page 10, a source terminal connected to ground voltage VSS, and a gate terminal to which the signal CSN_OC_EN is input.

[0025] The control unit 100 also includes a voltage supply unit 130 that supplies an equalizer voltage VBLEQ. In the example shown in FIG. 4, the voltage supply unit 130 has three nMOSFETs connected to each other, and a signal CSEQ is input to the gate terminal of each nMOSFET. Of the three nMOSFETs, the drain terminal of a first nMOSFET is connected to the voltage VBLEQ, and the source terminal of the first nMOSFET is connected to the drain terminal of a second nMOSFET. Of the three nMOSFETs, the source terminal of the second nMOSFET is connected to the drain terminal of a third nMOSFET, and the source terminal of the third nMOSFET is connected to the voltage VBLEQ. In addition, a node between the source terminal of the first nMOSFET and the drain terminal of the second nMOSFET is connected to a node CSP, and a node between the source terminal of the second nMOSFET and the drain terminal of the third nMOSFET is connected to a node CSN.

[0026] The control unit 100 further includes an nMOSFET 140 having a drain terminal connected to a power supply voltage VBLH, a source terminal connected to a node CSP, and a gate terminal to which a signal BLC_EN is input. The control unit 100 also includes an nMOSFET 150 having a drain terminal connected to a node CSN, a source terminal connected to a ground voltage VSS, and a gate terminal to which a signal BLC_EN is input.

[0027] In this embodiment, when a charge sharing operation (CS) is performed in any one of the multiple pages 10, the control unit 100 may be configured to supply another voltage (here, an equalizer voltage VBLEQ) instead of the power supply voltage VBLH to the multiple sense amplifiers 11 of the page 10. Furthermore, the other voltage (equalizer voltage VBLEQ) may be a voltage lower than the power supply voltage VBLH (e.g., half the voltage of the power supply voltage VBLH). As a result, when a charge sharing operation (CS) is performed in any one of the pages 10, the other voltage (equalizer voltage VBLEQ) is supplied to the multiple sense amplifiers 11 of the page 10, making it possible to stop (suppress) the supply of the power supply voltage VBLH to the multiple sense amplifiers 11 of the page 10.

[0028] 5, an example of the operation of the control unit 100 when executing an offset cancel operation sequence in one of multiple pages 10 will be described. Note that here, it is assumed that an offset cancel operation (OC) is performed between time t11 and time t12, a charge sharing operation (CS) is performed between time t12 and time t13, a pre-sensing operation (PS) is performed between time t13 and time t14, a bit line charge operation (BC) is performed between time t14 and time t15, a bit line charge hold operation (BCP) is performed between time t15 and time t16, and the bit line charge operation (BC) is resumed after time t16. Note that each of the offset cancel operation (OC), charge sharing operation (CS), pre-sensing operation (PS), and bit line charge operation (BC) may be similar to the operation described in Patent Document 1 mentioned above.

[0029] When the offset cancellation operation (OC) starts at time t11, the signals OC_EN_B and CSEQ go to low level. Also, the signal BLC_EN is at low level. As a result, a high-level signal CSP_OC_EN having a voltage VGP is input to the CSP driver 112, and the power supply voltage VBLH is connected to the node CSP. Here, the voltage VCSP supplied to the node CSP is a voltage dropped from the power supply voltage VBLH by the on-resistance of the nMOSFET of the CSP driver 112. Also, a high-level signal CSN_OC_EN having a voltage VGN is input to the CSN driver 122, and the ground voltage VSS is connected to the node CSN. Then, the voltage VCSN is supplied to the node CSN.

[0030] When the charge sharing operation (CS) starts at time t12, the signals OC_EN_B and CSEQ go high. The signal BLC_EN goes low. This turns off the CSP driver 112, disconnecting the power supply voltage VBLH from the node CSP, and turns off the CSN driver 122, disconnecting the ground voltage VSS from the node CSN. The equalizer voltage VBLEQ is supplied from the voltage supply unit 130 to the nodes CSP and CSN. In this way, when a charge sharing operation is performed in any of the pages 10, another voltage (the equalizer voltage VBLEQ) is supplied to each sense amplifier 11 of any of the pages 10. At time t12, a voltage is applied to the word line WL to be accessed.

[0031] When the pre-sensing operation (PS) starts at time t13, the signals OC_EN_B and CSEQ go low. Also, the signal BLC_EN is low. As a result, similar to time t11, the power supply voltage VBLH is connected to the node CSP, and the ground voltage VSS is connected to the node CSN. Then, the voltage VCSP is supplied to the node CSP, and the voltage VCSN is supplied to the node CSN.

[0032] At time t14, the pair of bit lines BLT, BLB are disconnected (isolated) from the nodes of the sense amplifier 11 (nodes N1, N2 in the example of FIG. 3), and a bit line charge operation (BC) begins. Here, the operation of disconnecting the pair of bit lines BLT, BLB from the nodes of the sense amplifier 11 (nodes N1, N2) may be the same as the operation described in Patent Document 1 mentioned above.

[0033] Next, when a predetermined operation (e.g., a pre-sensing operation (PS)) is started in a page 10 other than one of the multiple pages 10, a bit line charge hold operation (BCP) is started at time t15. At this time, signal OC_EN_B becomes high level. Also, signals CSEQ and BLC_EN are low level. In this case, since each of nodes CSP and CSN is not connected to any voltage, nodes CSP and CSN are in a floating state.

[0034] Then, for example, when the pre-sensing operation (PS) is completed for all of the multiple pages 10, the bit line charging operation (BC) is resumed at time t16. At this time, the signal OC_EN_B goes high and the signal CSEQ goes low. Also, the signal BLC_EN goes high. As a result, the power supply voltage VBLH is supplied to the node CSP via the nMOSFET 140, and the ground voltage VSS is supplied to the node CSN via the nMOSFET 150.

[0035] In this manner, the offset cancel operation sequence is executed on any one of the pages 10.

[0036] With reference to FIG. 6, an example of changes in the power supply voltage and the ground voltage when an offset cancel operation sequence is executed on a plurality of pages 10 in this embodiment will be described.

[0037] 6, when N (N is an integer of 2 or more) pages are provided, the control unit 100 may be configured to start the offset cancel operation (OC) on the (i+1)th page when the offset cancel operation (OC) on the i-th (i is an integer of 1 to N) page ends. This makes it possible to shift the timing at which the offset cancel operation sequence starts for each of the multiple pages 10.

[0038] 6, the control unit 100 may be configured to simultaneously perform a bit line charge operation (BC) on all of the multiple pages 10 after the pre-sensing operation (PS) is completed on all of the multiple pages 10. In this case, the content of the sensing data of each sense amplifier 11 of each of the multiple pages 10 has already been determined by the pre-sensing operation (PS), so even if the bit line charge operation (BC) is simultaneously performed on all of the multiple pages 10, it is possible to transfer correct data to a pair of bit lines BLT and BLB.

[0039] In the example shown in Figure 6, the control unit 100 controls the timing of executing the offset cancel operation sequence in each page 10 (i.e., controls the logical levels of the signals OC_EN_B, CSEQ, and BLC_EN to be sent to each page 10) so that a predetermined operation (e.g., an offset cancel operation (OC), a pre-sensing operation (PS), or a bit line charge operation (BC)) is not performed in any other page 10 (pages 2 to 4) other than the page (page 1) while a predetermined operation (e.g., an offset cancel operation (OC), a pre-sensing operation (PS), or a bit line charge operation (BC)) is being performed in any one of the pages 10 (e.g., page 1).

[0040] Also, in the example shown in Figure 6, when a predetermined operation (e.g., a bit line charge operation (BC)) is being performed in one of the pages 10 (e.g., page 1) and a predetermined operation (e.g., a pre-sensing operation (PS)) is started in another page 10 (e.g., page 2), the control unit 100 stops supplying the power supply voltage VBLH to the sense amplifier 11 in one of the pages 10 (page 1) (i.e., performs an operation (here, a bit line charge hold operation (BCP)) in which the power supply voltage VBLH is not supplied to the sense amplifier 11).

[0041] Furthermore, in the example shown in FIG. 6, when the control unit 100 starts a predetermined operation (e.g., offset cancellation operation (OC)) on one of the pages 10 (e.g., page 1) while another page 10 (e.g., page 2) is performing a predetermined operation (e.g., offset cancellation operation (OC)), the control unit 100 starts the predetermined operation (offset cancellation operation (OC)) on the other page 10 (page 2) after the predetermined operation (offset cancellation operation (OC)) on one of the pages 10 (page 1) has finished.

[0042] In this way, by preventing the power supply voltage VBLH and the ground voltage VSS from being simultaneously supplied to each sense amplifier 11 of multiple pages 10, the power supply noise generated in the power supply voltage VBLH and the ground voltage VSS can be reduced, as shown in Figure 6.

[0043] As described above, according to the semiconductor memory device and the control method thereof of this embodiment, while a predetermined operation of supplying the power supply voltage VBLH common to all pages to the sense amplifiers 11 is being performed in one of the multiple pages 10, the predetermined operation is controlled not to be performed in the other pages 10, thereby preventing the power supply voltage VBLH from being simultaneously supplied to the sense amplifiers 11 of the multiple pages 10. This makes it possible to reduce power supply noise generated in the power supply voltage VBLH compared to, for example, a case where each sense amplifier 11 of the multiple pages 10 is connected to the power supply voltage VBLH, and therefore, even when an offset cancellation operation sequence is performed on the multiple sense amplifiers 11 of each of the multiple pages 10, the sense margin of the sense amplifier can be improved.

[0044] In the above-described embodiment, the control unit 100 includes the first control unit 110, the second control unit 120, the voltage supply unit 130, and the nMOSFETs 140 and 150. However, the present invention is not limited to this. For example, the control unit 100 may be configured with other circuits that provide the same effects as those of the above-described embodiment. [Explanation of symbols]

[0045] 10...Page 11...Sense amplifier (SA) 11a...A pair of P-channel field-effect transistors (pMOSFETs) 11b...A pair of N-channel field effect transistors (nMOSFETs) 100...Control unit 110...First control section 111...CSP control section 112...CSP driver 120...Second control section 121...CSN control section 122...CSN driver BLC_EN,CSEQ,CSP_OC_EN,CSN_OC_EN,OC_EN_B…signal VBLEQ: Equalizer voltage VBLH: Power supply voltage VSS: Ground voltage

Claims

1. a plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each memory cell; a control unit that executes an offset cancel operation sequence for the plurality of sense amplifiers of each page, the offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to all pages to the sense amplifiers; the control unit is configured to control a timing of executing the offset cancel operation sequence for each page when executing the offset cancel operation sequence for each of the plurality of pages so that, while the predetermined operation is being performed on any one of the plurality of pages, the predetermined operation is not performed on any other page other than the one of the plurality of pages. Semiconductor memory device.

2. the control unit is configured to execute the offset cancel operation sequence for the plurality of sense amplifiers of each of the plurality of pages when refreshing the plurality of memory cells of each of the plurality of pages.

2. The semiconductor memory device according to claim 1.

3. the control unit is configured to stop supplying the power supply voltage to the sense amplifier in one of the pages when the predetermined operation is started in the other page while the predetermined operation is being performed in the other page.

2. The semiconductor memory device according to claim 1.

4. the control unit is configured to, when starting the predetermined operation on one of the pages while the predetermined operation is being performed on the other page, start the predetermined operation on the other page after the predetermined operation on the one of the pages has ended.

2. The semiconductor memory device according to claim 1.

5. the predetermined operation includes at least one of an offset cancel operation of a sense amplifier, a pre-sensing operation of the sense amplifier, and a bit line charging operation; 2. The semiconductor memory device according to claim 1.

6. the offset cancel operation sequence includes the offset cancel operation, a sense amplifier charge sharing operation after the offset cancel operation, the pre-sensing operation after the charge sharing operation, and the bit line charging operation after the pre-sensing operation.

6. The semiconductor memory device according to claim 5.

7. the control unit is configured to supply another voltage, instead of the power supply voltage, to the plurality of sense amplifiers of the any one of the plurality of pages when the charge sharing operation is performed in the any one of the plurality of pages.

7. The semiconductor memory device according to claim 6.

8. the other voltage is a voltage lower than the power supply voltage; 8. The semiconductor memory device according to claim 7.

9. the control unit is configured to start the offset cancel operation on the (i+1)th page when the offset cancel operation on the i-th page (i is an integer of 1 to N) is completed in a case where N (N is an integer of 2 or more) pages are provided.

7. The semiconductor memory device according to claim 6.

10. the control unit is configured to simultaneously perform the bit line charging operation on all of the plurality of pages when the pre-sensing operation is completed on all of the plurality of pages.

7. The semiconductor memory device according to claim 6.

11. each of the plurality of sense amplifiers includes a pair of first transistors and a pair of second transistors; 2. The semiconductor memory device according to claim 1.

12. one of the pair of first transistors and the pair of second transistors is an N-channel field effect transistor, and the other of the pair of first transistors and the pair of second transistors is a P-channel field effect transistor; 12. The semiconductor memory device according to claim 11.

13. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device comprises: a plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each memory cell; a control unit that executes an offset cancel operation sequence for the plurality of sense amplifiers of each page, the offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to all pages to the sense amplifiers; The control unit When the offset cancel operation sequence is executed for each of the plurality of pages, a step of controlling a timing of executing the offset cancel operation sequence for each page is executed so that the predetermined operation is not executed for any page other than the certain page while the predetermined operation is being executed for any page among the plurality of pages. A method for controlling a semiconductor memory device.

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