Temperature-compensated and DC offset-eliminating baseband amplifiers, elimination circuits, and chips

Abstract

This invention relates to the field of wireless sensing, and in particular to a baseband amplifier, elimination circuit, and chip for temperature compensation and DC offset cancellation. The baseband amplifier includes a fully inverting amplifier, a power supply circuit, and multiple DC offset cancellation circuits. The power supply circuit includes an LDO circuit, a gain temperature compensation circuit, and a resistor divider network. The gain temperature compensation circuit provides the LDO with a temperature reference voltage that compensates for the amplifier's gain temperature degradation characteristics and a zero-temperature drift reference current. The output of the LDO, after being divided by the resistor divider network, serves as a reference voltage V. CM The DC offset cancellation circuits are connected across each transimpedance amplifier, and are configured according to V. CM This invention generates a control current in real time to counteract the unbalanced DC current injected by the pre-amplifier mixer. It solves the problems of gain instability, multi-source offset, and difficulty in balancing circuit overhead and accuracy in existing fully inverter-type amplifiers.

Description

Technical Field

[0001] This invention relates to the field of wireless sensing, and in particular to a baseband amplifier with temperature compensation and DC offset cancellation, as well as a corresponding DC offset cancellation circuit and millimeter-wave transceiver chip. Background Technology

[0002] As semiconductor processes evolve towards deeper submicron (e.g., 22nm and below), millimeter-wave transceiver chips based on CMOS technology have been widely used due to their high integration and low cost. However, the stability of CMOS devices in complex outdoor thermal environments has become a core bottleneck restricting the development of high-performance systems.

[0003] In the trend towards low-voltage (e.g., 0.8V~1.0V) designs, the inverter-based architecture has become the core choice for baseband amplifiers due to its extremely high transconductance efficiency and near-full-swing output advantage. However, its physical characteristics are extremely affected by temperature: carrier mobility ( ) and threshold voltage ( Temperature drift will directly lead to transconductance ( Significant changes in the gain of the receiver link can lead to severe fluctuations. Furthermore, the architecture lacks the clamping effect of the tail current source, making it extremely sensitive to power supply fluctuations and DC offset, which can easily cause amplitude distortion and seriously affect the accuracy of quantitative remote sensing imaging.

[0004] To address the aforementioned issues, existing industry solutions include digital calibration, bias current methods, and passive resistor methods. However, there are significant trade-offs between the performance metrics and system overhead of these solutions. For example, digital calibration uses a temperature sensor in conjunction with a lookup table (LUT) for discrete adjustment. While offering a wide compensation range, it results in complex logic circuitry and substantial chip area and power consumption. More importantly, the "instantaneous jumps" in gain caused by digital adjustment lead to discontinuities in the received signal, resulting in severe phase noise and image artifacts in synthetic aperture radar (SAR) imaging. The bias current method primarily uses bias current compensation for differential pair structures with tail current sources. For fully inverter architectures, introducing complex bias current adjustment circuitry disrupts the original structural symmetry of the inverter, leading to a significant deterioration in the power supply rejection ratio (PSRR). This makes the amplifier highly susceptible to power supply noise interference, reducing the system's signal-to-noise ratio. The passive resistor method utilizes the temperature characteristics of resistors to compensate for transconductance changes. However, in advanced CMOS processes, the absolute resistance value of on-chip resistors is greatly affected by process corner deviations (typically ±30%). This uncontrollable process deviation makes it difficult to guarantee compensation accuracy in mass production, resulting in extremely poor gain consistency between different chips.

[0005] In summary, existing gain temperature compensation techniques often come at the cost of sacrificing area, power consumption, or power supply rejection performance, and struggle to resolve the coupling contradiction between "gain compensation" and "DC stability." Especially under dynamic power supply voltage fluctuations, achieving a smooth, continuous gain temperature compensation and DC suppression scheme that does not sacrifice PSRR and is robust to process variations is a critical technical problem that urgently needs to be solved in the field of lightweight radar chips using advanced CMOS processes. Summary of the Invention

[0006] To address the problems of gain instability, multi-source offset, and difficulty in balancing circuit overhead and accuracy in existing fully inverter-type amplifiers, this invention provides a baseband amplifier with temperature compensation and DC offset elimination, along with a corresponding DC offset elimination circuit and a millimeter-wave transceiver chip.

[0007] The technical solution provided by this invention is as follows:

[0008] A temperature-compensated and DC offset-cancelled baseband amplifier includes: a fully inverting amplifier, a power supply circuit, and multiple DC offset cancellation circuits. The power supply circuit includes a low-dropout linear regulator (LDO), a gain temperature compensation circuit, and a resistor divider network. The gain temperature compensation circuit provides a temperature reference voltage V to the LDO to compensate for gain temperature degradation characteristics. tr and the reference current I with zero temperature drift ref V tr The LDO circuit's output voltage V varies with temperature at a specified slope. LDO The voltage V is used as the power supply for the fully inverting amplifier and then divided by a resistor divider network to serve as the reference voltage. CM .

[0009] The DC offset cancellation circuits are connected across each transimpedance amplifier (TIA) in the fully inverting amplifier. Each DC offset cancellation circuit includes two capacitors C0 and C1, three resistors R15 to R17, amplifier OP2, and voltage-controlled current source VCCS. One end of R15 is connected to V... CM One end of R16 is connected to the non-inverting input of OP2, along with one end of C0; the other end of C0 is grounded; one end of R16 is connected to the output of TIA, and the other end is connected to the inverting input of OP1, along with one end of R17; the other end of R17 is connected to one end of C1, and the other end of C1 is connected to the control terminal of the voltage-controlled current source VCCS, along with the output of OP2; the input terminal of the voltage-controlled current source VCCS is connected to V... LDO Or VDD; the output terminal of the voltage-controlled current source VCCS is connected to the input terminal of TIA.

[0010] As a further improvement of the present invention, the gain temperature compensation circuit includes a CTAT voltage generation circuit, a PTAT voltage generation circuit, an amplifier OP0, a bandgap reference circuit, a fixed resistor R0, and a variable resistor R adj R adj Connect between the inverting input and output of OP0; one end of R0 is connected to the inverting input of OP0, and the other end is connected to the output signal of the CTAT voltage generation circuit or the PTAT voltage generation circuit; the output of the bandgap reference circuit is connected to the non-inverting input of OP0.

[0011] Among them, the bandgap reference circuit is used to directly output a reference current I with zero temperature drift. ref And output a zero-temperature-drift reference voltage V to OP0 ref The CTAT voltage generation circuit outputs a voltage signal with a fixed slope and a negative temperature coefficient; the PTAT voltage generation circuit outputs a voltage signal with a fixed slope and a positive temperature coefficient. This is achieved by selectively connecting either the CTAT or PTAT voltage generation circuit to OP0 and adjusting R. adj The resistance value is such that the output of OP0 outputs a temperature reference voltage V with a specified temperature characteristic and slope value. tr .

[0012] As a further improvement of this invention, in the gain temperature compensation circuit, the outputs of the CTAT voltage generation circuit and the PTAT voltage generation circuit are respectively connected to the two inputs of a 2-to-1 selector MUX, and the output of the MUX is connected to the corresponding port of R0; thus, a 1-bit control code ctrl0 is used to select the CTAT voltage generation circuit and the PTAT voltage generation circuit. Variable resistor R adj A numerically controlled resistor array is used, and the resistance value is adjusted through a multi-bit control code Ctrl.

[0013] As a further improvement of the present invention, the method for determining the code values ​​of Ctrl0 and Ctrl includes:

[0014] The slope values ​​of the temperature-reference voltage curves output by Ctrl0 and Ctrl under different values ​​in the gain temperature compensation circuit were determined by simulation, and the first mapping relationship between the two was established.

[0015] Gain-temperature degradation curves were pre-tested under different ambient temperature conditions to determine the temperature reference voltage V that can compensate for it. tr The slope value changes with temperature, and a second mapping relationship is established between the two.

[0016] Based on the measured gain-temperature degradation curve of any circuit at a specified process corner, the second mapping relationship and the first mapping relationship are consulted to determine the code values ​​of Ctrl0 and Ctrl that can achieve the best compensation.

[0017] As a further improvement of this invention, the CTAT voltage generation circuit includes three PMOS transistors M28, M29, and M32, two NMOS transistors M30 and M31, an NPN transistor Q3, and two resistors R8 and R9. The circuit connections are as follows: the sources of M28, M29, and M32 are connected to VDD; the drains of M28 and M30 are connected to the gates of M30 and M31; the gates of M28, M29, and M32 are connected to the drains of M29 and M31; the source of M30 is connected to the emitter of Q3; the source of M31 is connected to one end of R8; and the drain of M32 is connected to one end of R9, serving as the negative temperature coefficient voltage V. CTAT The output port of Q3; the base and collector of Q3 are connected to the other end of R8 and R9 to VSS.

[0018] As a further improvement of this invention, the PTAT voltage generation circuit includes three PMOS transistors M33, M34, and M37, two NMOS transistors M35 and M36, two resistors R10 and R11, and NPN transistors Q4 and Q5; the ratio of Q4 to Q5 is 1:N2. The circuit connections are as follows: the sources of M33, M34, and M37 are connected to VDD; the drains of M33 and M35 are connected to the gates of M35 and M36; the gates of M33, M34, and M37 are connected to the drains of M34 and M36; the source of M35 is connected to the emitter of Q4; the source of M36 is connected to one end of R10, and the other end of R10 is connected to the emitter of Q5; the drain of M37 is connected to one end of R11 and serves as the positive temperature coefficient voltage V. PTAT The output port of Q4 and Q5; the base and collector of Q4 and Q5 are connected to the other end of R11 to VSS.

[0019] As a further improvement of this invention, the bandgap reference circuit includes six PMOS transistors M19~M25, two NMOS transistors M26 and M27, six resistors R2~R7, and NPN transistors Q0~Q2; the ratio of Q1 to Q2 is N1:1. The circuit connection is as follows:

[0020] The sources of M19~M24 are connected to VDD; the gates of M19~M23 are connected to the drain of M27 and the output of OP1; the gate and drain of M24 are connected to the source of M25; the drains of M25 and M26 are connected to the gate of M27; the gates of M25 and M26 are connected to one end of R2 and R5, the drain of M19, the inverting input of OP1, and the emitter of Q0; one end of R3, R4, and R6 is connected to the drain of M20 and the non-inverting input of OP1; the other end of R4 is connected to the emitter of Q1; the other ends of R5 and R6 are connected to the drain of M21 and the emitter of Q2; the drain of M22 is connected to one end of R7 and used to output VDD. refThe sources of M26 and M27, the other ends of R2, R3, and R7, and the collectors and bases of Q0, Q1, and Q2 are connected to VSS; the drain of M23 is used for output I. ref .

[0021] As a further improvement of the present invention, the resistor voltage divider network is composed of resistors R18 and R19, with one end of R19 connected to V. LDO The other end is connected to one end of R18 and serves as V. CM The output port of R18; the other end of R18 is grounded.

[0022] As a further improvement of the present invention, the fully inverting amplifier includes a multi-stage transimpedance amplifier (TIA); in the DC offset cancellation circuit connected to each stage of the TIA, the values ​​of C1 and R17 are optimized to ensure the stability of the corresponding loop.

[0023] As a further improvement of the present invention, the baseband amplifier includes a single-ended structure and a differential structure; the differential baseband amplifier includes two sets of mirrored fully inverting amplifiers and a DC offset cancellation circuit, as well as one less power supply circuit.

[0024] As a further improvement of the present invention, the baseband amplifier also includes a low-pass filter connected between the input terminal of the gain temperature compensation circuit and the Vref input port of the LDO to filter out ambient noise.

[0025] This invention also includes a DC offset cancellation circuit, comprising capacitors C0 and C1, resistors R15 to R17, amplifier OP2, and voltage-controlled current source VCCS. One end of R15 is connected to a reference voltage V. CM The other end is connected to the non-inverting input of OP2, sharing one end with C0; the other end of C0 is grounded; one end of R16 serves as the input of the DC offset cancellation circuit. IN The other end of R16 and one end of R17 are connected to the inverting input of OP1; the other end of R17 is connected to one end of C1, and the other end of C1 and the output of OP2 are connected to the control terminal of the voltage-controlled current source VCCS; the input terminal of the voltage-controlled current source VCCS is connected to the power supply; the output terminal of the voltage-controlled current source VCCS serves as the output terminal V of the DC offset cancellation circuit. OUT .

[0026] The present invention also includes a millimeter-wave transceiver chip that employs a baseband amplifier with temperature compensation and DC offset elimination as described above.

[0027] The present invention has the following beneficial effects:

[0028] This invention introduces gain temperature compensation technology based on power supply modulation and DC offset cancellation technology into the fully inverter amplifier, thereby obtaining a stable architecture for a centralized baseband amplifier. It compensates for transconductance temperature drift by dynamically adjusting the power supply of the fully inverter amplifier and simultaneously linking the DC offset cancellation (DCOC) loop to forcibly maintain the stability of the amplifier's DC operating point under large power supply fluctuations.

[0029] The gain temperature compensation technique based on power supply modulation is implemented through a newly added power supply circuit. This circuit provides a base reference via an internally integrated second-order bandgap reference source and utilizes a gain-adjustable inverting amplifier to precisely scale the slope of the voltage signal with either a positive or negative temperature coefficient. This ensures that the generated reference voltage slope accurately matches the chip's measured gain-temperature degradation curve, thus serving as the input reference for the LDO and enabling dynamic compensation of the baseband amplifier output gain as ambient temperature changes.

[0030] DC offset cancellation technology is achieved through a DC offset cancellation circuit. On one hand, the DC offset cancellation circuit sets a voltage-controlled current source at the differential input node of the fully inverter amplifier stage (i.e., the output of the pre-mixer). The DC offset detection signal at the output drives this current source to perform current pumping in real time, thereby directly canceling the unbalanced DC current injected by the pre-mixer at the physical level and preventing offset from entering the amplification core. On the other hand, the DC reference voltage V used in the DC offset cancellation circuit loop... CM It is not a fixed value, but rather the output voltage V modulated directly from the LDO using a resistor divider network. LDO Real-time extraction from V. This mapping mechanism ensures that V... CM It always shifts proportionally in real time with the power supply, so that the amplifier is always locked at the geometric center of the current power supply during full-temperature modulation. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the baseband amplifier with temperature compensation and DC offset elimination provided in Embodiment 1 of the present invention.

[0032] Figure 2 This is a schematic diagram of the gain temperature compensation circuit used in the baseband amplifier of Embodiment 1 of the present invention.

[0033] Figure 3 This is a circuit diagram of the resistor voltage divider network used in the baseband amplifier of Embodiment 1 of the present invention.

[0034] Figure 4 This is a circuit diagram of the DC offset cancellation circuit used in the baseband amplifier of Embodiment 1 of the present invention.

[0035] Figure 5This is a circuit diagram of a typical three-stage single-ended fully inverting amplifier.

[0036] Figure 6 This is a circuit diagram of the fully inverting amplifier with a DC offset cancellation circuit introduced in Embodiment 1 of the present invention.

[0037] Figure 7 This is a circuit diagram of a baseband amplifier with a differential structure that incorporates power supply voltage and DC offset cancellation circuitry, as provided in Embodiment 1 of the present invention.

[0038] Figure 8 This is a schematic diagram of a baseband amplifier including a low-pass filter provided in Embodiment 1 of the present invention.

[0039] Figure 9 This is a circuit diagram of the CTAT voltage generation circuit used in Embodiment 1 of the invention.

[0040] Figure 10 This is a circuit diagram of the PTAT voltage generation circuit used in Embodiment 1 of the invention.

[0041] Figure 11 This is a circuit diagram of the second-order curvature compensation bandgap reference circuit used in Embodiment 1 of the present invention.

[0042] Figure 12 This is a circuit diagram of the high power supply rejection ratio and low dropout linear regulator used in Embodiment 1 of the present invention.

[0043] Figure 13 This is a comparison graph showing how the gain of different circuit schemes changes with ambient temperature during the test experiment.

[0044] Figure 14 This is a comparison chart showing the changes in the output DC operating point of different circuit schemes under the condition of unbalanced current injected into the pre-amplifier during the test experiment. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] Example 1

[0048] like Figure 1 As shown, this embodiment provides a temperature-compensated and DC offset-cancelled baseband amplifier, which includes a fully inverter-type amplifier, a power supply circuit, and multiple DC offset cancellation circuits (DCOC). The power supply circuit provides a dynamic voltage V to the fully inverter-type amplifier. LDO and V LDO This serves as the power supply voltage required for the operation of the fully inverter-type amplifier, compensating for gain temperature fluctuations caused by temperature variations. On the other hand, it provides a voltage compatible with V for the DC offset cancellation circuit. LDO Dynamic reference voltage V with the same temperature coefficient CM The DC offset cancellation circuit uses V CM Drive and control the voltage-controlled current source to accurately output a current signal that can cancel the offset voltage of the baseband amplifier.

[0049] Specifically, in this embodiment, the power supply circuit includes a low-dropout linear regulator (LDO), a gain temperature compensation circuit (GTC), and a resistor divider network; the gain temperature compensation circuit provides the low-dropout linear regulator with a temperature reference voltage V that can compensate for the gain temperature degradation characteristics. tr and the reference current I with zero temperature drift ref Temperature reference voltage V with gain compensation effect tr The voltage value can change with the ambient temperature at a specified slope. The output voltage V of the LDO circuit... LDO The voltage is divided by a resistor divider network and used as the reference voltage V. CM .

[0050] In the typical solution provided in this embodiment, such as Figure 2 As shown, the gain temperature compensation circuit includes a CTAT voltage generation circuit, a PTAT voltage generation circuit, an amplifier OP0, a bandgap reference circuit, a fixed resistor R0, and a variable resistor R. adj R adj Connect between the inverting input and output of OP0; one end of R0 is connected to the inverting input of OP0, and the other end is connected to the output signal of the CTAT voltage generation circuit or the PTAT voltage generation circuit; the output of the bandgap reference circuit is connected to the non-inverting input of OP0.

[0051] Among them, the bandgap reference circuit is used to directly output a reference current I with zero temperature drift. ref And output a zero-temperature-drift reference voltage V to OP0 refThe CTAT voltage generation circuit outputs a voltage signal with a fixed slope and a negative temperature coefficient; the PTAT voltage generation circuit outputs a voltage signal with a fixed slope and a positive temperature coefficient. This is achieved by selectively connecting either the CTAT or PTAT voltage generation circuit to OP0 and adjusting R. adj The resistance value is such that the output of OP0 outputs a temperature reference voltage V with a specified temperature characteristic and slope value. tr V tr As the reference input for subsequent LDO circuits, the output voltage of the LDO has a specific temperature slope, which can be used to power an inverter-type baseband amplifier to counteract the fluctuations in its gain with temperature.

[0052] In this embodiment, in order to ensure V CM Temperature characteristics and V LDO With consistent temperature characteristics, the resistive voltage divider network, such as Figure 3 As shown, it consists of resistors R18 and R19, with one end of R19 connected to V. LDO The other end is connected to one end of R18 and serves as V. CM The output port of R18; the other end of R18 is grounded. Wherein, V CM With V LDO The voltage ratio is controlled by the resistance values ​​of R18 and R19.

[0053] To achieve a dynamic voltage V with gain compensation effect at the power supply circuit output in different schemes LDO The slope of the voltage change with temperature is quantitatively adjusted. In this embodiment, the outputs of the CTAT voltage generation circuit and the PTAT voltage generation circuit are respectively connected to the two inputs of a 2-to-1 selector MUX, and the output of the MUX is connected to the corresponding port of R0. At this time, the CTAT voltage generation circuit and the PTAT voltage generation circuit are selected using a 1-bit control code ctrl0. Correspondingly, the variable resistor R... adj A numerically controlled resistor array can be used, which consists of Poly resistors with low process variation as resistor units. Poly resistors offer relatively high control precision, and their resistance value can be adjusted using a multi-bit control code Ctrl. Alternatively, in other embodiments, the numerically controlled resistor array can be composed of CMOS transistors as resistor units, thereby reducing circuit area. The length of the control code Ctrl is related to the size of the numerically controlled resistor array and its control precision.

[0054] Specifically, in the gain temperature compensation circuit, an adjustable-gain inverting amplifier circuit linearly scales the original slope of the voltage with positive temperature coefficient (PTAT) or negative temperature coefficient (CTAT), thereby achieving the desired output temperature reference voltage V. trThe slope is flexibly adjusted according to temperature changes. Wherein, V tr The "trend direction" of the slope changing with temperature is related to the temperature coefficient of the gated CTAT voltage generation circuit or PTAT voltage generation circuit; while V tr The magnitude of the slope of the temperature change can be determined by the variable resistor R. adj The resistance value is adjusted. Therefore, by jointly adjusting the values ​​of control codes Ctrl0 and Ctrl, the gain temperature compensation circuit can output a temperature reference voltage with an arbitrary slope.

[0055] After introducing this power supply circuit into the baseband amplifier, when changes in ambient temperature cause variations in the transconductance and gain fluctuations within the fully inverter amplifier, the GTC monitors the temperature change and adjusts the output reference voltage. The LDO then adjusts the power supply voltage supplied to the amplifier. Since the gain of the inverter structure increases with increasing power supply voltage, this mechanism can accurately compensate for temperature-induced gain drops, keeping fluctuations within 1 dB over a wide temperature range.

[0056] In practical applications, users can flexibly adjust the scaling factor using digital control codes based on the measured gain-temperature degradation curve of the chip, thereby fitting and outputting a temperature reference voltage V with a specific compensation slope. tr This serves as the reference input for subsequent LDOs. For example, for a specific circuit chip employing a baseband amplifier, the methods for determining the code values ​​of Ctrl0 and Ctrl include:

[0057] (1) The slope values ​​of the temperature-reference voltage curves output by ctrl0 and Ctrl under different values ​​in the gain temperature compensation circuit are determined by simulation; and the first mapping relationship between the two is established.

[0058] This mapping relationship is mainly related to the temperature characteristics of each component and circuit in the gain temperature compensation circuit. Under different circuit structures, this mapping relationship needs to be predetermined.

[0059] (2) Test the gain-temperature degradation curves under different ambient temperature conditions in advance, and determine the temperature reference voltage V that can compensate for it. tr The slope value changes with temperature, and a second mapping relationship is established between the two.

[0060] This mapping relationship is mainly related to parameters such as the baseband amplifier and its process angle. In different circuits or chips, this mapping relationship needs to be predetermined.

[0061] (3) Based on the gain-temperature degradation curve of any circuit measured at a specified process angle, query the second mapping relationship and the first mapping relationship to determine the code values ​​of ctrl0 and Ctrl that can achieve the best compensation.

[0062] In this embodiment, the DC offset cancellation circuit is connected across each transimpedance amplifier (TIA) in the fully inverting amplifier. Figure 4 As shown, each DC offset cancellation circuit includes two capacitors C0 and C1, three resistors R15 to R17, an amplifier OP2, and a voltage-controlled current source VCCS. One end of R15 is connected to V. CM One end of R16 is connected to the non-inverting input of OP2, along with one end of C0; the other end of C0 is grounded; one end of R16 is connected to the output of TIA, and the other end is connected to the inverting input of OP1, along with one end of R17; the other end of R17 is connected to one end of C1, and the other end of C1 is connected to the control terminal of the voltage-controlled current source VCCS, along with the output of OP2; the input terminal of the voltage-controlled current source VCCS is connected to V... LDO Or VDD; the output terminal of the voltage-controlled current source VCCS is connected to the input terminal of TIA.

[0063] For example, in this embodiment, a typical three-stage single-ended fully inverting amplifier is as follows: Figure 5 As shown, the first stage includes one transimpedance amplifier TIA0 and one transconductance amplifier Gm0; TIA0 is composed of an inverter INV0 and a resistor R12. The second stage includes one transimpedance amplifier TIA1 and one transconductance amplifier Gm1; TIA1 is composed of an inverter INV1 and a resistor R13. The third stage includes one transimpedance amplifier TIA2 and a buffer; TIA2 is composed of an inverter INV2 and a resistor R14. After introducing the DC offset cancellation circuit, the circuit diagram of the single-ended fully inverter type amplifier is as follows: Figure 6 As shown.

[0064] exist Figure 6 In the fully inverting amplifier shown, each stage's transimpedance amplifier (TIA) and the newly added DC offset cancellation circuit form a loop. The DC offset cancellation circuit monitors the offset of the DC potential relative to the reference DC potential (generated by the LDO output through a resistor divider network) in real time by constructing a low-pass sampling network at the output, and uses this to drive the controlled compensation current source connected to the input node. This loop uses a negative feedback mechanism to perform precise current pumping at the input, physically neutralizing the unbalanced DC current injected by the local oscillator leakage of the preceding mixer or device mismatch, thus achieving source cancellation of the offset voltage.

[0065] It is worth emphasizing that: the fully inverting amplifier includes multiple stages of transimpedance amplifiers (TIAs); in the DC offset cancellation circuit connected to each stage of the TIA, the values ​​of C1 and R17 can be flexibly optimized to ensure that the stability of each corresponding loop meets the design requirements.

[0066] Figure 6The circuit diagram of a fully inverting amplifier with a single-ended structure is shown. In practical applications, the baseband amplifier with temperature-compensated power supply voltage and DC offset cancellation circuitry provided in this embodiment is also suitable for differential circuits. Specifically, as... Figure 7 As shown, the differential baseband amplifier includes two sets of mirrored fully inverter amplifiers and a DC offset cancellation circuit, as well as one less power supply circuit. This power supply circuit simultaneously provides the power supply voltage V to both fully inverter amplifiers. LDO It also provides a reference voltage V for the two sets of DC offset cancellation circuits. CM Of course, the power supply circuit can also provide V to the input terminal of the voltage-controlled current source in the two sets of DC offset cancellation circuits. LDO .

[0067] like Figure 8 As shown, in a further optimized embodiment, the baseband amplifier may also include a low-pass filter connected between the input of the gain temperature compensation circuit and the Vref input port of the LDO to filter out ambient noise. Baseband amplifiers with low-pass filters are typically used in applications where high ambient noise suppression performance is required.

[0068] In summary, the baseband amplifier provided in this embodiment introduces gain temperature compensation technology and DC offset cancellation technology based on power supply modulation on the basis of the fully inverting amplifier; the former is implemented through the power supply circuit, and the latter is implemented through the DC offset cancellation circuit.

[0069] In the power supply circuit, the gain temperature compensation circuit integrates a high-precision second-order bandgap reference source to generate a zero-temperature coefficient reference level with curvature compensation. The core feature of the gain temperature compensation circuit is that it linearly scales the original slope of the positive temperature coefficient (PTAT) or negative temperature coefficient (CTAT) voltage using a gain-adjustable inverting amplifier circuit. Users can flexibly adjust the scaling factor via digital control codes based on the chip's measured gain-temperature degradation curve, thereby fitting and outputting a temperature reference voltage with a specific compensation slope as the reference input for the subsequent LDO circuit. The LDO circuit employs an architecture with high power supply rejection ratio (PSRR) and extremely low output noise, responsible for linearly mapping the temperature-varying reference signal generated by the GTC to the dynamic supply voltage of the fully inverter amplifier. Through this power supply modulation mechanism, when ambient temperature changes cause a shift in the transistor's physical transconductance, the LDO output voltage compensates accordingly, adjusting the transistor's overdrive voltage to offset the transconductance temperature drift, thus suppressing full-chain gain fluctuations to a very small range.

[0070] In the DC offset cancellation circuit, on the one hand, the circuit monitors the DC potential offset in real time by constructing a low-pass sampling network at the output, and uses this to drive the voltage-controlled current source connected to the input node. This loop uses a negative feedback mechanism to perform precise current pumping at the input, physically neutralizing the unbalanced DC current injected by the local oscillator leakage of the pre-amplifier or device mismatch, thus achieving source cancellation of the offset voltage. On the other hand, the loop's DC reference bias point is extracted in real time from the modulated output voltage of the LDO through a resistor divider network, establishing a dynamic proportional mapping relationship between the reference and the supply voltage. This design ensures that regardless of the power supply voltage fluctuations caused by the temperature compensation process, the loop can forcefully smooth out the pre-amplifier-injected offset and the potential offset caused by temperature drift to an extremely low level, keeping the inverter stably biased at the center (high linearity region) of the current voltage environment, effectively preventing signal clipping.

[0071] In the typical solution provided in this embodiment, such as Figure 9 As shown, the CTAT voltage generation circuit can employ a circuit including three PMOS transistors M28, M29, and M32, two NMOS transistors M30 and M31, an NPN transistor Q3, and two resistors R8 and R9. The circuit connections are as follows: the sources of M28, M29, and M32 are connected to VDD; the drains of M28 and M30 are connected to the gates of M30 and M31; the gates of M28, M29, and M32 are connected to the drains of M29 and M31; the source of M30 is connected to the emitter of Q3; the source of M31 is connected to one end of R8; and the drain of M32 is connected to one end of R9, serving as the negative temperature coefficient voltage V. CTAT The output port of Q3; the base and collector of Q3 are connected to VSS along with the other ends of R8 and R9.

[0072] like Figure 10 As shown, the PTAT voltage generation circuit can include three PMOS transistors M33, M34, and M37, two NMOS transistors M35 and M36, two resistors R10 and R11, and NPN transistors Q4 and Q5; the ratio of Q4 to Q5 is 1:N². The circuit connections are as follows: the sources of M33, M34, and M37 are connected to VDD; the drains of M33 and M35 are connected to the gates of M35 and M36; the gates of M33, M34, and M37 are connected to the drains of M34 and M36; the source of M35 is connected to the emitter of Q4; the source of M36 is connected to one end of R10, and the other end of R10 is connected to the emitter of Q5; the drain of M37 is connected to one end of R11 and serves as the positive temperature coefficient voltage V. PTAT The output port of Q4 and Q5; the base and collector of Q4 and Q5 are connected to the other end of R11 to VSS.

[0073] like Figure 11As shown, the bandgap reference circuit in this embodiment adopts a second-order curvature-compensated bandgap reference circuit, which includes six PMOS transistors M19~M25, two NMOS transistors M26 and M27, six resistors R2~R7, and NPN transistors Q0~Q2; the ratio of Q1 to Q2 is N1:1, and the value of N1 is determined so that the circuit can output the required zero-temperature-drift reference voltage and reference current. The circuit connection relationship is as follows:

[0074] The sources of M19~M24 are connected to VDD; the gates of M19~M23 are connected to the drain of M27 and the output of OP1; the gate and drain of M24 are connected to the source of M25; the drains of M25 and M26 are connected to the gate of M27; the gates of M25 and M26 are connected to one end of R2 and R5, the drain of M19, the inverting input of OP1, and the emitter of Q0; the ends of R3, R4, and R6 are connected to the drain of M20 and the non-inverting input of OP1; the other end of R4 is connected to the emitter of Q1; the other ends of R5 and R6 are connected to the drain of M21 and the emitter of Q2; the drain of M22 is connected to one end of R7 and used to output VDD. ref The sources of M26 and M27, the other ends of R2, R3, and R7, and the collectors and bases of Q0, Q1, and Q2 are connected to VSS; the drain of M23 is used for output I. ref .

[0075] like Figure 12 As shown, the LDO circuit in this embodiment uses a high power supply rejection ratio and low dropout linear regulator, which consists of PMOS transistors M0, M1, M6, M10, M11, M12, M16, M17, and M38, NMOS transistors M2~M5, M7~M9, M13~M15, and M18, power transistor MP, capacitors CC, CQ, and CP, and resistor R1. The circuit connection is as follows:

[0076] The sources of M0, M1, M6, M10, M11, M12, M16, M17, M38, and MP are connected to VDD; the drain of M38 is connected to the drain of M4 and the gates of M4 and M5, and serves as the input port of Iref; the drains of M0 and M3 are connected to the gates of M0, M1, and M10; the gate of M3 is connected to VDD. LDO The sources of M2 and M3 are connected to the drain of M5; the gate of M2 is connected to V. trThe drains of M1 and M2 are connected to the gates of M6, M11, and M16; the drains of M6 and M7 are connected to the gates of M7 and M8; the drains of M10, M8, and M9 are connected to the gates of M9, M13, and M14; the drains of M11, M12, and M13 are connected to the gates of M12 and M17; the drains of M14, M15, and M16 are connected to the gates of M15 and M18; the drain of M17 is connected to the gates of M38 and MP, as well as one end of CP, with the node denoted as VG; the other end of CP is connected to the drain of MP and one end of R1, and connected to V. LDO The other end of R1 is connected to VSS via M4, M5, M7~M9, M13~M15, and M18; one end of CC is connected to the drain of M2, and the other end is connected to VSS. LDO One end of CQ is connected to the drain of M0, and the other end is connected to the drain of M17.

[0077] Example 2

[0078] Based on the scheme in Embodiment 1, this embodiment further provides a DC offset cancellation circuit, which includes capacitors C0 and C1, resistors R15 to R17, amplifier OP2, and voltage-controlled current source VCCS. One end of R15 is connected to the reference voltage V. CM The other end is connected to the non-inverting input of OP2, sharing one end with C0; the other end of C0 is grounded; one end of R16 serves as the input of the DC offset cancellation circuit. IN The other end of R16 and one end of R17 are connected to the inverting input of OP1; the other end of R17 is connected to one end of C1, and the other end of C1 and the output of OP2 are connected to the control terminal of VCCS; the input of VCCS is connected to the power supply; the output of VCCS serves as the output terminal V of the DC offset cancellation circuit. OUT .

[0079] This DC offset cancellation circuit can be used as an independent circuit module and applied to various existing fully inverter-type amplifiers to eliminate unbalanced current injected by the pre-amplifier, device mismatch, and DC point offset caused by drastic environmental changes, thereby overcoming the multi-source offset problem of the circuit.

[0080] Example 3

[0081] Based on the scheme in Embodiment 1, this embodiment further provides a millimeter-wave transceiver chip, which adopts a baseband amplifier with temperature compensation and DC offset elimination as in Embodiment 1.

[0082] Performance testing

[0083] To verify the performance of the temperature-compensated and DC offset-eliminating baseband amplifier provided by this invention, technicians conducted simulations and performance tests on the relevant circuit modules and radar transceiver system using a 22nm CMOS process.

[0084] 1. Gain Temperature Compensation

[0085] This experiment first compared and tested the gain of the baseband amplifier using the gain temperature compensation technology of this invention with that of the amplifier without the relevant power supply circuit, as a function of ambient temperature. The results are as follows: Figure 13 As shown.

[0086] Analysis of the data in the graph shows that without temperature compensation, the gain fluctuation exceeds 5dB between -40℃ and 80℃; with temperature compensation, the gain fluctuation is less than 1dB. Using the power supply circuit of this invention can significantly reduce the gain fluctuation of the baseband amplifier with temperature.

[0087] 2. Elimination of DC offset

[0088] This experiment further tested the output DC operating point of the differential fully inverter baseband amplifier after employing a DC offset cancellation circuit, under the condition of injecting unbalanced current into the pre-stage mixer. The experimental results are as follows: Figure 14 As shown.

[0089] Analysis of the data in the figure shows that when the injected differential unbalanced current is within 360uA (this value can be increased by increasing the size of the controlled current source transistor), the DC offset elimination circuit can ensure the stability of the DC operating point of the circuit.

[0090] 3. Monte Carlo simulation

[0091] This experiment further performed a global Monte Carlo simulation on the DC operating point of the baseband amplifier designed in this invention, which includes temperature compensation and DC offset cancellation functions. Distribution plots from 200 simulations were obtained. Based on the data in the plots, it was determined that the 3σ fluctuation of the DC operating point was less than 10mV in the 200 simulation results, demonstrating the superiority of the proposed DC offset cancellation circuit in dealing with mismatch.

[0092] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A baseband amplifier with temperature compensation and DC offset cancellation, characterized in that, It includes: Totally inverting amplifier The power supply circuit includes a low-dropout linear regulator, a gain temperature compensation circuit, and a resistor divider network. The gain temperature compensation circuit is used to provide a temperature reference voltage V for low-dropout linear regulators that can compensate for the gain temperature degradation characteristics. tr and the reference current I with zero temperature drift ref V tr The output voltage V of the low-dropout linear regulator varies with temperature at a specified slope. LDO The voltage V is used as the power supply for the fully inverting amplifier and then divided by a resistor divider network to serve as the reference voltage. CM ; Multiple DC offset cancellation circuits are connected across each transimpedance amplifier (TIA) in the fully inverting amplifier. Each DC offset cancellation circuit includes capacitors C0 and C1, resistors R15 to R17, amplifier OP2, and voltage-controlled current source VCCS. One end of R15 is connected to V... CM One end of R16 is connected to the non-inverting input of OP2, along with one end of C0; the other end of C0 is grounded; one end of R16 is connected to the output of TIA, and the other end is connected to the inverting input of OP1, along with one end of R17; the other end of R17 is connected to one end of C1, and the other end of C1 is connected to the control terminal of the voltage-controlled current source VCCS, along with the output of OP2; the input terminal of the voltage-controlled current source VCCS is connected to V... LDO Or VDD; the output terminal of the voltage-controlled current source VCCS is connected to the input terminal of TIA.

2. The baseband amplifier with temperature compensation and DC offset elimination according to claim 1, characterized in that: The gain temperature compensation circuit includes a CTAT voltage generation circuit, a PTAT voltage generation circuit, an amplifier OP0, a bandgap reference circuit, a fixed resistor R0, and a variable resistor R. adj ;R adj Connect between the inverting input and output of OP0; one end of R0 is connected to the inverting input of OP0, and the other end is connected to the output signal of the CTAT voltage generation circuit or the PTAT voltage generation circuit; the output of the bandgap reference circuit is connected to the non-inverting input of OP0. The bandgap reference circuit is used to directly output a reference current I with zero temperature drift. ref And output a zero-temperature-drift reference voltage V to OP0 ref By selectively connecting the CTAT voltage generation circuit and the PTAT voltage generation circuit to OP0 and adjusting R... adj The resistance value is such that the output of OP0 outputs a temperature reference voltage V with a specified temperature characteristic and slope value. tr .

3. The baseband amplifier with temperature compensation and DC offset elimination according to claim 2, characterized in that: In the gain temperature compensation circuit, the outputs of the CTAT voltage generation circuit and the PTAT voltage generation circuit are respectively connected to the two inputs of a 2-to-1 selector MUX, and the output of MUX is connected to the corresponding port of R0; then, the CTAT voltage generation circuit and the PTAT voltage generation circuit are selected by a 1-bit control code ctrl0. The variable resistor R adj A numerically controlled resistor array is used, and the resistance value is adjusted through a multi-bit control code Ctrl.

4. The baseband amplifier with temperature compensation and DC offset elimination according to claim 3, characterized in that: The methods for determining the code values ​​of Ctrl0 and Ctrl include: The slope values ​​of the temperature-reference voltage curves output by Ctrl0 and Ctrl under different values ​​in the gain temperature compensation circuit were determined by simulation; and the first mapping relationship between the two was established. Gain-temperature degradation curves were pre-tested under different ambient temperature conditions to determine the temperature reference voltage V that can compensate for it. tr The slope value changes with temperature, and a second mapping relationship is established between the two; Based on the gain-temperature degradation curve of any circuit measured at a specified process corner, the second mapping relationship and the first mapping relationship are queried to determine the code values ​​of Ctrl0 and Ctrl that can achieve the best compensation.

5. The baseband amplifier with temperature compensation and DC offset elimination according to claim 2, characterized in that: The CTAT voltage generation circuit includes three PMOS transistors M28, M29, and M32, two NMOS transistors M30 and M31, an NPN transistor Q3, and two resistors R8 and R9; the circuit connection is as follows: The sources of M28, M29, and M32 are connected to VDD; the drains of M28 and M30 are connected to the gates of M30 and M31; the gates of M28, M29, and M32 are connected to the drains of M29 and M31; the source of M30 is connected to the emitter of Q3; the source of M31 is connected to one end of R8; and the drain of M32 is connected to one end of R9, serving as the negative temperature coefficient voltage V. CTAT The output port of Q3; the base and collector of Q3 are connected to VSS at the other end of R8 and R9; And / or, the PTAT voltage generation circuit includes three PMOS transistors M33, M34, and M37, two NMOS transistors M35 and M36, two resistors R10 and R11, and NPN transistors Q4 and Q5; the ratio of Q4 to Q5 is 1:N2; the circuit connection is as follows: The sources of M33, M34, and M37 are connected to VDD; the drains of M33 and M35 are connected to the gates of M35 and M36; the gates of M33, M34, and M37 are connected to the drains of M34 and M36; the source of M35 is connected to the emitter of Q4; the source of M36 is connected to one end of R10, and the other end of R10 is connected to the emitter of Q5; the drain of M37 is connected to one end of R11 and serves as the positive temperature coefficient voltage V. PTAT The output port of Q4 and Q5; the base and collector of Q4 and Q5 are connected to the other end of R11 to VSS.

6. The baseband amplifier with temperature compensation and DC offset elimination according to claim 2, characterized in that: The bandgap reference circuit includes 6 PMOS transistors M19~M25, 2 NMOS transistors M26 and M27, 6 resistors R2~R7 and NPN transistors Q0~Q2; the ratio of Q1 to Q2 is N1:

1. The sources of M19~M24 are connected to VDD; the gates of M19~M23 are connected to the drain of M27 and the output of OP1; the gate and drain of M24 are connected to the source of M25; the drains of M25 and M26 are connected to the gate of M27; the gates of M25 and M26 are connected to one end of R2 and R5, the drain of M19, the inverting input of OP1, and the emitter of Q0; one end of R3, R4, and R6 is connected to the drain of M20 and the non-inverting input of OP1; the other end of R4 is connected to the emitter of Q1; the other ends of R5 and R6 are connected to the drain of M21 and the emitter of Q2; the drain of M22 is connected to one end of R7 and used to output VDD. ref The sources of M26 and M27, the other ends of R2, R3, and R7, and the collectors and bases of Q0, Q1, and Q2 are connected to VSS; the drain of M23 is used for output I. ref .

7. The baseband amplifier with temperature compensation and DC offset elimination according to claim 1, characterized in that: The resistor voltage divider network consists of resistors R18 and R19, with one end of R19 connected to V. LDO The other end is connected to one end of R18 and serves as V. CM The output port of R18; the other end of R18 is grounded.

8. The baseband amplifier with temperature compensation and DC offset elimination according to claim 1, characterized in that: The fully inverter-type amplifier includes a multi-stage transimpedance amplifier (TIA); in the DC offset cancellation circuit connected to each stage of the TIA, the values ​​of C1 and R17 are optimized to ensure the stability of the corresponding loop; And / or, the baseband amplifier includes a single-ended structure and a differential structure; The differential baseband amplifier includes two sets of mirrored fully inverting amplifiers and a DC offset cancellation circuit, as well as one less power supply circuit; And / or, the baseband amplifier further includes a low-pass filter connected between the input of the gain temperature compensation circuit and the Vref input port of the LDO to filter out ambient noise.

9. A millimeter-wave transceiver chip, characterized in that, It employs a baseband amplifier with temperature compensation and DC offset elimination as described in any one of claims 1-8.

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