Semiconductor device

Abstract

To provide a semiconductor device for reducing inclination or displacement of a terminal.SOLUTION: A semiconductor device includes a semiconductor chip 20, a first terminal, a case 30, and a second terminal. The semiconductor chip 20 has a first electrode and a second electrode. The first terminal is electrically connected to the first electrode of the semiconductor chip 20. The case 30 accommodates the semiconductor chip 20. Part of the first terminal is embedded in the case 30. The second terminal includes a conductive portion 52 electrically connected to the second electrode of the semiconductor chip 20 and a protruding portion 53 electrically insulated from the conductive portion 52. The first terminal includes a through hole 42 provided in a portion exposed from the case. The protruding portion 53 is inserted into the through hole 42.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The semiconductor device described in Patent Document 1 includes a resin case having a plurality of terminal holders formed therein, external terminals held by the terminal holders, and a terminal locking member fixed to the upper end of the resin case. The terminal locking member holds the external terminals so that they do not slip out of the upper end of the resin case. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-126682 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, the external terminals are inserted into the resin case and fixed in place with a terminal locking member. During the assembly process, if the external terminals held in the resin case are tilted, it is difficult to fit the terminal locking member onto the upper end of the resin case, which reduces workability.

[0005] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device that reduces tilt or misalignment of terminals. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a semiconductor chip, a first terminal, a case, and a second terminal. The semiconductor chip has a first electrode and a second electrode. The first terminal is electrically connected to the first electrode of the semiconductor chip. The case houses the semiconductor chip. A portion of the first terminal is embedded in the case. The second terminal includes a conductive portion electrically connected to the second electrode of the semiconductor chip and a protruding portion electrically insulated from the conductive portion. The first terminal includes a through hole provided in a portion exposed from the case. The protruding portion is inserted into the through hole. [Effects of the Invention]

[0007] According to the present disclosure, a semiconductor device is provided that reduces tilt or misalignment of terminals.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a side view showing the internal configuration of the semiconductor device. [Figure 3] FIG. 2 is a top view showing the internal wiring configuration of the semiconductor device; [Figure 4] FIG. 2 is a perspective view showing the configuration of a case. [Figure 5] FIG. 2 is a perspective view showing the configuration of an insert terminal and an outsert terminal. [Figure 6] 4A and 4B are cross-sectional views showing the configurations of an insert terminal and an outsert terminal. [Figure 7] FIG. 2 is a perspective view showing the configuration of an insert terminal. [Figure 8] FIG. 2 is a perspective view showing the configuration of an outsert terminal. [Figure 9] FIG. 2 is a perspective view showing the configuration of a protrusion and a through hole. [Figure 10] FIG. 2 is a diagram showing an equivalent circuit for one phase included in a three-level inverter. [Figure 11] FIG. 10 is a perspective view showing the configuration of an insert terminal and an outsert terminal in a second embodiment. [Figure 12] FIG. 11 is a perspective view showing the configuration of an insert terminal and an outsert terminal in a third embodiment. [Figure 13] 1A is a perspective view showing the configuration of an outsert terminal, FIG. 1B is a perspective view showing the configuration of an external connection end of the outsert terminal, and FIG. 1C is a perspective view showing the configuration of a hook portion. [Figure 14] FIG. 10 is a perspective view showing the configuration of an outsert terminal in a fourth embodiment. [Figure 15] FIG. 2 is a perspective view showing the configuration of a conductive portion of an outsert terminal. [Figure 16] FIG. 13 is a perspective view showing the configuration of an outsert terminal in a fifth embodiment. [Figure 17] FIG. 2 is a perspective view showing the configuration of a conductive portion and a protrusion of an outsert terminal. [Figure 18] 13 is a side view showing the configuration of an insert terminal and an outsert terminal in a sixth embodiment. FIG. [Figure 19] 13 is a side view showing the configuration of an insert terminal and an outsert terminal in a seventh embodiment. FIG. [Figure 20] 13 is a side view showing the configuration of an insert terminal and an outsert terminal in the eighth embodiment. FIG. [Figure 21] FIG. 13 is a perspective view showing the configuration of an insert terminal and an outsert terminal in a ninth embodiment. [Figure 22] FIG. 23 is a perspective view showing the configuration of an insert terminal and an outsert terminal in a tenth embodiment. [Figure 23] FIG. 23 is a perspective view showing the configuration of an insert terminal and an outsert terminal in an eleventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "rear" do not necessarily correspond to positions and directions in actual implementation.

[0011] Fig. 1 is a perspective view showing the configuration of a semiconductor device in embodiment 1. Fig. 2 is a side view showing the internal configuration of the semiconductor device. Fig. 3 is a top view showing the internal wiring configuration of the semiconductor device. The semiconductor device is, for example, a power module.

[0012] The semiconductor device includes an insulating substrate 10 with a conductive layer, a semiconductor chip 20 (semiconductor chip 21 and semiconductor chip 22 in FIG. 3 are collectively referred to as semiconductor chip 20), a case 30, an insert terminal 40 (first terminal), and an outsert terminal 50 (second terminal). In the first embodiment, a terminal with an insulating portion molded as a separate part from the case 30 is fixed to a predetermined position on the case 30, which is referred to as an "outsert," and the outsert terminal is referred to as an "outsert terminal."

[0013] Fig. 4 is a perspective view showing the configuration of case 30. Fig. 5 is a perspective view showing the configuration of insert terminal 40 and outsert terminal 50. Fig. 6 is a cross-sectional view showing the configuration of insert terminal 40 and outsert terminal 50. Fig. 7 is a perspective view showing the configuration of insert terminal 40. Fig. 8 is a perspective view showing the configuration of outsert terminal 50.

[0014] As shown in FIG. 6, the conductive layer-equipped insulating substrate 10 includes a conductive layer 11, an insulating layer 12, and a heat dissipation metal layer 13. The conductive layer 11 is provided on the upper surface of the heat dissipation metal layer 13, with the insulating layer 12 interposed therebetween. The insulating layer 12 is made of an insulating material such as ceramic or resin. The conductive layer 11 and the heat dissipation metal layer 13 are made of Cu, for example. As shown in FIG. 3, the conductive layer 11 includes a first circuit pattern 111 and a second circuit pattern 112. The first circuit pattern 111 has a connection portion 111A to which the insert terminal 40 is connected. The second circuit pattern 112 has a connection portion 112A to which the outsert terminal 50 is connected.

[0015] The semiconductor chip 20 has a first electrode (not shown) and a second electrode (not shown). The first electrode is electrically connected to a first circuit pattern 111. The second electrode is electrically connected to a second circuit pattern 112. The semiconductor chip 20 is a switching element chip 21 including switching elements 211-214, or a diode element chip 22 including diode elements 221-224.

[0016] When the semiconductor chip 20 includes IGBTs (Insulated Gate Bipolar Transistors) as the switching elements 211 to 214, the first electrode is one of the collector electrode, the emitter electrode, and the gate electrode, and the second electrode is one of the collector electrode, the emitter electrode, and the gate electrode that is different from the first electrode.

[0017] When the semiconductor chip 20 includes MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) as the switching elements 211 to 214, the first electrode is any one of the drain electrode, source electrode, and gate electrode, and the second electrode is any one of the drain electrode, source electrode, and gate electrode that is different from the first electrode.

[0018] When the semiconductor chip 20 includes the diode elements 221 to 224, the first electrode is either one of the cathode electrode or the anode electrode. The second electrode is either the cathode electrode or the anode electrode, which is different from the first electrode. The diode elements 221 to 224 may be SBDs (Schottky Barrier Diodes) or PNDs (PN junction diodes).

[0019] The semiconductor chip 20 may be an RC-IGBT (Reverse-Conducting IGBT) chip in which the IGBT and the diode elements 221 to 224 are provided within one chip.

[0020] As shown in FIGS. 2 and 4, the case 30 has a frame. The case 30 accommodates the conductive layer 11 of the conductive layer-equipped insulating substrate 10 and the semiconductor chip 20 inside the frame. The case 30 is bonded to the conductive layer-equipped insulating substrate 10 with an adhesive (not shown). The adhesive is, for example, a thermosetting resin-based adhesive primarily composed of epoxy resin, phenolic resin, or the like. Alternatively, the adhesive may be an organic adhesive primarily composed of silicone rubber. As shown in FIG. 1, a lid 36 is provided on the top of the case 30. The lid 36 is fixed to the case 30 with, for example, screws (not shown). An insert terminal 40, an outsert terminal 50, a C terminal 31, a P terminal 32, an N terminal 33, a C terminal 34, and an AC terminal 35, which are electrically connected to the semiconductor chip 20, are exposed from the top surfaces of the case 30 and the lid 36. The case 30 and the lid 36 are made of synthetic resin such as PPS (Polyphenylene Sulfide).

[0021] The insert terminal 40 is integrated with the case 30 and is produced by insert molding. As shown in FIGS. 5 to 7, a portion of the insert terminal 40 is embedded in the case 30 and the insert terminal 40 is fixed to the case 30. The insert terminal 40 is formed of a metal such as Al, Cu, or Au. The insert terminal 40 includes a protrusion 41, a through hole 42, an internal connection end 43, and an external connection end 44.

[0022] The protrusion 41 protrudes inward from the frame of the case 30 and is exposed from the case 30 .

[0023] The through hole 42 is provided in the protruding portion 41, that is, the portion exposed from the case 30.

[0024] The internal connection end portion 43 extends to the inside of the frame of the case 30. The internal connection end portion 43 is joined to the joining portion 111A of the first circuit pattern 111 shown in FIG. 3. That is, the insert terminal 40 is electrically connected to the first electrode of the semiconductor chip 20.

[0025] The external connection end 44 is exposed on the top surface of the case 30 and is configured to be connectable to an external circuit (not shown).

[0026] The outsert terminals 50 are held in the case 30. While the insert terminals 40 are molded integrally with the case 30, the outsert terminals 50 are not. For example, the case 30 shown in FIG. 4 has six insert terminals 40 formed integrally with the case 30. In the semiconductor device shown in FIG. 1, two outsert terminals 50 are inserted into the case 30, resulting in a total of eight terminals. As shown in FIG. 5, the outsert terminals 50 are inserted into and fixed in predetermined positions in the case 30. As shown in FIG. 8, the outsert terminals 50 include a conductive portion 51, an insulating portion 52, and a protruding portion 53.

[0027] The conductive portion 51 includes an internal connection end portion 51A and an external connection end portion 51B. The internal connection end portion 51A is joined to a joining portion 112A of the second circuit pattern 112 shown in FIG. 3 directly or via solder or the like. That is, the conductive portion 51 of the outsert terminal 50 is electrically connected to the second electrode of the semiconductor chip 20. The external connection end portion 51B is exposed on the upper surface of the insulating portion 52 and is configured to be connectable to an external circuit. The conductive portion 51 is formed of a metal such as Al, Cu, or Au.

[0028] The insulating portion 52 covers a portion of the conductive portion 51 and holds the conductive portion 51. In other words, a portion of the conductive portion 51 is embedded in the insulating portion 52. The outsert terminal 50 is a component formed so that the conductive portion 51 and the insulating portion 52 are integrated together. The insulating portion 52 is held by the case 30. The insulating portion 52 is formed of a synthetic resin such as PPS (Polyphenylene Sulfide), for example.

[0029] Protrusion 53 is electrically insulated from conductive portion 51. Protrusion 53 in the first embodiment is provided on insulating portion 52 and is made of the same insulator as insulating portion 52. Therefore, protrusion 53 is easily formed when conductive portion 51 and insulating portion 52 are molded to be integrated.

[0030] 9 is a perspective view showing the configuration of protrusion 53 and through hole 42. As shown in FIGS. 6 and 9, protrusion 53 of outsert terminal 50 is inserted into through hole 42 of insert terminal 40. Protrusion 53 is in direct contact with through hole 42. Specifically, the outer periphery of protrusion 53 is in contact with the inner surface of through hole 42.

[0031] Next, a method for manufacturing a semiconductor device will be described. First, the semiconductor chip 20 is electrically joined to the insulating substrate 10 with a conductive layer.

[0032] (1) The semiconductor chip 20 and the conductive layer 11 of the insulating substrate 10 with a conductive layer are connected by a bonding wire 25. This step is a wire bonding step.

[0033] (2) The case 30 and the insulating substrate 10 with a conductive layer are fixed together with an adhesive.

[0034] (3) The insert terminal 40 and the first circuit pattern 111 of the insulating substrate 10 with a conductive layer are joined.

[0035] (4) The protrusion 53 of the outsert terminal 50 is inserted into the through hole 42 of the insert terminal 40 .

[0036] (5) The outsert terminal 50 and the second circuit pattern 112 of the insulating substrate 10 with a conductive layer are joined.

[0037] The order of performing step (1) and steps (2) to (5) does not matter. If any of the insert terminals 40, outsert terminals 50, and case 30 covers bonding wire 25, it is preferable that the wire bonding step at least at that position be performed before steps (2) to (5).

[0038] Step (2) is preferably performed simultaneously with step (3) and step (5) or before step (3) and step (5). For example, if in step (2) the case 30 and the insulating substrate 10 with a thermosetting adhesive are joined together, and in steps (3) and (5) the terminals and the insulating substrate 10 with a solder are joined together, the adhesive is thermally cured and soldered in a single heating process.

[0039] Step (4) is performed before step (5). That is, the insertion of the protrusion 53 into the through hole 42 is performed before the internal connection end 51A of the outsert terminal 50 and the second circuit pattern 112 of the conductive layer-equipped insulating substrate 10 are joined together.

[0040] Next, a sealing material (not shown) is filled into the case 30. The sealing material seals the semiconductor chip 20, the first circuit pattern 111, the second circuit pattern 112, the bonding wires 25, and the internal connection ends 43, 51A inside the case 30. The sealing material is a resin.

[0041] Finally, the lid 36 is fixed to the case 30. In this manner, the semiconductor device shown in FIGS.

[0042] In the first embodiment, when the outsert terminal 50 is attached to the case 30, the protrusion 53 is inserted into the through hole 42. The insert terminal 40 having the through hole 42 is fixed to the case 30. This reduces tilt and misalignment of the outsert terminal 50. The internal connection end 51A of the outsert terminal 50 is stably joined to the second circuit pattern 112 of the insulating substrate 10 with a conductive layer.

[0043] To summarize the above, the semiconductor device in embodiment 1 includes a semiconductor chip 20, an insert terminal 40 (first terminal), a case 30, and an outsert terminal 50 (second terminal). The semiconductor chip 20 has a first electrode and a second electrode. The insert terminal 40 is electrically connected to the first electrode of the semiconductor chip 20. The case 30 houses the semiconductor chip 20. A portion of the insert terminal 40 is embedded in the case 30. The outsert terminal 50 includes a conductive portion 51 and a protrusion 53. The conductive portion 51 is electrically connected to the second electrode of the semiconductor chip 20. The protrusion 53 is electrically insulated from the conductive portion 51. The insert terminal 40 includes a through hole 42 provided in a portion exposed from the case 30. The protrusion 53 is inserted into the through hole 42.

[0044] This configuration reduces tilt or misalignment when bonding the outsert terminals 50 and the second circuit pattern 112. As a result, workability in the manufacturing process of the semiconductor device is improved. Bonding between the outsert terminals 50 and the conductive layer 11 is improved, and the reliability of the semiconductor device is also improved.

[0045] Furthermore, by reducing the tilt or misalignment when the outsert terminals 50 and the second circuit pattern 112 are joined, the joining area between the outsert terminals 50 and the second circuit pattern 112 is reduced, which allows the case 30 to be made smaller and allows for higher density mounting.

[0046] The present disclosure is effective for semiconductor devices including many control terminals, such as a power device for a three-level inverter. Alternatively, for example, it is possible to manufacture a power device for a three-level inverter by adding an outsert terminal 50 to the case 30 of a power device for a two-level inverter. In this case, the case 30 for the two-level inverter and the case 30 for the three-level inverter are made common.

[0047] Next, the circuit configuration of the semiconductor device and the configuration of the semiconductor chip 20 will be described in detail. As shown in Fig. 3, the semiconductor device includes a plurality of semiconductor chips 20. Each of the plurality of semiconductor chips 20 includes switching elements 211 to 214 or diode elements 221 to 224. Here, the semiconductor device is a three-level inverter. Fig. 10 is a diagram showing an equivalent circuit for one phase included in the three-level inverter.

[0048] 10 are IGBTs, but may also be MOSFETs. When the switching elements 211 to 214 are IGBTs, a collector electrode (positive electrode) is provided as a main electrode on the back surface of the semiconductor chip 20, and a gate electrode (control electrode) and an emitter electrode (negative electrode) are provided on the front surface of the semiconductor chip 20. When the switching elements 211 to 214 are MOSFETs, a drain electrode (positive electrode) is provided as a main electrode on the back surface of the semiconductor chip 20, and a gate electrode (control electrode) and a source electrode (negative electrode) are provided on the front surface of the semiconductor chip 20.

[0049] The diode elements 221 to 224 are connected in anti-parallel to the switching elements 211 to 214. In other words, the diode elements 221 to 224 are connected to the switching elements 211 to 214 so that the forward direction of the diode elements 221 to 224 is opposite to the direction in which a normal current flows in the switching elements 211 to 214. When the semiconductor chip 20 includes the diode elements 221 to 224, a cathode electrode is provided on the back surface of the semiconductor chip 20, and an anode electrode is provided on the front surface of the semiconductor chip 20.

[0050] The back surface of the semiconductor chip 20 is bonded to the first circuit pattern 111 or the second circuit pattern 112 by a bonding material. The bonding material is, for example, solder or a sintered body. The sintered body contains, for example, Ag or Cu.

[0051] The surface of the semiconductor chip 20 is electrically connected to the first circuit pattern 111 or the second circuit pattern 112 by a bonding wire 25. For example, one end of the bonding wire 25 is directly bonded to an electrode provided on the surface of the semiconductor chip 20, and the other end is directly bonded to the first circuit pattern 111 or the second circuit pattern 112. The first circuit pattern 111 is electrically connected to the insert terminal 40, and the second circuit pattern 112 is electrically connected to the outsert terminal 50. In FIG. 3, the connection points of the gate terminals (terminals G1 to G4), the emitter sense terminals (terminals Es1 to Es4), and the C terminals 31 and 34 are not shown. Note that if the emitter electrodes of different semiconductor chips 20 have approximately the same potential, it is not necessarily necessary to provide an emitter sense terminal for each, and a common terminal may be used. For example, in the equivalent circuit of FIG. 10, the emitter electrode of the switching element 2311 and the emitter electrode of the switching element 2321 are at approximately the same potential, so the emitter sense terminal may be configured as one common terminal.

[0052] (First Modification of First Embodiment) The semiconductor chip 20 in the first variation of the first embodiment includes an IGBT. The connection point 111A of the first circuit pattern 111 shown in FIG. 3 has approximately the same potential as the gate electrode. The connection point 112A of the second circuit pattern 112 has approximately the same potential as the emitter electrode. The internal connection end 43 of the insert terminal 40 is connected to the connection point 111A of the first circuit pattern 111. In other words, the first electrode electrically connected to the insert terminal 40 is the gate electrode. The internal connection end 51A of the outsert terminal 50 is connected to the connection point 112A of the second circuit pattern 112. In other words, the second electrode electrically connected to the outsert terminal 50 is the emitter electrode. As shown in FIG. 5, the outsert terminal 50 and the insert terminal 40 are disposed close to each other. This configuration reduces the magnetic flux passing through the gate-emitter loop. As a result, the potential fluctuation of the gate is reduced.

[0053] (Modification 2 of Embodiment 1) As in the first modification, the insert terminal 40 is electrically connected to the gate terminal, and the outsert terminal 50 is electrically connected to the emitter terminal. As shown in FIGS. 5 to 7, the insert terminal 40 and the conductive portion 51 of the outsert terminal 50 have a twisted positional relationship. That is, the conductive portion 51 of the outsert terminal 50 intersects with the insert terminal 40 in plan and side views. There may be two or more intersections. This configuration further reduces the magnetic flux passing through the loop.

[0054] (Third Modification of First Embodiment) 5, the internal connection end 43 of the insert terminal 40 and the internal connection end 51A of the outsert terminal 50 may be L-shaped. This increases the contact area between the internal connection end 43, 51A and the conductive layer 11, making bonding easier. This also increases bonding stability and reduces variations in bonding strength.

[0055] (Fourth Modification of First Embodiment) The conductive portion 51 of the outsert terminal 50 may be softer than the second circuit pattern 112. For example, by subjecting the outsert terminal 50 to an annealing treatment or the like, the outsert terminal 50 becomes softer than the second circuit pattern 112. Such an outsert terminal 50 absorbs misalignment caused by curvature or undulation of the conductive layer-equipped insulating substrate 10. As a result, the bond between the internal connection end portion 51A of the outsert terminal 50 and the second circuit pattern 112 is stabilized.

[0056] <Embodiment 2> FIG. 11 is a perspective view showing the configuration of the insert terminal 40 and the outsert terminal 50 according to the second embodiment.

[0057] The insert terminal 40 includes a plurality of protrusions 41 and a plurality of through holes 42. The protrusions 41 protrude into the inside of the case 30 and are exposed from the case 30. The through holes 42 are provided in the protrusions 41, i.e., the portions exposed from the case 30. The outsert terminal 50 includes a plurality of protrusions 53 electrically insulated from the conductive portion 51. The plurality of protrusions 53 are inserted into the plurality of through holes 42, respectively. The insertion manner is the same as in Figures 6 and 9.

[0058] This configuration further reduces tilt or misalignment of the outsert terminal 50. The internal connection end 51A of the outsert terminal 50 is stably joined to the second circuit pattern 112 of the conductive layer-equipped insulating substrate 10. As a result, for example, high-density packaging is achieved.

[0059] 2 or 4, the semiconductor device is provided with a plurality of insert terminals 40. Each of the plurality of insert terminals 40 may be provided with at least one through hole 42. Furthermore, the plurality of through holes 42 may be offset from one another in the height direction (up and down direction). In this case, the outsert terminal 50 has a shape corresponding to the shape of the insert terminal 40 into which the protrusion 53 is inserted. For example, each of the plurality of protrusions 53 has a configuration corresponding to the position (height) of each of the plurality of through holes 42.

[0060] <Third Embodiment> 12 is a perspective view showing the configuration of the insert terminal 40 and the outsert terminal 50 according to the third embodiment. FIG.

[0061] The outsert terminal 50 includes a hook portion 54 that hooks onto and is held in the case 30. The hook portion 54 is formed on the insulating portion 52 using, for example, the same material as the insulating portion 52. In this case, the hook portion 54 is formed when the outsert terminal 50 is molded.

[0062] This configuration further reduces tilt or misalignment of the outsert terminals 50 when bonding the internal connection end portions 51A and the second circuit pattern 112. As a result, more stable bonding and high-density mounting are achieved.

[0063] FIG. 13(b) is a perspective view showing the configuration of the outsert terminal 50. FIG. 13(c) is a perspective view showing the configuration of the hook portion 54. The outsert terminal 50 may have a configuration in which the external connection end portion 51B shown in FIG. 13(b) is combined with the hook portion 54 shown in FIG. 13(c). The hook portion 54 is fixed to the external connection end portion 51B with an adhesive or a screw. Alternatively, the hook portion 54 is sandwiched and fixed between the bent external connection end portion 51B and the insulating portion 52. Alternatively, the hook portion 54 is fixed by combining these fixing means.

[0064] <Fourth Embodiment> Fig. 14 is a perspective view showing the configuration of an outsert terminal 50 according to the fourth embodiment. Fig. 15 is a perspective view showing the configuration of a conductive portion 51 of the outsert terminal 50.

[0065] The outsert terminal 50 includes a plurality of internal connection end portions 51 A. The plurality of internal connection end portions 51 A are joined to the second circuit pattern 112, as in the other embodiments.

[0066] This configuration further reduces tilt or misalignment of the outsert terminal 50 when bonding the internal connection end portion 51A and the second circuit pattern 112. As a result, a more stable bond is achieved.

[0067] <Fifth Embodiment> Fig. 16 is a perspective view showing the configuration of outsert terminal 50 in embodiment 5. Fig. 17 is a perspective view showing the configuration of conductive portion 51 and protrusion 53 of outsert terminal 50.

[0068] The protrusion 53 is formed of a highly rigid metal such as Cu, and is electrically insulated from the conductive portion 51 by the insulating portion 52.

[0069] Because protrusion 53 is made of metal, it has a certain strength. When protrusion 53 is inserted into through-hole 42 or when outsert terminal 50 is joined to second circuit pattern 112, damage to protrusion 53 due to stress or the like is prevented, improving assembly efficiency.

[0070] <Sixth Embodiment> FIG. 18 is a side view showing the configuration of insert terminal 40 and outsert terminal 50 according to the sixth embodiment.

[0071] The protrusion 53 of the outsert terminal 50 is formed facing upward. The protrusion 53 is inserted into the through-hole 42 of the insert terminal 40 from below the through-hole 42. The insulating portion 52 of the outsert terminal 50 contacts the underside of the insert terminal 40 at at least one point. In FIG. 18 , the insulating portion 52 contacts the underside of the protrusion 41 where the through-hole 42 of the insert terminal 40 is formed.

[0072] The step of inserting the protrusion 53 into the through hole 42 is performed before the step of bonding the internal connection end 51A of the outsert terminal 50 to the second circuit pattern 112. After the protrusion 53 is inserted into the through hole 42, the second circuit pattern 112 is pressed against the underside of the internal connection end 51A. At this time, the outsert terminal 50 receives forces from above and below by the protrusion 41 of the insert terminal 40 and the insulating substrate 10 with a conductive layer. In this state, the internal connection end 51A is bonded to the second circuit pattern 112. The internal connection end 51A may be bonded to the second circuit pattern 112 directly or via a bonding material (not shown) such as solder. The forces applied from above and below during bonding stabilize the outsert terminal 50, reducing variations in bonding strength.

[0073] <Seventh Embodiment> FIG. 19 is a side view showing the configuration of insert terminal 40 and outsert terminal 50 according to the seventh embodiment.

[0074] Outsert terminal 50 includes conductive portion 51, insulating portion 52, and recess 55. Recess 55 is electrically insulated from conductive portion 51. In the seventh embodiment, recess 55 is formed in insulating portion 52. Therefore, recess 55 is easily formed when outsert terminal 50 is molded.

[0075] The insert terminal 40 includes a protruding portion 41 that protrudes from the case 30. The protruding portion 41 is inserted into a recessed portion 55 of the outsert terminal 50. The protruding portion 41 contacts the outsert terminal 50 at least at one point.

[0076] The step of inserting the protrusion 41 into the recess 55 is performed before the step of bonding the internal connection end 51A of the outsert terminal 50 to the second circuit pattern 112. After the protrusion 41 is inserted into the recess 55, the second circuit pattern 112 is pressed against the underside of the internal connection end 51A. At this time, the bottom surface of the recess 55 of the outsert terminal 50 is pressed against the underside of the protrusion 41 of the insert terminal 40. In this state, the internal connection end 51A is bonded to the second circuit pattern 112. The internal connection end 51A may be bonded to the second circuit pattern 112 directly or via a bonding material (not shown) such as solder. The outsert terminal 50 is stabilized by forces applied from above and below during bonding, reducing variation in bonding strength.

[0077] <Embodiment 8> FIG. 20 is a side view showing the configuration of insert terminal 40 and outsert terminal 50 according to the eighth embodiment.

[0078] The recess 55 of the outsert terminal 50 is formed upward from the lower surface of the insulating portion 52. The recess 55 is electrically insulated from the conductive portion 51. The recess 55 of the eighth embodiment is formed in the insulating portion 52. Therefore, the recess 55 is easily formed when the outsert terminal 50 is molded.

[0079] The tip of the protrusion 41 of the insert terminal 40 is formed to face upward and is inserted into the recess 55 of the outsert terminal 50.

[0080] The step of inserting the protrusion 41 into the recess 55 is performed before the step of bonding the internal connection end 51A of the outsert terminal 50 to the second circuit pattern 112. After the protrusion 41 is inserted into the recess 55, the internal connection end 51A is bonded to the second circuit pattern 112. The internal connection end 51A may be bonded to the second circuit pattern 112 directly or via a bonding material (not shown) such as solder. During bonding, tilt or misalignment of the outsert terminal 50 is further reduced. As a result, a more stable bond is achieved.

[0081] <Ninth Embodiment> FIG. 21 is a perspective view showing the configuration of the insert terminal 40 and the outsert terminal 50 according to the ninth embodiment.

[0082] The insert terminal 40 includes a plurality of protrusions 41 and a plurality of through holes 42. The protrusions 41 protrude inward from the case 30 and are exposed from the case 30. The through holes 42 are provided in the protrusions 41, i.e., in the portions exposed from the case 30.

[0083] Outsert terminal 50 includes conductive portion 51, insulating portion 52, and multiple protrusions 53. Multiple protrusions 53 are inserted into multiple through holes 42 of insert terminal 40, respectively. The insertion manner is the same as in FIGS. 6 and 9.

[0084] The conductive portion 51 includes an external connection end portion 51B and a wire bond area 51C. The wire bond area 51C is provided on the upper surface of the insulating portion 52. The wire bond area 51C may be formed, for example, as an integral part with the external connection end portion 51B. Alternatively, the wire bond area 51C may be formed as a separate part from the external connection end portion 51B and electrically connected to the external connection end portion 51B. The wire bond area 51C is electrically insulated from the protrusion portion 53 of the outsert terminal 50.

[0085] The wire bond area 51C is electrically connected to one or more of the conductive layer 11 of the conductive layer-equipped insulating substrate 10, the surface electrodes of the switching elements 211-214, and the surface electrodes of the diode elements 221-224 by bonding wires 25 (not shown).

[0086] The semiconductor device of the ninth embodiment may have the following connection configuration: The first circuit pattern 111 is electrically connected to one of the collector electrode, the emitter electrode, and the gate electrode of the semiconductor chip 20. The insert terminal 40 is electrically connected to the first circuit pattern 111.

[0087] The wire bond area 51C is electrically connected by a bonding wire 25 to an electrode different from the gate electrode or emitter electrode of the semiconductor chip 20 that is electrically connected to the first circuit pattern 111. For example, one end of the bonding wire 25 is directly bonded to the wire bond area 51C, and the other end is directly bonded to an electrode different from the electrode of the semiconductor chip 20 that is electrically connected to the first circuit pattern 111.

[0088] Such a connection configuration using bonding wires 25 reduces the influence of curvature or undulation of the conductive layer-equipped insulating substrate 10. Assembly, such as electrical connection, becomes easier.

[0089] Furthermore, since the multiple protrusions 53 are inserted into the multiple through holes 42, tilt or misalignment of the outsert terminal 50 is further reduced. Because the outsert terminal 50 is firmly fixed, it is possible to apply a stronger force when wire bonding to the outsert terminal 50. For example, a bonding wire 25 made of a harder material can be stably bonded. This increases the options for the wire bonding process.

[0090] <Tenth Embodiment> FIG. 22 is a perspective view showing the configuration of the insert terminal 40 and the outsert terminal 50 according to the tenth embodiment.

[0091] In addition to the configuration of the ninth embodiment, the outsert terminal 50 includes a hook portion 54. The hook portion 54 is hooked onto and held in the case 30. The other configurations are the same as those of the ninth embodiment.

[0092] The hook portion 54 more firmly fixes the outsert terminal 50 to the case 30. This allows wire bonding to the outsert terminal 50 with a stronger force. As in the ninth embodiment, for example, a bonding wire 25 made of a harder material can be stably bonded. This increases the options for the wire bonding process.

[0093] <Embodiment 11> FIG. 23 is a perspective view showing the configuration of the insert terminal 40 and the outsert terminal 50 according to the eleventh embodiment.

[0094] Outsert terminal 50 includes support pillar 56 in addition to conductive portion 51, insulating portion 52, and protrusion 53. Support pillar 56 is electrically insulated from conductive portion 51, including wire bond area 51C. The bottom surface of support pillar 56 contacts conductive layer 11 or insulating layer 12 of conductive-layer-equipped insulating substrate 10. In other words, support pillar 56 contacts conductive-layer-equipped insulating substrate 10. The other configurations are the same as those of embodiment 9.

[0095] Because the support posts 56 are in contact with the insulating substrate 10 with a conductive layer, it is possible to apply a stronger force to wire bond to the outsert terminal 50. As in the ninth embodiment, for example, a bonding wire 25 made of a harder material can be stably bonded. This increases the options available in the wire bonding process.

[0096] <Embodiment 12> The semiconductor chip 20 is a power semiconductor chip. The switching elements 211 to 214 or the diode elements 221 to 224 may be formed of a normal semiconductor such as silicon (Si), or may be formed of a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond.

[0097] When the semiconductor chip 20 is made of a wide bandgap semiconductor, stable operation under high temperature and high voltage conditions, high switching speed, and miniaturization of the semiconductor device are achieved.

[0098] In the present disclosure, the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0099] Various aspects of the present disclosure are summarized below as appendices.

[0100] (Appendix 1) a semiconductor chip having a first electrode and a second electrode; a first terminal electrically connected to the first electrode of the semiconductor chip; a case that houses the semiconductor chip and in which a portion of the first terminal is embedded; a second terminal including a conductive portion electrically connected to the second electrode of the semiconductor chip and a protruding portion electrically insulated from the conductive portion; the first terminal includes a through hole provided in a portion exposed from the case, The protrusion is inserted into the through hole.

[0101] (Appendix 2) a first circuit pattern electrically connected to the first terminal and the first electrode of the semiconductor chip; a second circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip, the first electrode is any one of a collector electrode, an emitter electrode, and a gate electrode of the semiconductor chip; 2. The semiconductor device according to claim 1, wherein the second electrode is one of the collector electrode, the emitter electrode, and the gate electrode of the semiconductor chip that is different from the first electrode.

[0102] (Appendix 3) a circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip; the second terminal includes a connecting end joined to the circuit pattern, 3. The semiconductor device according to claim 1, wherein the connection end portion has an L-shape.

[0103] (Appendix 4) the first electrode of the semiconductor chip is a gate electrode, the second electrode of the semiconductor chip is an emitter electrode, 4. The semiconductor device according to claim 1, wherein the first terminal and the second terminal are disposed adjacent to each other.

[0104] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the conductive portion of the second terminal intersects with the first terminal at least at one point in at least one of a plan view and a side view.

[0105] (Appendix 6) a circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip; 6. The semiconductor device according to claim 1, wherein the conductive portion of the second terminal is softer than the circuit pattern.

[0106] (Appendix 7) the first terminal includes a plurality of through holes provided in a portion exposed from the case, the second terminal includes a plurality of protrusions electrically insulated from the conductive portion; 7. The semiconductor device according to claim 1, wherein the plurality of protrusions are inserted into the plurality of through holes, respectively.

[0107] (Appendix 8) 8. The semiconductor device according to claim 1, wherein the second terminal includes a hook portion that is hooked onto and held by the case.

[0108] (Appendix 9) a circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip, 9. The semiconductor device according to claim 1, wherein the second terminal includes a plurality of connection ends joined to the circuit pattern.

[0109] (Appendix 10) 10. The semiconductor device according to claim 1, wherein the protrusion is made of metal.

[0110] (Appendix 11) the second terminal includes an insulating portion that covers a portion of the conductive portion and is held by the case; the protrusion is formed facing upward and inserted into the through hole from below the through hole, 11. The semiconductor device according to claim 1, wherein the insulating portion is in contact with a lower surface of the first terminal at least at one point.

[0111] (Appendix 12) a semiconductor chip having a first electrode and a second electrode; a first terminal electrically connected to the first electrode of the semiconductor chip; a case that houses the semiconductor chip and in which a portion of the first terminal is embedded; a second terminal including a conductive portion electrically connected to the second electrode of the semiconductor chip and a recessed portion electrically insulated from the conductive portion; the first terminal includes a protrusion that protrudes from the case, The protrusion is inserted into the recess and is in contact with the second terminal at least at one point.

[0112] (Appendix 13) A semiconductor chip; a conductive layer electrically connected to one of a collector electrode, an emitter electrode, and a gate electrode of the semiconductor chip; a first terminal electrically connected to the conductive layer; a case that houses the semiconductor chip and in which a portion of the first terminal is embedded; a second terminal including a wire bond area and a protrusion electrically isolated from the wire bond area; the first terminal includes a through hole provided in a portion exposed from the case, the protrusion is inserted into the through hole, A semiconductor device, wherein the wire bond area is electrically connected by a bonding wire to a circuit pattern different from the conductive layer, or to an electrode different from the gate electrode or the emitter electrode of the semiconductor chip that is electrically connected to the conductive layer.

[0113] (Appendix 14) the first terminal includes a plurality of through holes provided in a portion exposed from the case, the second terminal includes a plurality of protrusions electrically isolated from the wire bond area; 14. The semiconductor device according to claim 13, wherein the plurality of protrusions are inserted into the plurality of through holes, respectively.

[0114] (Appendix 15) 15. The semiconductor device according to claim 13, wherein the second terminal includes a hook portion that is hooked onto and held by the case.

[0115] (Appendix 16) a conductive layer-attached insulating substrate that includes the circuit pattern and holds the semiconductor chip; the second terminal includes a post electrically isolated from the wire bond area; 16. The semiconductor device according to claim 13, wherein the support pillar is in contact with the insulating substrate with a conductive layer.

[0116] (Appendix 17) 17. The semiconductor device according to claim 1, wherein the semiconductor chip includes a power semiconductor chip formed of a wide bandgap semiconductor. [Explanation of symbols]

[0117] 10 insulating substrate with conductive layer, 11 conductive layer, 12 insulating layer, 13 heat dissipation metal layer, 20 semiconductor chip, 21 switching element chip, 22 diode element chip, 25 bonding wire, 30 case, 31 C terminal, 32 P terminal, 33 N terminal, 34 C terminal, 35 AC terminal, 40 insert terminal, 41 protrusion, 42 through hole, 43 internal connection end, 44 external connection end, 50 outsert terminal, 51 conductive portion, 51A internal connection end, 51B external connection end, 51C wire bond area, 52 insulating portion, 53 protrusion, 54 hook portion, 55 recess, 56 support, 111 first circuit pattern, 111A joint portion, 112 second circuit pattern, 112A joint portion, 211 to 214 switching elements, 221 to 224 diode elements.

Claims

1. a semiconductor chip having a first electrode and a second electrode; a first terminal electrically connected to the first electrode of the semiconductor chip; a case that houses the semiconductor chip and in which a portion of the first terminal is embedded; a second terminal including a conductive portion electrically connected to the second electrode of the semiconductor chip and a protruding portion electrically insulated from the conductive portion; the first terminal includes a through hole provided in a portion exposed from the case, The protrusion is inserted into the through hole.

2. a first circuit pattern electrically connected to the first terminal and the first electrode of the semiconductor chip; a second circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip, the first electrode is any one of a collector electrode, an emitter electrode, and a gate electrode of the semiconductor chip; 2. The semiconductor device according to claim 1, wherein said second electrode is one of said collector electrode, said emitter electrode and said gate electrode of said semiconductor chip, which is different from said first electrode.

3. a circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip; the second terminal includes a connecting end portion joined to the circuit pattern, The semiconductor device according to claim 1 , wherein said connection end portion has an L-shape.

4. the first electrode of the semiconductor chip is a gate electrode, the second electrode of the semiconductor chip is an emitter electrode, The semiconductor device according to claim 1 , wherein the first terminal and the second terminal are disposed adjacent to each other.

5. The semiconductor device according to claim 1 , wherein the conductive portion of the second terminal intersects with the first terminal at least at one point in at least one of a plan view and a side view.

6. a circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip; The semiconductor device according to claim 1 , wherein the conductive portion of the second terminal is softer than the circuit pattern.

7. the first terminal includes a plurality of through holes provided in a portion exposed from the case, the second terminal includes a plurality of protrusions electrically insulated from the conductive portion; The semiconductor device according to claim 1 , wherein the plurality of protrusions are inserted into the plurality of through holes, respectively.

8. The semiconductor device according to claim 1 , wherein the second terminal includes a hook portion that is hooked onto and held by the case.

9. a circuit pattern electrically connected to the second terminal and the second electrode of the semiconductor chip, The semiconductor device according to claim 1 , wherein the second terminal includes a plurality of connection ends joined to the circuit pattern.

10. The semiconductor device according to claim 1 , wherein said protrusion is made of metal.

11. the second terminal includes an insulating portion that covers a portion of the conductive portion and is held by the case; the protrusion is formed facing upward and inserted into the through hole from below the through hole, The semiconductor device according to claim 1 , wherein the insulating portion is in contact with the lower surface of the first terminal at least at one point.

12. a semiconductor chip having a first electrode and a second electrode; a first terminal electrically connected to the first electrode of the semiconductor chip; a case that houses the semiconductor chip and in which a portion of the first terminal is embedded; a second terminal including a conductive portion electrically connected to the second electrode of the semiconductor chip and a recessed portion electrically insulated from the conductive portion; the first terminal includes a protrusion protruding from the case, The protrusion is inserted into the recess and is in contact with the second terminal at least at one point.

13. A semiconductor chip; a conductive layer electrically connected to one of a collector electrode, an emitter electrode, and a gate electrode of the semiconductor chip; a first terminal electrically connected to the conductive layer; a case that houses the semiconductor chip and in which a portion of the first terminal is embedded; a second terminal including a wire bond area and a protrusion electrically isolated from the wire bond area; the first terminal includes a through hole provided in a portion exposed from the case, the protrusion is inserted into the through hole, A semiconductor device, wherein the wire bond area is electrically connected by a bonding wire to a circuit pattern different from the conductive layer, or to an electrode different from the gate electrode or the emitter electrode of the semiconductor chip that is electrically connected to the conductive layer.

14. the first terminal includes a plurality of through holes provided in a portion exposed from the case, the second terminal includes a plurality of protrusions electrically isolated from the wire bond area; The semiconductor device according to claim 13 , wherein the plurality of protrusions are inserted into the plurality of through holes, respectively.

15. The semiconductor device according to claim 13 , wherein the second terminal includes a hook portion that is hooked onto and held by the case.

16. a conductive layer-attached insulating substrate that includes the circuit pattern and holds the semiconductor chip; the second terminal includes a post electrically isolated from the wire bond area; The semiconductor device according to claim 13 , wherein the support pillar is in contact with the insulating substrate with a conductive layer.

17. 14. The semiconductor device according to claim 1, wherein the semiconductor chip includes a power semiconductor chip formed of a wide bandgap semiconductor.

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