Semiconductor device

Abstract

SOLUTION: A semiconductor device has a diode portion. The semiconductor device includes a drift region of a first conductivity type provided in a semiconductor substrate, a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, and a front surface electrode portion provided above the front surface of the semiconductor substrate, in which the diode portion has a plug region of a second conductivity type provided in the semiconductor substrate and in contact with the front surface electrode portion, and a first conductivity type mesa region of a first conductivity type in contact with the plug region in a mesa portion between the plurality of trench portions.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A diode portion having a P-type anode region is known (see, for example, Patent Documents 1 and 2). Patent Document 1: International Publication No. 2015 / 050262 Patent Document 2: JP 2023-172272 A Summary of the Invention

[0003] A first aspect of the present invention provides a semiconductor device including a diode portion, the semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trenches extending in a predetermined trench extension direction on a front surface side of the semiconductor substrate; and a front surface electrode portion provided above the front surface of the semiconductor substrate. The diode portion may include a plug region of a second conductivity type provided in the semiconductor substrate and in contact with the front surface electrode portion, and a first conductivity type mesa region of the first conductivity type in a mesa portion between the plurality of trenches and in contact with the plug region.

[0004] In the above semiconductor device, the first conductivity type mesa region may be the drift region.

[0005] In any of the above semiconductor devices, the first conductivity type mesa region may have a doping concentration higher than that of the drift region.

[0006] In any of the above semiconductor devices, the front surface electrode portion may have a trench contact portion extending from the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0007] In any of the above semiconductor devices, the plug region may cover the side and bottom surfaces of the trench contact portion at a depth position deeper than the front surface of the semiconductor substrate.

[0008] In any of the above semiconductor devices, the plug region may cover a part of a side surface and a bottom surface of the trench contact portion at a depth deeper than the front surface of the semiconductor substrate, and the trench contact portion may form a Schottky junction with the first conductivity type mesa region at the side surface.

[0009] In any of the above semiconductor devices, the plug region may contact adjacent trench portions among the plurality of trench portions.

[0010] Any of the above semiconductor devices may include a trench bottom region that contacts a bottom end of at least one of the plurality of trench portions.

[0011] In any of the above semiconductor devices, the trench bottom region may be of the second conductivity type.

[0012] Any of the above semiconductor devices may include a transistor section, and the trench bottom region may be provided in the transistor section, but not in the diode section.

[0013] In any of the above semiconductor devices, the trench bottom region may be of the first conductivity type.

[0014] In any of the above semiconductor devices, the trench portion provided in the diode portion among the plurality of trench portions may have a first trench width at a predetermined depth position in the semiconductor substrate, and a second trench width that is larger than the first trench width at a position deeper than the depth position of the first trench width.

[0015] In any of the above semiconductor devices, the distance between two adjacent trench portions at the closest depth positions may be 0.1 μm or more and 0.5 μm or less.

[0016] In any of the above semiconductor devices, a mesa width of a mesa portion between the plurality of trench portions may be smaller than a trench width of the plurality of trench portions.

[0017] In any of the above semiconductor devices, the mesa width of the mesa portion between the plurality of trench portions may be not less than 0.2 μm and not more than 0.5 μm.

[0018] In any of the above semiconductor devices, the front surface electrode portion may have a silicide layer in contact with the plug region.

[0019] In any of the above semiconductor devices, the front surface electrode portion may have a barrier metal portion in contact with the silicide layer, and the front surface electrode portion may have a plug portion provided inside the barrier metal portion in the contact hole.

[0020] In any of the above semiconductor devices, a barrier height between the front surface electrode portion and the semiconductor substrate may be 0.6 eV or more and 1.0 eV or less.

[0021] Any of the above semiconductor devices may include a transistor section. The transistor section may include a base region of a second conductivity type provided above the drift region. The transistor section may include an emitter region of a first conductivity type provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. The transistor section may include a plurality of contact regions of a second conductivity type provided above the drift region and having a doping concentration higher than that of the base region.

[0022] In any of the above semiconductor devices, the mesa width of the diode section may be smaller than the mesa width of the transistor section.

[0023] In any of the above semiconductor devices, the transistor section may have a main region and a boundary region that is more adjacent to the diode section than the main region.

[0024] In any of the above semiconductor devices, the boundary region may not have the base region in a region where a contact hole for connecting the semiconductor substrate and the front surface electrode portion is provided.

[0025] In any of the above semiconductor devices, the boundary region may have a first boundary mesa portion that does not include the base region in a region where a contact hole for connecting the semiconductor substrate and the front-surface electrode portion is provided, and the boundary region may have a second boundary mesa portion that is provided closer to the main region than the first boundary mesa portion and that includes the base region in a region where a contact hole for connecting the semiconductor substrate and the front-surface electrode portion is provided.

[0026] Any of the above semiconductor devices may include an interlayer insulating film provided above the semiconductor substrate. Any of the above semiconductor devices may include a second conductivity type well region provided in the semiconductor substrate. The base region may extend from an end of the well region toward an end of a contact hole provided in the interlayer insulating film in the trench extension direction. A distance L0 between the base region and an end of the contact hole in the trench extension direction may be greater than 0 μm and within a width Wd of a depletion layer spreading from the base region toward the drift region.

[0027] A second aspect of the present invention provides a semiconductor device including a transistor portion and a diode portion, the semiconductor device including: a first conductivity type drift region provided in a semiconductor substrate; a plurality of trenches extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; and a front surface electrode portion provided above the front surface of the semiconductor substrate. The transistor portion may have a main region and a boundary region that is more adjacent to the diode portion than the main region. The main region may include a second conductivity type base region provided above the drift region. The boundary region may not include the base region in an area where a contact hole for connecting the semiconductor substrate and the front surface electrode portion is provided.

[0028] In any of the above semiconductor devices, the first conductivity type region of the boundary region may occupy 50% or more of a mesa portion at a depth shallower than a lower end of the base region.

[0029] In any of the above semiconductor devices, the diode section may have an anode region of a second conductivity type provided above the drift region.

[0030] A third aspect of the present invention provides a semiconductor device including a diode section. The semiconductor device may include a first conductivity type drift region provided in a semiconductor substrate, a plurality of trench sections extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, and a front surface electrode section provided above the front surface of the semiconductor substrate. The diode section may have a first conductivity type mesa region of the first conductivity type provided in a mesa section between the plurality of trench sections. The front surface electrode section may form a Schottky junction with the first conductivity type mesa region.

[0031] In any of the above semiconductor devices, the front surface electrode portion may cover the upper sides of the plurality of trench portions and the upper sides of the plurality of mesa portions between the plurality of trench portions in the diode portion, and may be in contact with the plurality of trench portions and the plurality of mesa portions.

[0032] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0033] [Figure 1] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 2A] FIG. 2 is an enlarged view of an area A in FIG. [Figure 2B] FIG. 2B is a diagram showing an example of an XZ cross section including the aa' cross section in FIG. 2A. [Figure 2C]FIG. 2B is a diagram showing an example of an XZ cross section including the bb' cross section in FIG. 2A. [Figure 2D] 10 is an enlarged view of an XZ cross section passing through a mesa portion 81. FIG. [Figure 2E] 2B shows an example of a YZ cross section including the cc' cross section in FIG. 2A. [Figure 3A] 10 is an enlarged view of a modified example of an XZ cross section passing through a mesa portion 81. FIG. [Figure 3B] 10 is an enlarged view of a modified example of an XZ cross section passing through a mesa portion 81. FIG. [Figure 4A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 4B] FIG. 4B is a diagram showing an example of an XZ cross section including the dd' cross section in FIG. 4A. [Figure 5A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 5B] FIG. 5B is a diagram showing an example of an XZ cross section including the ee' cross section in FIG. 5A. [Figure 6A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 6B] FIG. 6B is a diagram showing an example of an XZ cross section including the ff' cross section in FIG. 6A. [Figure 7A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 7B] FIG. 7B is a diagram showing an example of an XZ cross section including the gg' cross section in FIG. 7A. [Figure 7C] FIG. 7B is a diagram showing an example of an XZ cross section including the hh' cross section in FIG. 7A. [Figure 8A] 2B is a diagram showing a modified example of the XZ cross section including the aa' cross section in FIG. 2A. FIG. [Figure 8B] 2B is a diagram showing a modified example of the XZ cross section including the aa' cross section in FIG. 2A. FIG. [Figure 8C] 2B is a diagram showing a modified example of the XZ cross section including the aa' cross section in FIG. 2A. FIG. [Figure 9] 10 is an enlarged view of a modified example of an XZ cross section passing through a mesa portion 81. FIG. [Figure 10A] 10 is an enlarged view of a modified example of an XZ cross section passing through a mesa portion 81. FIG. [Figure 10B] 10 is a modified example of an XZ cross section passing through the mesa portion 81. FIG. [Figure 11A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 11B] FIG. 11B is a diagram showing an example of an XZ cross section including the ii' cross section in FIG. 11A. [Figure 12A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 12B] FIG. 12B is a diagram showing an example of an XZ cross section including the j-j' cross section in FIG. 12A. [Figure 13A] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 13B] FIG. 13B is a diagram showing an example of an XZ cross section including the k-k' cross section in FIG. 13A. [Figure 14] 1 is an example of a cross-sectional view of a semiconductor device 100. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0034] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0035] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0036] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0037] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0038] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0039] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0040] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0041] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0042] As used herein, chemical concentration refers to the atomic density of impurities measured regardless of their electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. Carriers refer to charge carriers, such as electrons or holes. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0043] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0044] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. A decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystalline structure caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, spreading resistance is measured and the carrier concentration is calculated from the measured spreading resistance. The carrier mobility used here is the mobility in the crystalline state. On the other hand, at locations where lattice defects are introduced, the carrier mobility is decreased, but the carrier concentration is calculated using the carrier mobility in the crystalline state. Therefore, the value obtained is lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0045] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of their chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is used. In this specification, distance and length may be expressed in centimeters (cm). In this case, various calculations may be performed by converting to meters (m). Regarding numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 16 The display of 1E-16 indicates 1 x 10 -16 Shows.

[0046] FIG. 1 shows an example of a top view of a semiconductor device 100. In FIG. 1, the positions of each component projected onto the top surface of a semiconductor substrate 10 are shown. In FIG. 1, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80.

[0047] The transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode section 80 includes a diode such as a free wheel diode (FWD). The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT) that has the transistor section 70 and the diode section 80 on the same chip.

[0048] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a diamond substrate, a nitride semiconductor substrate such as gallium nitride, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate. The semiconductor substrate 10 in this example is a silicon substrate. The semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0049] The semiconductor substrate 10 has end edges 102 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of end edges 102 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to one of the end edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has an active region 160 and an edge termination structure 170.

[0050] The active region 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 during operation of the semiconductor device 100. An emitter electrode is provided above the active region 160, but is not shown in FIG.

[0051] At least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD) is provided in the active region 160. In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10.

[0052] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0053] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10.

[0054] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0055] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0056] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of the gate trench portion of the active region 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 112 and the gate trench portion.

[0057] The gate wiring 130 is electrically connected to the gate conductive portion of the transistor portion 70 and applies a gate voltage to the transistor portion 70. The gate wiring 130 is provided so as to surround the outer periphery of the active region 160 in a top view. The gate wiring 130 is electrically connected to a gate pad 112 provided in the edge termination structure portion 170.

[0058] The semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting unit (not shown) which simulates the operation of a transistor unit provided in the active region 160.

[0059] In the present example, the semiconductor device 100 includes an edge termination structure 170 between the active region 160 and the edge 102 when viewed from above. The edge termination structure 170 in the present example is disposed between the gate wiring 130 and the edge 102. The edge termination structure 170 reduces electric field concentration on the top surface side of the semiconductor substrate 10. The edge termination structure 170 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active region 160.

[0060] 2A is an enlarged view of region A in Fig. 1. Region A is a region including the transistor section 70, the diode section 80, and the gate wiring 130. In this example, the gate wiring 130 includes a gate metal layer 50 and a gate runner section 51.

[0061] The transistor section 70 has a main region 75 and a boundary region 90. The boundary region 90 is provided on the front surface 21 of the semiconductor substrate 10 between the main region 75 of the transistor section 70 and the diode section 80. The front surface 21 of the semiconductor substrate 10 refers to one of two opposing main surfaces of the semiconductor substrate 10. The front surface 21 will be described later.

[0062] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 17, an emitter region 12, a base region 14, and a contact region 15 formed inside the front surface 21 side of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0063] An interlayer insulating film is formed between emitter electrode 52 and gate metal layer 50 and front surface 21 of semiconductor substrate 10, but the interlayer insulating film is omitted in Fig. 2A. In this example, contact holes 54, 55, and 56 are formed in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0064] The emitter electrode 52 is electrically connected to the emitter region 12, the contact region 15, and the base region 14 on the front surface 21 of the semiconductor substrate 10 through a contact hole 54 opened in the interlayer insulating film. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion.

[0065] The gate metal layer 50 contacts the gate runner portion 51 through the contact hole 55. The gate runner portion 51 is formed of a semiconductor such as polysilicon doped with impurities. The gate runner portion 51 is connected to a gate conductive portion in the gate trench portion 40 on the front surface 21 of the semiconductor substrate 10.

[0066] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound below the region made of aluminum or the like. Each electrode may further have a plug formed by embedding tungsten or the like in a contact hole so as to contact the barrier metal and aluminum or the like.

[0067] The well region 17 is provided so as to overlap the gate metal layer 50 and the gate runner portion 51. The well region 17 is also provided so as to extend by a predetermined width into an area where it does not overlap with the gate metal layer 50 and the gate runner portion 51. In this example, the well region 17 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate metal layer 50. The well region 17 is a region of a second conductivity type provided in the semiconductor substrate 10. The doping concentration of the well region 17 may be higher than the doping concentration of the base region 14. In this example, the base region 14 is P- type, and the well region 17 is P+ type.

[0068] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the trench arrangement direction on the front surface 21 of the semiconductor substrate 10. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately arranged along the trench arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are arranged along the trench arrangement direction. In this example, the diode section 80 does not have a gate trench section 40. The trench arrangement direction may be the same as or different from the arrangement direction of the transistor section 70 and the diode section 80. In this example, the trench arrangement direction is the same as the arrangement direction of the transistor section 70 and the diode section 80.

[0069] In the transistor section 70, one or more gate trench sections 40 are arranged at predetermined intervals along the trench arrangement direction. The gate conductive section inside the gate trench section 40 is electrically connected to the gate metal layer 50, and a gate potential is applied thereto. In the transistor section 70, one or more dummy trench sections 30 may be arranged at predetermined intervals along the trench arrangement direction. A potential different from the gate potential is applied to the dummy conductive section inside the dummy trench section 30. In this example, the dummy conductive section is electrically connected to the emitter electrode 52, and an emitter potential is applied thereto.

[0070] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along a predetermined trench arrangement direction. The dummy trench sections 30 are arranged at predetermined intervals along the predetermined trench arrangement direction in the diode section 80 and the boundary region 90. Note that the transistor section 70 may not be provided with dummy trench sections 30 and may be composed of only the gate trench sections 40.

[0071] The gate trench portion 40 in this example may have two extension portions 41 (portions of the trench that are linear along the extension direction) that extend along a trench extension direction perpendicular to the trench arrangement direction, and a connection portion 43 that connects the two extension portions 41. The trench extension direction in FIG. 2A is the Y-axis direction. The trench extension direction may be the same as or different from the extension direction of the transistor portion 70 and the diode portion 80. The trench extension direction in this example is the same as the extension direction of the transistor portion 70 and the diode portion 80.

[0072] At least a part of the connecting portion 43 is preferably curved in a top view. By connecting the ends of the two extending portions 41 in the Y-axis direction with each other by the connecting portion 43, electric field concentration at the ends of the extending portions 41 can be alleviated.

[0073] In the transistor section 70, the dummy trench section 30 is provided between the extension portions 41 of the gate trench section 40. One or more dummy trench sections 30 may be provided between the extension portions 41. The dummy trench section 30 may have a linear shape extending in a predetermined trench extension direction, and may have an extension portion 31 and a connection portion 33, similar to the gate trench section 40. The semiconductor device 100 may include both linear dummy trench sections 30 without a connection portion 33 and dummy trench sections 30 with a connection portion 33. The direction in which the extension portion 41 of the gate trench section 40 or the extension portion 31 of the dummy trench section 30 extends long in the trench extension direction is defined as the longitudinal direction of the trench section. The longitudinal direction of the gate trench portion 40 or the dummy trench portion 30 may coincide with the extension direction of the transistor portion 70 and the diode portion 80. In this example, the extension direction of the transistor portion 70 and the diode portion 80 and the longitudinal direction of the trench portion are the Y-axis direction. The trench arrangement direction in which multiple gate trench portions 40 or dummy trench portions 30 are arranged is defined as the short-side direction of the trench portion. The short-side direction may coincide with the arrangement direction of the transistor portions 70 and the diode portions 80. The short-side direction may also be perpendicular to the longitudinal direction. In this example, the longitudinal direction and the short-side direction are perpendicular. In this example, the arrangement direction of the transistor portion 70 and the diode portion 80 and the short-side direction of the trench portion are the X-axis direction.

[0074] At a connection portion 43 at the tip of the gate trench portion 40, the gate conductive portion in the gate trench portion 40 and the gate runner portion 51 are connected. The gate trench portion 40 may be provided so as to protrude toward the gate runner portion 51 further than the dummy trench portion 30 in the trench extension direction (Y-axis direction). The protruding portion of the gate trench portion 40 is connected to the gate runner portion 51.

[0075] The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 17 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 17. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0076] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between two adjacent trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench portion in the trench extension direction (Y-axis direction).

[0077] The primary region 75 is a region in the transistor section 70 through which a primary current flows in the depth direction. The primary region 75 includes the emitter region 12 and the contact region 15. The area of ​​the primary region 75 may be larger than the area of ​​the boundary region 90.

[0078] The boundary region 90 is provided on the diode section 80 side of the transistor section 70. That is, the boundary region 90 is provided closer to the diode section 80 than the main region 75 is in the transistor section 70. The boundary region 90 may have a dummy trench portion 30 and may be a region in which a collector region 22 is provided on the back surface side of the semiconductor substrate 10. Both ends of the mesa portion of the boundary region 90 in the trench arrangement direction may contact the dummy trench portion 30. All of the trench portions in the boundary region 90 may be dummy trench portions 30. The boundary region 90 may also include a gate trench portion 40. In this example, the boundary region 90 does not have a first conductivity type emitter region 12 provided in the mesa portion on the front surface side of the semiconductor substrate 10. The boundary region 90 may have a base region 14 on the front surface 21. The boundary region 90 may have an emitter region 12 or a contact region 15 on the front surface 21. In this example, boundary region 90 has contact region 14 and contact region 15 on front surface 21. Note that Figure 2A shows the positions of collector region 22 and cathode region 82 provided on the back surface side of semiconductor substrate 10 when projected onto the front surface side.

[0079] The mesa portion 71 is a mesa portion provided in the main region 75 of the transistor portion 70. The mesa portion 81 is a mesa portion provided in the diode portion 80. The mesa portion 91 is a mesa portion provided in the boundary region 90. In this specification, when simply referred to as a mesa portion, it may refer to any of the mesa portion 71, the mesa portion 81, or the mesa portion 91. The extension portion of each trench portion may be considered as one trench portion. The region sandwiched between two extension portions may be considered as a mesa portion.

[0080] Each mesa may have a base region 14. Of the base regions 14 exposed on the front surface 21 of the semiconductor substrate 10 in the mesa, the region closest to the gate metal layer 50 is referred to as the base region 14-e. While FIG. 2A shows the base region 14-e at one end of each mesa in the trench extension direction, a base region 14-e may also be provided at the other end of each mesa. Each mesa may have at least one of a first-conductivity emitter region 12 and a second-conductivity contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0081] The mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 71 may be provided with a contact region 15 exposed on the front surface 21 of the semiconductor substrate 10.

[0082] The emitter region 12 is provided on the front surface 21 of the semiconductor substrate 10 and is a region of the first conductivity type having a higher doping concentration than the drift region 18. The drift region 18 will be described later. The doping concentration of the emitter region 12 is 1E21 cm -3 Above, 1E22cm -3 The emitter region 12 in this example extends in the trench arrangement direction from one trench portion in contact with the mesa portion 71 to the other opposing trench portion.

[0083] A first-conductivity-type mesa region 61 is provided in the mesa portion 81 of the diode portion 80. Base regions 14-e may be provided on both ends of the first-conductivity-type mesa region 61 in the trench extension direction. An emitter region 12 is not provided on the front surface 21 of the mesa portion 81, but an emitter region 12 may be provided thereon. A contact region 15 may be provided on the front surface 21 of the mesa portion 81.

[0084] The first-conductivity-type mesa region 61 is a first-conductivity-type region provided in a mesa portion between multiple trench portions. In this example, the first-conductivity-type mesa region 61 is provided in the diode portion 80, but may also be provided in the boundary region 90, or may be provided in both the diode portion 80 and the boundary region 90. In this example, the first-conductivity-type mesa region 61 is N-type, but is not limited to this. The first-conductivity-type mesa region 61 will be described later.

[0085] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14-e along the trench extension direction. In this example, the contact holes 54 are provided above the emitter region 12, the contact region 15, the base region 14, and the first-conductivity-type mesa region 61. The contact holes 54 do not need to be provided in regions corresponding to the base region 14-e and the well region 17. The contact holes 54 may be arranged in the center of the mesa portion in the trench arrangement direction (X-axis direction).

[0086] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between a rear surface 23 of the semiconductor substrate 10 and a buffer region 20, which will be described later. In FIG. 2A , a boundary 78 between the cathode region 82 and the collector region 22 is indicated by a dashed line. The rear surface 23 will be described later.

[0087] The cathode region 82 is disposed away from the well region 17 in the trench extension direction. This ensures a distance between the cathode region 82 and a P-type region (well region 17) that has a relatively high doping concentration and is formed deep, improving the breakdown voltage and suppressing hole injection from the well region 17. In this example, the end of the cathode region 82 in the trench extension direction is disposed farther from the well region 17 than the end of the contact hole 54 in the trench extension direction. In another example, the end of the cathode region 82 in the trench extension direction may be disposed between the well region 17 and the contact hole 54.

[0088] The base region 14 is provided in the mesa portion 91 of the boundary region 90. The boundary region 90 may have a plurality of mesa portions 91. The mesa portion 91 may be provided with a contact region 15. The mesa portion 91 in this example has the contact region 15 around the end of the contact hole 54 in the trench extension direction.

[0089] The trench contact portion 58 is provided in a mesa portion between two adjacent trench portions among the plurality of trench portions. The trench contact portion 58 extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The trench contact portion 58 may be provided extending from the upper end of the interlayer insulating film 38 to the inside of the semiconductor substrate 10. The trench contact portion 58 of this example is provided in the contact hole 54. By providing the trench contact portion 58, the semiconductor device 100 of this example can reduce the base resistance during turn-off and improve latch-up resistance.

[0090] 2B is a diagram showing an example of an XZ cross section including the a-a' cross section in FIG. 2A. The XZ cross section including the a-a' cross section is an XZ plane passing through the emitter region 12 in the main region 75. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the XZ cross section including the a-a' cross section. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0091] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0092] The buffer region 20 is a region of the first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is provided closer to the back surface 23 of the semiconductor substrate 10 than the center of the semiconductor substrate 10 in the depth direction. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0093] The collector region 22 and the cathode region 82 are provided on the back surface 23 of the semiconductor substrate 10. The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. A boundary 78 between the collector region 22 and the cathode region 82 may be the boundary between the transistor section 70 and the diode section 80.

[0094] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. At least a portion of the collector electrode 24 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).

[0095] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71. The base region 14 may also be provided in the mesa portion 91. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0096] The accumulation region 16 is provided above the drift region 18. That is, the accumulation region 16 is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type. The doping concentration of the accumulation region 16 is 1E16 cm -3 Above, 1E18cm -3 The accumulation region 16 may be provided in the mesa portion 71. The accumulation region 16 may be provided in the mesa portion 81 and the mesa portion 91.

[0097] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0098] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions are not limited to those formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include those formed after the trenches have been formed.

[0099] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0100] The gate conductive portion 44 includes a region facing the base region 14 across the gate insulating film 42. When a predetermined voltage is applied to the gate conductive portion 44, an electron channel is formed by an inversion layer in the surface layer of the base region 14 at the interface that contacts the gate trench.

[0101] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0102] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0103] The front surface electrode portion 200 is provided above the front surface 21 of the semiconductor substrate 10. The front surface electrode portion 200 has an emitter electrode 52, a barrier metal portion 220, and a plug portion 230. The front surface electrode portion 200 may have a silicide layer 210, which will be described later. The front surface electrode portion 200 may have a trench contact portion 58. The front surface electrode portion 200 may be in ohmic contact with a plug region 13, which will be described later.

[0104] The barrier metal portion 220 is provided on the sidewall and bottom surface of the contact hole 54. The barrier metal portion 220 may be provided on the entire bottom surface of the contact hole 54. The material of the barrier metal portion 220 may be titanium and / or a titanium compound. The barrier metal portion 220 may contain Ti or TiN.

[0105] The plug portion 230 is provided inside the barrier metal portion 220 in the contact hole 54. The material of the plug portion 230 may be tungsten. The material of the plug portion 230 may be the same as the material of the emitter electrode 52. In other words, the plug portion 230 may be the portion of the emitter electrode 52 that is embedded in the contact hole 54.

[0106] Although the semiconductor device 100 of this example does not include a lifetime control unit having a lifetime killer, it may include a lifetime control unit. The semiconductor device 100 may include a lifetime killer region closer to the front surface 21 than the center in the depth direction of the semiconductor substrate 10, or may include a lifetime killer region closer to the back surface 23 than the center in the depth direction of the semiconductor substrate 10.

[0107] The first-conductivity-type mesa region 61 is a region of the first conductivity type that contacts the plug region 13 in a mesa portion between multiple trench portions. The first-conductivity-type mesa region 61 in this example contacts the plug region 13 in a mesa portion 81. The first-conductivity-type mesa region 61 in this example is the drift region 18. The first-conductivity-type mesa region 61 may be a region having a doping concentration different from that of the drift region 18.

[0108] The plug region 13 is a region of the second conductivity type provided above the drift region 18 and having a higher doping concentration than the base region 14. The plug region 13 may have a higher doping concentration than the contact region 15. In this example, the plug region 13 is of P++ type, but is not limited to this.

[0109] The plug region 13 may be provided in the semiconductor substrate 10 and in contact with the front surface electrode portion 200. The plug region 13 in this example is provided below the trench contact portion 58. The plug region 13 may be in contact with the trench contact portion 58. The plug region 13 in this example is in contact with the bottom surface of the trench contact portion 58. The plug region 13 may be in contact with the side surface of the trench contact portion 58. The plug region 13 may cover the entire side surface of the trench contact portion 58. The plug region 13 in this example covers the side surface and bottom surface of the trench contact portion 58 at a depth position deeper than the front surface 21 of the semiconductor substrate 10.

[0110] The plug region 13 may be provided continuously on the bottom surface of the trench contact portion 58, extending in the trench extension direction. The plug region 13 may be provided over the entire bottom surface of the trench contact portion 58. The plug region 13 may be provided discretely on the bottom surface of the trench contact portion 58 in the trench extension direction. The plug region 13 may be provided in at least one of the main region 75, the diode portion 80, or the boundary region 90. In this example, the plug region 13 is provided in each of the main region 75, the diode portion 80, and the boundary region 90.

[0111] The plug region 13 may be in contact with the first conductivity type mesa region 61 in the mesa portion 81. The plug region 13 may be in contact with the emitter region 12 and the base region 14 in the mesa portion 71. The lower end of the plug region 13 may be deeper than the lower end of the emitter region 12 and shallower than the lower end of the base region 14. The plug region 13 may be in contact with the base region 14 in the mesa portion 91.

[0112] The bottom end of the trench contact portion 58 may be deeper than the bottom end of the emitter region 12. The bottom end of the trench contact portion 58 may be shallower than the bottom end of the base region 14. The bottom end of the trench contact portion 58 may be shallower than the top end of the accumulation region 16. The shape of the trench contact portion 58 may be the same or different in the main region 75, the diode portion 80, and the boundary region 90.

[0113] 2C is a diagram showing an example of an XZ cross section including the b-b' cross section in FIG. 2A. The XZ cross section including the b-b' cross section is an XZ plane that passes through the contact region 15 in the main region 75. In this example, differences from the a-a' cross section in FIG. 2B that passes through the emitter region 12 will be particularly described. Other points may be the same as the a-a' cross section in FIG. 2B.

[0114] The lower end of the contact region 15 may be deeper than the lower end of the emitter region 12. The contact region 15 may contact the plug region 13 and the base region 14 in the mesa portion 71.

[0115] The plug region 13 may contact the contact region 15 and the base region 14 at the mesa portion 71. The bottom end of the plug region 13 may be deeper than the bottom end of the contact region 15 and shallower than the bottom end of the base region 14.

[0116] The lower end of the trench contact portion 58 may be deeper than the lower end of the contact region 15. The lower end of the trench contact portion 58 may be shallower than the lower end of the base region 14. The lower end of the trench contact portion 58 may be shallower than the upper end of the accumulation region 16. The shape of the trench contact portion 58 in an XZ cross section passing through the contact region 15 may be the same as the shape of the trench contact portion 58 in an XZ cross section passing through the emitter region 12.

[0117] The mesa portion 81 may be the same as the mesa portion 81 in the aa' cross section of Figure 2B. The mesa portion 91 may be the same as the mesa portion 91 in the aa' cross section of Figure 2B.

[0118] 2D is an enlarged view of an XZ cross section passing through the mesa portion 81. This figure shows the mesa portion 81 sandwiched between two adjacent dummy trench portions 30. The front surface electrode portion 200 has a silicide layer 210, a barrier metal portion 220, a plug portion 230, and an emitter electrode 52.

[0119] The silicide layer 210 is in contact with the semiconductor substrate 10. If the semiconductor substrate 10 is made of silicon, the silicide layer 210 may be a layer formed by silicidation of the barrier metal portion 220 through reaction with the semiconductor substrate 10. The silicide layer 210 is provided on both the bottom and side surfaces of the trench contact portion 58. In this example, the silicide layer 210 is in contact with the plug region 13. The silicide layer 210 does not need to be provided in a region that is not in contact with the semiconductor substrate 10. The material of the buffer region 20 in this example is TiSi, but is not limited to this.

[0120] The barrier metal portion 220 is in contact with the silicide layer 210. The barrier metal portion 220 may contain a material that reacts with Si of the semiconductor substrate 10 to form a silicide. The barrier metal portion 220 may contain Ti. The barrier metal portion 220 of this example has a first barrier metal layer 221 and a second barrier metal layer 222.

[0121] The first barrier metal layer 221 is provided on the side surface of the trench contact portion 58. The first barrier metal layer 221 may be in contact with the silicide layer 210 provided on the side surface and bottom surface of the trench contact portion 58. A part of the first barrier metal layer 221 may be in contact with the interlayer insulating film 38 on the side surface of the trench contact portion 58. The material of the first barrier metal layer 221 in this example is Ti.

[0122] The second barrier metal layer 222 is provided inside the first barrier metal layer 221 in the trench contact portion 58. The second barrier metal layer 222 is provided close to the bottom and side surfaces of the trench contact portion 58. The second barrier metal layer 222 may be in contact with the first barrier metal layer 221. In this example, the material of the second barrier metal layer 222 is TiN.

[0123] The plug portion 230 is provided inside the barrier metal portion 220 in the trench contact portion 58. In this example, the plug portion 230 is provided inside the second barrier metal layer 222 in the trench contact portion 58. The plug portion 230 in this example is in contact with the second barrier metal layer 222. The plug portion 230 may be formed using a method and material that can fill the inside of the contact hole 54. The material of the plug portion 230 in this example is tungsten.

[0124] As described above, the semiconductor device 100 may have a layered structure of the semiconductor substrate 10, the silicide layer 210, the first barrier metal layer 221, the second barrier metal layer 222, and the plug portion 230. In one example, the semiconductor device 100 has a layered structure of a Si substrate, a TiSi layer, a Ti layer, a TiN layer, and a W layer. The barrier height between the front surface electrode portion 200 and the semiconductor substrate 10 may be adjusted by changing the material of the front surface electrode portion 200. The barrier height between the front surface electrode portion 200 and the semiconductor substrate 10 may be 0.6 eV or more and 1.0 eV or less.

[0125] Depth D58 indicates the distance from front surface 21 to the bottom end of trench contact portion 58 in the depth direction of semiconductor substrate 10. Increasing depth D58 suppresses the amount of holes injected from transistor portion 70 to diode portion 80, making it easier to reduce reverse recovery loss Err.

[0126] The front surface electrode portion 200 is separated from the first conductivity type mesa region 61. That is, the silicide layer 210 is covered with the plug region 13 and separated from the first conductivity type mesa region 61. This makes it easier to suppress initial leakage of current.

[0127] The mesa width Wm is the width of the mesa portion in the trench arrangement direction. In this example, the mesa width Wm indicates the mesa width of the mesa portion 81. The trench width Wt is the width of any one of the multiple trench portions in the trench arrangement direction. In this example, the trench width Wt indicates the trench width of the dummy trench portion 30. In this example, the mesa width Wm is larger than the trench width Wt, but may be smaller than or the same as the trench width Wt.

[0128] 2E shows an example of a YZ cross section including the c-c' cross section in FIG. 2A. The YZ cross section including the c-c' cross section is a YZ plane passing through the mesa portion 81 of the diode portion 80. The c-c' cross section is a cross section passing through the contact hole 54.

[0129] The base region 14 extends in the trench extension direction from an end of the well region 17 toward an end of the contact hole 54 provided in the interlayer insulating film 38. The base region 14 may be spaced apart from the plug region 13 in the trench extension direction. The plug region 13 in this example is provided continuously below the trench contact portion 58 and extends in the trench extension direction. The plug region 13 may be provided below the trench contact portion 58 and spaced apart in the trench extension direction. The plug region 13 may cover a side surface of the end of the trench contact portion 58 in the trench extension direction.

[0130] The distance L0 is the distance in the trench extension direction between the base region 14 and the end of the contact hole 54. The distance L0 may be greater than 0 μm and within the width Wd of the depletion layer that spreads from the base region 14 toward the drift region 18.

[0131] Distance L1 is the distance in the trench extension direction between the end of contact hole 54 and cathode region 82. By setting distance L1 to an appropriate size, it is possible to improve the breakdown voltage at the end of contact hole 54 and increase reliability.

[0132] 3A is an enlarged view of a modified example of an XZ cross section passing through the mesa portion 81. The mesa portion 81 of this example differs from the mesa portion 81 of FIG. 2D in the position where the plug region 13 is provided. In this example, differences from the mesa portion 81 of FIG. 2D will be particularly described, and other points may be the same as the mesa portion 81 of FIG. 2D. In this example, the mesa portion 81 of the diode portion 80 will be described, but the position where the plug region 13 is provided may also be applied to the mesa portion 71 of the transistor portion 70 and the mesa portion 91 of the boundary region 90.

[0133] The plug region 13 contacts adjacent trench portions among the multiple trench portions. In this example, the plug region 13 contacts the dummy trench portion 30, but may also contact the gate trench portion 40. In this example, the plug region 13 contacts the dummy trench portion 30 at both ends in the trench arrangement direction. One end of the plug region 13 in the trench arrangement direction may contact the dummy trench portion 30, and the other end may contact the gate trench portion 40. The plug region 13 may also contact the gate trench portion 40 at both ends in the trench arrangement direction. A first-conductivity-type mesa region 61 may be provided above the point where the plug region 13 and the trench portion contact. The lower surface of the plug region 13 may contact the first-conductivity-type mesa region 61.

[0134] In the semiconductor device 100 of this example, the plug region 13 is formed to extend toward the trench portion, which facilitates diffusion of the depletion layer in the trench arrangement direction, thereby preventing the depletion layer from reaching the front surface electrode portion 200.

[0135] 3B is an enlarged view of a modified example of an XZ cross section passing through the mesa portion 81. The mesa portion 81 of this example differs from the mesa portion 81 of FIG. 2D in the position where the plug region 13 is provided. In this example, differences from the mesa portion 81 of FIG. 2D will be particularly described, and other points may be the same as the mesa portion 81 of FIG. 2D. In this example, the mesa portion 81 of the diode portion 80 will be described, but the position where the plug region 13 is provided may also be applied to the mesa portion 71 of the transistor portion 70 and the mesa portion 91 of the boundary region 90.

[0136] The plug region 13 covers a portion of the side surface and the bottom surface of the trench contact portion 58 at a depth deeper than the front surface 21 of the semiconductor substrate 10. That is, the plug region 13 does not need to be in contact with a portion of the side surface of the trench contact portion 58. The percentage of the area of ​​the side surface of the trench contact portion 58 that is covered by the plug region 13 may be 30% or more, 50% or more, 80% or less, 90% or less, or less than 100%. In this example, the plug region 13 is separated from the dummy trench portion 30, but may be in contact with the dummy trench portion 30.

[0137] The trench contact portion 58 may be in contact with the first conductivity type mesa region 61 and the plug region 13 on its side surface. In this example, the silicide layer 210 is in contact with the first conductivity type mesa region 61 and the plug region 13 on its side surface of the trench contact portion 58. The trench contact portion 58 may form a Schottky junction with the first conductivity type mesa region 61 on its side surface.

[0138] 4A is a top view of a modified example of the semiconductor device 100. In the semiconductor device 100 of this example, the structure of the boundary region 90 is different from that of the boundary region 90 of FIG. 2A. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described. Other aspects may be the same as those of the semiconductor device 100 of FIG. 2A.

[0139] The boundary region 90 does not have a base region 14 in a region where a contact hole 54 for connecting the semiconductor substrate 10 and the front surface electrode portion 200 is provided. The boundary region 90 of this example has a first conductivity type mesa region 61 exposed on the front surface 21 of the semiconductor substrate 10. The first conductivity type mesa region 61 may be provided in a region where the contact hole 54 is provided in the mesa portion 91 of the boundary region 90. The boundary region 90 may have a base region 14-e at an end of the mesa portion 91 in the trench extension direction.

[0140] 4B is a diagram showing an example of an XZ cross section including the dd' cross section in FIG. 4A. The XZ cross section including the dd' cross section is an XZ plane passing through the emitter region 12 in the main region 75. The cross-sectional structure of the mesa portion 91 may be the same as that of the mesa portion 91 in the XZ plane passing through the contact region 15 in the main region 75.

[0141] The mesa portion 91 has a plug region 13 and a first-conductivity-type mesa region 61. The first-conductivity-type mesa region 61 may be the drift region 18. The mesa portion 91 of this example does not have a base region 14 below the contact hole 54. The plug region 13 of the mesa portion 91 may be in contact with the first-conductivity-type mesa region 61. The structure of the mesa portion 91 may be the same as the structure of the mesa portion 81.

[0142] In the semiconductor device 100 of this example, the first conductivity type mesa region 61 is provided in the boundary region 90 in addition to the diode section 80, thereby suppressing the amount of holes injected from the transistor section 70 into the diode section 80, making it easier to further reduce the reverse recovery loss Err. The width of the boundary region 90 in the trench arrangement direction may be determined in consideration of the amount of holes injected from the transistor section 70 into the diode section 80.

[0143] 5A is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the boundary region 90 of FIG. 2A in the structure of the boundary region 90. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described. Other aspects may be the same as the semiconductor device 100 of FIG. 2A.

[0144] The boundary region 90 of this example has a first boundary mesa portion 191 and a second boundary mesa portion 291 as examples of mesa portions 91. The first boundary mesa portion 191 and the second boundary mesa portion 291 may have different proportions of the second conductivity type region in the mesa portion 91. The second boundary mesa portion 291 may have a larger proportion of the second conductivity type region than the first boundary mesa portion 191.

[0145] The first boundary mesa portion 191 is a region where a contact hole 54 for connecting the semiconductor substrate 10 and the front surface electrode portion 200 is provided, and does not include the base region 14. However, the first boundary mesa portion 191 may have a base region 14-e provided at an end portion in the trench extension direction. The first boundary mesa portion 191 may be provided adjacent to the diode portion 80. In this example, the first boundary mesa portion 191 contacts the dummy trench portion 30, but may also contact the gate trench portion 40.

[0146] The second boundary mesa portion 291 is provided closer to the main region 75 than the first boundary mesa portion 191. The second boundary mesa portion 291 may be provided between the first boundary mesa portion 191 and the main region 75. The second boundary mesa portion 291 is a region including the base region 14 in a region where a contact hole 54 for connecting the semiconductor substrate 10 and the front surface electrode portion 200 is provided. In this example, the second boundary mesa portion 291 contacts the dummy trench portion 30, but may also contact the gate trench portion 40.

[0147] In the semiconductor device 100 of this example, the second conductivity type base region 14 is omitted from the first boundary mesa portion 191 adjacent to the diode portion 80. By reducing the proportion of the second conductivity type region in the first boundary mesa portion 191 adjacent to the diode portion 80, the semiconductor device 100 can suppress hole injection and reduce the reverse recovery loss Err.

[0148] 5B is a diagram showing an example of an XZ cross section including the e-e' cross section in FIG. 5A. The XZ cross section including the e-e' cross section is an XZ plane that passes through the emitter region 12 in the main region 75. The cross-sectional structure of the mesa portion 91 may be the same as that of the mesa portion 91 in the XZ plane that passes through the contact region 15 in the main region 75.

[0149] The first boundary mesa portion 191 has a plug region 13 and a first-conductivity-type mesa region 61. The first boundary mesa portion 191 may have a drift region 18. The first-conductivity-type mesa region 61 may be the drift region 18. The first boundary mesa portion 191 does not have a base region 14 below the contact hole 54. The plug region 13 of the first boundary mesa portion 191 may be in contact with the first-conductivity-type mesa region 61. That is, the structure of the first boundary mesa portion 191 may be the same as the structure of the mesa portion 81.

[0150] The second boundary mesa portion 291 has a plug region 13 and a base region 14. In this example, the second boundary mesa portion 291 has the base region 14 below the contact hole 54. The plug region 13 of the second boundary mesa portion 291 may be in contact with the base region 14. The second boundary mesa portion 291 may have a drift region 18.

[0151] The boundary region 90 may include a plurality of first boundary mesas 191 and a plurality of second boundary mesas 291. In this example, the boundary region 90 has the same number of first boundary mesas 191 and second boundary mesas 291, but may have different numbers of first boundary mesas 191 and second boundary mesas 291. The number of first boundary mesas 191 may be greater or smaller than the number of second boundary mesas 291. The ratio of the number of first boundary mesas 191 to the number of second boundary mesas 291 may be determined taking into consideration the amount of holes injected from the transistor section 70 to the diode section 80.

[0152] 6A is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in the structures of the diode section 80 and the boundary region 90. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described. Other aspects may be the same as those of the semiconductor device 100 of FIG. 2A. The diode section 80 of this example has an anode region 19.

[0153] The main region 75 includes a base region 14 of the second conductivity type provided above the drift region 18. On the other hand, the boundary region 90 does not include the base region 14 in a region where a contact hole 54 for connecting the semiconductor substrate 10 and the front surface electrode portion 200 is provided. The first conductivity type mesa region 61 may be provided in a region where the contact hole 54 is provided in the mesa portion 91 of the boundary region 90. The boundary region 90 may have a base region 14-e at an end of the mesa portion 91 in the trench extension direction.

[0154] The anode region 19 is a second conductivity type region provided above the drift region 18. The anode region 19 is provided in the mesa portion 81. The anode region 19 may be in contact with the dummy trench portion 30. In this example, the anode region 19 is provided in the mesa portion 81, extending in the trench arrangement direction from one adjacent dummy trench portion 30 to the other adjacent dummy trench portion 30. The anode region 19 may be provided in contact with the gate trench portion 40. The depth of the anode region 19 may be deeper, shallower, or equal to the depth of the base region 14 in the depth direction of the semiconductor substrate 10. In this example, the depth of the anode region 19 is equal to the depth of the base region 14.

[0155] The doping concentration of the anode region 19 may be the same as that of the base region 14, or may be lower or higher than that of the base region 14. The maximum doping concentration of the anode region 19 may be lower, higher, or equal to the maximum doping concentration of the base region 14. In this example, the maximum doping concentration of the anode region 19 is the same as the maximum doping concentration of the base region 14. The integral of the doping concentration of the anode region 19 along the depth direction of the semiconductor substrate 10 may be smaller, larger, or equal to the integral of the doping concentration of the base region 14. In this example, the integral of the doping concentration of the anode region 19 is the same as the integral of the doping concentration of the base region 14. In this example, the anode region 19 is P-type.

[0156] 6B is a diagram showing an example of an XZ cross section including the f-f' cross section in FIG. 6A. The XZ cross section including the f-f' cross section is an XZ plane that passes through the emitter region 12 in the main region 75. The cross-sectional structure of the mesa portion 91 may be the same as that of the mesa portion 91 in the XZ plane that passes through the contact region 15 in the main region 75.

[0157] The mesa portion 81 has a plug region 13 and an anode region 19. The mesa portion 81 may have a drift region 18. The plug region 13 of the mesa portion 81 may be in contact with the anode region 19. The lower end of the anode region 19 may be at the same depth as the lower end of the base region 14, or may be at a different depth.

[0158] The mesa portion 91 has a plug region 13 and a first-conductivity-type mesa region 61. The mesa portion 91 may have a drift region 18. The first-conductivity-type mesa region 61 may be the drift region 18. The mesa portion 91 does not have a base region 14 or an anode region 19 below the contact hole 54. The plug region 13 of the mesa portion 91 may be in contact with the first-conductivity-type mesa region 61.

[0159] The first conductivity type region of the boundary region 90 may occupy 50% or more of the mesa portion 91 at a depth shallower than the lower end of the base region 14. In other words, the first conductivity type mesa region 61 may occupy 50% or more of the combined area of ​​the first conductivity type mesa region 61 and the plug region 13. When the first conductivity type mesa region 61 is the drift region 18, the lower end of the first conductivity type mesa region 61 may be defined as being at the same position as the lower end of the base region 14.

[0160] In the semiconductor device 100 of this example, by reducing the second conductivity type region in the boundary region 90, the amount of holes injected from the transistor section 70 to the diode section 80 is suppressed, making it easier to reduce the reverse recovery loss Err.

[0161] 7A is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in that it does not include the trench contact portion 58. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described. Other aspects may be the same as the semiconductor device 100 of FIG. 2A.

[0162] 7B is a diagram showing an example of an XZ cross section including the g-g' cross section in FIG. 7A. The XZ cross section including the g-g' cross section is an XZ plane passing through the emitter region 12 in the main region 75. The front surface electrode portion 200 contacts the semiconductor substrate 10 at the front surface 21. The semiconductor device 100 of this example differs from the semiconductor device 100 including the trench contact portion 58 in that the contact hole 54 does not extend in the depth direction of the semiconductor substrate 10.

[0163] The plug region 13 is provided in the mesa portion 81. The plug region 13 contacts the front surface electrode portion 200 on the front surface 21. The plug region 13 is provided below the contact hole 54. The plug region 13 may be provided so as to cover the lower surface of the front surface electrode portion 200 provided in the contact hole 54. The plug region 13 may contact the first conductivity type mesa region 61. The plug region 13 may be provided in the mesa portion 91. The plug region 13 does not have to be provided in the region of the mesa portion 71 where the emitter region 12 is provided.

[0164] The first-conductivity-type mesa region 61 may be provided so as to be exposed on the front surface 21 of the semiconductor substrate 10. In this example, the first-conductivity-type mesa region 61 is the drift region 18. However, the first-conductivity-type mesa region 61 may also be a region of the first conductivity type having a doping concentration different from that of the drift region 18. The first-conductivity-type mesa region 61 may be provided in a mesa portion 91.

[0165] The structure in which the front surface electrode portion 200 is connected to the semiconductor substrate 10 on the front surface 21 may be applied as appropriate to the semiconductor device 100 of other embodiments. In this way, whether or not the trench contact portion 58 is provided may be changed as appropriate.

[0166] 7C is a diagram showing an example of an XZ cross section including the h-h' cross section in FIG. 7A. The XZ cross section including the h-h' cross section is an XZ plane that passes through the contact region 15 in the main region 75. The front surface electrode portion 200 contacts the semiconductor substrate 10 on the front surface 21. In this example, differences from the g-g' cross section in FIG. 7B will be particularly described. Other points may be the same as the g-g' cross section in FIG. 7B.

[0167] The plug region 13 is also provided in the region of the mesa portion 71 where the contact region 15 is provided. The plug region 13 is provided below the contact hole 54. The plug region 13 may be provided so as to cover the lower surface of the front surface electrode portion 200 provided in the contact hole 54. The doping concentration of the plug region 13 may be higher than the doping concentration of the contact region 15. The plug region 13 may be in contact with the contact region 15. The lower end of the plug region 13 may be shallower than the lower end of the contact region 15. The plug region 13 may also be provided in the mesa portion 81 and the mesa portion 91.

[0168] 8A is a diagram showing a modified example of the XZ cross section including the a-a' cross section in FIG. 2A. The semiconductor device 100 of this example differs from the a-a' cross section of FIG. 2B in that it includes a trench bottom region 65. In this example, differences from the a-a' cross section of FIG. 2B will be particularly described. Other aspects may be the same as the a-a' cross section of FIG. 2B.

[0169] The trench bottom region 65 contacts the bottom end of at least one of the multiple trench portions. In this example, the trench bottom region 65 is provided below the trench portions of the transistor portion 70 and the diode portion 80. The trench bottom region 65 may also be provided below the trench portion of the boundary region 90. The trench bottom region 65 is provided over the entire area below the mesa portion, but it does not have to be provided in part of the area below the mesa portion.

[0170] The trench bottom region 65 may be in contact with the drift region 18. In this example, the upper and lower ends of the trench bottom region 65 are in contact with the drift region 18. The semiconductor device 100 in this example does not include an accumulation region 16, but may include an accumulation region 16. If the semiconductor device 100 includes the accumulation region 16, the upper end of the trench bottom region 65 may be in contact with the lower end of the accumulation region 16.

[0171] The trench bottom region 65 in this example is of the second conductivity type. The doping concentration of the trench bottom region 65 may be lower than the doping concentration of the contact region 15. The doping concentration of the trench bottom region 65 may be lower than or the same as the doping concentration of the base region 14. When the trench bottom region 65 is of the second conductivity type, the doping concentration of the trench bottom region 65 is 1.0E15 cm -3 Above, 2.0E17cm -3 It may be the following:

[0172] The semiconductor device 100 of this example can reduce the feedback capacitance and the turn-on loss Eon by including the trench bottom region 65. Furthermore, even if the base region 14 and the anode region 19 are omitted, the semiconductor device 100 of this example can diffuse the injected holes to make the distribution of the holes more uniform.

[0173] 8B is a diagram showing a modified example of the XZ cross section including the a-a' cross section in FIG. 2A. The semiconductor device 100 of this example differs from the a-a' cross section of FIG. 8A in the region including the trench bottom region 65. In this example, differences from the a-a' cross section of FIG. 8A will be particularly described. Other aspects may be the same as the a-a' cross section of FIG. 8A.

[0174] The trench bottom region 65 is provided in the transistor section 70, but not in the diode section 80. The trench bottom region 65 may be provided in both the main region 75 and the boundary region 90. The trench bottom region 65 does not have to be provided in the boundary region 90, or may be provided in only a part of the boundary region 90. The trench bottom region 65 may be provided extending from the main region 75 to partway through the boundary region 90 in the trench arrangement direction. In this example, the trench bottom region 65 is provided extending from the main region 75 to the boundary 78 between the transistor section 70 and the diode section 80 in the trench arrangement direction.

[0175] In the semiconductor device 100 of this example, by not providing a trench bottom region 65 in the diode section 80, hole injection can be suppressed and the reverse recovery loss Err can be more easily reduced compared to when the trench bottom region 65 is provided in the diode section 80.

[0176] 8C is a diagram showing a modified example of the XZ cross section including the a-a' cross section in FIG. 2A. In the semiconductor device 100 of this example, the conductivity type of the trench bottom region 65 differs from that of the a-a' cross section in FIG. 8A. In this example, differences from the a-a' cross section in FIG. 8A will be particularly described. Other aspects may be the same as the a-a' cross section in FIG. 8A.

[0177] The trench bottom region 65 is of the first conductivity type. The doping concentration of the trench bottom region 65 may be higher than the doping concentration of the drift region 18. If the semiconductor device 100 includes an accumulation region 16, the doping concentration of the trench bottom region 65 may be lower than the doping concentration of the accumulation region 16. The doping concentration of the trench bottom region 65 is 1.0E15 cm when the trench bottom region 65 is of the first conductivity type. -3 Above, 1.0E16cm -3 It may be the following:

[0178] In this example, the trench bottom region 65 is provided in each of the main region 75, the diode region 80, and the boundary region 90, but may be provided in only some of the regions. In this example, the trench bottom region 65 is provided over the entire surface below the mesa portion, but it does not have to be provided in only some of the areas below the mesa portion.

[0179] The trench bottom region 65 may be applied as appropriate to the semiconductor device 100 of other embodiments. Although the semiconductor device 100 of this embodiment includes the trench contact portion 58, it may also have a structure in which the front surface electrode portion 200 is connected to the semiconductor substrate 10 on the front surface 21 without providing the trench contact portion 58.

[0180] 9 is an enlarged view of a modified example of an XZ cross section passing through the mesa portion 81. The mesa portion 81 of this example differs from the mesa portion 81 of FIG. 2D in the shape of the trench portion. In this example, differences from the mesa portion 81 of FIG. 2D will be particularly described, and other points may be the same as the mesa portion 81 of FIG. 2D. In this example, the mesa portion 81 of the diode portion 80 will be described, but the shape of the trench portion may also be applied to the mesa portion 71 of the transistor portion 70 and the mesa portion 91 of the boundary region 90.

[0181] This figure shows a mesa portion 81 sandwiched between two adjacent dummy trench portions 30. The shape of the trench portion in this example may also be applied to the gate trench portion 40.

[0182] The trench width Wt of the multiple trench portions may vary in the depth direction of the semiconductor substrate 10. In this example, the trench portion has a trench width Wt that gradually increases as the depth position in the semiconductor substrate 10 increases, but the shape of the trench portion is not limited to this. In this example, the trench portion has a first trench width Wt1 and a second trench width Wt2.

[0183] The first trench width Wt1 is the trench width at a predetermined depth position in the semiconductor substrate 10. In this example, the first trench width Wt1 is the trench width at the front surface 21. The first trench width Wt1 may be 0.5 μm or more and 2.0 μm or less.

[0184] The second trench width Wt2 is larger than the first trench width Wt1 at a position deeper than the depth position of the first trench width Wt1. The second trench width Wt2 may be 1.1 times or more and 1.4 times or less the first trench width Wt1.

[0185] The interval Pt is the interval between two adjacent trench portions at the closest depth position. The interval Pt may be 0.1 μm or more and 0.5 μm or less. In this example, the interval Pt is the interval between multiple trench portions at the depth position of the second trench width Wt2.

[0186] In the semiconductor device 100 of this example, by placing the dummy trench portions 30 close to each other, the potential of the region where the dummy trench portions 30 are close to each other can be made close to 0. As a result, the semiconductor device 100 of this example can suppress reach-through of the depletion layer to the front surface electrode portion 200.

[0187] 10A is an enlarged view of a modified example of an XZ cross section passing through mesa portion 81. Mesa portion 81 of this example differs from mesa portion 81 of FIG. 2D in the ratio of mesa width Wm to trench width Wt. In this example, differences from mesa portion 81 of FIG. 2D will be particularly described, and other aspects may be the same as mesa portion 81 of FIG. 2D. In this example, mesa portion 81 of diode portion 80 will be described, but it may also be applied to mesa portion 71 of transistor portion 70 and mesa portion 91 of boundary region 90.

[0188] The mesa width Wm may be smaller than the trench width Wt. The mesa width Wm may be 0.2 μm or more and 0.5 μm or less. In this example, the mesa width Wm of the mesa portion 81 is smaller than the trench width Wt of the dummy trench portion 30 adjacent to the mesa portion 81. The plug region 13 in this example is separated from the dummy trench portion 30, but may be in contact with the dummy trench portion 30. The plug region 13 in this example covers the side and bottom surfaces of the trench contact portion 58, but may not cover part of the side surfaces of the trench contact portion 58. The side surfaces of the trench contact portion 58 may be in contact with the first-conductivity-type mesa region 61.

[0189] The semiconductor device 100 of this example has a mesa width Wm that is smaller than the trench width Wt. The structure of this example may be appropriately applied to the semiconductor device 100 of other examples. By reducing the mesa width Wm, the depletion layer of the diode section 80 is pinched off, thereby suppressing a decrease in the breakdown voltage.

[0190] 10B is a modified example of an XZ cross section passing through the emitter region 12. In the semiconductor device 100 of this example, the ratio of the mesa width Wm to the trench width Wt is different from that of the semiconductor device 100 of FIG. 2B. In this example, differences from the semiconductor device 100 of FIG. 2B will be particularly described, and other aspects may be the same as those of the semiconductor device 100 of FIG. 2B.

[0191] The mesa width Wmd of the diode section 80 is smaller than the mesa width Wmt of the transistor section 70. The trench width Wtd of the diode section 80 is the same as the trench width Wtt of the transistor section 70, but may be different. The trench width Wtd of the diode section 80 may be larger or smaller than the trench width Wtt of the transistor section 70. Note that the mesa width Wmd of the diode section 80 may be the same as the mesa width Wmt of the transistor section 70. In this case, the trench width Wtd of the diode section 80 may be larger than the trench width Wtt of the transistor section 70.

[0192] The semiconductor device 100 of this example can suppress a decrease in breakdown voltage by pinching off the depletion layer in the diode section 80. In the transistor section 70 of this example, the mesa width Wmt is larger than the trench width Wtt, but the mesa width Wmt may be smaller than the trench width Wtt.

[0193] 11A is a top view of a modified example of the semiconductor device 100. In the semiconductor device 100 of this example, the doping concentration of the first-conductivity-type mesa region 61 differs from that of the first-conductivity-type mesa region 61 of FIG. 2A. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described. Other aspects may be the same as those of the semiconductor device 100 of FIG. 2A.

[0194] The doping concentration of the first conductivity type mesa region 61 is higher than the doping concentration of the drift region 18. The doping concentration of the first conductivity type mesa region 61 may be lower than the doping concentration of the accumulation region 16. The doping concentration of the first conductivity type mesa region 61 is 1E15 cm -3 Above, 1E16cm -3 It may be the following:

[0195] 11B is a diagram showing an example of an XZ cross section including the i-i' cross section in FIG. 11A. The XZ cross section including the i-i' cross section is an XZ plane passing through the emitter region 12 in the main region 75. The cross-sectional structure of the mesa portion 91 may be the same as that of the mesa portion 91 in the XZ plane passing through the contact region 15 in the main region 75.

[0196] The mesa portion 91 has a plug region 13 and a first-conductivity-type mesa region 61. The mesa portion 91 does not have a base region 14 below the contact hole 54. A lower surface of the first-conductivity-type mesa region 61 may be in contact with the drift region 18. An upper surface of the first-conductivity-type mesa region 61 may be exposed at the front surface 21 of the semiconductor substrate 10. The first-conductivity-type mesa region 61 may be in contact with the plug region 13. The depth position of the lower end of the first-conductivity-type mesa region 61 may be the same as or different from the depth position of the lower end of the base region 14.

[0197] 12A is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the diode section 80 of FIG. 2A in the structure of the diode section 80. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described. Other aspects may be the same as the semiconductor device 100 of FIG. 2A.

[0198] The diode section 80 does not have a contact hole 54. The diode section 80 of this example does not have a trench contact section 58. The diode section 80 may not have an interlayer insulating film 38 above the semiconductor substrate 10. In the diode section 80, the front surface electrode section 200 directly contacts the front surface 21 of the semiconductor substrate 10. In the diode section 80, the first conductivity type mesa region 61 may be exposed at the front surface 21 of the semiconductor substrate 10. The mesa section 81 may have a base region 14-e and a well region 17 at the end in the trench extension direction.

[0199] As will be described later, the emitter electrode 52 of this example may be in contact with the dummy conductive portion 34 of the dummy trench portion 30. This causes the potential of the dummy conductive portion 34 to become the emitter potential. The semiconductor device 100 of this example includes a connection portion 25 at the end of the dummy trench portion 30 in the trench extension direction. By electrically connecting the dummy trench portion 30 to the emitter electrode 52 via the connection portion 25, the dummy trench portion 30 can be set to the emitter potential more reliably.

[0200] 12B is a diagram showing an example of an XZ cross section including the j-j' cross section in FIG. 12A. The XZ cross section including the j-j' cross section is an XZ plane passing through the emitter region 12 in the main region 75. The cross-sectional structure of the mesa portion 81 may be the same as that of the mesa portion 81 in the XZ plane passing through the contact region 15 in the main region 75.

[0201] The mesa portion 81 has a first-conductivity-type mesa region 61. In this example, the first-conductivity-type mesa region 61 is the drift region 18. The mesa portion 81 does not need to have the base region 14 or the anode region 19. The mesa portion 81 contacts the emitter electrode 52 of the front surface electrode portion 200. The mesa portion 81 does not have the plug region 13, but may have the plug region 13 on the front surface 21. The mesa portion 71 and the mesa portion 91 may be provided with the plug region 13.

[0202] The front surface electrode unit 200 covers the upper portions of the trenches and the upper portions of the mesa portions 81 between the trenches in the diode unit 80, and is in contact with the trenches and the mesa portions 81. That is, the interlayer insulating film 38 does not need to be provided between the front surface electrode unit 200 and the semiconductor substrate 10. The interlayer insulating film 38 does not need to be provided above the dummy trenches 30, and does not need to be provided above the mesa portions 81. By omitting the interlayer insulating film 38, electric field concentration at the end portions of the interlayer insulating film 38 can be avoided. The material of the front surface electrode unit 200 may be Al-Si. The front surface electrode unit 200 may form a Schottky junction with the first conductivity type mesa region 61.

[0203] The dummy trench portion 30 may be in contact with the front surface electrode portion 200. The dummy conductive portion 34 in this example is in contact with the emitter electrode 52. This causes the potential of the dummy conductive portion 34 to become the emitter potential. A recess may be formed on the top surface of the dummy trench portion 30 by etching.

[0204] FIG. 13A is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the diode section 80 of FIG. 7A in the structure of the diode section 80. In this example, differences from the semiconductor device 100 of FIG. 7A will be particularly described. Other aspects may be the same as the semiconductor device 100 of FIG. 7A. The material of the emitter electrode 52 of this example is Al-Si, but is not limited to this. The width of the contact hole 54 of the mesa section 81 is larger than the width of the contact hole 54 of the transistor section 70, but is not limited to this. The width of the contact hole 54 of the mesa section 81 may be the same as the width of the contact holes 54 of the mesa section 71 and mesa section 91.

[0205] 13B is a diagram showing an example of an XZ cross section including the k-k' cross section in FIG. 13A. The XZ cross section including the k-k' cross section is an XZ plane that passes through the emitter region 12 in the main region 75. The cross-sectional structure of the mesa portion 81 may be the same as that of the mesa portion 81 in the XZ plane that passes through the contact region 15 in the main region 75. The front surface electrode portion 200 contacts the semiconductor substrate 10 on the front surface 21.

[0206] The mesa portion 81 has a plug region 13 and a first-conductivity-type mesa region 61. The plug region 13 is provided below the contact hole 54 and is in contact with the front-surface electrode portion 200. The plug region 13 is in contact with the first-conductivity-type mesa region 61. The first-conductivity-type mesa region 61 does not need to be in contact with the front-surface electrode portion 200. The first-conductivity-type mesa region 61 in this example is the drift region 18, but is not limited to this.

[0207] 14 is an example of a cross-sectional view of a semiconductor device 100. The semiconductor device 100 of this example includes a diode section 80 but does not include a transistor section 70. The diode section 80 of this example includes a plurality of dummy trench sections 30 but does not include a gate trench section 40. The semiconductor device 100 of this example includes a front surface electrode section 200 as a Schottky junction electrode. The dummy trench section 30 may be set to an anode potential as the potential of the Schottky junction electrode.

[0208] The front-surface electrode unit 200 is formed of a material containing metal. At least a portion of the front-surface electrode unit 200 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu), or aluminum-copper alloy (AlCu). The front-surface electrode unit 200 may have a barrier metal formed of titanium or a titanium compound, cobalt or a cobalt compound, nickel or a nickel compound, or the like, below the region formed of aluminum or the like.

[0209] The semiconductor device 100 of this example includes a contact hole 54 provided in the interlayer insulating film 38. However, the semiconductor device 100 may omit the interlayer insulating film 38 above the dummy trench portion 30 and the mesa portion 81. In this case, the front surface electrode portion 200 may be in contact with the upper surface of the mesa portion 81 and the upper surface of the dummy trench portion 30.

[0210] The structures disclosed in other embodiments may be applied as appropriate to the semiconductor device 100 that does not include the transistor section 70. That is, the semiconductor device 100 of this example may have the structure of the diode section 80 described for the semiconductor device 100 that includes the transistor section 70 and the diode section 80.

[0211] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0212] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0213] 10 semiconductor substrate, 12 emitter region, 13 plug region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 anode region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 30 dummy Trench portion, 31...extension portion, 32...dummy insulating film, 33...connection portion, 34...dummy conductive portion, 38...interlayer insulating film, 40...gate trench portion, 41...extension portion, 42...gate insulating film, 43...connection portion, 44...gate conductive portion, 50...gate metal layer, 51...gate runner portion, 52...emitter electrode, 54...contact hole, 5 5. Contact hole, 56. Contact hole, 58. Trench contact portion, 61. First conductivity type mesa region, 65. Trench bottom region, 70. Transistor portion, 71. Mesa portion, 75. Main region, 78. Boundary, 80. Diode portion, 81. Mesa portion, 82. Cathode region, 90. Boundary region, 91. Mesa portion, 100. Semiconductor Device, 102 edge, 112 gate pad, 130 gate wiring, 160 active region, 170 edge termination structure, 191 first boundary mesa, 200 front electrode, 210 silicide layer, 220 barrier metal, 221 first barrier metal layer, 222 second barrier metal layer, 230 plug, 291 second boundary mesa

Claims

1. A semiconductor device including a diode portion, a first conductivity type drift region provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; a front surface electrode portion provided above the front surface of the semiconductor substrate; Equipped with The diode section a second conductivity type plug region provided in the semiconductor substrate and in contact with the front surface electrode portion; a first conductivity type mesa region of a first conductivity type in contact with the plug region in a mesa portion between the plurality of trench portions; have Semiconductor device.

2. The first conductivity type mesa region is the drift region. The semiconductor device according to claim 1 .

3. The first conductivity type mesa region has a doping concentration higher than that of the drift region. The semiconductor device according to claim 1 .

4. The front surface electrode portion has a trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1 .

5. The plug region covers the side and bottom surfaces of the trench contact portion at a depth position deeper than the front surface of the semiconductor substrate. The semiconductor device according to claim 4 .

6. the plug region covers a part of a side surface and a bottom surface of the trench contact portion at a depth position deeper than the front surface of the semiconductor substrate; The trench contact portion forms a Schottky junction with the first conductivity type mesa region at the side surface. The semiconductor device according to claim 4 .

7. The plug region contacts adjacent trench portions among the plurality of trench portions. The semiconductor device according to claim 1 .

8. a trench bottom region that contacts a bottom end of at least one of the plurality of trench portions; The semiconductor device according to claim 1 .

9. The trench bottom region is of the second conductivity type. The semiconductor device according to claim 8 .

10. A transistor portion is provided, The trench bottom region is provided in the transistor section and is not provided in the diode section. The semiconductor device according to claim 8 .

11. The trench bottom region is of a first conductivity type. The semiconductor device according to claim 8 .

12. The trench portion provided in the diode portion among the plurality of trench portions is a first trench width at a predetermined depth position in the semiconductor substrate; a second trench width greater than the first trench width at a position deeper than the depth position of the first trench width; have The semiconductor device according to claim 1 .

13. Of the intervals between two adjacent trench portions, the interval between the plurality of trench portions at the closest depth position is 0.1 μm or more and 0.5 μm or less. The semiconductor device according to claim 12.

14. The mesa width of the mesa portion between the plurality of trench portions is smaller than the trench width of the plurality of trench portions. The semiconductor device according to claim 1 .

15. The mesa width of the mesa portion between the plurality of trench portions is 0.2 μm or more and 0.5 μm or less. The semiconductor device according to claim 1 .

16. The front surface electrode portion has a silicide layer in contact with the plug region. The semiconductor device according to claim 1 .

17. The front surface electrode portion is a barrier metal portion in contact with the silicide layer; a plug portion provided inside the barrier metal portion in the contact hole; have The semiconductor device according to claim 16.

18. The barrier height between the front surface electrode portion and the semiconductor substrate is 0.6 eV or more and 1.0 eV or less. The semiconductor device according to claim 1 .

19. A transistor portion is provided, The transistor section a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a plurality of contact regions of a second conductivity type provided above the drift region and having a doping concentration higher than that of the base region; have The semiconductor device according to claim 1 .

20. The mesa width of the diode section is smaller than the mesa width of the transistor section.

20. The semiconductor device according to claim 19.

21. The transistor section has a main region and a boundary region that is more adjacent to the diode section than the main region.

20. The semiconductor device according to claim 19.

22. The boundary region does not have the base region in a region where a contact hole for connecting the semiconductor substrate and the front surface electrode portion is provided.

22. The semiconductor device according to claim 21.

23. The boundary region is a first boundary mesa portion that does not include the base region in a region where a contact hole for connecting the semiconductor substrate and the front surface electrode portion is provided; a second boundary mesa portion provided closer to the main region than the first boundary mesa portion, the second boundary mesa portion including the base region in a region where a contact hole for connecting the semiconductor substrate and the front surface electrode portion is provided; 22. The semiconductor device according to claim 21, comprising:

24. an interlayer insulating film provided above the semiconductor substrate; a second conductivity type well region provided in the semiconductor substrate; Equipped with the base region extends in a trench extension direction from an end of the well region toward an end of a contact hole provided in the interlayer insulating film; In the trench extension direction, a distance L0 between the base region and the end of the contact hole is greater than 0 μm and is within a width Wd of a depletion layer that spreads from the base region toward the drift region.

20. The semiconductor device according to claim 19.

25. A semiconductor device including a transistor portion and a diode portion, a first conductivity type drift region provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; a front surface electrode portion provided above the front surface of the semiconductor substrate; Equipped with The transistor section A main area; a boundary region that is more adjacent to the diode portion than the main region; and the main region includes a base region of a second conductivity type provided above the drift region; The boundary region does not include the base region in a region where a contact hole for connecting the semiconductor substrate and the front surface electrode portion is provided. Semiconductor device.

26. The first conductivity type region of the boundary region occupies 50% or more of a mesa portion at a depth shallower than the bottom end of the base region.

26. The semiconductor device according to claim 25.

27. The diode section has an anode region of a second conductivity type provided above the drift region.

27. The semiconductor device according to claim 25 or 26.

28. A semiconductor device including a diode portion, a first conductivity type drift region provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; a front surface electrode portion provided above the front surface of the semiconductor substrate; Equipped with the diode section has a first conductivity type mesa region provided in a mesa section between the plurality of trench sections, The front surface electrode portion forms a Schottky junction with the first conductivity type mesa region. Semiconductor device.

29. The front surface electrode portion covers the upper portions of the plurality of trench portions and the upper portions of the plurality of mesa portions between the plurality of trench portions in the diode portion, and is in contact with the plurality of trench portions and the plurality of mesa portions.

29. The semiconductor device according to claim 28.

Images