Light emitting element, display device including the same, and method for manufacturing light emitting element

Abstract

To provide a light-emitting element with improved luminous efficiency, a display device incorporating the same, and a method for manufacturing the light-emitting element.SOLUTION: A light emitting element according to one embodiment comprises: a p-type semiconductor layer including a trench; a first insulating layer disposed on the p-type semiconductor layer around the trench; a light emitting layer disposed within the trench and including a side surface surrounded by the p-type semiconductor layer and the first insulating layer; and an n-type semiconductor layer arranged on the light emitting layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a light-emitting device, a display device including the same, and a method for manufacturing the light-emitting device. [Background technology]

[0002] Display devices have become increasingly important with the development of multimedia. In response to this, various display devices have been developed, such as liquid crystal display devices (LCDs) and light-emitting display devices (LEDs). Among these, light-emitting display devices using light-emitting elements are applied to various types of electronic devices, including portable electronic devices, televisions, virtual reality (VR) devices, and augmented reality (AR) devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2009-182249 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a light emitting device with improved luminous efficiency, a display device including the same, and a method for manufacturing the light emitting device.

[0005] The objectives of the present invention are not limited to the technical objectives mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A light-emitting device according to one embodiment includes a p-type semiconductor layer including a groove; a first insulating layer disposed on the p-type semiconductor layer around the groove; a light-emitting layer disposed within the groove and including side surfaces surrounded by the p-type semiconductor layer and the first insulating layer; and an n-type semiconductor layer disposed on the light-emitting layer.

[0007] In one embodiment, the light emitting layer includes an upper layer portion that protrudes above the p-type semiconductor layer and is surrounded by the first insulating layer, and the remaining portion of the light emitting layer excluding the upper layer portion may be completely surrounded by the p-type semiconductor layer.

[0008] In one embodiment, the light emitting layer includes quantum well layers and barrier layers alternately arranged on the p-type semiconductor layer, and the quantum well layers may be arranged at a height equal to or less than the height of the p-type semiconductor layer.

[0009] In one embodiment, the light emitting layer includes quantum well layers and barrier layers alternately arranged on the p-type semiconductor layer, and the sides of the quantum well layers may be completely surrounded by the p-type semiconductor layer.

[0010] In one embodiment, the n-type semiconductor layer may include an edge portion that overlaps with the p-type semiconductor layer, and the first insulating layer may be interposed between the p-type semiconductor layer and the n-type semiconductor layer in the portion where the p-type semiconductor layer and the n-type semiconductor layer overlap.

[0011] In one embodiment, the first insulating layer may include a first opening overlapping the groove and a second opening exposing a portion of the p-type semiconductor layer, and the light emitting device may further include a first electrode located in the second opening and connected to the p-type semiconductor layer.

[0012] In an embodiment, the light emitting device may further include a second electrode coupled to the n-type semiconductor layer.

[0013] In an embodiment, the light emitting device may further include a contact electrode disposed on the n-type semiconductor layer and connected between the n-type semiconductor layer and the second electrode.

[0014] In one embodiment, the light emitting device may further include a second insulating layer disposed on the first insulating layer and covering a side surface of the n-type semiconductor layer.

[0015] In one embodiment, the second electrode may be disposed on the second insulating layer.

[0016] In one embodiment, the light-emitting element may further include at least two grooves including the groove and formed spaced apart in the p-type semiconductor layer; at least two light-emitting layers including the light-emitting layer and disposed within each of the at least two grooves and spaced apart from each other; and at least two n-type semiconductor layers including the n-type semiconductor layer and disposed on the at least two light-emitting layers and spaced apart from each other.

[0017] In one embodiment, the first insulating layer may include at least two openings corresponding to the at least two grooves and surround upper layer portions of the at least two light-emitting layers.

[0018] In one embodiment, the light emitting device may further include a second insulating layer disposed on the first insulating layer and covering side surfaces of the at least two n-type semiconductor layers.

[0019] A display device according to one embodiment includes a pixel including a first pixel electrode, a second pixel electrode, and a light-emitting element connected between the first pixel electrode and the second pixel electrode, and the light-emitting element includes a p-type semiconductor layer including a groove; a first insulating layer disposed on the p-type semiconductor layer around the groove; a light-emitting layer disposed in the groove and including sides surrounded by the p-type semiconductor layer and the first insulating layer; and an n-type semiconductor layer disposed on the light-emitting layer.

[0020] In one embodiment, the light emitting layer includes an upper layer portion that protrudes above the p-type semiconductor layer and is surrounded by the first insulating layer, and the remaining portion of the light emitting layer excluding the upper layer portion may be completely surrounded by the p-type semiconductor layer.

[0021] In one embodiment, the light emitting layer includes quantum well layers and barrier layers alternately arranged on the p-type semiconductor layer, and the quantum well layers may be completely surrounded on their sides by the p-type semiconductor layer.

[0022] In one embodiment, the n-type semiconductor layer may include an edge portion that overlaps with the p-type semiconductor layer, and the first insulating layer may be interposed between the p-type semiconductor layer and the n-type semiconductor layer in the portion where the p-type semiconductor layer and the n-type semiconductor layer overlap.

[0023] A method for manufacturing a light emitting device according to one embodiment includes the steps of: forming a p-type semiconductor layer on a substrate; forming a first insulating layer on the p-type semiconductor layer; forming a first opening in the first insulating layer to expose a portion of the p-type semiconductor layer; etching a portion of the p-type semiconductor layer to form a groove in the p-type semiconductor layer; forming a light emitting layer inside the groove; and forming an n-type semiconductor layer on the light emitting layer.

[0024] In one embodiment, the method for manufacturing the light-emitting device may further include forming a second opening in the first insulating layer at a position spaced from the groove, exposing another portion of the p-type semiconductor layer; and forming a first electrode on the other portion of the p-type semiconductor layer.

[0025] In one embodiment, the method for manufacturing the light-emitting device may further include forming a contact electrode on the n-type semiconductor layer; forming a second insulating layer on the first insulating layer to cover a side surface of the n-type semiconductor layer; and forming a second electrode connected to the contact electrode on the contact electrode and the second insulating layer.

[0026] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0027] It is possible to provide a light emitting device with improved luminous efficiency, a display device including the same, and a method for manufacturing the light emitting device.

[0028] The effects of the embodiments are not limited to the above examples, and various other effects are included within this specification. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a perspective view illustrating a light emitting device according to an embodiment. [Figure 2] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment. [Figure 3] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment. [Figure 4] FIG. 4 is an enlarged cross-sectional view of region A1 in FIG. 3. [Figure 5] FIG. 2 is a plan view illustrating an arrangement of a light-emitting layer and a first insulating layer according to an embodiment. [Figure 6] 1 is a cross-sectional view illustrating a light emitting device substrate including a light emitting device according to an embodiment. [Figure 7] 1 is a cross-sectional view illustrating a light emitting device substrate including a light emitting device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light emitting device according to an embodiment. [Figure 17]1 is a perspective view illustrating a display device according to an embodiment. [Figure 18] FIG. 18 is a plan view showing an embodiment of the A2 region of FIG. [Figure 19] 1 is a cross-sectional view illustrating a display panel according to an embodiment. [Figure 20] 1 is a cross-sectional view illustrating a display panel according to an embodiment. [Figure 21] 1 is a cross-sectional view illustrating a display panel according to an embodiment. [Figure 22] 1 is a cross-sectional view illustrating a display panel according to an embodiment. [Figure 23] FIG. 1 illustrates a virtual reality system including a display device according to one embodiment. [Figure 24] FIG. 1 illustrates a smart device including a display device according to one embodiment. [Figure 25] 1 illustrates a vehicle instrument panel and center fascia including a display device according to one embodiment. [Figure 26] 1 is a diagram illustrating a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0030] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0031] When elements or layers are referred to as being "on" other elements or layers, this includes all cases where other layers or elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the details shown.

[0032] The features of the various embodiments of the present invention may be partially or fully combined or combined with one another and may be technically linked and driven in various ways, and each embodiment may be implemented independently of the others or in conjunction with one another.

[0033] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0034] Fig. 1 is a perspective view showing a light-emitting element LE according to an embodiment. Fig. 2 is a cross-sectional view showing a light-emitting element LE according to an embodiment. Fig. 3 is a cross-sectional view showing a light-emitting element LE according to an embodiment. For example, Fig. 1 shows a schematic shape of the light-emitting element LE along a first direction DR1, a second direction DR2, and a third direction DR3, and Fig. 2 shows a cross-section of the light-emitting element LE along a plane including the first direction DR1 and the third direction DR3. Fig. 3 shows a cross-section of the light-emitting element LE along a plane including the second direction DR2 and the third direction DR3.

[0035] 1 to 3 show a state in which the light-emitting element LE is disposed on the substrate SUB, but the embodiment is not limited thereto. For example, the light-emitting element LE may be manufactured on the substrate SUB and then separated from the substrate SUB. Also, while FIGS. 1 to 3 show a case in which only one or two light-emitting elements LE are disposed on the substrate SUB, the embodiment is not limited thereto. For example, more than two light-emitting elements LE may be disposed on the substrate SUB.

[0036] 1 to 3, the light-emitting element LE is disposed on a substrate SUB. In one embodiment, a buffer layer BFL is disposed on the substrate SUB, and the light-emitting element LE is disposed on the buffer layer BFL.

[0037] In one embodiment, the light emitting element LE may have a generally rectangular shape in a planar or cross-sectional view (e.g., a horizontal or vertical cross-sectional view) and may have a stepped shape in which the height of one portion is different from the height of the other portion. However, the shape of the light emitting element LE is not limited to the shapes shown in FIGS. 1 to 3 and may be variously modified depending on the embodiment. For example, the planar or cross-sectional shape of the light emitting element LE or the light emitting layer EML of the light emitting element LE may be variously modified. For example, the light emitting element LE or the light emitting layer EML may have a polygonal shape other than a square, a circle, or other shapes in a planar or cross-sectional view. Furthermore, although FIGS. 1 to 3 show an embodiment in which the light emitting element LE and the light emitting layer EML have side surfaces that are substantially perpendicular to the substrate SUB, the embodiment is not limited thereto. For example, the light emitting element LE or the light emitting layer EML may have side surfaces that are inclined obliquely relative to the substrate SUB.

[0038] The first direction DR1, the second direction DR2, and the third direction DR3 shown in Figures 1 to 3 may be perpendicular to one another. As an example, the first direction DR1 and the second direction DR2 may be perpendicular to one another and define a plane parallel to the main surface (e.g., the top surface) of the substrate SUB. The third direction DR3 may be perpendicular to the first direction DR1 and the second direction DR2. As an example, the third direction DR3 is perpendicular to the main surface of the substrate SUB and may be the height direction or thickness direction of the substrate SUB or the light-emitting element LE.

[0039] In one embodiment, the light emitting device LE may be an inorganic light emitting device formed of an inorganic material. For example, the light emitting device LE may be an inorganic light emitting diode formed of a nitride-based semiconductor material (e.g., GaN, AlGaN, GaAlN, InGaN, AlInGaN, AlN, InN, or other nitride-based semiconductor material), a phosphide-based semiconductor material (e.g., GaP, GaInP, AlGaP, AlInP, AlGaInP, AlP, InP, or other phosphide-based semiconductor material), or other inorganic material. In one embodiment, the light emitting device LE is formed of a nitride-based semiconductor material including GaN and InGaN and can emit light of a specific color (e.g., red light, green light, or blue light). The material constituting the light emitting device LE and the color or wavelength of the light emitted from the light emitting device LE may vary depending on the embodiment.

[0040] In one embodiment, the light-emitting element LE may be a micro light-emitting diode (micro LED) having a small size in the micrometer (μm) range. For example, the light-emitting element LE may be a micro LED having a length in a first direction DR1 (e.g., a horizontal or vertical length), a length in a second direction DR2 (e.g., a vertical or horizontal length), and a length in a third direction DR3 (e.g., a thickness or height) of several to several hundred micrometers. In one embodiment, the length in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 of the light-emitting element LE may each be approximately 100 μm or less. However, the size of the light-emitting element LE is not limited thereto, and the light-emitting element LE may be manufactured in various sizes.

[0041] The light-emitting element LE may include a p-type semiconductor layer SEM1 (also referred to as a "first semiconductor layer"), an emission layer EML (also referred to as an "active layer"), and an n-type semiconductor layer SEM2 (also referred to as a "second semiconductor layer"), which are sequentially arranged on a substrate SUB. As an example, the p-type semiconductor layer SEM1, the emission layer EML, and the n-type semiconductor layer SEM2 may be sequentially arranged on the buffer layer BFL (or substrate SUB) along the third direction DR3. In an embodiment, the p-type semiconductor layer SEM1 may include a groove GRV (for example, a groove or a recess), and the emission layer EML may be arranged inside the groove GRV of the p-type semiconductor layer SEM1 and surrounded by at least the p-type semiconductor layer SEM1. Here, "surrounding" means, for example, that at least a portion of component A (e.g., the light-emitting layer EML) is located inside at least component B (e.g., the p-type semiconductor layer SEM1). The light-emitting layer EML being surrounded by the p-type semiconductor layer SEM1 means that the light-emitting layer EML is close enough to the p-type semiconductor layer SEM1 to increase the number of holes (+) in the light-emitting layer EML. As an example, this means that at least a portion of the light-emitting layer EML is in contact with the p-type semiconductor layer SEM1. For example, an embodiment in which at least a portion of the light-emitting layer EML is surrounded by at least the p-type semiconductor layer SEM1 means an embodiment in which at least a portion of the light-emitting layer EML is disposed inside the groove GRV, so that at least a portion of the light-emitting layer EML is located within and in contact with at least the p-type semiconductor layer SEM1. As shown in the examples of FIGS. 2 and 3, the light-emitting layer EML is completely embedded in the groove GRV, the side and bottom surfaces of the light-emitting layer EML are in contact with the inner surfaces of the p-type semiconductor layer SEM1 that form the groove GRV, the top surface of the light-emitting layer EML coincides with the opening of the groove GRV, and the top surface of the light-emitting layer EML is not in contact with the p-type semiconductor layer SEM1. In the examples of FIGS. 2 and 3, the top surface of the light-emitting layer EML is in contact with the n-type semiconductor layer SEM2. Note that a portion of the light-emitting layer EML may be located within the groove GRV, and the top surface of the light-emitting layer EML may be located above the opening of the groove GRV and outside the groove GRV. 2 and 3, the entire emitting layer EML may be located in the groove GRV, and the top surface of the emitting layer EML may be located in the groove GRV below the opening surface of the groove GRV. The trench GRV is formed in the P-type semiconductor layer SEM1 so as to be recessed from its surface in the depth direction (third direction DR3). In Figures 2 and 3, the trench GRV has a rectangular shape in cross-sectional view, with its lower surface extending along a plane including the first direction DR1 and the second direction DR2, its side surface extending along a plane including the second direction DR2 and the third direction DR3 or the first direction DR1 and the third direction DR3, and its opening surface extending along a plane including the first direction DR1 and the second direction DR2, like the lower surface. However, the shape of the trench GRV is not limited as long as the trench GRV is formed so that at least a part of the light-emitting layer EML is disposed therein; for example, the trench GRV may be arc-shaped or polygonal in cross-sectional view.

[0042] In some embodiments, the light emitting device LE may include at least two grooves GRV formed in the p-type semiconductor layer SEM1 and spaced apart from each other, and at least two light emitting layers EML disposed within and / or on each of the grooves GRV and spaced apart from each other. The light emitting device LE may also include at least two n-type semiconductor layers SEM2 disposed on the at least two light emitting layers EML and spaced apart from each other. However, the number of grooves GRV in the p-type semiconductor layer SEM1, the light emitting layers EML, and the n-type semiconductor layers SEM2 provided in the light emitting device LE is not particularly limited and may vary depending on the embodiment. For example, the light emitting device LE may include at least one groove GRV formed in the p-type semiconductor layer SEM1, at least one light emitting layer EML disposed within and / or on the groove GRV, and at least one n-type semiconductor layer SEM2 disposed on the light emitting layer EML.

[0043] In some embodiments, the light-emitting element LE may further include a first insulating layer INS1, a second insulating layer INS2, and a contact electrode CTE. In one embodiment, the light-emitting element LE may include a plurality of contact electrodes CTE individually disposed on the plurality of n-type semiconductor layers SEM2. In some embodiments, the light-emitting element LE may further include at least one of a first electrode ET1 and a second electrode ET2.

[0044] 2 and 3 disclose an embodiment in which the light emitting element LE includes all of the contact electrode CTE, the first electrode ET1, and the second electrode ET2, but the embodiment is not limited thereto. For example, at least one of the contact electrode CTE, the first electrode ET1, and the second electrode ET2 may be formed separately from the light emitting element LE and contact or be connected (for example, electrically connected) to the light emitting element LE. Alternatively, the light emitting element LE may include only one of the contact electrode CTE and the second electrode ET2.

[0045] The substrate SUB (also referred to as a "growth substrate" or "production substrate") may be a semiconductor substrate used in manufacturing the light-emitting element LE. The substrate SUB may be a manufacturing substrate or wafer suitable for epitaxial growth. For example, the p-type semiconductor layer SEM1, the light-emitting layer EML, and the n-type semiconductor layer SEM2 of the light-emitting element LE may be formed by epitaxial growth on the substrate SUB.

[0046] In one embodiment, the substrate SUB may be a substrate containing a material such as GaAs, silicon (Si), sapphire, SiC, GaN, or ZnO. For example, the substrate SUB may be a silicon or sapphire substrate. The type and material of the substrate SUB are not particularly limited as long as epitaxial growth for manufacturing the light emitting device LE can be smoothly performed. In one embodiment, the substrate SUB may be used as a substrate for epitaxial growth for manufacturing the light emitting device LE, and then may be finally separated from the light emitting device LE. For example, a plurality of light emitting devices LE may be simultaneously formed on the substrate SUB by epitaxial growth, and then the light emitting devices LE may be separated from the substrate SUB.

[0047] The buffer layer BFL is disposed on the substrate SUB. The buffer layer BFL may be formed to reduce the difference in lattice constant between the p-type semiconductor layer SEM1 and the substrate SUB. In one embodiment, the buffer layer BFL may include an undoped semiconductor material. "Undoped" refers to a semiconductor material that is not doped with impurities. However, impurities may be unavoidably mixed in during the manufacturing process. Therefore, a material with an impurity concentration below a predetermined concentration may also be considered undoped. The impurity concentration in an undoped material is, for example, a level that can reduce the difference in lattice constant between the p-type semiconductor layer SEM1 and the substrate SUB. For example, the buffer layer BFL may be an undoped semiconductor layer including a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the buffer layer BFL may be a single-layer or multi-layer semiconductor layer including undoped GaN, AlGaN, InGaN, InAlGaN, AlN, InN, or other nitride-based semiconductor material.

[0048] The p-type semiconductor layer SEM1 is disposed on the substrate SUB. The p-type semiconductor layer SEM1 may include a semiconductor material doped with a p-type dopant. For example, the p-type semiconductor layer SEM1 may include a nitride-based semiconductor material or a phosphide-based semiconductor material, and may further include a p-type dopant such as Mg, Zn, Ca, Se, or Ba. In one embodiment, the p-type semiconductor layer SEM1 may include GaN doped with a p-type dopant (e.g., p-GaN), but the material of the p-type semiconductor layer SEM1 is not limited thereto. In the examples of FIGS. 2 and 3, the p-type semiconductor layer SEM1 is disposed on the buffer layer BFL.

[0049] In an embodiment, the p-type semiconductor layer SEM1 may include at least one groove GRV, and an emission layer EML is disposed inside each groove GRV. Therefore, the p-type semiconductor layer SEM1 may surround the emission layer EML. For example, the p-type semiconductor layer SEM1 may cover the surface of the emission layer EML, including the bottom surface and side surface (or part of the side surface) of the emission layer EML. In one embodiment, the p-type semiconductor layer SEM1 may be in direct contact with the emission layer EML.

[0050] In one embodiment, the groove GRV may include a vertical sidewall extending in the third direction DR3. However, the shape of the groove GRV is not limited thereto. For example, the groove GRV may include a sidewall shaped like an inclined surface inclined with respect to the third direction DR3. The shape or size of the groove GRV may vary depending on the embodiment.

[0051] The light emitting layer EML is disposed on the p-type semiconductor layer SEM1. For example, the light emitting layer EML can be disposed directly on a portion of the p-type semiconductor layer SEM1 so as to be in contact with the p-type semiconductor layer SEM1.

[0052] In the embodiment, the light emitting layer EML may be disposed on the p-type semiconductor layer SEM1 in a form surrounded by the p-type semiconductor layer SEM1. For example, the light emitting layer EML may be disposed inside and / or on the groove GRV formed in the p-type semiconductor layer SEM1. For example, at least a portion of the light emitting layer EML may be disposed inside the groove GRV of the p-type semiconductor layer SEM1 (for example, on the upper part of the lower surface of the groove GRV) and surrounded or covered by the p-type semiconductor layer SEM1.

[0053] In one embodiment, the light-emitting layer EML may be formed to a height equal to or greater than the height of the p-type semiconductor layer SEM1, and the side surfaces of the light-emitting layer EML may be surrounded or covered by the p-type semiconductor layer SEM1 and the first insulating layer INS1 on the p-type semiconductor layer SEM1. For example, the light-emitting layer EML may include an upper portion protruding above the p-type semiconductor layer SEM1, and the upper portion of the light-emitting layer EML may be surrounded or covered by the first insulating layer INS1 disposed around the groove GRV. In the examples of FIGS. 2 and 3 , the upper surfaces of the upper portion of the light-emitting layer EML and the first insulating layer INS1 are flush with each other. However, this is not limited thereto, and the upper surface of the upper portion of the light-emitting layer EML may be located within the thickness of the first insulating layer INS1 or may protrude beyond the first insulating layer INS1. The remaining portion of the light-emitting layer EML excluding the upper portion (e.g., a portion of the light-emitting layer EML located below the upper portion) may be completely surrounded or covered by the p-type semiconductor layer SEM1.

[0054] The light-emitting layer EML may be interposed between the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2. The light-emitting layer EML can emit light by recombination of electron-hole pairs in response to an electric signal applied via the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2.

[0055] The light-emitting layer EML may include a nitride-based semiconductor material, a phosphide-based semiconductor material, or other semiconductor material and may have a single or multiple quantum well structure. In one embodiment, the light-emitting layer EML may include at least one of GaN and InGaN and have a multiple quantum well structure. For example, the light-emitting layer EML may include a quantum well layer including InGaN and a barrier layer including GaN, AlGaN, or GaAlN. When the light-emitting layer EML includes InGaN, the color of light emitted from the light-emitting layer EML may vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength band of the light emitted from the light-emitting layer EML may shift toward the red wavelength band, and as the indium (In) content decreases, the wavelength band of the light emitted from the light-emitting layer EML may shift toward the blue wavelength band. The material or structure of the light-emitting layer EML may vary depending on the embodiment.

[0056] The first insulating layer INS1 may be disposed on the p-type semiconductor layer SEM1 and may surround the trench GRV. For example, the first insulating layer INS1 may be disposed on the p-type semiconductor layer SEM1 around the trench GRV and may have an opening corresponding to the trench GRV.

[0057] The first insulating layer INS1 may cover a portion of the p-type semiconductor layer SEM1 and expose another portion of the p-type semiconductor layer SEM1. For example, the first insulating layer INS1 may expose the p-type semiconductor layer SEM1 at least in the region where the groove GRV is formed. In one embodiment, the first insulating layer INS1 may be opened to expose a portion of the p-type semiconductor layer SEM1 at a position spaced apart from the groove GRV. A first electrode ET1 may be disposed on the exposed portion of the p-type semiconductor layer SEM1. In the example of FIG. 3 etc., the first insulating layer INS1 is not disposed within the groove GRV, but covers at least a portion of the p-type semiconductor layer SEM1 in an adjacent region corresponding to the opening in the p-type semiconductor layer SEM1 corresponding to the groove GRV. The first insulating layer INS1 is not formed in a position (other portion) spaced apart from the adjacent region corresponding to the opening in the p-type semiconductor layer SEM1, and the first electrode ET1 is disposed in this other exposed portion of the p-type semiconductor layer SEM1.

[0058] The first insulating layer INS1 may cover a portion of the side surface of the light-emitting layer EML. For example, the first insulating layer INS1 may cover the side surface of an upper portion of the light-emitting layer EML that protrudes above the p-type semiconductor layer SEM1. The first insulating layer INS1 may stably suppress contact (for example, direct contact) or bonding between the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2, thereby ensuring the electrical stability of the light-emitting element LE.

[0059] In one embodiment, the p-type semiconductor layer SEM1 may include at least two grooves GRV that are separated or spaced apart from each other, and the first insulating layer INS1 may include at least two openings corresponding to the at least two grooves GRV. Also, the first insulating layer INS1 may surround or cover upper layer portions of the at least two light emitting layers EML arranged in the at least two grooves GRV.

[0060] The first insulating layer INS1 is made of silicon oxide (SiO x ) (for example, SiO2), silicon nitride (SiN x ) (for example, Si3N4), aluminum oxide (Al x O y ) (for example, Al2O3), titanium oxide (Ti x Oy ) (for example, TiO2) and hafnium oxide (HfO x ) or other insulating materials. In one embodiment, the first insulating layer INS1 may include, but is not limited to, a material suitable for use as a mask in a process of forming the trench GRV in the p-type semiconductor layer SEM1.

[0061] The n-type semiconductor layer SEM2 is disposed on the light-emitting layer EML. For example, the n-type semiconductor layer SEM2 can be disposed on the light-emitting layer EML so as to be in direct contact with the light-emitting layer EML. In one embodiment, the n-type semiconductor layer SEM2 can have a width wider than that of the light-emitting layer EML. For example, the n-type semiconductor layer SEM2 can include a central portion overlapping with the light-emitting layer EML and an edge portion overlapping with the p-type semiconductor layer SEM1 around the light-emitting layer EML. In the portion where the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2 overlap, a first insulating layer INS1 can be interposed between the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2. For example, the first insulating layer INS1 can be disposed between the edge of the n-type semiconductor layer SEM2 and the p-type semiconductor layer SEM1, thereby preventing direct contact between the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2.

[0062] The n-type semiconductor layer SEM2 may include a semiconductor material doped with an n-type dopant. For example, the n-type semiconductor layer SEM2 may include a nitride-based semiconductor material or a phosphide-based semiconductor material and may further include an n-type dopant such as Si, Ge, or Sn. In one embodiment, the n-type semiconductor layer SEM2 may include GaN doped with an n-type dopant (for example, n-GaN), but the material of the n-type semiconductor layer SEM2 is not limited thereto.

[0063] The contact electrode CTE is disposed on the n-type semiconductor layer SEM2. The contact electrode CTE protects the n-type semiconductor layer SEM2 and can smoothly connect the n-type semiconductor layer SEM2 to at least one electrode, circuit element, wiring, etc. In one embodiment, the contact electrode CTE may be connected between the n-type semiconductor layer SEM2 and the second electrode ET2.

[0064] The contact electrode CTE can include a metal, a metal oxide, or other conductive material. In one embodiment, the contact electrode CTE is a transparent electrode layer including a transparent conductive material, so that light generated in the light-emitting layer EML can pass through the contact electrode CTE.

[0065] The second insulating layer INS2 is disposed on the first insulating layer INS1. The second insulating layer INS2 can surround or cover the side surfaces of the n-type semiconductor layer SEM2 to protect the n-type semiconductor layer SEM2. In the example of FIG. 3, the first insulating layer INS1 is formed on the p-type semiconductor layer SEM1 in an adjacent region corresponding to the trench GRV, while the first electrode ET1 is formed on the p-type semiconductor layer SEM1 at a position spaced apart from the adjacent region. The second insulating layer INS2 is formed on the first insulating layer INS1 and surrounds the side surfaces of the second insulating layer INS2 on the light-emitting layer EML. In one embodiment, the second insulating layer INS2 can further cover at least a portion of the contact electrode CTE. For example, the second insulating layer INS2 can be formed to a height equal to or greater than the height of the n-type semiconductor layer SEM2 and can cover a portion of the side surfaces of the contact electrode CTE.

[0066] The second insulating layer INS2 may be a single-layer or multi-layer insulating layer including at least one insulating material. In one embodiment, the second insulating layer INS2 includes an organic insulating layer including at least one organic insulating material, and can planarize one surface of the light emitting element LE on which the n-type semiconductor layer SEM2 and the like are disposed.

[0067] In one embodiment, the p-type semiconductor layer SEM1 includes at least two grooves GRV that are separated or spaced apart from each other, and the second insulating layer INS2 may surround or cover the side surfaces of at least two n-type semiconductor layers SEM2 that are arranged on top of the light emitting layer EML that are arranged in the at least two grooves GRV.

[0068] The first electrode ET1 may be disposed on the p-type semiconductor layer SEM1 and coupled (for example, electrically connected) to the p-type semiconductor layer SEM1. For example, the first electrode ET1 may be disposed directly on a portion of the p-type semiconductor layer SEM1 exposed in the opened region of the first insulating layer INS1 and the second insulating layer INS2 and coupled to the p-type semiconductor layer SEM1. The first electrode ET1 may include at least one conductive material (for example, a metal, a metal oxide, or another conductive material).

[0069] The second electrode ET2 may be disposed on the contact electrode CTE and the second insulating layer INS2 and may be coupled (for example, electrically connected) to the n-type semiconductor layer SEM2. For example, the second electrode ET2 may be disposed on a portion of each of the contact electrode CTE and the second insulating layer INS2 and may be electrically connected to the n-type semiconductor layer SEM2 via the contact electrode CTE. The second electrode ET2 may include at least one conductive material. In one embodiment, the first electrode ET1 and the second electrode ET2 may include, but are not limited to, the same conductive material.

[0070] In one embodiment, the first electrode ET1 and the second electrode ET2 may be disposed on the upper surface of the light-emitting element LE and may be located at different heights on the substrate SUB. However, the embodiment is not limited thereto. For example, the first electrode ET1 and the second electrode ET2 may be disposed on different surfaces of the light-emitting element LE to face each other, or the light-emitting element LE may not include at least one of the first electrode ET1 and the second electrode ET2. For example, the light-emitting element LE may not include the second electrode ET2, and the contact electrode CTE of the light-emitting element LE may be directly connected to a pixel electrode provided on a backplane substrate of the display panel.

[0071] According to the above-described embodiment, the groove GRV is formed in the p-type semiconductor layer SEM1, and the light-emitting layer EML is disposed inside the groove GRV, thereby surrounding or covering the light-emitting layer EML with the p-type semiconductor layer SEM1. According to the embodiment, the occurrence of surface defects (e.g., surface states) in the light-emitting element LE is suppressed or reduced, thereby suppressing non-radiative recombination due to the surface defects and increasing the amount of holes injected into the light-emitting layer EML. For example, by surrounding or covering the side surfaces of the light-emitting layer EML with the p-type semiconductor layer SEM1, the crystal bonding of the light-emitting element LE is improved, and holes, which travel a shorter distance than electrons, can also be smoothly injected into the light-emitting layer EML. Therefore, the radiative bonding of holes and electrons is increased, thereby improving the luminous efficiency of the light-emitting element LE.

[0072] In some embodiments, the light-emitting element LE includes a first insulating layer INS1 disposed on the p-type semiconductor layer SEM1 around the groove GRV in which the light-emitting layer EML is disposed, and the side surfaces of the light-emitting layer EML may be surrounded by the p-type semiconductor layer SEM1 and the first insulating layer INS1. For example, the upper layer portion of the light-emitting layer EML may be surrounded by the first insulating layer INS1, and the remaining portion of the light-emitting layer EML may be surrounded by the p-type semiconductor layer SEM1. This makes it possible to stably suppress contact or bonding between the p-type semiconductor layer SEM1 and the n-type semiconductor layer SEM2. This prevents driving defects of the light-emitting element LE and further improves the light-emitting efficiency of the light-emitting element LE.

[0073] Figure 4 is an enlarged cross-sectional view of region A1 in Figure 3. For example, Figure 4 shows the detailed structure of the emitting layer EML shown in Figures 2 and 3, and the paths of holes (+) and electrons (-) flowing into the emitting layer EML. In Figure 4, solid arrows indicate the direction of hole (+) movement, and dotted arrows indicate the direction of electron (-) movement.

[0074] 1 to 4, the light emitting layer EML may have a multiple quantum well structure including a barrier layer BRL and a quantum well layer QWL. For example, the light emitting layer EML may include a plurality of quantum well layers QWL and a plurality of barrier layers BRL alternately arranged on the p-type semiconductor layer SEM1 (for example, on a portion of the p-type semiconductor layer SEM1 including the trench GRV) along the third direction DR3.

[0075] In one embodiment, the quantum well layer QWL may be disposed at a height equal to or less than the height of the p-type semiconductor layer SEM1. The side surfaces of the quantum well layer QWL may be completely surrounded or covered by the p-type semiconductor layer SEM1. This may effectively increase the amount of holes (+) injected into the quantum well layer QWL. For example, holes (+) may be injected from the p-type semiconductor layer SEM1 into the quantum well layer QWL via each side surface of the quantum well layer QWL as well as via each upper and / or lower surface of the quantum well layer QWL. This may more effectively improve the luminous efficiency of the light-emitting element LE. In the example of FIG. 4, the quantum well layer QWL is located in a groove GRV formed in the p-type semiconductor layer SEM1, and the side surfaces of the quantum well layer QWL are in contact with the p-type semiconductor layer SEM1. When multiple quantum well layers QWL are located in the groove GRV, the side surfaces of some of the quantum well layers QWL may be in contact with the p-type semiconductor layer SEM1, but it is preferable that the side surfaces of all of the quantum well layers QWL are in contact with the p-type semiconductor layer SEM1. More specifically, in the example of FIG. 4, the lowest barrier layer BRL is arranged so as to be in contact with the bottom surface of the groove GRV, and the lowest quantum well layer QWL is arranged on the lowest barrier layer BRL. Further, the barrier layers BRL and quantum well layers QWL are arranged alternately on top of that. The highest quantum well layer QWL is located in the groove GRV and in contact with the p-type semiconductor layer SEM1. The highest barrier layer BRL is located on the highest quantum well layer QWL. The n-type semiconductor layer SEM2 is arranged on the highest barrier layer BRL. The side surface of the uppermost barrier layer BRL is in contact with the first insulating layer INS1. Note that the side surface of the uppermost barrier layer BRL may be in contact with the first insulating layer INS1 and the remaining part may be in contact with the p-type semiconductor layer SEM1.

[0076] 5 is a plan view illustrating an arrangement of the emitting layer EML and the first insulating layer INS1 according to one embodiment. For example, FIG. 5 schematically illustrates an arrangement of the emitting layer EML and the first insulating layer INS1 in a plan view at a position corresponding to area A1 in FIG.

[0077] 1 to 5, the first insulating layer INS1 includes a first opening OPN1 corresponding to the light emitting layer EML and is arranged around the light emitting layer EML. For example, the first insulating layer INS1 includes a first opening OPN1 overlapping the groove GRV of the p-type semiconductor layer SEM1 in which the light emitting layer EML is arranged, and is arranged on the p-type semiconductor layer SEM1 around the groove GRV, and can surround or cover at least a portion of the light emitting layer EML (the upper layer portion in the example of FIG. 3 etc.). In one embodiment, the light emitting element LE may include a plurality of light emitting layers EML arranged in a plurality of grooves GRV, and the first insulating layer INS1 may include a plurality of first openings OPN1 corresponding to the respective grooves GRV.

[0078] 5 shows an embodiment in which the groove GRV and the emitting layer EML have a rectangular planar shape, but the embodiment is not limited thereto. For example, the groove GRV and the emitting layer EML may have a planar shape corresponding to a non-rectangular polygon, a circle, or other shapes. Furthermore, the first insulating layer INS1 may include a first opening OPN1 having a shape suitable for the shape of the groove GRV and the emitting layer EML.

[0079] Fig. 6 is a cross-sectional view showing a light emitting device substrate LSUB including a light emitting device LE according to an embodiment. Fig. 7 is a cross-sectional view showing a light emitting device substrate LSUB including a light emitting device LE according to an embodiment. Figs. 6 and 7 show different embodiments in relation to the size of the light emitting device LE.

[0080] 6 and 7 in addition to FIGS. 1 to 5, the light-emitting element substrate LSUB may include a substrate SUB and a plurality of light-emitting elements LE disposed on the substrate SUB. As an example, the light-emitting element substrate LSUB may include a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 disposed spaced apart from each other on the substrate SUB along the first direction DR1. Each of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may have substantially the same or similar structure as the light-emitting element LE according to the embodiment of FIGS. 1 to 5.

[0081] 6 and 7 show a light emitting element substrate LSUB in which a plurality of light emitting elements LE are arranged on the substrate SUB along the first direction DR1, but the embodiment is not limited thereto. For example, the light emitting element substrate LSUB may include a plurality of light emitting elements LE arranged in at least one of the first direction DR1 and the second direction DR2. As an example, the light emitting element substrate LSUB may include a plurality of light emitting elements LE arranged along the second direction DR2.

[0082] In one embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed together on a substrate SUB and patterned to be separated or spaced apart from one another. For example, after forming the light-emitting layer EML and the n-type semiconductor layer SEM2 of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be separated into individual patterns by etching the p-type semiconductor layer SEM1.

[0083] In one embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may include light-emitting layers EML that emit light of the same color, and the light-emitting layers EML of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed substantially simultaneously. For example, the light-emitting layers EML of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed substantially simultaneously by epitaxial regrowth with the respective grooves GRV exposed.

[0084] Alternatively, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may include light-emitting layers EML emitting light of different colors, and the light-emitting layers EML of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed sequentially or in stages. For example, grooves GRVs are sequentially exposed at positions corresponding to the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3. The light-emitting layers EML of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed sequentially or in stages by epitaxial regrowth in and / or on the exposed grooves GRV. That is, for example, the groove GRV corresponding to the first light-emitting element LE1 is exposed, and the light-emitting layer EML of the first light-emitting element LE1 is formed in the groove GRV by epitaxial regrowth. Next, the groove GRV corresponding to the second light-emitting element LE2 is exposed, and the light-emitting layer EML of the second light-emitting element LE2 is formed in the groove GRV by epitaxial regrowth. Next, the groove GRV corresponding to the third light-emitting element LE3 is exposed, and the light-emitting layer EML of the third light-emitting element LE3 is formed in the groove GRV by epitaxial regrowth.

[0085] In one embodiment, the light emitting element substrate LSUB may include light emitting elements LE of uniform size (for example, the same area, height, and / or volume as one another). For example, as shown in FIG. 6, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be formed to have substantially the same size. In addition, the light emitting layers EML of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may also be formed to have substantially the same size.

[0086] In another embodiment, the light-emitting element substrate LSUB may include at least two light-emitting elements LE having different sizes. In one embodiment, as shown in FIG. 7, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed with different sizes, and the light-emitting layers EML of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be formed with different sizes. For example, the second light-emitting element LE2 may be formed with a smaller size than the first light-emitting element LE1 and the third light-emitting element LE3, and the light-emitting layer EML of the second light-emitting element LE2 may be formed with a smaller size than the light-emitting layer EML of the first light-emitting element LE1 and the light-emitting layer EML of the third light-emitting element LE3. The third light-emitting element LE3 may be formed with a larger size than the first light-emitting element LE1 and the second light-emitting element LE2, and the light-emitting layer EML of the third light-emitting element LE3 may be formed with a larger size than the light-emitting layer EML of the first light-emitting element LE1 and the light-emitting layer EML of the second light-emitting element LE2. Alternatively, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be formed to have substantially the same size, and the light emitting layers EML of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be formed to have different sizes. Alternatively, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be formed to have different sizes, and the light emitting layers EML of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be formed to have substantially the same size. Examples of the multiple light-emitting elements LE being of different sizes include when the lengths in the first direction DR1 of the multiple light-emitting elements LE are different in cross-sectional view as shown in Figure 7 (the length in the first direction between the ends of separated light-emitting elements LE, the lengths of the parts indicated by LE1, LE2, and LE3 in the example of Figure 7), when the lengths in the second direction DR2 of the multiple light-emitting elements LE are different in cross-sectional view, when the lengths in the third direction DR3 of the multiple light-emitting elements LE are different in cross-sectional view, when the areas of the multiple light-emitting elements LE are different in plan view, and when the volumes of the multiple light-emitting elements LE are different. Furthermore, examples of the light-emitting layers EML of multiple light-emitting elements LE being different in size include when the lengths in the first direction DR1 of the multiple light-emitting layers EML (the length in the first direction between the ends of separated light-emitting layers EML) are different in cross-sectional view as shown in Figure 7, when the lengths in the second direction DR2 of the multiple light-emitting layers EML are different in cross-sectional view, when the lengths in the third direction DR3 of the multiple light-emitting layers EML are different in cross-sectional view, when the areas of the multiple light-emitting layers EML are different in plan view, and when the volumes of the multiple light-emitting layers EML are different.

[0087] In one embodiment, light emitting elements LE having different sizes or light emitting layers EML having different sizes may emit light of different colors. However, the embodiment is not limited thereto. For example, light emitting elements LE emitting light of the same color may be formed in different sizes as needed.

[0088] 8 to 16 are cross-sectional views illustrating an example of a method for manufacturing a light emitting device LE according to an embodiment. For example, FIGS. 8 to 16 sequentially illustrate manufacturing steps for manufacturing a light emitting device LE according to the embodiment of FIGS.

[0089] 8, a substrate SUB for manufacturing a light emitting element LE is prepared using an epitaxial growth method, and a p-type semiconductor layer SEM1 is formed on the substrate SUB. In one embodiment, a buffer layer BFL is first formed on the substrate SUB, and then the p-type semiconductor layer SEM1 is formed on the buffer layer BFL.

[0090] The substrate SUB may be a semiconductor substrate suitable for epitaxial growth. The substrate SUB may be a semiconductor substrate including any of the materials listed above. By way of example, but not limited to, the substrate SUB may be a silicon or sapphire substrate.

[0091] Once the substrate SUB is prepared, a buffer layer BFL is formed on the substrate SUB. In one embodiment, the buffer layer BFL may be formed of an undoped semiconductor material including the materials exemplified above (e.g., undoped GaN).

[0092] Thereafter, a p-type semiconductor layer SEM1 is formed on the buffer layer BFL. In one embodiment, the p-type semiconductor layer SEM1 may be formed of any of the semiconductor materials exemplified above and may be doped to include a p-type dopant. As an example, the p-type semiconductor layer SEM1 may be formed of a semiconductor layer including GaN doped with a p-type dopant (for example, p-GaN), but is not limited thereto.

[0093] In one embodiment, the buffer layer BFL and the p-type semiconductor layer SEM1 may be formed on the substrate SUB by epitaxial growth. For example, the buffer layer BFL and the p-type semiconductor layer SEM1 may be sequentially formed on the substrate SUB by epitaxial growth using a process technique such as MOCVD (Metal-organic Chemical Vapor Deposition), MOVPE (Metal-organic Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy), LPE (Liquid Phase Epitaxy), or VPE (Vapor Phase Epitaxy). The materials and methods for forming the buffer layer BFL and the p-type semiconductor layer SEM1 are not limited to the exemplified materials and methods and may vary depending on the embodiment.

[0094] 9 and 10, a first insulating layer INS1 is formed on the p-type semiconductor layer SEM1. For example, as shown in FIG. 9, the first insulating layer INS1 may be formed over the entire surface of the p-type semiconductor layer SEM1. In one embodiment, the first insulating layer INS1 may be formed using any of the insulating materials exemplified above. The first insulating layer INS1 may be formed by a deposition method using a process technique such as ALD or CVD, but the method for forming the first insulating layer INS1 is not limited thereto.

[0095] 10, a first opening OPN1 is formed in the first insulating layer INS1. For example, the first opening OPN1 can be formed in the first insulating layer INS1 by etching the first insulating layer INS1 to expose a portion of the p-type semiconductor layer SEM1 corresponding to the region where the light emitting layer EML is to be formed. In an embodiment, when manufacturing a light emitting device LE including a plurality of light emitting layers EML, a plurality of first openings OPN1 can be formed in each light emitting device region where the respective light emitting devices LE are to be formed. In an embodiment, by adjusting or changing the size of the first opening OPN1, the size of the light emitting layer EML formed in the first opening OPN1 and / or the size of the light emitting device LE including the light emitting layer EML can be appropriately adjusted or changed.

[0096] 11 , the grooves GRV are formed in the p-type semiconductor layer SEM1. In one embodiment, the p-type semiconductor layer SEM1 can be etched using the first insulating layer INS1 as a mask. For example, the grooves GRV can be formed in the p-type semiconductor layer SEM1 by etching a portion of the p-type semiconductor layer SEM1 exposed by the first openings OPN1 in the first insulating layer INS1 to a partial thickness. In one embodiment, in each light emitting element region, a plurality of first openings OPN1 can be formed in the first insulating layer INS1, and a plurality of grooves GRV can be formed in the p-type semiconductor layer SEM1.

[0097] A patterned substrate is prepared by the above-described manufacturing process, in which regions where the light emitting layer EML, etc. are to be formed are defined. As an example, the patterned substrate is prepared as a p-type semiconductor substrate including a p-type semiconductor layer SEM1 grown on a substrate SUB and etched to include the trench GRV, and the remaining portion excluding the trench GRV is covered with a first insulating layer INS1.

[0098] 12, an emission layer EML is formed inside the groove GRV of the p-type semiconductor layer SEM1 (or the groove GRV defined by the p-type semiconductor layer SEM1 and the first insulating layer INS1). In one embodiment, the emission layer EML may be formed of any of the semiconductor materials exemplified above and may have a multiple quantum well structure including a barrier layer BRL and a quantum well layer QWL. For example, the emission layer EML having a multiple quantum well structure may be formed by alternately forming barrier layers BRL including GaN, AlGaN, or GaAlN and quantum well layers QWL including InGaN on a portion of the p-type semiconductor layer SEM1 exposed by the first opening OPN1.

[0099] In one embodiment, the light emitting layer EML may be formed to a height equal to or greater than the height of the p-type semiconductor layer SEM1. As an example, the light emitting layer EML may be formed to a height equal to or greater than the height of the first insulating layer INS1. In one embodiment, each quantum well layer QWL may be formed to a height equal to or less than the height of the p-type semiconductor layer SEM1, and therefore may be surrounded or covered by the p-type semiconductor layer SEM1. In one embodiment, the barrier layer BRL located at the top of the light emitting layer EML may be formed to a height equal to or greater than the height of the p-type semiconductor layer SEM1, and may be surrounded or covered by the first insulating layer INS1.

[0100] 13, an n-type semiconductor layer SEM2 is formed on the light-emitting layer EML. In one embodiment, the n-type semiconductor layer SEM2 may be formed of any of the semiconductor materials exemplified above and doped to include an n-type dopant. As an example, the n-type semiconductor layer SEM2 may be formed of a semiconductor layer including GaN doped with an n-type dopant (for example, n-GaN), but is not limited thereto.

[0101] In one embodiment, the n-type semiconductor layer SEM2 may be formed to have a larger area than the light emitting layer EML. For example, a portion of the n-type semiconductor layer SEM2 may be formed on a portion of the first insulating layer INS1 adjacent to the groove GRV.

[0102] In one embodiment, the light emitting layer EML and the n-type semiconductor layer SEM2 may be formed on the p-type semiconductor layer SEM1 by epitaxial regrowth (or epitaxial growth). For example, the light emitting layer EML and the n-type semiconductor layer SEM2 may be sequentially formed on the p-type semiconductor layer SEM1 by epitaxial regrowth using a process technique such as MOCVD, MOVPE, MBE, LPE, or VPE. The materials and methods for forming the light emitting layer EML and the n-type semiconductor layer SEM2 are not limited to the exemplified materials and methods and may vary depending on the embodiment.

[0103] 14, a contact electrode CTE is formed on the n-type semiconductor layer SEM2. When manufacturing a light-emitting element LE that does not include a contact electrode CTE, the step of forming the contact electrode CTE does not need to be performed.

[0104] In one embodiment, the contact electrode CTE may be formed of the above-mentioned exemplified conductive material (for example, a transparent conductive material). The contact electrode CTE may be formed in a shape corresponding to the n-type semiconductor layer SEM2. For example, the contact electrode CTE may be formed in a shape and / or size corresponding to the shape (for example, a planar shape) and / or size (for example, an area) of the n-type semiconductor layer SEM2 in a plan view.

[0105] Referring to FIG. 15, a second insulating layer INS2 is formed on the first insulating layer INS1. In one embodiment, the second insulating layer INS2 is formed of the insulating material (e.g., an organic insulating material) exemplified above and can reduce steps due to the n-type semiconductor layer SEM2 and / or the contact electrode CTE. In one embodiment, the second insulating layer INS2 is formed to a height equal to or greater than the height of the n-type semiconductor layer SEM2 and can surround or cover the side surfaces of the n-type semiconductor layer SEM2. In one embodiment, the second insulating layer INS2 can be formed to a height equal to or less than the height of the contact electrode CTE. Therefore, the top surface of the contact electrode CTE can be exposed. In one embodiment, the second insulating layer INS2 can be formed to surround or cover a portion (e.g., a lower portion) of the contact electrode CTE.

[0106] 16, at a position away from the groove GRV, for example, at a position where the light emitting element LE is not formed, the first insulating layer INS1 and the second insulating layer INS2 may be etched to expose a portion of the p-type semiconductor layer SEM1. For example, by etching the first insulating layer INS1 and the second insulating layer INS2 at a position away from the groove GRV, a second opening OPN2 may be formed in the first insulating layer INS1 and the second insulating layer INS2. The second opening OPN2 may expose a portion of the p-type semiconductor layer SEM1 at a position away from the groove GRV.

[0107] In one embodiment, when manufacturing the light-emitting element LE including the first electrode ET1 and the second electrode ET2 shown in FIG. 3, a process of forming the first electrode ET1 and the second electrode ET2 may be further performed after the process of FIG. 16. For example, the first electrode ET1 may be formed on a portion of the p-type semiconductor layer SEM1 exposed by the second opening OPN2, and the second electrode ET2 may be formed on the second insulating layer INS2 and the contact electrode CTE. In one embodiment, a portion of the second electrode ET2 may be disposed directly on the contact electrode CTE. Therefore, the second electrode ET2 may be connected to the contact electrode CTE.

[0108] When manufacturing a plurality of light emitting elements LE on the substrate SUB, a process of etching the p-type semiconductor layer SEM1, etc. to form the light emitting elements LE into individual patterns may be further performed after the process of Fig. 16. For example, as shown in Fig. 6 or 7, the light emitting elements LE may be patterned into individual patterns so that they are spaced apart or separated from one another on the substrate SUB. For example, as shown in Fig. 16, with the substrate SUB, buffer layer BFL, p-type semiconductor layer SEM1, light emitting layer EML formed in the groove GRV of the p-type semiconductor layer SEM1, first insulating layer INS1, n-type semiconductor layer SEM2, second insulating layer INS2, and contact electrode CTE formed, the p-type semiconductor layer SEM1, the first insulating layer INS1, and the second insulating layer INS2 between each light emitting element are etched to separate each light emitting element LE.

[0109] In one embodiment, when manufacturing the light emitting element LE (or the light emitting element LE) separated from the substrate SUB or transferring the light emitting element LE to a backplane substrate of a display panel, a process of separating the light emitting element LE from the substrate SUB may be further performed. In one embodiment, the substrate SUB may be separated from the light emitting element LE by electrical and / or chemical etching, laser lift-off, or other methods.

[0110] Fig. 17 is a perspective view showing a display device 10 according to an embodiment. Fig. 18 is a plan view showing an embodiment of the A2 region of Fig. 17.

[0111] 17 and 18, a display device 10 according to an embodiment may include a display panel 100 including a display area DA and a non-display area NDA.

[0112] The display panel 100 may have a rectangular planar shape with longer sides in a first direction DR1 and shorter sides in a second direction DR2. In Figures 17 and 18, the first direction DR1 indicates the horizontal (or vertical) direction of the display panel 100, and the second direction DR2 indicates the vertical (or horizontal) direction of the display panel 100. The third direction DR3 indicates the thickness or height direction of the display panel 100. However, the planar shape of the display panel 100 is not limited to this, and the display panel 100 may have a different shape. For example, the display panel 100 may have a polygonal, circular, elliptical, or irregular planar shape in addition to a rectangular shape.

[0113] The display area DA may be an area where an image is displayed, and the non-display area NDA may be an area where an image is not displayed. In one embodiment, the planar shape of the display area DA may conform to the planar shape of the display panel 100. FIG. 1 illustrates an example in which the planar shape of the display area DA is rectangular. The display area DA is disposed in the central area of ​​the display panel 100. The non-display area NDA is disposed on the periphery of the display area DA. As an example, the non-display area NDA may surround the display area DA.

[0114] The display panel 100 may include a number of pixels PX arranged in a display area DA. For example, the display panel 100 may include a first pixel PX1 (e.g., a first-color subpixel) emitting light of a first color, a second pixel PX2 (e.g., a second-color subpixel) emitting light of a second color, and a third pixel PX3 (e.g., a third-color subpixel) emitting light of a third color. In an embodiment, the first color may be blue, the second color may be green, and the third color may be red, but is not limited thereto. At least one first pixel PX1, at least one second pixel PX2, and at least one third pixel PX3 adjacent to each other may constitute a unit pixel UPX that can emit light of various colors. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 sequentially arranged along the first direction DR1 in the Kth (K is a natural number) row of the display area DA may constitute one unit pixel UPX. The number, type, and / or arrangement of the pixels PX constituting the unit pixel UPX may vary depending on the embodiment.

[0115] Each pixel PX may include at least one light-emitting element LE. In one embodiment, each pixel PX may include a light-emitting element LE according to at least one of the above-described embodiments. For example, as shown in FIGS. 1 to 5 , each pixel PX may include a light-emitting element LE including an emission layer EML disposed in a groove GRV of a p-type semiconductor layer SEM1 and surrounded by the p-type semiconductor layer SEM1 and a first insulating layer INS1.

[0116] The pixels PX may include light-emitting elements LE that emit light of the same color or light of different colors. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light-emitting elements LE that emit light of the same color (e.g., blue light or white light), and a light conversion pattern (e.g., a wavelength conversion pattern including quantum dots) and / or a color filter may be disposed in the light-emitting region of the first pixel PX1, the second pixel PX2, and / or the third pixel PX3 to convert or control the color of light emitted from the light-emitting element LE provided in each pixel PX. Alternatively, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light-emitting elements LE that emit light of a first color, light of a second color, and light of a third color, respectively.

[0117] The pixels PX may include light-emitting elements LE of substantially the same size or different sizes. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light-emitting elements LE of substantially the same size or different sizes.

[0118] In one embodiment, the pixels PX may be arranged in the display area DA in a matrix, stripe, or other shape. The size of the pixels PX (or the light-emitting areas of the pixels PX) may be substantially the same or different from one another. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may have substantially the same size (e.g., the same area) or different sizes from one another. The arrangement, position, size, etc. of the pixels PX may be variously changed depending on the embodiment.

[0119] In one embodiment, the pixel PX may have a quadrilateral planar shape such as a rectangle or a diamond, but the embodiment is not limited thereto. For example, the pixel PX may have a quadrilateral or other polygonal planar shape, a circle, an ellipse, or other shapes.

[0120] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad area PDA1, a second pad area PDA2, and a peripheral area PHA.

[0121] The first common voltage supply region CVA1 is disposed between the first pad region PDA1 and the display region DA. The second common voltage supply region CVA2 is disposed between the second pad region PDA2 and the display region DA. Each of the first common voltage supply region CVA1 and the second common voltage supply region CVA2 may include a common electrode connector CVS electrically connected to the second pixel electrode PXE2 of each pixel PX. A second pixel voltage (e.g., a low-potential pixel voltage or a common voltage) may be supplied to the pixel PX via the common electrode connector CVS.

[0122] The common electrode connector CVS is disposed in a common voltage supply region (e.g., the first common voltage supply region CVA1 and / or the second common voltage supply region CVA2) of the non-display area NDA. The common electrode connector CVS may include a conductive material (e.g., a metal material such as aluminum (Al)). Although FIGS. 17 and 18 illustrate a display device 10 in which the common electrode connector CVS is disposed in the non-display area NDA, the embodiment is not limited thereto. For example, the common electrode connector CVS may be disposed in the display area DA.

[0123] The common electrode connector CVS of the first common voltage supply region CVA1 may be electrically connected to one of the first pads PD1 of the first pad region PDA1. For example, the common electrode connector CVS of the first common voltage supply region CVA1 may receive a second pixel voltage from one of the first pads PD1 of the first pad region PDA1.

[0124] The first pad PD1 is disposed in the first pad area PDA1. The first pad PD1 may be connected to a circuit board (not shown) via a conductive connecting member. For example, the first pad PD1 may be electrically connected to a circuit pad provided on the circuit board via a wire.

[0125] The common electrode connector CVS of the second common voltage supply region CVA2 may be electrically connected to one of the second pads of the second pad region PDA2. For example, the common electrode connector CVS of the second common voltage supply region CVA2 may receive a second pixel voltage from one of the second pads of the second pad region PDA2. In some embodiments, the display panel 100 may not include the second common voltage supply region CVA2.

[0126] The first pad area PDA1 is disposed on one side (for example, the upper side) of the display panel 100. The first pad area PDA1 may include a first pad PD1 connected to an external circuit board.

[0127] The second pad area PDA2 is disposed on another side (for example, the bottom side) of the display panel 100. The second pad area PDA2 may include second pads connected to an external circuit board. In some embodiments, the display panel 100 may not include the second pad area PDA2.

[0128] The second pads are disposed in the second pad area PDA2 of the non-display area NDA. The second pads may be connected to a circuit board (not shown) via a conductive connecting member. For example, the second pads may be electrically connected to circuit pads provided on the circuit board via wires.

[0129] The peripheral area PHA may be the remaining area of ​​the non-display area NDA excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA may surround not only the display area DA but also the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0130] Figure 19 is a cross-sectional view of a display panel 100 according to an embodiment. For example, Figure 19 illustrates an embodiment of a cross-section of the display panel 100 corresponding to line X1-X1' in Figure 18, and shows a schematic cross-section of two pixels PX adjacent to each other in the second direction DR2.

[0131] FIG. 19 illustrates an embodiment in which the display device 10 is an LEDoS (Light Emitting Diode on Silicon) in which light emitting diodes are arranged as light emitting elements LE on a semiconductor circuit substrate (for example, a backplane substrate BP of a display panel 100 in which pixel circuits PXC and the like are formed based on a silicon wafer) formed by a semiconductor process using a silicon wafer. However, devices including the light emitting elements LE according to the embodiment are not limited thereto. For example, the light emitting elements LE manufactured according to the embodiment may be applied to display devices of other types and / or structures, or to devices of other types and / or structures, such as lighting devices. For example, the light emitting elements LE according to the above-described embodiment may also be applied to manufacturing devices of other types and / or structures.

[0132] 17 to 19, the display panel 100 may include a backplane substrate BP and a light emitting element LE disposed on the backplane substrate BP. The display panel 100 may further include electrodes and pixel structures disposed around the light emitting element LE on the backplane substrate BP.

[0133] In some embodiments, the display panel 100 may further include additional components, such as a light conversion layer for converting the color and / or wavelength of light emitted from at least some of the light emitting elements LE, a color filter layer for controlling each light emitting area EA to emit light of a specific color, and a light output structure (such as a lens) for improving the light output efficiency of the pixel PX.

[0134] The backplane substrate BP may include a display area DA in which the pixels PX are arranged. In one embodiment, the backplane substrate BP may be a semiconductor circuit substrate formed by a semiconductor process using a silicon wafer. For example, a silicon wafer may be used as a base member for forming the display panel 100. The backplane substrate BP may further include a non-display area NDA shown in FIGS. 17 and 18. In one embodiment, the backplane substrate BP may further include a common electrode connector CVS, a first pad PD1, and / or a second pad located in the non-display area NDA.

[0135] The backplane substrate BP may include pixel circuits PXC and wiring provided in the display area DA. In one embodiment, the wiring may include power wiring VSL connected to the second pixel electrodes PXE2 of the pixels PX, and the second pixel electrodes PXE2 may be connected to the common electrode connector CVS via the power wiring VSL. Alternatively, the second pixel electrodes PXE2 may be formed to be connected to each other in a mesh-like pattern within the display area DA and extend to the non-display area NDA to be directly connected to the common electrode connector CVS. The connection structure between the second pixel electrodes PXE2 and the common electrode connector CVS may also be modified in various ways depending on the embodiment. Figure 19 only shows the schematic locations of the pixel circuits PXC and the power wiring VSL.

[0136] Each pixel PX may include a first pixel electrode PXE1 and a second pixel electrode PXE2, and a light-emitting element LE coupled between the first pixel electrode PXE1 and the second pixel electrode PXE2. In one embodiment, each pixel PX may further include a pixel circuit PXC coupled to the first pixel electrode PXE1.

[0137] The pixel circuits PXC are provided in the display area DA corresponding to the areas where the respective pixels PX are formed. In one embodiment, each of the pixel circuits PXC may include a complementary metal-oxide semiconductor (CMOS) circuit formed on the backplane substrate BP using a semiconductor process.

[0138] Each of the pixel circuits PXC may include at least one transistor formed by a semiconductor process, and may further include at least one capacitor formed by a semiconductor process.

[0139] The pixel circuit PXC of each pixel PX may be electrically connected to the first pixel electrode PXE1 of the corresponding pixel PX. Each pixel circuit PXC may apply a first pixel voltage (e.g., a high-potential pixel voltage) to the first pixel electrode PXE1 connected thereto.

[0140] The pixel electrodes PXE and light-emitting elements LE of the pixels PX are disposed on the backplane substrate BP. In one embodiment, at least one of bonding electrodes BDE, banks BNK, and an insulating layer may be further disposed on the backplane substrate BP. In one embodiment, the insulating layer on the backplane substrate BP may include an inorganic film IOL, an organic film ORL, and an overcoat layer OC.

[0141] The pixel electrode PXE may include a first pixel electrode PXE1 and a second pixel electrode PXE2 of each pixel PX. The pixel electrode PXE may be a single-layer or multi-layer electrode including at least one conductive material.

[0142] In one embodiment, each first pixel electrode PXE1 may be electrically connected to the pixel circuit PXC of the corresponding pixel PX. Also, each first pixel electrode PXE1 may be electrically connected to the first electrode ET1 of the light-emitting element LE provided in the corresponding pixel PX. For example, each first pixel electrode PXE1 may be connected between the pixel circuit PXC of the corresponding pixel PX and the first electrode ET1 of the light-emitting element LE.

[0143] Each second pixel electrode PXE2 may be connected to at least one common electrode connector CVS or a power line VSL connected thereto. Also, each second pixel electrode PXE2 may be electrically connected to the second electrode ET2 of the light-emitting element LE provided in the corresponding pixel PX. For example, each second pixel electrode PXE2 may be connected between the power line VSL (or the common electrode connector CVS) and the second electrode ET2 of the light-emitting element LE.

[0144] At least one insulating layer is disposed around the pixel electrode PXE. For example, an inorganic film IOL is disposed around the pixel electrode PXE. The inorganic film IOL may expose at least a portion (for example, an upper surface) of the pixel electrode PXE. The inorganic film IOL may be made of at least one inorganic insulating material (for example, silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), hafnium oxide (HfO x ) or other inorganic insulating materials).

[0145] In one embodiment, a bonding electrode BDE is disposed on the pixel electrode PXE, for example, a first bonding electrode BDE1 is disposed on each first pixel electrode PXE1, and a second bonding electrode BDE2 is disposed on each second pixel electrode PXE2.

[0146] Each of the first bonding electrodes BDE1 is disposed between the first pixel electrode PXE1 of each pixel PX and the first electrode ET1 of the light-emitting element LE, and can connect the first pixel electrode PXE1 of each pixel PX to the first electrode ET1 of the light-emitting element LE.

[0147] In one embodiment, a bank BNK is disposed under each first bonding electrode BDE1. For example, the bank BNK may be disposed between each first pixel electrode PXE1 and the first bonding electrode BDE1, and at least a portion of the first bonding electrode BDE1 may protrude upward. This allows each first bonding electrode BDE1 to be properly contacted or connected to the first electrode ET1 of the light emitting element LE. In one embodiment, the bank BNK may include, but is not limited to, an organic insulating material.

[0148] Each second bonding electrode BDE2 is disposed between the second pixel electrode PXE2 of each pixel PX and the second electrode ET2 of the light-emitting element LE, and may connect the second pixel electrode PXE2 of each pixel PX and the second electrode ET2 of the light-emitting element LE.

[0149] The bonding electrode BDE may be a single-layer or multi-layer electrode including at least one conductive material. In one embodiment, the bonding electrode BDE may include a conductive bonding material suitable for bonding or adhering the light-emitting element LE to the pixel electrode PXE. For example, the bonding electrode BDE may be a single-layer or multi-layer electrode including gold (Au), copper (Cu), aluminum (Al), tin (Sn), or other metal material. In another embodiment, when the backplane substrate BP does not include the bonding electrode BDE and the light-emitting element LE is directly bonded or adhered to the pixel electrode PXE, the pixel electrode PXE may include a conductive material (for example, a metal material suitable for use as a bonding metal) that can be appropriately connected to the light-emitting element LE by a bonding process or an adhesion process.

[0150] The pixel PX may include a light-emitting element LE according to the above-described embodiments. For example, each pixel PX includes at least one light-emitting element LE connected between a first pixel electrode PXE1 and a second pixel electrode PXE2, and the light-emitting element LE may be a light-emitting element LE according to at least one of the embodiments shown in FIGS. 1 to 7. As an example, the light-emitting element LE provided in each pixel PX may include, as shown in FIGS. 1 to 3, a p-type semiconductor layer SEM1 including a groove GRV, a first insulating layer INS1 disposed on the p-type semiconductor layer SEM1 around the groove GRV, an emission layer EML disposed in the groove GRV and having side surfaces surrounded or covered by the p-type semiconductor layer SEM1 and the first insulating layer INS1, and an n-type semiconductor layer SEM2 disposed on the emission layer EML. In one embodiment, each light-emitting element LE may further include at least one of a contact electrode CTE, a second insulating layer INS2, a first electrode ET1, and a second electrode ET2. In one embodiment, each light-emitting element LE is disposed such that a surface on which the contact electrode CTE, the first electrode ET1, and the second electrode ET2 are formed faces the backplane substrate BP. Therefore, the first electrode ET1 and the second electrode ET2 can be bonded onto the bonding electrode BDE (or the pixel electrode PXE) as appropriate.

[0151] At least one insulating layer is disposed around the light emitting element LE. For example, an organic film ORL is disposed around the light emitting element LE. In one embodiment, the organic film ORL may be a filler filled between the light emitting elements LE. In one embodiment, the organic film ORL is formed to have substantially the same height as or a similar height to the light emitting element LE, thereby reducing the step caused by the light emitting element LE. The organic film ORL may include an organic insulating material. For example, the organic film ORL may be a single-layer or multi-layer organic insulating film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or other organic insulating material.

[0152] An overcoat layer OC is disposed on the light emitting element LE and the organic film ORL. In one embodiment, the overcoat layer OC may be disposed or formed over the entire display area DA. The overcoat layer OC may be a single-layer or multi-layer insulating layer including at least one insulating material.

[0153] In an embodiment, the display panel 100 may further include additional components. For example, the display panel 100 may further include at least one of a reflective layer and a light-shielding layer disposed around the light-emitting element LE, and a capping layer disposed between the light-emitting element LE and the overcoat layer OC.

[0154] 20 is a cross-sectional view of a display panel 100 according to an embodiment. For example, FIG. 20 illustrates an embodiment of a cross-section of the display panel 100 corresponding to line X1-X1' in FIG. 18, and shows a schematic cross-section of two pixels PX adjacent to each other in the second direction DR2.

[0155] Fig. 20 shows a cross section of a pixel PX in which the arrangement direction of the light-emitting element LE is different from that of the embodiment in Fig. 19. In describing the embodiment in Fig. 20, redundant descriptions of configurations that are the same as or similar to those in the embodiment in Fig. 19 will be omitted.

[0156] 17 to 20, each light-emitting element LE is arranged such that the surface on which the contact electrode CTE, first electrode ET1, and second electrode ET2 are formed faces the upper surface of the display panel 100. Each light-emitting element LE may be connected to the pixel electrode PXE via a bridge electrode BE. For example, the display panel 100 may further include a bridge electrode BE connected between the light-emitting element LE and the pixel electrode PXE. The first electrode ET1 of the light-emitting element LE may be connected to the first pixel electrode PXE1 via the first bridge electrode BE1, and the second electrode ET2 of the light-emitting element LE may be connected to the second pixel electrode PXE2 via the second bridge electrode BE2. In one embodiment, the display panel 100 may not include the bonding electrode BDE according to the embodiment of FIG. 19.

[0157] In one embodiment, the display panel 100 further includes a first organic film ORL1 disposed on the backplane substrate BP, and the light emitting element LE is disposed on the first organic film ORL1. In one embodiment, the first organic film ORL1 is disposed on the pixel electrode PXE so as to overlap at least a portion of the pixel electrode PXE in each pixel PX, but the embodiment is not limited thereto. In a process of transferring the light emitting element LE to the display panel 100, the light emitting element LE can be temporarily fixed or adhered by the first organic film ORL1.

[0158] The banks BNK are disposed on the backplane substrate BP and can define respective pixel regions (or light-emitting regions of the pixels PX) in which the respective light-emitting elements LE are disposed. In one embodiment, the banks BNK are disposed between the backplane substrate BP and the pixel electrodes PXE so as to overlap with portions of the pixel electrodes PXE. In one embodiment, the pixel electrodes PXE can be connected to respective pixel circuits PXC or power supply wiring VSL, etc., through respective contact holes (or via holes) that penetrate the banks BNK.

[0159] In one embodiment, the display panel 100 may further include a light-shielding layer BM disposed on the bank BNK. The light-shielding layer BM is disposed around the luminous region of the pixel PX in which the light-emitting element LE is disposed so as to surround the luminous region.

[0160] In one embodiment, the display panel 100 may further include a second organic film ORL2 disposed around the light emitting element LE. In one embodiment, the second organic film ORL2 is formed to have substantially the same or similar height as the light emitting element LE or the light blocking layer BM, thereby reducing steps caused by the light emitting element LE, the light blocking layer BM, etc.

[0161] In one embodiment, the display panel 100 may further include a capping layer CAP disposed over the entire surface of the second organic film ORL2 and the light-blocking layer BM, and an overcoat layer OC disposed on the capping layer CAP. In one embodiment, the capping layer CAP may include at least one inorganic insulating material suitable for blocking moisture permeation, etc.

[0162] FIG. 21 is a cross-sectional view of a display panel 100 according to an embodiment. FIG. 22 is a cross-sectional view of a display panel 100 according to an embodiment. For example, FIGS. 21 and 22 illustrate embodiments of a cross section of the display panel 100 corresponding to line X2-X2' in FIG. 18, and show different embodiments related to the size of the light-emitting element LE provided in the pixel PX. While FIGS. 21 and 22 illustrate a display panel 100 in which the surface on which the contact electrode CTE of the light-emitting element LE is formed faces the backplane substrate BP, as in the embodiment of FIG. 19, embodiments are not limited thereto.

[0163] 17 to 21, the pixel PX may include light-emitting elements LE of substantially the same size. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 provided in the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively, may be manufactured to have substantially the same size. In one embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be light-emitting elements that emit light of the same color. Alternatively, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be light-emitting elements that emit light of different colors. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit light of a first color, a second color, and a third color, respectively. The pixel PX may include respective light-emitting regions in which the respective light-emitting elements LE are disposed. The light-emitting regions of the pixel PX may have substantially the same size or different sizes.

[0164] 17 to 22, the pixel PX may include light emitting elements LE of different sizes. For example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 provided in the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively, may be manufactured to have different sizes. For example, the first light emitting element LE1 may be larger (e.g., wider area) than the second light emitting element LE2 and smaller (e.g., narrower area) than the third light emitting element LE3. The heights of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be substantially the same or different from each other.

[0165] In one embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be light-emitting elements that emit light of the same color. Alternatively, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be light-emitting elements that emit light of different colors. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit light of a first color, a second color, and a third color, respectively. In one embodiment, the size of the light-emitting element LE or the size of the light-emitting area in which the light-emitting element LE is disposed may be differentiated depending on the luminous efficiency of each light-emitting element LE or the pixel PX including the light-emitting element LE, the area of ​​the light-emitting area of ​​the pixel PX, the white balance of the light emitted from the pixel PX, etc.

[0166] The display device 10 according to the embodiments of Figures 17 to 22 may include a pixel PX including a light-emitting element LE according to at least one of the embodiments of Figures 1 to 7 (or a light-emitting element LE manufactured according to the embodiments of Figures 8 to 16), thereby improving the luminous efficiency of the pixel PX and the display device 10 including the pixel PX.

[0167] FIG. 23 is a diagram showing a virtual reality device 1 including a display device 10_1 according to an embodiment.

[0168] 23, the virtual reality device 1 according to an embodiment may be a device in the form of glasses. The virtual reality device 1 according to an embodiment includes a display device 10_1, a left eye lens 10a, a right eye lens 10b, a support frame 20, glasses frames 30a and 30b, a reflective member 40, and a display device housing 50.

[0169] 23 illustrates a virtual reality device 1 including eyeglass frames 30a and 30b, but the virtual reality device 1 according to an embodiment can also be applied to a head-mounted display including a head-mounted band that can be worn on the head instead of eyeglass frames 30a and 30b. For example, the virtual reality device 1 according to an embodiment is not limited to the form shown in FIG. 23 and can be applied in various forms to various other electronic devices.

[0170] The display device housing 50 may include a display device 10_1 and a reflective member 40. An image displayed on the display device 10_1 is reflected by the reflective member 40 and provided to the user's right eye through the right eye lens 10b. This allows the user to view the virtual reality image displayed on the display device 10_1 through the right eye.

[0171] 23 illustrates an example in which the display device housing 50 is disposed at the right end of the support frame 20, but the embodiment is not limited thereto. For example, the display device housing 50 may be disposed at the left end of the support frame 20. In this case, the image displayed on the display device 10_1 is reflected by the reflective member 40 and provided to the left eye of the user through the left eye lens 10a. This allows the user to view the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device housing 50 may be disposed at both the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10_1 through both the left and right eyes.

[0172] FIG. 24 is a diagram showing a smart device including a display device 10_2 according to an embodiment.

[0173] 24, a display device 10_2 according to an embodiment can be applied to a smartwatch 2, which is a type of smart device. The planar shape of the clock display unit of the smartwatch 2 may conform to the planar shape of the display device 10_2. For example, if the display device 10_2 according to an embodiment has a circular or elliptical planar shape, the clock display unit of the smartwatch 2 may also have a circular or elliptical planar shape. Alternatively, if the display device 10_2 according to an embodiment has a rectangular planar shape, the clock display unit of the smartwatch 2 may also have a rectangular planar shape. However, the embodiment is not limited thereto, and the clock display unit of the smartwatch 2 does not have to conform to the planar shape of the display device 10_2.

[0174] Fig. 25 is a diagram showing an instrument panel and a center fascia of a vehicle including display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to an embodiment. Fig. 25 shows an automobile to which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to an embodiment are applied.

[0175] 25, the display devices 10_a, 10_b, and 10_c according to an embodiment may be applied to an instrument panel, a center fascia, or a CID (Center Information Display) disposed on the dashboard of a vehicle. Alternatively, the display devices 10_d and 10_e according to an embodiment may be applied to a room mirror display that replaces the side mirror of a vehicle.

[0176] FIG. 26 is a diagram showing a transparent display device including a display device 10_3 according to an embodiment.

[0177] 26, a display device 10_3 according to an embodiment can be applied to a transparent display device. A transparent display device can display an image IM and transmit light at the same time. Therefore, a user positioned in front of the transparent display device can not only view the image IM displayed on the display device 10_3, but also view an object RS or a background positioned behind the transparent display device. When the display device 10_3 is applied to a transparent display device, the display panel 100 can include a light-transmitting portion that transmits light, or can be formed on a substrate member made of a light-transmitting material.

[0178] According to the above, a light-emitting element, a display device including the light-emitting element, and a manufacturing method thereof can be provided in which a groove is formed in a p-type semiconductor layer and a light-emitting layer is disposed inside the groove, thereby surrounding the light-emitting layer with the p-type semiconductor layer. According to this aspect, it is possible to suppress or reduce the occurrence of surface defects in the light-emitting element, suppress non-radiative recombination due to the surface defects, and increase the amount of holes injected into the light-emitting layer. As a result, the light-emitting efficiency of the light-emitting element can be improved.

[0179] According to the above, it is possible to provide a light-emitting element, a display device including the light-emitting element, and a manufacturing method thereof, in which the light-emitting layer can protrude above the p-type semiconductor layer and the upper portion of the light-emitting layer is surrounded by a first insulating layer disposed on the p-type semiconductor layer. According to this aspect, it is possible to stably suppress contact or bonding between the p-type semiconductor layer and the n-type semiconductor layer, and further improve the luminous efficiency of the light-emitting element.

[0180] According to the above, it is possible to provide a light-emitting element, a display device including the light-emitting element, and a manufacturing method thereof, in which the light-emitting layer includes a barrier layer and a quantum well layer, and the side surfaces of the quantum well layer are completely surrounded by a p-type semiconductor layer, thereby effectively increasing the amount of holes injected into the quantum well layer.

[0181] According to the above, the display device according to the embodiment may include a pixel including the light emitting element, thereby improving the luminous efficiency of the pixel and the display device including the pixel.

[0182] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0183] 10 Display device 100 Display Panel BRL Barrier Layer CTE contact electrode EML Light Emitting Layer ET1 1st electrode ET2 2nd electrode GRV groove INS1 First insulating layer INS2 Second insulating layer LE light-emitting element OPN1 1st opening OPN2 2nd opening PX pixels PXE1 First pixel electrode PXE2 Second pixel electrode QWL Quantum Well Layer SEM1 p-type semiconductor layer SEM2 n-type semiconductor layer SUB board

Claims

1. a p-type semiconductor layer including a trench; a first insulating layer disposed on the p-type semiconductor layer around the trench; a light emitting layer disposed in the groove and having a side surface surrounded by the p-type semiconductor layer and the first insulating layer; and The light-emitting device includes an n-type semiconductor layer disposed on the light-emitting layer.

2. the light emitting layer includes an upper layer portion that protrudes above the p-type semiconductor layer and is surrounded by the first insulating layer, The light-emitting device according to claim 1 , wherein the remaining portion of the light-emitting layer excluding the upper layer portion is completely surrounded by the p-type semiconductor layer.

3. the light emitting layer includes quantum well layers and barrier layers alternately arranged on the p-type semiconductor layer; The light-emitting device according to claim 1 , wherein the quantum well layer is disposed at a height equal to or lower than the height of the p-type semiconductor layer.

4. the light emitting layer includes quantum well layers and barrier layers alternately arranged on the p-type semiconductor layer; The light-emitting device according to claim 1 , wherein the quantum well layer has a side surface completely surrounded by the p-type semiconductor layer.

5. the n-type semiconductor layer includes an edge portion overlapping the p-type semiconductor layer; The light-emitting element according to claim 1 , wherein the first insulating layer is interposed between the p-type semiconductor layer and the n-type semiconductor layer in a portion where the p-type semiconductor layer and the n-type semiconductor layer overlap.

6. the first insulating layer includes a first opening overlapping the groove and a second opening exposing a portion of the p-type semiconductor layer; The light emitting device of claim 1 , further comprising a first electrode located in the second opening and connected to the p-type semiconductor layer.

7. The light emitting device of claim 1 , further comprising a second electrode connected to the n-type semiconductor layer.

8. The light emitting device of claim 7 , further comprising a contact electrode disposed on the n-type semiconductor layer and connected between the n-type semiconductor layer and the second electrode.

9. The light emitting device according to claim 7 , further comprising a second insulating layer disposed on the first insulating layer and covering a side surface of the n-type semiconductor layer.

10. The light-emitting device of claim 9 , wherein the second electrode is disposed on the second insulating layer.

11. at least two grooves including the groove formed in the p-type semiconductor layer and spaced apart from each other; at least two light-emitting layers including the light-emitting layer, the light-emitting layers being disposed within each of the at least two grooves and spaced apart from one another; and The light-emitting device according to claim 1 , further comprising at least two n-type semiconductor layers that include the n-type semiconductor layer and are disposed on the at least two light-emitting layers and spaced apart from each other.

12. The light-emitting device according to claim 11 , wherein the first insulating layer includes at least two openings corresponding to the at least two grooves and surrounds upper layer portions of the at least two light-emitting layers.

13. The light-emitting device according to claim 12 , further comprising a second insulating layer disposed on the first insulating layer and covering side surfaces of the at least two n-type semiconductor layers.

14. a pixel including a first pixel electrode, a second pixel electrode, and a light emitting element connected between the first pixel electrode and the second pixel electrode; The light-emitting element is a p-type semiconductor layer including a trench; a first insulating layer disposed on the p-type semiconductor layer around the trench; a light emitting layer disposed in the groove and having a side surface surrounded by the p-type semiconductor layer and the first insulating layer; and The display device includes an n-type semiconductor layer disposed on the light-emitting layer.

15. the light emitting layer includes an upper layer portion that protrudes above the p-type semiconductor layer and is surrounded by the first insulating layer, The display device according to claim 14 , wherein the remaining portion of the light emitting layer excluding the upper layer portion is completely surrounded by the p-type semiconductor layer.

16. the light emitting layer includes quantum well layers and barrier layers alternately arranged on the p-type semiconductor layer; The display device according to claim 14 , wherein the quantum well layer is completely surrounded on its sides by the p-type semiconductor layer.

17. the n-type semiconductor layer includes an edge portion overlapping the p-type semiconductor layer; The display device according to claim 14 , wherein the first insulating layer is interposed between the p-type semiconductor layer and the n-type semiconductor layer in a portion where the p-type semiconductor layer and the n-type semiconductor layer overlap.

18. forming a p-type semiconductor layer on a substrate; forming a first insulating layer on the p-type semiconductor layer; forming a first opening in the first insulating layer to expose a portion of the p-type semiconductor layer; etching the portion of the p-type semiconductor layer by a partial thickness to form a groove in the p-type semiconductor layer; forming a light-emitting layer within the groove; and A method for manufacturing a light emitting device, comprising forming an n-type semiconductor layer on the light emitting layer.

19. forming a second opening in the first insulating layer at a position spaced from the groove, the second opening exposing another portion of the p-type semiconductor layer; and The method of claim 18 , further comprising forming a first electrode on the other portion of the p-type semiconductor layer.

20. forming a contact electrode on the n-type semiconductor layer; forming a second insulating layer on the first insulating layer to cover a side surface of the n-type semiconductor layer; and The method of claim 18 , further comprising forming a second electrode connected to the contact electrode on the contact electrode and the second insulating layer.

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