Semiconductor detector and method of fabricating the same

Abstract

To improve the performance of a semiconductor detector.SOLUTION: The present disclosure describes a detector used in critical dimension scanning electron microscopes (CD-SEM) and review SEM systems. In one embodiment, the detector includes a semiconductor structure having a p-n junction and a hole through which a scanning beam is passed to a target. The detector also includes a top electrode (250) (e.g., anode or cathode) for the p-n junction that provides an active area for detecting electrons or electromagnetic radiation (e.g., backscattering from the target). The top electrode has a doped layer (230) and a buried portion (260) beneath the doped layer to reduce a series resistance of the top electrode without changing the active area. In another embodiment, an isolation structure can be formed in the semiconductor structure near sidewalls of the hole to electrically isolate the active area from the sidewalls. A method for forming the buried portion of the top electrode is also described.SELECTED DRAWING: Figure 2C

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application No. 62 / 786,865, filed December 31, 2018, and U.S. Application No. 62 / 927,451, filed October 29, 2019, each of which is incorporated by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE

[0002] The present disclosure relates generally to radiation detectors, such as may be used in scanning electron microscope (SEM) systems. [Background technology]

[0003]

[0003] Radiation detectors are used in a variety of applications. As used herein and elsewhere, the term "radiation" refers to electromagnetic waves or moving particles. For example, in manufacturing processes used to produce integrated circuit (IC) components, unfinished or completed circuit components are inspected to ensure they are manufactured according to a specified design and are free of defects. Inspection systems using optical microscopes or charged particle (e.g., electron) beam microscopes, such as SEMs, can be employed. As the physical dimensions of various features on IC components continue to decrease, the accuracy and yield achieved by these inspection systems become more important. Currently, these systems tend to be limited, at least in part, by the sensitivity and speed of the semiconductor radiation detectors, or simply the semiconductor detectors, used to detect backscattered or secondary electrons from the target being inspected. Therefore, improving the performance of semiconductor detectors is highly desirable. Summary of the Invention

[0004] The following presents a simplified summary of one or more aspects of various embodiments of the present disclosure in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is not intended to identify key or critical elements of all aspects or to delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0005]

[0005] In an aspect of an embodiment, a detector is described having a semiconductor structure with a hole for passing a scanning beam to a target, the semiconductor structure including a p-n junction. The detector also has a top electrode for the p-n junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode including a doped layer and a buried portion underlying the doped layer, the buried portion configured to reduce the series resistance of the top electrode without changing the active area provided for detection.

[0006]

[0006] In another aspect of an embodiment, a detector is described having a semiconductor structure with a hole for passing a scanning beam to a target, the semiconductor structure including a p-n junction. The detector also has a top electrode for the p-n junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode including a doped layer. The detector also has an isolation structure formed near a sidewall of the hole in the semiconductor structure, the isolation structure configured to electrically isolate the active area from the sidewall of the hole.

[0007]

[0007] In yet another aspect of an embodiment, a detector is described having a semiconductor structure with a hole for passing a scanning beam to a target, the semiconductor structure including a p-n junction. The detector also has a top electrode for the p-n junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode including a doped layer and a buried portion underlying the doped layer, the buried portion configured to reduce the series resistance of the top electrode without altering the active area provided for detection. The detector also has an isolation structure formed near a sidewall of the hole in the semiconductor structure, the isolation structure configured to electrically isolate the active area from the sidewall of the hole.

[0008]

[0008] Yet another aspect of the embodiment describes a method for forming an embedded portion of an upper electrode in a semiconductor detector, the method comprising depositing a dopant layer on a surface of a semiconductor structure having an active area of ​​the upper electrode, and then performing a heat treatment to drive dopant from the dopant layer into the semiconductor structure and below a detection layer of the upper electrode to form the embedded portion of the upper electrode.

[0009] According to another aspect of another embodiment, a method is disclosed for fabricating a semiconductor detector including an element for generating an electrical signal in response to receiving radiation and a circuit including at least one structure electrically connected to the element and incapable of withstanding processing temperatures above temperature T, the method including the steps of fabricating a first portion of the circuit capable of withstanding temperature T, performing a processing step at temperature T, and fabricating a second portion of the circuit including the structure incapable of withstanding temperature T. Performing the processing step at temperature T may include performing high temperature chemical vapor deposition. Performing high temperature chemical vapor deposition may include performing high temperature chemical vapor deposition of boron. Performing high temperature chemical vapor deposition of boron may include high temperature chemical vapor deposition of pure boron. Fabricating the first portion of the circuit may include partial fabrication of a CMOS circuit. Fabricating the second portion of the circuit includes completing fabrication of the CMOS circuit. Temperature T may be greater than 700°C.

[0010]

[0010] According to another aspect of another embodiment, a method for manufacturing a semiconductor detector comprising an element for generating a signal in response to receiving radiation and a CMOS circuit electrically connected to the element and comprising at least one structure that cannot withstand a processing temperature T exceeding 700°C, the method comprising the steps of fabricating a first portion that can withstand the temperature T of the CMOS circuit, performing an HT PureB CVD processing step at a temperature T, and fabricating a second portion that includes a structure that cannot withstand the temperature T of the CMOS circuit is disclosed.

[0011]

[0011] According to another aspect of another embodiment, a process for manufacturing a single-die imaging semiconductor radiation detector is disclosed, the process including the steps of providing a starting wafer; performing a first partial circuit formation step on a processing surface of the starting wafer, the first partial circuit layer being limited to forming a circuit that can withstand a processing temperature T; bonding a first bonded wafer to the first partial circuit layer; etching away a portion of the starting wafer to expose the first partial circuit layer; depositing a boron layer on the first partial circuit layer; bonding a second bonded wafer to the boron layer; peeling the first bonded wafer from the first partial circuit layer; performing a second partial circuit formation step on the first partial circuit layer, the second partial circuit layer including forming a circuit structure that cannot withstand the processing temperature T, to form a completed circuit layer; bonding a third bonding layer to the completed circuit layer; and peeling the second bonded wafer from the boron layer. Performing the first partial circuit formation step may include performing a first partial CMOS circuit formation step. Performing a second partial circuit formation step on the first partial circuit layer to form a completed circuit layer may include performing a second partial CMOS circuit formation step on the first partial circuit layer to form a completed CMOS circuit layer. Depositing a boron layer on the first partial circuit layer includes using HT PureB CVD. The temperature T may be greater than 700°C.

[0012]

[0012] According to another aspect of another embodiment, a single-die semiconductor detector is disclosed that includes an element for generating a signal in response to receiving radiation and a CMOS circuit electrically connected to the element and having at least one structure that cannot withstand a processing temperature T above 700°C, wherein the detector is manufactured by a method that includes the steps of fabricating a first portion of the CMOS circuit that can withstand the temperature T, performing an HT PureB CVD processing step at a temperature T, and fabricating a second portion that includes the structure that cannot withstand the temperature T of the CMOS circuit.

[0013] To the accomplishment of the foregoing and related ends, aspects of the embodiments include the features hereinafter described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features, however, are indicative of but a few of the various ways in which the principles of the various aspects may be employed, and the description is intended to include all such aspects and their equivalents. [Brief explanation of the drawings]

[0014] [Figure 1A]

[0014] FIG. 1 illustrates a semiconductor detector in an SEM system. [Figure 1B]

[0015] FIG. 1 illustrates a semiconductor detector in an off-axis SEM system. [Figure 2A]

[0016] FIG. 1 illustrates a partial cross-sectional view of a semiconductor detector with an external Al grid on the top electrode, according to some embodiments of the present disclosure. [Figure 2B]

[0017] FIG. 2 illustrates a partial cross-sectional view of a semiconductor detector having a recessed portion of the top electrode, according to some aspects of the present disclosure. [Figure 2C]

[0018] FIG. 2 illustrates a partial cross-sectional view of a semiconductor detector having a buried portion of a top electrode and a capping layer, according to some aspects of the present disclosure. [Figure 3]

[0019] 1 is a plot of a simulated electron position distribution at a detection plane, according to some aspects of the present disclosure. [Figure 4A]

[0020] FIG. 1 illustrates a partial cross-sectional view of a semiconductor detector having a large "dead area" around the hole, according to some aspects of the present disclosure. [Figure 4B]

[0021] FIG. 1 illustrates a partial cross-sectional view of a semiconductor detector having isolation structures to create a small "dead area" around the hole, according to some aspects of the present disclosure. [Figure 4C]

[0021] A diagram showing a partial cross-sectional view of a semiconductor detector having an isolation structure for creating a small "dead area" around a hole, according to some aspects of the present disclosure. [Figure 5A]

[0022] 1A-1C illustrate top views of example recessed portions of upper electrodes with multiple recessed sections arranged radially, in accordance with some aspects of the present disclosure. [Figure 5B]

[0023] 1A-1C illustrate top views of example buried portions of upper electrodes with multiple buried sections arranged in a grid, according to some aspects of the present disclosure. [Figure 6]

[0024] 1 is a flowchart illustrating an example method for forming a recessed portion of a top electrode in a semiconductor detector, according to some aspects of the present disclosure. [Figure 7]

[0025] 1A-1C illustrate an example method for forming a semiconductor detector, according to some aspects of the present disclosure. [Figure 8A]

[0026] 1A-1C illustrate an example method for forming a semiconductor detector, according to some aspects of the present disclosure. [Figure 8B]

[0026] FIG. 1 illustrates an example method for forming a semiconductor detector according to some aspects of the present disclosure. [Figure 8C]

[0026] FIG. 1 illustrates an example method for forming a semiconductor detector according to some aspects of the present disclosure. [Figure 8D]

[0026] FIG. 1 illustrates an example method for forming a semiconductor detector according to some aspects of the present disclosure. [Figure 9]

[0027] 1 is a flowchart illustrating an example method of forming a semiconductor detector, according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0028] As described above, inspection systems using optical microscopes or charged particle (e.g., electron) beam microscopes such as SEMs can be employed for the inspection of finished or unfinished IC components (e.g., semiconductor wafer inspection or die inspection). As the critical dimensions of IC components continue to decrease, resulting in an ever-increasing number of transistors and pushing the overall throughput of inspection systems higher, the accuracy, yield, and speed achieved by these inspection systems become more important. One of the key components of these systems is a semiconductor detector used to evaluate errors and inconsistencies resulting from the manufacturing process by detecting backscattered or secondary electrons from the target being inspected. With higher throughput, more sensitive or faster semiconductor detectors can be useful to enable sufficient information to be detected more quickly. Semiconductor detectors with improved sensitivity, wider bandwidth, or other features described herein can enable increased accuracy, yield, or speed in inspection systems. This disclosure describes various techniques for improving the sensitivity of semiconductor detectors, for example, by increasing their active area, and for improving the bandwidth of semiconductor detectors, for example, by reducing their series resistance to shorten their time constant.

[0016]

[0029] Reference will now be made in detail to exemplary aspects of the embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numerals in different drawings indicate the same or similar elements unless otherwise indicated. The implementations set forth in the following description of exemplary aspects of the embodiments do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of structures and processes consistent with aspects of the embodiments related to the claimed disclosure. For example, while some aspects of the present disclosure are described in the context of an inspection system using electronic scanning and electronic detection, these aspects may be applicable to other types of inspection systems.

[0017]

[0030] FIG. 1A shows a diagram 100a illustrating an overview of an SEM system (e.g., an inspection system). SEM systems are sometimes referred to as electron beam systems or e-beam systems. Diagram 100 includes a source 110 that provides a scanning beam 115 (e.g., an electron beam), which passes through a hole 125 in a detector 120 (e.g., a semiconductor detector) and is directed toward a target 130 (e.g., a wafer or die being inspected). Hole 125 can be located in the center of detector 120 or elsewhere on detector 120. Because detector 120 is arranged between source 110 and target 130, detector 120 is sometimes referred to as an in-lens detector. The axis formed by the positioning of source 110 and detector 120 along a vertical direction is sometimes referred to as the optical axis of the SEM system.

[0018]

[0031] The scanning beam 150 is used to characterize one or more features on the top surface of the target 130, resulting in backscattered or secondary electrons 135 that reach the downward-facing surface of the detector 120 and are detected. Based on the electrons 135 received by the detector 120, the detector 120 can then generate and provide a signal (not shown) that conveys information associated with the inspected feature of the target 130. This information is then used to generate an SEM image of the scanned target. In some embodiments, two or more scanning beams 150 may be generated and provided by the source 110 to enable inspection of multiple targets.

[0019]

[0032] 1B shows a diagram 100b illustrating an overall view of an off-axis SEM system. In this example, the detector 120 can be positioned on a secondary axis 170 that is different from the primary axis 140 of the scanning beam 115. In such a case, the detector 120 can be referred to as an off-axis detector, and does not need to have a hole 125 through which the scanning beam 115 passes.

[0020]

[0033] The SEM system shown in diagram 100b also includes a source 110 (or similar electron or radiation source), a gun aperture plate 145, a condenser lens 150, a source conversion unit 155, a primary projection system 160, and a target 130, all of which are aligned with the major axis 140. A beam separator 175 and a polarization scanning unit 180 may be located within the primary projection system 160. The primary projection system 160 may also include an objective lens 185. The SEM system of diagram 100b also includes a secondary imaging system 165 that, together with the detector 120, is aligned with the minor axis 170.

[0021]

[0034] The beam separator 175 may be configured to deflect the secondary electrons 135 (e.g., a beam including the secondary electrons 135) by an angle a toward the secondary imaging system 165. The angle a may be determined as the angle between the major axis 140 and the minor axis 170, and thus the angle a may represent the angle of separation between the on-axis scanning beam 115 and the secondary electrons 135 that are directed by the beam separator 175 toward the secondary imaging system 165 and the off-axis detector 120. In some embodiments, the angle a may be set within a range of 5 degrees to 25 degrees.

[0022]

[0035] The current in-lens detector, i.e., off-axis detector 120, may be a secondary electron (SE) detector with a single silicon PIN photodiode about 20 millimeters (mm) in diameter and having a hole 125 about 0.5 mm in diameter to allow the primary electron beam (e.g., scanning beam 115) to pass through. In this disclosure, the terms "about" or "approximately" when used may refer to a value relative to a nominal value, where the difference between the two values ​​may be less than 1%, 1%-5%, 1%-10%, or 1%-20%.

[0023]

[0036] Typically, there is an approximately 50 nanometer (nm) aluminum (Al) coating on top of the PIN photodiode surface that improves series resistance and reflects stray light (e.g., light generated by the laser and scattered inside the column of the SEM system).

[0024]

[0037] The use of semiconductor detectors as detector 120 (e.g., single silicon PIN photodiodes) has been prominent as in-lens detectors for electron beam (e-beam) wafer inspection systems. Meanwhile, Everhart-Thornley detectors (ET detectors), consisting of scintillators and photomultiplier tubes (PMTs), are used for critical dimension scanning electron microscope (CD-SEM) and review SEM systems. By using semiconductor detectors instead of ET detectors, wafer inspection systems can operate at high inspection throughputs, typically with 10-100 times higher beam currents and higher detection bandwidths for imaging. Therefore, semiconductor detectors were a natural choice due to their superior bandwidth and robustness against radiation damage, even though they have a relatively higher noise floor than ET detectors.

[0025]

[0038] With the continuous miniaturization of semiconductor wafer designs (e.g., shrinking critical dimensions, or CD), e-beam wafer inspection systems now often operate at very low beam currents to ensure the necessary resolution of the SEM images. As this trend continues, the noise floor of the semiconductor detectors used for SEM scanning will need to be reduced to prevent the SNR from swamping the small output current generated by the semiconductor detector.

[0026]

[0039] A typical wafer inspection system uses a retarding objective lens SEM column configuration in which the wafer being inspected (e.g., target 130) is biased to a negative high voltage Vw to achieve an incident energy (Vle) of V volts according to the following equation: Vle=Vc-Vw where Vc is the acceleration voltage of the electron beam cathode. Secondary electrons (e.g., electrons 135) emitted from the wafer surface in response to the scanning beam 115 are accelerated to (Vc-Vw) eV and strike the surface of the detector 120 with such kinetic energy.

[0027]

[0040] In one example, the cathode voltage Vc may be −10 kilovolts (KV) or greater to ensure that the kinetic energy of electrons (e.g., electrons 135) incident on the detector 120 is maintained at a minimum above approximately 8 KeV. Electrons that travel to the surface of the detector 120 must reach a depletion region that penetrates the thickness of the p++ layer and np junction and the top aluminum coating used to reflect scattered photons. If the electron kinetic energy drops below 8 KeV, quantum efficiency drops sharply as the change in signal current per electron becomes smaller, reducing the SNR of the SEM image. However, for specific needs in building an SEM system, as well as system reliability and system cost, it may be desirable to maintain the cathode voltage below 6 KV. In these situations, the detector 120 may need to allow a majority of the incident electrons to reach the depletion region with minimal energy loss to minimize SNR degradation in the SEM image.

[0028]

[0041] An off-axis detector (e.g., detector 120 on the secondary axis in diagram 100b of FIG. 1B) does not need to have a hole, but an in-lens or on-axis detector (e.g., in-lens detector 120 in diagram 100a of FIG. 1A) needs to have a hole (e.g., hole 125) through which the primary electron beam (e.g., scanning beam 115) passes. The distance between the hole inner diameter (ID) surface and the active detection surface must be properly designed so that additional dark current is minimized.

[0029]

[0042] As discussed above, detectors in e-beam inspection systems need to support high bandwidth for high inspection throughput when relatively large beam currents are used. Detector bandwidth depends, at least in part, on junction capacitance and series resistance. Therefore, if one wishes to use a retarding objective lens SEM column with a fixed cathode voltage, such as 6 kV, it is desirable to reduce or lower the series resistance to give the in-lens detector a shorter time constant (e.g., faster response or higher bandwidth) without reducing the probability that electrons reaching the detector surface will also reach the depletion region in order to maintain high quantum efficiency.

[0030]

[0043] CD-SEM applications present several challenges related to detector design that need to be overcome. In CD-SEM applications, low beam or probe currents are required to maintain good resolution, resulting in very low total beam doses. In this situation, having very low circuit noise levels is required to maintain an acceptable SNR and, therefore, good image quality. The noise characteristics of existing PIN photodiode detectors combined with preamplifier circuits do not meet these requirements. In current preamplifier designs, detector capacitance is a significant factor affecting not only bandwidth but also noise.

[0031]

[0044] To address at least some of these issues, a thin layer can be added to the detector to increase collection efficiency. In some embodiments, this thin layer includes boron (B), and a detector with a boron layer can be referred to as a pure-B detector. The boron layer is typically a few nanometers of pure or nearly pure amorphous boron. Other elements can also be used in pure or nearly pure form to provide functionality similar to that of a pure boron layer. However, such detectors must still meet low capacitance and fast response time requirements. Due to the low beam or probe current, low incident energy, and high bandwidth requirements, the corresponding signal (e.g., secondary electrons or SE electrons) generated by the detector 120 is much lower than in existing platforms. It is therefore desirable to maintain the collection efficiency of the detector as high as possible (the proposed boron layer of the pure-B detector addresses this issue through inherent design features of the boron layer) and to maximize the fill factor (e.g., the detection area or active area of ​​the detector) by reducing unused or dead areas, which may include "safety margins" of the active area relative to the edges of the hole 125 and separation areas between different segments of the detector.

[0032]

[0045] In some cases, secondary or backscattered electrons emerging from the top surface of target 130 will be accelerated backward along the optical axis by a field of approximately 5 KeV. The spatial distribution of secondary electrons on the surface of detector 120 is roughly Gaussian, with the distribution centered on the optical axis, although the spread of the curve depends on operating conditions (see, for example, FIG. 3). To increase signal power and thereby improve SNR, it is preferable to make the dead area as small as possible while still maintaining a low leakage current.

[0033]

[0046] An aspect of using a pure boron layer in electron detection applications is the high sheet resistance (e.g., about 10 kG x cm) of nanometer-thick boron layers. For fast-response electron detection, low series resistance on the top electrode (e.g., anode) is generally preferred, as it allows for faster response times along with low capacitance per unit area. The current solution to reducing the series resistance of the pure B layer on the top electrode is to form an aluminum (Al) grid on top of the boron layer (see, e.g., Figure 2A). However, this results in a loss of active area because electrons that adhere to the aluminum grid do not reach the depletion region and are not detected. The aluminum grid also creates topography on the active area, which can hinder the detection of incident electrons.

[0034]

[0047] FIG. 2A shows a diagram 200a illustrating a partial cross-section of a semiconductor detector (e.g., detector 120) with an external aluminum (Al) grid 240 on a top electrode 250. The semiconductor detector may be an in-lens / on-axis semiconductor detector (see, e.g., FIG. 1A) or an off-axis semiconductor detector (see, e.g., FIG. 1B). In diagram 200a, detector 120 includes a semiconductor structure 210 (e.g., a silicon-based photodiode) and a top electrode 250. The semiconductor structure 210 may be a high-resistivity (HR) semiconductor layer and includes a pn junction (not shown) that creates a depletion region (not shown). The pn junction may be a pn junction to form a pn photodiode in the semiconductor structure 210. FIG. 2A also shows an isolation layer 220 between the top electrode 250 and the semiconductor structure 210.

[0035]

[0048] The top electrode 250 provides an active area 245 for detecting electrons (or electromagnetic radiation), i.e., the top electrode 250 is disposed on the surface of the detector 120 facing the target 130 and receiving secondary or backscattered electrons 135 from the target 130. The top electrode 250 may be referred to as the detection layer and includes a doped layer 230 that may be doped with pure boron to provide the boron layer discussed above to improve the collection efficiency of the detector 120.

[0036]

[0049] As mentioned above, the use of aluminum grid 240 results in a loss of active area 245 because aluminum grid 240 prevents electrons that attach to aluminum grid 240 from reaching the depletion region of the p-n junction and going undetected. Aluminum grid 240 also creates topography on the active area (e.g., height differences above the surface of detector 120) that can interfere with the detection of incident electrons.

[0037]

[0050] One alternative would be to form a "buried grid" or "buried portion" of the top electrode 250 (see, e.g., FIG. 2B). A buried grid is expected to be a better solution than an aluminum grid 240 that uses a boron layer (e.g., doped layer 230) to reduce the series resistance of the photodiode because it does not cause loss of the active or detection area 245, there is no topography on the active area 245, and a soft material such as aluminum is not used on the active area 245.

[0038]

[0051] 2B shows diagram 200b illustrating a partial cross-section of a semiconductor detector (e.g., detector 120) having a buried portion 260 of a top electrode 250. In this example, there is no aluminum grid 240 as shown in diagram 200a. Instead, top electrode 250 comprises a doped layer 230 (e.g., a boron layer or other layer having similar functionality) and a buried portion 260 underlying doped layer 230, which is configured to reduce the series resistance of top electrode 250 without changing the active area 245 provided for detection.

[0039]

[0052] In one embodiment, the semiconductor detector of FIG. 2B includes a semiconductor structure 210 that is a silicon-based semiconductor structure, a top electrode 250 that is an anode electrode, and a doped layer 230 that is doped with a p-type dopant. A buried portion 260 of the top electrode 250 is formed by thermal treatment of the same type of dopant as the doped layer 230 (see, e.g., FIG. 6 ). Thus, in this case, the buried portion 260 of the top electrode 250 is a low-resistivity (LR) p-type region, while the semiconductor structure 210 is a high-resistivity (HR) n-type layer. The dopant used to form the buried portion 260 of the top electrode 250 can be deposited in the semiconductor structure 210 by various implantation processes, one of which can be a chemical vapor deposition (CVD) process. Also, as noted above, the p-type dopant of the doped layer 230 can include boron. In some embodiments, the p-type dopant of the doped layer 230 can be a different element (or a composite element or alloy), which can be, for example, at least partially selected from the same column of the periodic table as boron.

[0040]

[0053] In another embodiment, the semiconductor detector of FIG. 2B has a semiconductor structure 210 that is again a silicon-based semiconductor structure, an upper electrode 250 that is now a cathode electrode, and a doped layer 230 that is doped with an n-type dopant. In this embodiment, the doped layer 230 is not a boron layer because it is n-type doped, but it plays the same or similar role as a boron layer would play if the upper electrode 250 were an anode electrode. The buried portion 260 of the upper electrode 250 is again formed by thermal treatment of a dopant of the same type as the doped layer 230 (see, for example, FIG. 6 ), and the dopant used to form the buried portion 260 of the upper electrode 250 can also be deposited on the semiconductor structure 210 by a CVD process. Therefore, in this case, the buried portion 260 of the upper electrode 250 is an LRn-type region, while the semiconductor structure 210 is an HRp-type layer. The same type of dopant used in the buried portion 260 of the upper electrode 250 and the doped layer 230 can be different n-type dopants. Additionally, the n-type dopants of doped layer 230 may include one or more of arsenic, phosphorus, or antimony.

[0041]

[0054] It should be understood from the diagrams 200a and 200b of Figures 2A and 2B, respectively, that the top electrode 250 may also include a top electrode metal contact 270 disposed on the periphery of the semiconductor structure 210 and partially overlapping the top electrode doped layer 230, and that the buried portion 260 of the top electrode 250 allows current generated by the p-n junction from the detection of electrons (or electromagnetic radiation) to be available at the top electrode metal contact 270.

[0042]

[0055] The goal of reducing the series resistance of the top electrode 250 may alternatively or additionally be achieved by capping the pure boron layer (e.g., doped layer 230) of the top electrode 250 (e.g., when the top electrode 250 is an anode electrode) with a thin low-resistivity (LR) layer and / or a controlled top electrode (e.g., anode) doping drive-in. This approach should not significantly affect collection efficiency, as the corresponding reduction in relative electron gain is expected to be negligible for electron energies of interest. These three alternative options, namely, the use of a buried grid or buried portion, a thin LR capping layer, and a top electrode drive-in, can be used individually or in some combination to reduce the series resistance of the detector 120.

[0043]

[0056] 2C shows a diagram 200c illustrating a partial cross-sectional view of a semiconductor detector (e.g., detector 120) with a buried portion 260 of top electrode 250 and a capping layer 280. As shown in diagram 200c, capping layer 280, which may include one or more LR layers, is disposed above doped layer 230. Additionally, capping layer 280 may be made of a conductive material.

[0044]

[0057] It should be understood that each of the semiconductor detectors shown in Figures 2A to 2C may be a secondary electron (SE) detector configured to detect secondary electrons and / or backscattered electrons from a target (e.g., target 130), or a radiation detector configured to detect electromagnetic radiation generated by or backscattered from a target (e.g., target 130).

[0045]

[0058] Another relevant aspect of this disclosure that directly impacts the performance of a particular electron detector is the extent of the "dead area" around the hole (e.g., hole 125 in diagram 100 of FIG. 1) through which the primary beam (e.g., scanning beam 115) passes. Ideally, this dead area should be as small as possible, since the position distribution of secondary electrons (SEs) is highly concentrated around the hole. FIG. 3 shows a plot 300 of simulated electron position distribution at the detector plane, which clearly shows that most electrons land in the center of the detector, and the larger the "dead area" around the hole, the fewer electrons will be detected. Therefore, another aspect of this disclosure is to reduce the "dead area" of the detector 120 as much as possible to improve overall efficiency and / or sensitivity.

[0046]

[0059] In existing semiconductor detector designs, the limit to reducing this "dead area" is the lateral extent of the deep depletion region required for fast response (e.g., reduced junction capacitance). In fact, it is most preferable for the depletion layer not to reach the surface of hole 125 to prevent a significant increase in leakage current (e.g., in the segment of detector 120 closest to hole 125).

[0047]

[0060] 4A shows a diagram 400a illustrating a partial cross section of a semiconductor detector (e.g., detector 120) having a large "dead area" 410a around hole 125. In this example, "dead area" 410a spans the region between top electrode metal contacts 270 of top electrode 250, including hole 125 and adjacent areas. In this example, first layer 420 and second layer 425 form a p-n junction that produces a depletion region 427 having a constant depletion length (e.g., depth or thickness of depletion region 420) that extends into second layer 425 based on an applied reverse bias, and this depletion length is large enough to reduce the junction capacitance of the p-n junction of semiconductor structure 210. This increases the response time and bandwidth of the semiconductor detector. In some embodiments, the first layer 420 is a p-type doped layer and the second layer 425 is an n-type doped layer (e.g., a high-resistivity n-type device layer), while in other embodiments, the first layer 420 is an n-type doped layer and the second layer 425 is a p-type doped layer. Meanwhile, the large depletion region 427 also extends laterally. To prevent the depletion region 427 from reaching the sidewall 430 of the hole 125 and increasing leakage current, the top electrode 250 is configured so that its active area starts away from the hole 125, thereby creating a large "dead area" 410a found in existing semiconductor detector designs.

[0048]

[0061] The present disclosure proposes a different approach than that described in diagram 400a. Figures 4B and 4C show diagrams 400b and 400c, respectively, illustrating partial cross-sectional views of a semiconductor detector (e.g., detector 120) with isolation structures for creating a small or smaller "dead area" around hole 125. For example, "dead area" 410b in diagram 400b and "dead area" 410c in diagram 400c are smaller than "dead area" 410a in diagram 400a.

[0049]

[0062] For example, in diagram 400b, semiconductor structure 210 includes an isolation structure 440 that separates depletion region 427 from sidewall 430 of hole 125. Isolation structure 440 comprises a deep trench 445 formed near sidewall 430 of hole 125 and having doped sidewalls 450 that provide a defect-free stop surface that limits lateral extension of depletion region 420 toward hole 125. Deep trench 445 may be filled with an insulating material, such as a dielectric material (e.g., oxide). The doping of doped sidewall 450 may be of an opposite doping or doping type to that of second layer 425. This allows the "dead area" 410 between hole 125 and the active area provided by top electrode 250 to be reduced to tens of microns; therefore, having a smaller "dead area" 410 is expected to significantly improve detection of secondary electrons and / or backscattered electrons (e.g., electrons 135). In this example, the distance between the isolation structure 440 and the sidewall 430 of the hole 125 may be less than 60 microns. Thus, the isolation structure 440, having the deep trench 440 and sidewall 450, may be substantially parallel to, but not in contact with, the sidewall 430 of the hole 125.

[0050]

[0063] In diagram 400c, the semiconductor structure 210 includes an isolation structure 460 that separates the depletion region 420 from the sidewall 430 of the hole 125. The isolation structure 460 is formed in close proximity to the sidewall 430 of the hole 125, is substantially parallel to and adjacent to the sidewall 430 of the hole 125, and comprises a doped layer that restricts the depletion region 427 from extending laterally toward the hole 125. That is, the material, doping, and / or structural characteristics of the isolation structure 460 are configured to restrict the depletion region 427 from extending laterally as close as possible to the sidewall 430 of the hole 125. This can reduce the "dead area" 410c between the hole 125 and the active area provided by the top electrode 250, improving detection of secondary electrons and / or backscattered electrons (e.g., electrons 135). In this example, the distance between the isolation structure 460 and the sidewall 430 of the hole 125 can be less than 1 micron. However, in some cases, the isolation structure 460 may be in direct contact with the sidewall 430 of the hole 125 .

[0051]

[0064] 2B, the semiconductor detector (e.g., detector 120) of FIGS. 4B and 4C may have a semiconductor structure 210 that is a silicon-based semiconductor structure, a top electrode 250 that is an anode electrode, and a doped layer 230 that is doped with a p-type dopant (e.g., boron), or may have a semiconductor structure 210 that is a silicon-based semiconductor structure, a top electrode 250 that is a cathode electrode, and a doped layer 230 that is doped with an n-type dopant (e.g., one or more of arsenic, phosphorus, or antimony). In each of these cases, a recessed portion of top electrode 250 (not shown in FIGS. 4B and 4C) may be formed by heat treatment of a dopant of the same type as doped layer 230.

[0052]

[0065] In addition to the various features described above, a solid-state detector (e.g., detector 120) can have multiple segments. Each segment introduces a new anode (or cathode) with position sensing capabilities that allows for resolution of electrons collected by the same segment. As explained below, various resolution profiles can be used.

[0053]

[0066] 5A shows a diagram 500a illustrating a top view of an example of a buried portion 260 of a top electrode 250 having multiple buried sections arranged in a radial pattern. That is, the buried portion 260 of the top electrode 250 includes multiple buried sections in the active area 245 provided by the top electrode 250, which are arranged to form a radial shape as shown in diagram 500a.

[0054]

[0067] 5B shows diagram 500b illustrating a top view of an example buried portion 260 of top electrode 250 in which multiple buried sections are arranged in a grid pattern. That is, buried portion 260 of top electrode 250 includes multiple buried sections in active area 245 provided by top electrode 250, which are arranged to form a grid pattern as shown in diagram 500b.

[0055]

[0068] In other examples, the various sections forming the recessed portion 260 of the tope electrode 250 need not intersect with one another as in the examples of diagrams 500a (FIG. 5A) and 500b (FIG. 5B). For example, the various sections can include multiple lines (e.g., straight lines, curved lines) that do not overlap, cross one another, and / or touch one another. Also, the various sections forming the recessed portion 260 of the tope electrode 250 can include curved sections similar to those shown in the radial shape of diagram 500a (FIG. 5A), straight sections similar to those shown in the grid shape of diagram 500b (FIG. 5B), or a combination of both curved and straight sections.

[0056]

[0069] The buried portion 260 of the top electrode 250, whether configured in a radial, lattice, or some other shape, is formed by heat treatment of the same type of dopant as the doped layer 230, and in some cases the dopant is the same, but this is not always necessary (see, e.g., the description of FIG. 2B).

[0057]

[0070] FIG. 6 is a flow chart illustrating an example method 600 for forming a buried portion 260 of a top electrode 250 in a semiconductor detector (eg, detector 120).

[0058]

[0071] The method 600 includes, at 610, depositing a dopant layer on a surface of a semiconductor structure (e.g., semiconductor structure 210) having an active area (e.g., active area 245) of a top electrode 250. The dopant layer is different from a doped layer, such as doped layer 230.

[0059]

[0072] The method 600 optionally includes depositing a capping layer (e.g., capping layer 280) over the dopant layer at 620, where the capping layer is deposited before performing the thermal treatment. Typically, the capping layer is a dielectric layer.

[0060]

[0073] At 630, the method 600 includes performing a thermal process (e.g., a heat treatment) to drive the dopant from the dopant layer into the semiconductor structure and beneath the detection layer (e.g., doped layer 230) of the top electrode 250 to form the buried portion 260 of the top electrode 250.

[0061]

[0074] In some embodiments of the method 600, depositing the dopant layer includes depositing the dopant layer by a CVD process.

[0062]

[0075] In another embodiment of method 600, the top electrode 250 can be an anode electrode, and the dopant in the dopant layer can include a p-type dopant (e.g., boron), and the dopant in the detection layer can be of the same type as the dopant in the dopant layer.

[0063]

[0076] In another embodiment of method 600, the top electrode 250 can be a cathode electrode, and the dopant in the dopant layer can include an n-type dopant (e.g., one or more of arsenic, phosphorus, or antimony), and the dopant in the detection layer can be of the same type as the dopant in the dopant layer.

[0064]

[0077] In another embodiment of the method 600, the semiconductor detector may be an SE detector or a radiation detector.

[0065]

[0078] 1 through 6, embodiments supported by the present disclosure include a detector having a first layer of a first conductivity type (e.g., a p-doped layer) on a first surface of a substrate to form an anode for receiving secondary electrons of a scanning electron microscope (SEM) inspection system, a buried section of the first conductivity type (e.g., buried portion 260) on the first surface of the substrate to reduce the series resistance of the anode, and a second layer of a second conductivity type (e.g., an n-doped layer) to enable formation of a pn diode including the first and second layers. In another aspect of the embodiment, forming the buried section can include implanting a dopant into the substrate, where the dopant can be, for example, boron. The buried section can also be lattice-shaped (see, for example, FIG. 5A ) or other shapes.

[0066]

[0079] In yet another embodiment supported by the present disclosure, a substrate comprises a semiconductor structure (e.g., semiconductor structure 210) having a hole (e.g., hole 125) that also has a deep trench isolation (e.g., isolation structure 440) surrounding the hole, a first layer of a first conductivity type (e.g., a p-type or n-type doped layer) on a first surface of the semiconductor structure for receiving secondary electrons of an SEM system, and a second layer of a second conductivity type (e.g., an n-type or p-type doped layer) adjacent to the deep trench isolation for enabling formation in the semiconductor structure of a pn diode including the first and second layers.

[0067]

[0080] As mentioned above, it is highly desirable for imaging systems that detect backscattered electrons to have a detector that can reliably and quickly detect electrons. Ideally, such a detector would combine, on a single die, the detector that detects electrons—that is, generates a signal in response to receiving electrons—with the circuitry that receives the signal. However, to speed up the detector, it is desirable to use a step in the manufacturing process called HT PureB CVD, which stands for high-temperature pure boron chemical vapor deposition. As the name suggests, this step involves exposing the wafer on which the circuit is formed to very high temperatures. It is also desirable to use a circuit type known as CMOS circuitry. Unfortunately, these high temperatures exceed those that CMOS circuits can withstand. This has traditionally presented a fundamental incompatibility. According to one disclosure herein, this fundamental incompatibility is resolved by dividing the formation of the circuitry into two parts: (1) a first part that involves only fabricating structures that can survive the subsequent high-temperature steps; and (2) a second part that occurs after the high-temperature step, allowing for the safe fabrication of structures that would not otherwise be able to withstand the previous high-temperature steps. Thus, according to one aspect, HT PureB CVD processing steps are integrated into a standard BSI CMOS process to provide a highly sensitive, robust, radiation hard, very fast, and power efficient detector / imager and readout electronics. In other words, the resulting detector will have higher sensitivity, faster response time, and higher signal-to-noise ratio for optimal image quality. The process also allows for more functionality to be provided within the detector.

[0068]

[0081] In other words, as described above, according to aspects of an embodiment, the in-lens SE detector may be configured as a single silicon PIN detector with a center hole for passing the primary electron beam. An aluminum coating is present on top of the diode surface to improve series resistance and reflect stray light from the laser beam scattered inside the column. The SE detector is the first stage of the entire imaging channel, and its signal-to-noise ratio (SNR) determines the upper limit of the SNR for the rest of the channel.

[0069]

[0082] Technology exists for using a low-temperature (LT) PureB process with a standard CMOS process for the fabrication of single-die imagers for low-penetration-depth radiation, such as EUV / DUV photons and low-energy electrons. See U.S. Patent No. 9,331,117, issued May 3, 2016, entitled "Sensor and Lithographic Apparatus," the disclosure of which is incorporated herein by reference in its entirety. The integration of the LT PureB process with a standard CMOS process enables the fabrication of multi-pixel detectors (imagers) for imaging low-penetration-depth radiation on a single die. However, the LT PureB process is characterized by a very high sheet resistance, but is not capable of high-speed imaging.

[0070]

[0083] There is a technical need for ultrafast pixelated radiation detectors capable of detecting low-energy (low penetration depth) electrons. One solution for fabricating such detectors is to combine the HT PureB process with standard CMOS processes on a single silicon die. The HT PureB process provides a shallow pn junction for detecting charged and uncharged particles with low penetration depths, such as DUV and EUV photons, or low-energy electrons at the high readout speeds for which PureB technology (CVD boron deposition on crystalline silicon) is beneficial, along with a thin, dense, protective passivation amorphous boron layer on top of the silicon. Locating the CMOS readout electronics on the same silicon die as the radiation-responsive element shortens the signal path, reduces parasitic resistance and capacitance, and enables power-efficient, very fast signal processing.

[0071]

[0084] However, one technical challenge to achieving these benefits is that the temperatures for chemical vapor deposition (CVD) of boron onto silicon in the HT PureB process are typically above 700° C. At such temperatures, CMOS parts can be destroyed if they are first processed.

[0072]

[0085] According to aspects of one embodiment, this technical challenge is overcome by dividing the CMOS processing of the die into two parts: (1) a first part that occurs before the HT CVD of pure boron, and (2) a second part that occurs after the HT CVD of pure boron. The CMOS structure fabricated before the HT CVD boron is selected to be able to withstand further die processing at temperatures up to 800°C. Next, an HT PureB CVD process is performed (e.g., at about 750°C), followed by the remaining intolerable high-temperature steps of the CMOS process. In this manner, the temperature sequence of the wafer processing steps may be arranged so that each step uses a lower temperature than the previous step.

[0073]

[0086] One method for achieving this processing sequence uses temporary wafer bonding and debonding. Figure 7 shows an example of the overall processing sequence for a single-die CMOS image sensor (CIS) using integrated HT CVD of boron using temporary wafer bonding and debonding. The process begins with an initial structure 700, which is a starting wafer W1. Next, initial CMOS processing 702 is performed on one surface of the starting wafer W1 to obtain an intermediate structure 710. This initial CMOS processing can include steps to form CMOS circuits that can withstand subsequent high-temperature CVD steps. For example, this initial CMOS processing can include forming polysilicon gates. Next, a first bonded wafer BW1 is bonded to the portion of the starting wafer W1 that has the initial CMOS structure 702 to obtain an intermediate structure 720. Next, portions of the initial wafer W1 other than the CMOS structure 702 are etched away to form an intermediate structure 730. Next, a boron layer 742 is deposited on the CMOS layer 702 using HT PureB CVD to form an intermediate structure 740. A second bonded wafer BW2 is then bonded to the boron layer 742 to obtain intermediate structure 750. The first bonded wafer BW1 is then debonded from the CMOS layer 702 to form intermediate structure 760. A second portion of the CMOS processing is then performed to create a CMOS structural layer 772 to obtain intermediate structure 770. A third bonded wafer BW3 is then bonded to the CMOS structural layer 772 to obtain intermediate structure 780. Finally, the bonding layer BW2 is debonded from the boron layer 742 to obtain final structure 790. It will be understood that this final structure may undergo additional processing steps. For each bonding / debonding step, an appropriate bonding / debonding technique must be chosen along with an appropriate thermal treatment sequence before and after the bonding / debonding step.

[0074]

[0087] FIGS. 8A through 8D illustrate the overall process of FIG. 7 in more detail. The top portion of FIG. 8A shows initial CMOS processing 702 applied to one surface of starting wafer W1 to obtain intermediate structure 710. This initial CMOS processing can include steps to form CMOS circuitry that can withstand subsequent high-temperature CVD steps. For example, this initial CMOS processing can include forming polysilicon gates. The next portion of FIG. 8A, proceeding downward, shows bonding a first bonded wafer BW1 to the portion of starting wafer W1 that has initial CMOS structure 702 to obtain intermediate structure 720. The next portion of FIG. 8A, proceeding downward, shows etching away portions of initial wafer W1 other than the CMOS layer 702 to form intermediate structure 730.

[0075]

[0088] Referring to Figure 8B, the top portion of Figure 8B shows the deposition of a boron layer 742 on the CMOS layer 702 using HT PureB CVD to form intermediate structure 740. The next portion of Figure 8B, moving downward in the figure, shows the bonding of a second bonded wafer BW2 to the boron layer 742 to obtain intermediate structure 750.

[0076]

[0089] Referring to Figure 8C, the top portion of Figure 8C shows the first bonded wafer BW1 being peeled from the CMOS layer 702 to form intermediate structure 760. The next portion of Figure 8C, moving downward in the figure, shows the second part of the CMOS processing being performed to create a CMOS structure layer 772, resulting in intermediate structure 770.

[0077]

[0090] 8D shows the bonding of a third bonded wafer BW3 to the CMOS structural layer 772 to obtain intermediate structure 780. Finally, the second bonded wafer BW2 is debonded from the boron layer 742 to obtain final structure 790.

[0078]

[0091] FIG. 9 is a flowchart illustrating process steps for fabricating a single-die CMOS detector using temporary wafer bonding and debonding, according to one aspect of an embodiment. In step S10, initial CMOS processing is performed on a starting wafer. This processing is performed to create only structures that can withstand the high heat of later steps, specifically the high-temperature CVD deposition steps. In step S20, a first bonded wafer is bonded to the processed side of the starting wafer. In step S30, the starting wafer is etched to partially expose the CMOS-processed surface. In step S40, a layer of material, such as pure boron, is deposited on the CMOS-processed surface using, for example, HT PureB CVD. In step S50, a second bonded wafer is bonded to the boron layer. In step S60, the first bonded wafer is debonded from the combination of the second bonded wafer and its layers. In step S70, additional CMOS processing is performed on the CMOS processing layer. This step allows for the creation of structures that cannot withstand high-temperature steps, such as HT PureB CVD, because these steps have already been performed. In step S80, a third bonded wafer is bonded to the CMOS processed layer. In step S90, the second bonded wafer is delaminated from the combination of the third body wafer and its layers.

[0079]

[0092] The embodiments may be further described using the following clauses: 1. A semiconductor structure having a pn junction; and a top electrode for a pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode comprising a doped layer and a buried portion at least partially below the doped layer and configured to reduce series resistance of the top electrode. 2. The detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system; 10. The detector of claim 1, wherein the semiconductor structure has a hole that allows the scanning beam to pass through to the target. 3. A detector according to clause 1, wherein the embedded portion is configured to reduce the series resistance of the top electrode without changing the active area provided for detection. 4. The semiconductor structure is a silicon-based semiconductor structure; The upper electrode is an anode electrode, 10. The detector of claim 1, wherein the doped layer is doped with a p-type dopant. 5. The detector of clause 4, wherein the buried portion of the top electrode is formed by heat treatment of a dopant of the same type as the doped layer. 6. The detector of clause 5, wherein the dopant used to form the buried portion of the top electrode is deposited on the semiconductor structure by a chemical vapor deposition process. 7. The detector of clause 4, wherein the p-type dopant of the doped layer comprises boron. 8. The semiconductor structure is a silicon-based semiconductor structure; The upper electrode is a cathode electrode, The detector of clause 1, wherein the doped layer is doped with an n-type dopant. 9. The detector of clause 8, wherein the buried portion of the top electrode is formed by heat treatment of a dopant of the same type as the doped layer. 10. The detector of clause 9, wherein the dopant used to form the buried portion of the top electrode is deposited on the semiconductor structure by a chemical vapor deposition process. 11. The detector of clause 9, wherein the same type dopants in the buried portion of the top electrode and the doped layer are different n-type dopants. 12. The detector of clause 8, wherein the n-type dopant of the doped layer comprises one or more of arsenic, phosphorus, or antimony. 13. The detector of clause 1, further comprising a top electrode metal contact disposed on the periphery of the semiconductor structure and partially overlapping the doped layer of the top electrode, the recessed portion of the top electrode reducing the series resistance of the top electrode so that current generated by the pn junction from detection of electrons or electromagnetic radiation is available at the top electrode metal contact. 14. The detector of clause 1, further comprising a capping layer disposed above the doped layer. 15. The detector of clause 14, wherein the capping layer is a conductive layer. 16. The detector of clause 1, wherein the pn junction is a pin junction. 17. The detector is a secondary electron (SE) detector and detecting electrons includes detecting backscattered electrons from the target; or 10. The detector of clause 1, wherein the detector is a radiation detector and detecting the electromagnetic radiation includes detecting backscattered electromagnetic radiation from the target. 18. The detector of clause 1, wherein the recessed portion of the upper electrode includes a plurality of recessed sections in the active area provided by the upper electrode. 19. A detector of clause 18, in which multiple embedded sections do not intersect with each other. 20. The detector of clause 19, wherein the plurality of embedded sections includes straight sections, curved sections, or both. 21. The detector of clause 19, wherein a plurality of embedded sections are arranged in a grid pattern. 22. A detector according to clause 19, in which a plurality of embedded sections are arranged radially. 23. A detector according to clause 1, wherein the detector is configured for off-axis operation in an SEM inspection system. 24. A semiconductor structure having a pn junction and a hole for passing the scanning beam to the target; a top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation and comprising a doped layer; an isolation structure formed near a sidewall of the hole in the semiconductor structure and configured to electrically isolate the active area from the sidewall of the hole. 25. The detector of clause 24, wherein a hole is formed in the center of the semiconductor structure. 26. The detector of clause 24, wherein the isolation structure is configured to restrict a depletion region formed by the pn junction from reaching the sidewalls of the hole, thereby electrically isolating the active area from the sidewalls of the hole. 27. The detector of clause 24, wherein the distance between the isolation structure and the sidewall of the hole is less than 60 microns. 28. The detector of clause 24, wherein the isolation structure is a deep trench structure that is substantially parallel to but does not contact the sidewalls of the hole. 29. The detector of clause 28, wherein the deep trench structure has doped sidewalls to provide a defect-free stopping surface for electrically isolating the active area by limiting the depletion region formed by the pn junction from reaching the sidewalls of the hole. 30. The detector of clause 24, wherein the isolation structure is a doped layer substantially parallel to and adjacent to the sidewall of the hole. 31. The detector of clause 30, wherein the distance between the isolation structure and the sidewall of the hole is less than 1 micron. 32. The detector of clause 30, wherein the doped layer is in contact with a sidewall of the hole. 33. The semiconductor structure is a silicon-based semiconductor structure; The upper electrode is an anode electrode, 25. The detector of clause 24, wherein the doped layer is doped with a p-type dopant. 34. The detector of clause 33, wherein the p-type dopant of the doped layer comprises boron. 35. The semiconductor structure is a silicon-based semiconductor structure; The upper electrode is a cathode electrode, 25. The detector of clause 24, wherein the doped layer is doped with an n-type dopant. 36. The detector of clause 35, wherein the n-type dopant of the doped layer comprises one or more of arsenic, phosphorus, or antimony. 37. The detector of clause 24, wherein the pn junction is a pin junction. 38. The detector is a secondary electron (SE) detector and the detection of electrons includes the detection of backscattered electrons from the target; or 25. The detector of clause 24, wherein the detector is a radiation detector and detecting electromagnetic radiation includes detecting backscattered electromagnetic radiation from the target. 39. A detector according to clause 24, wherein the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system. 40. A semiconductor structure having a pn junction and a hole for passing the scanning beam to the target; a top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode comprising a doped layer and a buried portion at least partially underlying the doped layer and configured to reduce the series resistance of the top electrode without altering the active area provided for backscattering detection; an isolation structure formed near a sidewall of the hole in the semiconductor structure and configured to electrically isolate the active area from the sidewall of the hole. 41. The detector of clause 40, wherein the hole is formed in the center of the semiconductor structure. 42. The semiconductor structure is a silicon-based semiconductor structure; The upper electrode is an anode electrode, The doped layer is doped with a p-type dopant, 42. The detector of clause 40, wherein the buried portion of the top electrode is formed by heat treatment of a dopant of the same type as the doped layer. 43. The detector of clause 42, wherein the dopant used to form the buried portion of the top electrode is deposited on the semiconductor structure by a chemical vapor deposition process. 44. The detector of clause 42, wherein the p-type dopant of the doped layer comprises boron. 45. The semiconductor structure is a silicon-based semiconductor structure; The upper electrode is a cathode electrode, The doped layer is doped with an n-type dopant, The detector of clause 40, wherein the buried portion of the top electrode is formed by heat treatment of a dopant of the same type as the doped layer. 46. ​​The detector of clause 45, wherein the dopant used to form the buried portion of the top electrode is deposited on the semiconductor structure by a chemical vapor deposition process. 47. The detector of clause 45, wherein the same type dopants in the buried portion of the top electrode and the doped layer are different n-type dopants. 48. The detector of clause 45, wherein the n-type dopant of the doped layer comprises one or more of arsenic, phosphorus, or antimony. 49. The separation structure is a deep trench structure with doped sidewalls that are substantially parallel to but do not contact the sidewalls of the hole; or The detector of clause 40, wherein the doped layer is substantially parallel to and adjacent to the sidewall of the hole. 50. A detector according to clause 40, wherein the detector is a secondary electron (SE) detector and the detection of electrons comprises detection of electrons backscattered from the target; or the detector is a radiation detector and the detection of electromagnetic radiation comprises detection of electromagnetic radiation backscattered from the target. 51. The detector of clause 40, wherein the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system. 52. A method of forming a recessed portion of a top electrode in a semiconductor detector, the method comprising: depositing a dopant layer on a surface of the semiconductor structure having an active area of ​​the upper electrode; and performing a thermal treatment to drive dopants from the dopant layer into the semiconductor structure and at least partially beneath a detection layer of the upper electrode to form a buried portion of the upper electrode including a plurality of buried sections that reduce series resistance of the upper electrode. 53. Forming a plurality of embedded sections Multiple disjoint embedded sections, a plurality of embedded sections, including straight sections, curved sections, or both; a plurality of embedded sections arranged in a grid, or Multiple radially arranged recessed sections, The method of clause 52, including forming 54. The method of clause 52, wherein depositing the dopant layer includes depositing the dopant layer by a chemical vapor deposition process. 55. The method of clause 52, further comprising depositing a capping layer over the dopant layer, the capping layer being deposited prior to performing the thermal treatment. 56. The method of clause 52, wherein the capping layer is a dielectric layer. 57. The upper electrode is an anode electrode; 53. The method of clause 52, wherein the dopant of the dopant layer comprises a p-type dopant. 58. The method of clause 57, wherein the p-type dopant comprises boron. 59. The method of clause 57, wherein the dopant in the detection layer is of the same type as the dopant in the dopant layer. 60. The upper electrode is a cathode electrode; 53. The method of clause 52, wherein the dopant of the doped layer comprises an n-type dopant. 61. The method of clause 60, wherein the n-type dopant comprises one or more of arsenic, phosphorus, or antimony. 62. The method of clause 60, wherein the dopant in the detection layer is of the same type as the dopant in the dopant layer. 63. The detector is a secondary electron (SE) detector configured to detect electrons above the active area; or 53. The method of clause 52, wherein the detector is a radiation detector configured to detect electromagnetic radiation above the active area. 64. A first layer of a first conductivity type on a first surface of the substrate for forming an anode for receiving secondary electrons of a scanning electron microscope (SEM) inspection system; a buried section of a first conductivity type on the first surface of the substrate for reducing the series resistance of the anode; a second layer of a second conductivity type to enable the formation of a pn diode including the first layer and the second layer; A detector comprising: 65. The detector of clause 64, wherein forming the buried section includes implanting a dopant into the substrate. 66. The detector of clause 65, wherein the dopant comprises boron. 67. A detector according to clause 64, wherein the embedded sections form a lattice. 68. A semiconductor structure having a hole and a deep trench isolation surrounding the hole; a first layer of a first conductivity type on a first surface of the semiconductor structure for receiving secondary electrons of the SEM system; a second layer of a second conductivity type adjacent to the deep trench isolation to enable formation in the semiconductor structure of a pn diode including the first layer and the second layer. 69. A method of manufacturing a semiconductor detector, the semiconductor detector comprising: an element for generating a signal in response to receiving radiation; and a circuit electrically connected to the element, the circuit comprising at least one structure incapable of withstanding processing temperatures above a temperature T; the method comprising: making a first part of the circuit capable of withstanding a temperature T; performing a treatment step at a temperature T; and fabricating a second portion including a structure that cannot withstand a temperature T of the circuit. 70. The method of clause 69, wherein performing the treating step at a temperature T includes performing high temperature chemical vapor deposition. 71. The method of clause 70, wherein performing high temperature chemical vapor deposition includes performing high temperature chemical vapor deposition of boron. 72. The method of clause 71, wherein performing high temperature chemical vapor deposition of boron includes performing high temperature chemical vapor deposition of pure boron. 73. The method of any one of clauses 69 to 72, wherein fabricating a first portion of a circuit comprises partially fabricating a CMOS circuit. 74. The method of any one of clauses 69 to 73, wherein fabricating the second portion of the circuitry comprises completing fabrication of the CMOS circuitry. 75. The method of any one of clauses 69 to 74, wherein the temperature T is greater than 700°C. 76. A method of manufacturing a semiconductor detector, the semiconductor detector comprising: an element for generating a signal in response to receiving radiation; and a CMOS circuit electrically connected to the element and comprising at least one structure incapable of withstanding a processing temperature T exceeding 700°C; the method comprising: fabricating a first portion of a CMOS circuit capable of withstanding a temperature T; performing an HT PureB CVD processing step at a temperature T; and fabricating a second portion including a structure that cannot withstand the temperature T of the CMOS circuit. 77. A process for manufacturing a single die semiconductor detector, comprising: providing a starting wafer; performing a first partial circuit formation step on the processing surface of the starting wafer, the first partial circuit layer being limited to forming a circuit that can withstand a processing temperature T; bonding a first bonding wafer to the first partial circuit layer; Etching away a portion of the starting wafer to expose a first partial circuit layer; depositing a boron layer on the first partial circuit layer; Bonding a second bonded wafer to the boron layer; peeling the first bonded wafer from the first partial circuit layer; performing a second partial circuit formation step on the first partial circuit layer, which includes forming a circuit structure that cannot withstand the processing temperature T, to form a completed circuit layer; bonding a third bonding layer to the completed circuit layer; and delaminating the second bonded wafer from the boron layer. 78. The process of clause 77, wherein performing a first partial circuit formation step includes performing a first partial CMOS circuit formation step. 79. The process of clause 77 or 78, wherein performing a second partial circuit formation step on the first partial circuit layer to form a completed circuit layer includes performing a second partial CMOS circuit formation step on the first partial circuit layer to form a completed CMOS circuit layer. 80. The process of any one of clauses 77 to 79, wherein depositing a boron layer on the first partial circuit layer includes using HT PureB CVD. 81. The process of any one of clauses 77 to 80, wherein the temperature T is greater than 700°C. 82. A single-die semiconductor detector comprising an element for generating a signal in response to receiving radiation, and a CMOS circuit electrically connected to the element and comprising at least one structure incapable of withstanding a processing temperature T exceeding 700°C, wherein the semiconductor detector: fabricating a first portion of a CMOS circuit capable of withstanding a temperature T; performing an HT PureB CVD processing step at a temperature T; and fabricating a second portion including a structure that cannot withstand the temperature T of the CMOS circuit.

[0080]

[0093] This disclosure, including Figures 1 through 9 and their respective descriptions, provides various techniques for improving the sensitivity, efficiency, and bandwidth of semiconductor detectors used in SEM systems. For example, this disclosure describes the use of a "buried grid" or "buried portion" of the top electrode in combination with pure boron technology (e.g., a pure boron layer or similar layer for the cathode electrode) to achieve low noise and fast response in electron detection when a filtering / absorbing metal stack (e.g., aluminum grid 240) is not used in the active area (as in extreme ultraviolet (EUV) applications). This disclosure also describes the use of isolation structures to maximize the active area and new positioning resolution (e.g., radial shape) of electrons incident on a segment of the semiconductor detector.

[0081]

[0094] The various diagrams described in connection with the drawings illustrate examples of the architecture, organization, functionality, and operation of possible implementations of various embodiments. With respect to flowcharts, each block may represent a portion of an overall method or process. It should also be noted that in some alternative implementations, the functions noted in the flowchart blocks may occur out of the order noted and / or concurrently with functions in different blocks.

[0082]

[0095] It should be understood that the described embodiments are not mutually exclusive, and that elements, components, materials, or steps described in connection with one exemplary embodiment may be combined with or removed from other embodiments in any suitable manner to achieve desired design objectives.

[0083]

[0096] As used herein, unless specifically stated otherwise, the term "or" includes all possible combinations unless impractical. For example, if it is stated that a component may include A or B, it may include A or B, or A and B, unless specifically stated otherwise or impractical. As a second example, if it is stated that a component may include A, B, or C, it may include A, B, or C, A and B, A and C, B and C, or A, B, and C, unless specifically stated otherwise or impractical.

[0084]

[0097] Additionally, the articles "a" and "an," as used in this specification and the appended claims, should generally be construed to mean "one or more" unless otherwise specified or clear from the context as to the singular form.

[0085]

[0098] The use of figure numbers or figure reference labels in the claims is intended to facilitate claim interpretation, and such use should not be construed as necessarily limiting the scope of the claims to the embodiments or examples shown in the corresponding figures.

[0086]

[0099] It will be further understood that various changes in the details, materials, and arrangements of parts described and shown to explain the principles of the described aspects or embodiments may be made by those skilled in the art without departing from the scope expressed in the following claims.

Claims

1. a semiconductor structure having a pn junction; and a top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode comprising a doped layer and a buried portion at least partially underlying the doped layer and configured to reduce a series resistance of the top electrode.

2. the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system; The detector of claim 1 , wherein the semiconductor structure has a hole that allows the scanning beam to pass through to the target.

3. The detector of claim 1 , wherein the recessed portion is configured to reduce the series resistance of the top electrode without altering the active area provided for detection.

4. the semiconductor structure is a silicon-based semiconductor structure; the upper electrode is an anode electrode, 2. The detector of claim 1, wherein said doped layer is doped with a p-type dopant.

5. 5. The detector of claim 4, wherein said buried portion of said top electrode is formed by heat treatment of a dopant of the same type as said doped layer.

6. 6. The detector of claim 5, wherein the dopant used to form the buried portion of the top electrode is deposited on the semiconductor structure by a chemical vapor deposition process.

7. 5. The detector of claim 4, wherein said p-type dopant in said doped layer comprises boron.

8. the semiconductor structure is a silicon-based semiconductor structure; the upper electrode is a cathode electrode, 2. The detector of claim 1, wherein said doped layer is doped with an n-type dopant.

9. 9. The detector of claim 8, wherein said buried portion of said top electrode is formed by heat treatment of a dopant of the same type as said doped layer.

10. 10. The detector of claim 9, wherein the dopant used to form the buried portion of the top electrode is deposited on the semiconductor structure by a chemical vapor deposition process.

11. 10. The detector of claim 9, wherein the same type dopants of the buried portion of the top electrode and the doped layer are different n-type dopants.

12. The detector of claim 8 , wherein the n-type dopant of the doped layer comprises one or more of arsenic, phosphorus, or antimony.

13. 2. The detector of claim 1, further comprising a top electrode metal contact disposed on a periphery of the semiconductor structure and partially overlapping the doped layer of the top electrode, wherein the recessed portion of the top electrode reduces the series resistance of the top electrode so that current generated by the pn junction from the detection of the electrons or electromagnetic radiation is available at the top electrode metal contact.

14. The detector of claim 1 further comprising a capping layer disposed above the doped layer.

15. The detector of claim 14 , wherein the capping layer is a conductive layer.

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