Semiconductor device

Abstract

To provide a semiconductor device having a high-quality SiO2 layer.SOLUTION: A semiconductor device includes a SiC semiconductor layer having a carbon density of 1.0×1022 cm-3 or more, an SiO2 layer formed on the SiC semiconductor layer and having a connection surface in contact with the SiC semiconductor layer and a non-connection surface located on the opposite side of the connection surface, a carbon density decreasing region formed on a surface layer of the connection surface of the SiO2 layer, in which the carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region formed on the surface layer of the non-connection surface of the SiO2 layer, having a carbon density of 1.0×1019 cm-3 or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a structure in which an SiO2 layer is formed on an SiC semiconductor layer. [Background technology]

[0002] In a structure in which an SiO2 layer is formed on a SiC semiconductor layer, there is a known problem of an increase in interface state density in the interface region where the SiC semiconductor layer contacts the SiO2 layer. There are various causes for the increase in interface state density, but one of the main causes is interfacial defects in the interface region between the SiC semiconductor layer and the SiO2 layer. Interfacial defects can be formed by carbon atoms present in the interface region.

[0003] The interface state density has a correlation with the channel mobility (also called carrier mobility). More specifically, an increase in the interface state density causes a decrease in the channel mobility. Examples of methods for improving the interface state density are disclosed in Patent Document 1 and Patent Document 2.

[0004] Patent Document 1 discloses a method for manufacturing a semiconductor device, which includes a step of forming a SiO2 layer on a SiC semiconductor substrate, and a step of subjecting the SiO2 layer to a heat treatment in an inert gas atmosphere containing Ar (argon).

[0005] Patent Document 2 discloses a method for manufacturing a semiconductor device, which includes the steps of forming an SiO2 layer on a SiC semiconductor substrate and heat-treating the SiO2 layer in an atmosphere containing POCl3 (phosphoryl chloride) to add phosphorus to the SiO2 layer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-345320 [Patent Document 2] International Publication No. 2011 / 074237A1 Summary of the Invention [Problem to be solved by the invention]

[0007] The manufacturing method described in Patent Document 1 allows carbon atoms to be desorbed from the interface region of the SiC semiconductor layer where it contacts the SiO2 layer. This reduces interface defects. However, in this case, the carbon atoms remain in the SiO2 layer, making it impossible to obtain satisfactory insulating properties.

[0008] The manufacturing method of Patent Document 2 allows the carbon atoms in the SiO2 layer to react with the oxygen atoms in the atmosphere. This removes the carbon atoms in the SiO2 layer, reducing interfacial defects. However, in this case, the P (phosphorus) added to the SiO2 layer functions as a charge trap, which may cause the SiO2 layer to deteriorate over time.

[0009] An embodiment of the present invention provides a semiconductor device that can reduce interface defects between a SiC semiconductor layer and an SiO2 layer and has a high-quality SiO2 layer. [Means for solving the problem]

[0010] One embodiment of the present invention is a 1.0×10 22 cm -3 a SiC semiconductor layer having a carbon density of 1.0×10 or more; an SiO2 layer formed on the SiC semiconductor layer and having a connection surface in contact with the SiC semiconductor layer and a non-connection surface located on the opposite side of the connection surface; a carbon density decreasing region formed on a surface layer of the connection surface of the SiO2 layer, the carbon density gradually decreasing toward the non-connection surface of the SiO2 layer; and a carbon density decreasing region formed on a surface layer of the non-connection surface of the SiO2 layer, the carbon density gradually decreasing toward the non-connection surface of the SiO2 layer. 19 cm -3 and a low carbon density region having a carbon density of:

[0011] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a cross-sectional view showing a region in which a trench gate type MISFET is formed in a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a process diagram illustrating an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 3A] FIG. 3A is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 3B] FIG. 3B is a cross-sectional view showing a step subsequent to FIG. 3A. [Figure 3C] FIG. 3C is a cross-sectional view showing a step subsequent to FIG. 3B. [Figure 3D] FIG. 3D is a cross-sectional view showing a step subsequent to FIG. 3C. [Figure 3E] FIG. 3E is a cross-sectional view showing a step subsequent to FIG. 3D. [Figure 3F] FIG. 3F is a cross-sectional view showing a step subsequent to FIG. 3E. [Figure 3G] FIG. 3G is a cross-sectional view showing a step subsequent to FIG. 3F. [Figure 3H] FIG. 3H is a cross-sectional view showing a step subsequent to FIG. 3G. [Figure 3I] FIG. 3I is a cross-sectional view showing a step subsequent to FIG. 3H. [Figure 3J] FIG. 3J is a cross-sectional view showing a step subsequent to FIG. 3I. [Figure 3K] FIG. 3K is a cross-sectional view showing a step subsequent to FIG. 3J. [Figure 3L] FIG. 3L is a cross-sectional view showing a step subsequent to FIG. 3K. [Figure 3M] FIG. 3M is a cross-sectional view showing a step subsequent to FIG. 3L. [Figure 3N] FIG. 3N is a cross-sectional view showing a step subsequent to FIG. 3M. [Figure 4] FIG. 4 is a graph showing the measurement results of the carbon density of the gate oxide layer. [Figure 5]FIG. 5 is a graph showing the measurement results of the high frequency CV characteristics and the quasi-static CV characteristics of the gate oxide layer. [Figure 6] FIG. 6 is a graph obtained by converting the graph of FIG. 5 into an interface state density based on the High-Low method. [Figure 7] FIG. 7 is a graph showing the measurement results of the current density characteristics of the gate oxide layer. [Figure 8] FIG. 8 is a cross-sectional view showing a region in which a planar gate type MISFET is formed in a semiconductor device according to a second embodiment of the present invention. [Figure 9] FIG. 9 is a process diagram for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 10A] FIG. 10A is a cross-sectional view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 10B] FIG. 10B is a cross-sectional view showing a step subsequent to FIG. 10A. [Figure 10C] FIG. 10C is a cross-sectional view showing a step subsequent to FIG. 10B. [Figure 10D] FIG. 10D is a cross-sectional view showing a step subsequent to FIG. 10C. [Figure 10E] FIG. 10E is a cross-sectional view showing a step subsequent to FIG. 10D. [Figure 10F] FIG. 10F is a cross-sectional view showing a step subsequent to FIG. 10E. [Figure 10G] FIG. 10G is a cross-sectional view showing a step subsequent to FIG. 10F. [Figure 10H] FIG. 10H is a cross-sectional view showing a step subsequent to FIG. 10G. [Figure 10I] FIG. 10I is a cross-sectional view showing a step subsequent to FIG. 10H. [Figure 10J] FIG. 10J is a cross-sectional view showing a step subsequent to FIG. 10I. [Figure 10K] FIG. 10K is a cross-sectional view showing a step subsequent to FIG. 10J. [Figure 10L] FIG. 10L is a cross-sectional view showing a step subsequent to FIG. 10K. [Figure 11]FIG. 11 is a cross-sectional view showing a region in which a trench gate type MISFET is formed in a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] FIG. 1 is a cross-sectional view showing a region in which a MISFET is formed in a semiconductor device 1 according to a first embodiment of the present invention.

[0014] The semiconductor device 1 has a basic configuration equipped with a trench-gate metal insulator semiconductor field effect transistor (MISFET). The semiconductor device 1 includes an n-type SiC semiconductor layer 2 doped with n-type impurities. In this configuration, the SiC semiconductor layer 2 is made of 4H—SiC single crystal. The n-type impurities in the SiC semiconductor layer 2 may be N (nitrogen), As (arsenic), or P (phosphorus).

[0015] The SiC semiconductor layer 2 includes a first main surface 3 on one side and a second main surface 4 on the other side. The first main surface 3 and the second main surface 4 may have an off angle inclined at an angle of 10° or less in the <11-20> direction with respect to the <0001> plane of the 4H—SiC single crystal. The off angle is also the angle between the normal to the first main surface 3 and the second main surface 4 and the c-axis of the 4H—SiC single crystal.

[0016] The off angle may be 0° or more and 4° or less. An off angle of 0° means that the normal direction of the first main surface 3 and the c-axis of the 4H—SiC single crystal are aligned. The off angle may be more than 0° and less than 4°. The off angle is typically set in the range of 2°±10% or 4°±10%.

[0017] More specifically, the SiC semiconductor layer 2 has a layered structure including a SiC semiconductor substrate 5 and a SiC epitaxial layer 6. The SiC semiconductor substrate 5 forms the second main surface 4 of the SiC semiconductor layer 2. The SiC epitaxial layer 6 forms the first main surface 3 of the SiC semiconductor layer 2.

[0018] The SiC semiconductor substrate 5 is + The 4H—SiC single crystal substrate is a 4H—SiC single crystal substrate. The primary surface of the 4H—SiC single crystal substrate may have an off-angle tilted at an angle of 10° or less in the <11-20> direction with respect to the <0001> plane. More specifically, the off-angle is 0° or more and 4° or less (e.g., 2° or 4°).

[0019] The SiC semiconductor substrate 5 is formed as a drain region 7 of the MISFET. The n-type impurity concentration of the SiC semiconductor substrate 5 is 1.0×10 15 cm -3 Over 1.0 x 10 21 cm -3 or less (e.g., 1.0 × 10 18 cm -3 degree).

[0020] The SiC epitaxial layer 6 is made of an n-type 4H—SiC single crystal layer having the off-axis angle. The SiC epitaxial layer 6 has an n-type impurity concentration lower than the n-type impurity concentration of the SiC semiconductor substrate 5. The n-type impurity concentration of the SiC epitaxial layer 6 is 1.0×10 15 cm -3 Over 1.0 x 10 17 cm -3 or less (e.g., 1.0 × 10 16 cm -3 The carbon density of the SiC epitaxial layer 6 may be about 1.0×10 22 cm -3 Over 1.0 x 10 24 cm -3 or less (e.g., 5.0 × 10 22 cm -3 degree).

[0021] A p-type body region 8 is formed in a surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. The body region 8 is formed on the first main surface 3 side with a gap between it and the SiC semiconductor substrate 5. A region in the SiC epitaxial layer 6 between the SiC semiconductor substrate 5 and the body region 8 is formed as a drift region 9.

[0022] A trench gate structure 10 is formed in a surface layer portion of the first main surface 3. The trench gate structure 10 includes a gate trench 11, a gate oxide layer 12, and a gate electrode layer 13. The gate trench 11 extends from the first main surface 3 through the body region 8 to the drift region 9. A corner portion connecting the sidewall and bottom wall of the gate trench 11 may have a curved surface.

[0023] The gate oxide layer 12 is formed as an example of an SiO2 (silicon oxide) layer. The gate oxide layer 12 is formed in a film shape along the inner wall surface of the gate trench 11, and defines a recessed space within the gate trench 11. The gate oxide layer 12 may be extended from the gate trench 11 and integrally include a covering portion that covers the first main surface 3.

[0024] The gate oxide layer 12 has a connection surface 21 in contact with the SiC semiconductor layer 2 and a non-connection surface 22 located on the opposite side of the connection surface 21. The gate oxide layer 12 may have a thickness of 20 nm or more and 500 nm or less. The thickness of the gate oxide layer 12 is preferably 150 nm or less. The thickness of the gate oxide layer 12 is more preferably 100 nm or less.

[0025] The thickness of the gate oxide layer 12 is the thickness between the connection surface 21 and the non-connection surface 22. In this embodiment, the thickness of the gate oxide layer 12 is also the thickness along the normal direction to the inner wall surface of the gate trench 11. In other words, the thickness direction of the gate oxide layer 12 coincides with the normal direction to the inner wall surface of the gate trench 11.

[0026] In this embodiment, the gate oxide layer 12 includes a first region 14 and a second region 15. The first region 14 is formed along the sidewall of the gate trench 11. The second region 15 is formed along the bottom wall of the gate trench 11. The second region 15 has a second thickness T2 that is equal to or greater than the first thickness T1 of the first region 14. The ratio T2 / T1 of the second thickness T2 to the first thickness T1 may be 1 or greater and 3 or less.

[0027] The first thickness T1 may be 20 nm or more and 200 nm or less. The first thickness T1 is preferably 150 nm or less. The first thickness T1 is more preferably 100 nm or less. The second thickness T2 may be 20 nm or more and 500 nm or less. The first region 14 may have a uniform thickness. The second region 15 may have a uniform thickness. When the first thickness T1 is equal to the second thickness T2, the first region 14 and the second region 15 are formed with uniform thicknesses.

[0028] In this embodiment, the gate oxide layer 12 includes a bulge 16 formed along a corner on the opening side of the gate trench 11. The bulge 16 curves and protrudes inward into the gate trench 11. The bulge 16 narrows the opening of the gate trench 11 at the opening of the gate trench 11.

[0029] The gate oxide layer 12 includes a carbon density decreasing region 23 and a low carbon density region 24. The carbon density decreasing region 23 and the low carbon density region 24 each contain carbon atoms that have diffused from the gate oxide layer 12.

[0030] The carbon density gradually decreasing region 23 and the low carbon density region 24 are formed in the gate oxide layer 12 in a region that contacts at least the body region 8 (a channel CH of a MISFET, which will be described later). The carbon density gradually decreasing region 23 and the low carbon density region 24 are also formed in the gate oxide layer 12 in a region that contacts the drift region 9 and a source region 26, which will be described later. The carbon density gradually decreasing region 23 and the low carbon density region 24 are formed uniformly in the gate oxide layer 12.

[0031] More specifically, the carbon density gradually decreasing region 23 is formed in the surface layer of the connection surface 21 of the gate oxide layer 12. In the carbon density gradually decreasing region 23, the carbon density of the SiC epitaxial layer 6 decreases (1.0×10 22 cm -3 or more) to 1.0 × 10 19 cm -3In this embodiment, the thickness of the carbon density decreasing region 23 measured from the connection surface 21 of the gate oxide layer 12 is 0.15 nm or more and 25 nm or less.

[0032] The low carbon density region 24 is formed in the surface layer portion of the non-connected surface 22 of the gate oxide layer 12. More specifically, the low carbon density region 24 is formed in the region of the gate oxide layer 12 between the non-connected surface 22 and the carbon density gradually decreasing region 23.

[0033] The low carbon density region 24 has a thickness obtained by subtracting the thickness of the carbon density decreasing region 23 from the thickness of the gate oxide layer 12. In the thickness direction of the gate oxide layer 12, the proportion of the low carbon density region 24 in the gate oxide layer 12 is equal to or greater than the proportion of the carbon density decreasing region 23 in the gate oxide layer 12. In other words, the low carbon density region 24 has a thickness equal to or greater than the thickness of the low carbon density region 24.

[0034] More specifically, in the thickness direction of the gate oxide layer 12, the proportion of the low carbon density region 24 in the gate oxide layer 12 is greater than the proportion of the gradually decreasing carbon density region 23 in the gate oxide layer 12. In other words, the low carbon density region 24 has a thickness greater than the thickness of the low carbon density region 24.

[0035] The low carbon density region 24 is 1.0×10 19 cm -3 The carbon density of the low carbon density region 24 is more specifically 1.0×10 19 cm -3 The carbon density of the low carbon density region 24 is more specifically less than 1.0×10 17 cm -3 Beyond 1.0 x 10 18 cm -3 The minimum value of the low carbon density region 24 is located at approximately the center of the gate oxide layer 12 in the thickness direction.

[0036] The low carbon density region 24 includes a first region having a relatively high carbon density and a second region having a lower carbon density than the first region. The first region is located on the non-connection surface 22 side, and the second region is located on the connection surface 21 side. More specifically, the second region is located in a region between the first region and the low carbon density region 24.

[0037] The first area is 1.0 x 10 18 cm -3 Beyond 1.0 x 10 19 cm -3 The second region has a carbon density of 1.0×10 17 cm -3 Beyond 1.0 x 10 18 cm -3 The carbon density of the low carbon density region 24 is as follows: The minimum value of the low carbon density region 24 is located in the second region.

[0038] For example, the first region may have a thickness of 5 nm to 20 nm. The first region may have a thickness of 5 nm to 10 nm, 10 nm to 15 nm, or 15 nm to 20 nm. The first region preferably has a thickness of 10 nm or more.

[0039] The thickness of the second region varies depending on the thickness of the gate oxide layer 12. For example, the second region may have a thickness of 5 nm to 50 nm. The second region may have a thickness of 5 nm to 10 nm, 10 nm to 15 nm, 15 nm to 20 nm, 15 nm to 20 nm, 20 nm to 25 nm, 25 nm to 30 nm, 30 nm to 35 nm, 35 nm to 40 nm, 40 nm to 45 nm, or 45 nm to 50 nm. The second region may have a thickness of 5 nm to 20 nm.

[0040] The second region preferably has a thickness of 10 nm or more and is preferably formed in the gate oxide layer 12 at a depth of at least 10 nm from the non-connection surface 22 toward the connection surface 21.

[0041] P (phosphorus) is not added to the low carbon density region 24 and the carbon density gradually decreasing region 23 (i.e., the gate oxide layer 12). This "addition" does not include "diffusion." In other words, if P (phosphorus) is included as an n-type impurity in the SiC semiconductor layer 2 and the P (phosphorus) as the n-type impurity diffuses into the gate oxide layer 12, this does not mean that P (phosphorus) has been added to the gate oxide layer 12.

[0042] When the gate oxide layer 12 contains P (phosphorus) as an n-type impurity, the n-type impurity concentration (phosphorus density) of the gate oxide layer 12 is less than the n-type impurity concentration (phosphorus density) of the SiC semiconductor layer 2 (SiC epitaxial layer 6). In this case, the n-type impurity concentration (phosphorus density) of the gate oxide layer 12 has a profile that gradually decreases from the connection surface 21 toward the non-connection surface 22. This profile is formed by the diffusion of P (phosphorus) from the SiC semiconductor layer 2. The n-type impurity concentration (phosphorus density) of the gate oxide layer 12 is 1.0×10 16 cm -3 is less than.

[0043] 1 again, the gate electrode layer 13 is embedded in the gate trench 11 with the gate oxide layer 12 sandwiched therebetween. More specifically, the gate electrode layer 13 is embedded in a concave space defined by the gate oxide layer 12 within the gate trench 11.

[0044] The upper end of the gate electrode layer 13 is in contact with the bulging portion 16 of the gate oxide layer 12. As a result, the upper end of the gate electrode layer 13 has a constricted portion that is recessed along the bulging portion 16 of the gate oxide layer 12. The gate electrode layer 13 may contain at least one of tungsten, titanium, titanium nitride, molybdenum, and conductive polysilicon.

[0045] An interface region 25 is formed at the boundary surface of the SiC semiconductor layer 2 that contacts the gate oxide layer 12. In this embodiment, the interface region 25 contains nitrogen atoms. More specifically, the interface region 25 is a nitrogen-terminated surface terminated by nitrogen atoms. The nitrogen density of the interface region 25 is 5.0×1018 cm -3 Over 5.0 x 10 21 cm -3 or less (e.g., 5.0 × 10 20 cm -3 The nitrogen atoms diffuse through the gate oxide layer 12 to the interface region 25. The nitrogen atom density on the connection surface 21 side of the gate oxide layer 12 is greater than the nitrogen atom density on the non-connection surface 22 side of the gate oxide layer 12.

[0046] In the surface layer of the body region 8, the region along the sidewall of the gate trench 11 contains n + The n-type source region 26 is formed. The n-type impurity concentration of the source region 26 is 1.0×10 15 cm -3 Over 1.0 x 10 21 cm -3 or less (e.g., 1.0 × 10 19 cm -3 The n-type impurity of the source region 26 may be As (arsenic) or P (phosphorus).

[0047] In the surface layer of the body region 8, a region spaced apart from the sidewall of the gate trench 11 is provided with p + A contact region 27 is formed on the p + The contact region 27 is electrically connected to the body region 8. The contact region 27 extends from the first main surface 3 through the source region 26 to the body region 8.

[0048] Thus, in the region along the sidewall of the gate trench 11 in the surface layer portion of the first main surface 3, the source region 26, the body region 8, and the drift region 9 are formed in this order from the first main surface 3 toward the second main surface 4. The channel CH of the MISFET is formed in a region of the body region 8 facing the gate electrode layer 13 with the gate oxide layer 12 sandwiched therebetween.

[0049] An interlayer insulating layer 31 is formed on the first main surface 3. The interlayer insulating layer 31 may contain silicon oxide or silicon nitride. In this embodiment, the interlayer insulating layer 31 contains silicon oxide. The interlayer insulating layer 31 covers the trench gate structure 10 and any region of the first main surface 3. A contact hole 32 is formed in the interlayer insulating layer 31. The contact hole 32 exposes the source region 26 and the contact region 27.

[0050] A source electrode 33 is formed on the interlayer insulating layer 31. The source electrode 33 extends from above the interlayer insulating layer 31 into the contact hole 32. The source electrode 33 is connected to the source region 26 and the contact region 27 within the contact hole 32. A drain electrode 34 is connected to the second main surface 4 of the SiC semiconductor layer 2.

[0051] Fig. 2 is a process diagram illustrating an example of a method for manufacturing the semiconductor device 1 shown in Fig. 1. Figs. 3A to 3N are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 1 shown in Fig. 1.

[0052] 3A, SiC semiconductor layer 2 is prepared (step S1 in FIG. 2). SiC semiconductor layer 2 is formed through a step of preparing SiC semiconductor substrate 5 and a step of forming SiC epitaxial layer 6 on the main surface of SiC semiconductor substrate 5. SiC epitaxial layer 6 is formed by epitaxially growing SiC from the main surface of SiC semiconductor substrate 5.

[0053] 3B, p-type body region 8 is formed in a surface layer portion of first main surface 3 of SiC semiconductor layer 2 (step S2 in FIG. 2). The step of forming body region 8 includes a step of introducing p-type impurities into the surface layer portion of first main surface 3. The p-type impurities may be introduced into the surface layer portion of first main surface 3 by ion implantation.

[0054] Next, referring to FIG. 3C, +A p-type contact region 27 is formed in a surface portion of the body region 8 (step S2 in FIG. 2). The step of forming the contact region 27 includes a step of doping a p-type impurity into the surface portion of the body region 8. The p-type impurity may be doped into the surface portion of the body region 8 by ion implantation using an ion implantation mask 41.

[0055] Next, referring to FIG. 3D, + An n-type source region 26 is formed in a surface portion of the body region 8 (Step S2 in FIG. 2). The step of forming the source region 26 includes a step of doping an n-type impurity into the surface portion of the body region 8. The n-type impurity may be doped into the surface portion of the body region 8 by ion implantation using an ion implantation mask 42.

[0056] The order of the steps of forming the body region 8, the contact region 27, and the source region 26 is merely an example and is not limited to the above order. The order of the steps of forming the body region 8, the contact region 27, and the source region 26 may be changed as necessary.

[0057] Next, referring to FIG. 3E, a hard mask 43 having a predetermined pattern is formed on the first main surface 3 (Step S3 in FIG. 2). The hard mask 43 may include an insulator (e.g., silicon oxide). The hard mask 43 has an opening 44 that exposes a region where the gate trench 11 is to be formed.

[0058] 3F, a portion of the first main surface 3 that will become the gate trench 11 is removed. The unnecessary portion of the SiC semiconductor layer 2 may be removed by an etching method (e.g., a dry etching method) using the hard mask 43. This forms the gate trench 11 in the first main surface 3. Thereafter, the hard mask 43 is removed.

[0059] Next, referring to FIG. 3G, a gate oxide layer 12 is formed on the first main surface 3 (step S4 in FIG. 2). The gate oxide layer 12 is formed by an oxidation process (more specifically, a thermal oxidation process). In this step, the first main surface 3 is oxidized at a temperature of 1000° C. or higher, thereby forming a gate oxide layer 12 having a thickness of 20 nm or higher.

[0060] For example, by oxidizing the first main surface 3 at a temperature of 1150°C for about 20 hours, a gate oxide layer 12 having a thickness of about 90 nm is formed. By oxidizing the first main surface 3 at a temperature of 1300°C for about 40 minutes, a gate oxide layer 12 having a thickness of about 60 nm is formed.

[0061] The oxidation process may include a dry oxidation process or a wet oxidation process. In this embodiment, the gate oxide layer 12 is formed by the dry oxidation process. The gate oxide layer 12 may be formed by a CVD (Chemical Vapor Deposition) process instead of the oxidation process.

[0062] Immediately after the gate oxide layer 12 is formed, dangling species and carbon atoms exist in the interface region 25 of the SiC semiconductor layer 2 that contacts the gate oxide layer 12. In FIG. 3G, the dangling species are simply indicated by "X" and the carbon atoms are simply indicated by "C." The dangling species and carbon atoms are one cause of interface defects in the interface region 25. In the presence of the dangling species and carbon atoms, excellent channel mobility cannot be obtained.

[0063] 3H, a nitrogen atom introducing step is performed (step S5 in FIG. 2) to introduce nitrogen atoms into the gate oxide layer 12. The nitrogen atom introducing step is also called a post-deposition annealing step or a post-oxidation annealing step.

[0064] The nitrogen atom introduction step includes a step of performing annealing in a gas atmosphere containing nitrogen atoms, but not containing phosphorus atoms, and may be performed at a temperature of 1000°C to 1400°C (for example, about 1250°C) for 1 minute to 600 minutes.

[0065] In this embodiment, the nitrogen-containing gas is a mixed gas obtained by diluting NO (nitric oxide) gas, which contains nitrogen and oxygen atoms, with an inert gas. The inert gas may include at least one of N2 (nitrogen) gas, Ar (argon) gas, and He (helium) gas. The content of the inert gas in the mixed gas may be 5% or more and 20% or less (for example, about 10%).

[0066] In this process, nitrogen atoms in NO (nitric oxide) gas are introduced into the gate oxide layer 12. These nitrogen atoms bond with dangling species present in the interface region 25 of the SiC semiconductor layer 2. In FIG. 3H, the nitrogen atoms are indicated by "N."

[0067] In this process, oxygen atoms in the NO (nitric oxide) gas are also introduced into the gate oxide layer 12. These oxygen atoms react with carbon atoms in the gate oxide layer 12. These oxygen atoms also react with carbon atoms present in the interface region 25 of the SiC semiconductor layer 2. As a result, the carbon atoms in the gate oxide layer 12 and the carbon atoms present in the interface region 25 of the SiC semiconductor layer 2 become CO (carbon monoxide) or CO2 (carbon dioxide).

[0068] In this step, the interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., the interface region 25) can be nitrogen-terminated with nitrogen atoms. In addition, in this step, carbon atoms can be desorbed from the gate oxide layer 12 and the interface region 25. Therefore, the interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., the interface region 25) can be reduced.

[0069] Referring to FIG. 3I, after the nitrogen atom introduction step, an oxygen atom introduction step is further performed to introduce oxygen atoms into the gate oxide layer 12 (step S6 in FIG. 2). The oxygen atom introduction step includes a step of performing an annealing treatment in a low oxygen partial pressure atmosphere diluted with a mixed gas containing an inert gas. The inert gas may contain a rare gas, nitrogen atoms, etc. The low oxygen partial pressure atmosphere does not contain phosphorus atoms.

[0070] The oxygen partial pressure in the low oxygen partial pressure atmosphere may be 0.1 Pa or more and 10 Pa or less. The oxygen atom introduction step may be carried out at a temperature of 800°C or more and 1500°C or less (for example, about 1300°C) for 1 minute or more and 600 minutes or less. The pressure of the mixed gas may be 0.1 atmospheres or more and 2 atmospheres or less (for example, about 1 atmosphere).

[0071] In this step, oxygen atoms in O2 (oxygen) gas are introduced into the gate oxide layer 12. These oxygen atoms react with carbon atoms in the gate oxide layer 12. These oxygen atoms also react with carbon atoms present in the interface region 25 of the SiC semiconductor layer 2.

[0072] As a result, the carbon atoms in the gate oxide layer 12 and the interface region 25 become CO (carbon monoxide) or CO2 (carbon dioxide). As a result, the carbon atoms can be desorbed from the gate oxide layer 12 and the interface region 25.

[0073] This makes it possible to further reduce interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., in the interface region 25). In particular, in an atmosphere with an oxygen partial pressure of 0.1 Pa or more and 10 Pa or less, oxidation of the interface region 25 can be suppressed and carbon atoms can be appropriately desorbed from the interface region 25.

[0074] Next, referring to FIG. 3J, a base electrode layer 45, which serves as a base for the gate electrode layer 13, is formed on the first main surface 3 (step S7 in FIG. 2). The base electrode layer 45 may include conductive polysilicon. The base electrode layer 45 may be formed by a CVD method. The base electrode layer 45 fills the gate trench 11 and covers the first main surface 3.

[0075] 3K, unnecessary portions of the base electrode layer 45 are removed. The unnecessary portions of the base electrode layer 45 may be removed by an etching method (e.g., wet etching) using a mask (not shown). The unnecessary portions of the base electrode layer 45 may be removed until the gate oxide layer 12 is exposed. This forms the gate electrode layer 13.

[0076] Next, referring to FIG. 3L, an interlayer insulating layer 31 is formed on the first main surface 3 (step S8 in FIG. 2). The interlayer insulating layer 31 may contain silicon oxide. The interlayer insulating layer 31 may be formed by a CVD method.

[0077] Next, referring to FIG. 3M, a mask 46 having a predetermined pattern is formed on the interlayer insulating layer 31 (step S9 in FIG. 2). The mask 46 may be a resist mask containing a photosensitive resin. The mask 46 has openings 47 that expose areas where the contact holes 32 are to be formed.

[0078] Next, unnecessary portions of the interlayer insulating layer 31 are removed. The unnecessary portions of the interlayer insulating layer 31 may be removed by etching (e.g., wet etching) using a mask 46. In this step, unnecessary portions of the gate oxide layer 12 are also removed. This forms the contact holes 32. After the contact holes 32 are formed, the mask 46 is removed.

[0079] 3N, a source electrode 33 is formed on the first main surface 3, and a drain electrode 34 is formed on the second main surface 4 (step S10 in FIG. 2). Through the steps including those described above, the semiconductor device 1 is manufactured.

[0080] 4 is a graph showing the measurement results of the carbon density of gate oxide layers manufactured under conditions different from those of gate oxide layer 12. In FIG. 4, the vertical axis represents the carbon density [cm -3 ], and the horizontal axis represents depth [nm]. More specifically, the horizontal axis represents the depth in the direction from the non-connected surface 22 of the gate oxide layer 12 toward the SiC semiconductor layer 2 (connected surface 21), with the non-connected surface 22 of the gate oxide layer 12 being set to zero.

[0081] 4 shows a first curve L1, a second curve L2, and a third curve L3. The first curve L1 represents the carbon density of the first reference gate oxide layer. In the process of forming the first reference gate oxide layer, the nitrogen atom introduction step (step S5) and the oxygen atom introduction step (step S6) are not performed. The thickness of the first reference gate oxide layer is approximately 54 nm.

[0082] The second curve L2 shows the carbon density of the second reference gate oxide layer. In the formation process of the second reference gate oxide layer, an annealing process is performed in an Ar (argon) gas atmosphere instead of the nitrogen atom introduction process (step S5) and the oxygen atom introduction process (step S6). The thickness of the second reference gate oxide layer is approximately 54 nm.

[0083] The third curve L3 shows the carbon density of the third reference gate oxide layer. In the process of forming the third reference gate oxide layer, the nitrogen atom introduction process (step S5) and the oxygen atom introduction process (step S6) are performed, but the gate trench 11 formation process (step S3) is not performed. The thickness of the third reference gate oxide layer is approximately 54 nm.

[0084] The process of forming the gate oxide layer 12 according to this embodiment is the same as the process of forming the third reference gate oxide layer. The process of forming the gate oxide layer 12 according to this embodiment differs from the process of forming the third reference gate oxide layer in that the gate oxide layer 12 is formed on the inner wall of the gate trench 11 (in the growth direction relative to the SiC semiconductor layer 2). However, the carbon density of the gate oxide layer 12 according to this embodiment is substantially equal to the carbon density of the third reference gate oxide layer.

[0085] Referring to the first curve L1, the first reference gate oxide layer has a carbon density decreasing region 23 and a low carbon density region 24. The carbon density decreasing region 23 is a region where the carbon density of the SiC semiconductor layer 2 (1.0×10 22 cm -3 or more) to 1.0 × 10 19 cm -3 The low carbon density region 24 gradually decreases to 1.0×10 19 cm -3 It has the following carbon density:

[0086] The carbon density of the first reference gate oxide layer is good. However, the nitrogen atom introduction step (step S5) and the oxygen atom introduction step (step S6) have not been performed on the first reference gate oxide layer. Therefore, as shown in FIG. 3G, dangling species and carbon atoms exist in the interface region 25 of the SiC semiconductor layer 2. Therefore, excellent channel mobility cannot be obtained.

[0087] Referring to the second curve L2, the second reference gate oxide layer has a carbon density decreasing region 23 and a low carbon density region 24. The carbon density decreasing region 23 is located at the carbon density (1.0×10 22 cm -3 or more) to 1.0 × 10 21 cm -3 The low carbon density region 24 gradually decreases to 8.0×10 19 cm -3 Over 1.0 x 10 21 cm -3 It has the following carbon density:

[0088] Annealing in an Ar (argon) gas atmosphere is effective in reducing interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., in the interface region 25). However, as can be seen from the second curve L2, the second reference gate oxide layer contains a large amount of carbon atoms, and therefore, an excellent dielectric strength cannot be obtained.

[0089] Referring to the third curve L3, the third reference gate oxide layer has a carbon density decreasing region 23 and a low carbon density region 24. The carbon density decreasing region 23 is located at the carbon density (1.0×10 22 cm -3 or more) to 1.0 × 10 19 cm -3 The low carbon density region 24 gradually decreases to 1.0×10 19 cm -3 It has the following carbon density:

[0090] As is clear from the comparison between the first curve L1 and the second curve L2, the carbon density of the third reference gate oxide layer is good. Furthermore, since the nitrogen atom introduction step (step S5) is performed in the process of forming the third reference gate oxide layer, the interface defects in the interface region 25 are nitrogen-terminated by nitrogen atoms. Furthermore, since the oxygen atom introduction step (step S6) is performed in the process of forming the third reference gate oxide layer, carbon atoms are desorbed from the interface region 25. Therefore, the third reference gate oxide layer (i.e., gate oxide layer 12) can achieve excellent channel mobility and excellent dielectric strength.

[0091] Furthermore, in the manufacturing method for the third reference gate oxide layer, annealing is not performed in an atmosphere containing P (phosphorus). Therefore, P (phosphorus) is not added to the third reference gate oxide layer. In other words, the introduction of charge traps is suppressed in the third reference gate oxide layer. Therefore, the third reference gate oxide layer (i.e., gate oxide layer 12) can suppress deterioration over time due to charge traps.

[0092] 5 is a graph showing the measurement results of the high-frequency CV characteristics and the quasi-static CV characteristics, in which the vertical axis represents the ratio C / Cox of the total capacitance C of the semiconductor device 1 to the capacitance Cox of the gate oxide layer 12, and the horizontal axis represents the gate voltage VG [V].

[0093] FIG. 5 shows a first hysteresis curve HL1, a second hysteresis curve HL2, and a third hysteresis curve HL3.

[0094] The first hysteresis curve HL1 shows the high-frequency CV characteristics (see solid line) and quasi-static CV characteristics (see dashed line) of the fourth reference gate oxide layer. In the process of forming the fourth reference gate oxide layer, the nitrogen atom introduction process (step S5) and the oxygen atom introduction process (step S6) are not performed.

[0095] The second hysteresis curve HL2 shows the high-frequency CV characteristics (see solid line) and quasi-static CV characteristics (see dashed line) of the fifth reference gate oxide layer. In the process of forming the fifth reference gate oxide layer, the nitrogen atom introduction process (step S5) was performed, but the oxygen atom introduction process (step S6) was not performed.

[0096] The third hysteresis curve HL3 shows the high-frequency CV characteristics (see solid line) and quasi-static CV characteristics (see dashed line) of the sixth reference gate oxide layer. The sixth reference gate oxide layer formation process includes the nitrogen atom introduction process (step S5) and the oxygen atom introduction process (step S6), but does not include the gate trench 11 formation process (step S3). The sixth reference gate oxide layer has a thickness of approximately 54 nm.

[0097] The gate oxide layer 12 according to this embodiment is formed using the sixth reference gate oxide layer formation process. The gate oxide layer 12 according to this embodiment differs from the sixth reference gate oxide layer formation process in that the gate oxide layer 12 is formed on the inner wall of the gate trench 11 (in the growth direction relative to the SiC semiconductor layer 2). However, the high-frequency CV characteristics and quasi-static CV characteristics of the gate oxide layer 12 according to this embodiment are substantially equal to those of the sixth reference gate oxide layer (see solid line) and quasi-static CV characteristics (see dashed line).

[0098] The larger the capacitance difference between the high-frequency CV characteristics (see solid line) and the quasi-static CV characteristics (see dashed line), the larger the interface state density Dit. In other words, the capacitance difference between the high-frequency CV characteristics (see solid line) and the quasi-static CV characteristics (see dashed line) indicates the amount of charge trapped by the gate oxide layer.

[0099] Referring to FIG. 5, it can be seen that the difference in capacitance between the high-frequency CV characteristics (see solid line) and the quasi-static CV characteristics (see dashed line) decreases in the order of the first hysteresis curve HL, the second hysteresis curve HL2, and the third hysteresis curve HL3.

[0100] The effective fixed charge of the fourth reference gate oxide layer is -7.0×10 11 cm -2 The effective fixed charge is calculated by multiplying the flat band voltage shift by the capacitance value of the gate oxide layer. The effective fixed charge of the fifth reference gate oxide layer is -1.0 × 10 11 cm -2 It was about that extent.

[0101] The effective fixed charge of the sixth reference gate oxide layer has a positive value. The effective fixed charge of the sixth reference gate oxide layer is 1.0×10 11 cm -2 Over 1.0 x 10 13 cm -2 or less (more specifically, 1.0 x 10 12 cm -2 (degree).

[0102] 6 is a graph in which the graph in FIG. 5 is converted into the interface state density Dit based on the High-Low method. In FIG. 6, the vertical axis represents the interface state density Dit [eV -1 ·cm -2 ], and the horizontal axis is the energy level EC-ET [eV -1 The energy level EC-ET from the conduction band edge is, more specifically, the difference between the energy level EC of the conduction band and the energy level ET of the trap band.

[0103] FIG. 6 shows a first curve L11, a second curve L12, and a third curve L13.

[0104] A first curve L11 shows the characteristics of the interface state density Dit in the interface region 25 that contacts the fourth reference gate oxide layer in the SiC semiconductor layer 2. A second curve L12 shows the characteristics of the interface state density Dit in the interface region 25 that contacts the fifth reference gate oxide layer in the SiC semiconductor layer 2.

[0105] A third curve L13 shows the characteristics of the interface state density Dit of the interface region 25 in contact with the sixth reference gate oxide layer in the SiC semiconductor layer 2. The process of forming the gate oxide layer 12 according to this embodiment differs from the process of forming the sixth reference gate oxide layer in that the gate oxide layer 12 is formed on the inner wall of the gate trench 11 (growth direction relative to the SiC semiconductor layer 2). However, the interface state density Dit of the gate oxide layer 12 according to this embodiment is substantially equal to the interface state density Dit of the sixth reference gate oxide layer.

[0106] 6, it can be seen that the interface state density Dit decreases in the order of the first curve L11, the second curve L12, and the third curve L13. Referring to the third curve L13, the interface state density Dit of the sixth reference gate oxide layer is 4.0×10 when the energy level EC-ET from the conduction band edge is in the range of 0.2 eV to 0.5 eV. 11 eV -1 ·cm -2 It was as follows.

[0107] The interface state density Dit of the sixth reference gate oxide layer is 2.0×10 in the range of the energy level EC-ET from the conduction band edge of 0.3 eV to 0.5 eV. 11 eV -1 ·cm -2 Furthermore, the interface state density Dit of the sixth reference gate oxide layer was 1.0×10 or less when the energy level EC-ET from the conduction band edge was in the range of 0.4 eV or more and 0.5 eV or less. 11 eV -1 ·cm -2 It was as follows.

[0108] The interface state density Dit and the channel mobility of the SiC semiconductor layer 2 are in a trade-off relationship. That is, when the interface state density Dit is high, the channel mobility of the SiC semiconductor layer 2 is low. On the other hand, when the interface state density Dit is low, the channel mobility of the SiC semiconductor layer 2 is high.

[0109] The interface state density Dit of the sixth reference gate oxide layer is 4.0×10 11 eV -1 ·cm -2 In the semiconductor device having the sixth reference gate oxide layer (i.e., the semiconductor device 1 having the gate oxide layer 12), the channel mobility of the SiC semiconductor layer 2 is 50 cm or less, which is relatively low. 2 / Vs or more.

[0110] 7 is a graph showing the measurement results of the current density characteristics of the gate oxide layer 12. In FIG. 7, the vertical axis represents the current density [A·cm 2 ] flowing through the gate oxide layer 12. -2 ], and the horizontal axis is the electric field strength [MV cm -1 ].

[0111] The electric field strength applied to the gate oxide layer 12 is 6.0 MV cm -1 The current density flowing through the gate oxide layer 12 is 1.0×10 -9 A cm -2 The electric field strength applied to the gate oxide layer 12 was 6.0 MV cm -1 to 9.0 MV·cm -1 When the temperature rises to 1.0×10 -6 A cm -2 increased to a certain extent.

[0112] The electric field strength applied to the gate oxide layer 12 is 9.0 MV cm -1 (More specifically, 9.5MV·cm -1 ) or more, the current density flowing through the gate oxide layer 12 increased significantly. -1 (More specifically, 9.5MV·cm -1) or more, it was found that the breakdown field strength was relatively high.

[0113] As described above, according to the method for manufacturing semiconductor device 1, nitrogen atoms are introduced into gate oxide layer 12 in the nitrogen atom introduction step (step S5 in FIG. 2). These nitrogen atoms reach interface region 25 in SiC semiconductor layer 2 that contacts gate oxide layer 12 (see also FIG. 3H). As a result, interface defects between SiC semiconductor layer 2 and gate oxide layer 12 (i.e., interface region 25) can be nitrogen-terminated with nitrogen atoms.

[0114] Furthermore, according to this manufacturing method, in the oxygen atom introduction step (step S6 in FIG. 2), an annealing treatment is performed on the gate oxide layer 12 in an atmosphere containing oxygen atoms, thereby introducing oxygen atoms into the gate oxide layer 12 (see also FIG. 3I).

[0115] These oxygen atoms react with carbon atoms in the gate oxide layer 12. These oxygen atoms also react with carbon atoms present in the interface region 25. As a result, the carbon atoms in the gate oxide layer 12 and the carbon atoms present in the interface region 25 become CO (carbon monoxide) or CO2 (carbon dioxide).

[0116] As a result, carbon atoms can be desorbed from the gate oxide layer 12 and the interface region 25. This makes it possible to reduce interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12, and to obtain a high-quality gate oxide layer 12.

[0117] The gate oxide layer 12 preferably has a relatively small thickness. More specifically, the thickness of the gate oxide layer 12 is preferably 20 nm or more and 150 nm or less. The thickness of the gate oxide layer 12 is more preferably 20 nm or more and 100 nm or less. By reducing the thickness of the gate oxide layer 12, carbon atoms in the gate oxide layer 12 can be appropriately released. This allows the carbon density in the interface region 25 to be appropriately reduced, and interface defects to be appropriately reduced.

[0118] 8 is a cross-sectional view showing a region in which a planar MISFET is formed in a semiconductor device 51 according to a second embodiment of the present invention. In the following, structures corresponding to those described in the semiconductor device 1 are given the same reference numerals and descriptions thereof will be omitted.

[0119] 8, semiconductor device 51 has a basic configuration including a planar-gate MISFET. Semiconductor device 51 includes an n-type SiC semiconductor layer 2. A well-shaped p-type body region 8 is formed in a surface layer portion of a first main surface 3 of SiC semiconductor layer 2. A source region 26 and a contact region 27 are formed in a surface layer portion of body region 8.

[0120] The source region 26 is formed at an interval from the periphery of the body region 8 to the inner region. The contact region 27 is formed in the center of the body region 8 in a plan view. The source region 26 may surround the contact region 27.

[0121] A planar gate structure 62 is formed on the first main surface 3 of the SiC semiconductor layer 2. The planar gate structure 62 has a laminated structure including a gate oxide layer 12 and a gate electrode layer 13 laminated in this order on the first main surface 3.

[0122] The gate oxide layer 12 faces the source region 26, the body region 8, and the drift region 9 on the first main surface 3. The gate oxide layer 12 may have a thickness of 20 nm or more and 500 nm or less. In this embodiment, the thickness of the gate oxide layer 12 is measured along the normal direction of the first main surface 3. The thickness of the gate oxide layer 12 is preferably 150 nm or less. The thickness of the gate oxide layer 12 is more preferably 100 nm or less. In this embodiment, the gate oxide layer 12 is formed to a uniform thickness.

[0123] Gate oxide layer 12 has a connection surface 21 in contact with first principal surface 3 and a non-connection surface 22 located opposite connection surface 21. Gate oxide layer 12 includes the aforementioned gradually decreasing carbon density region 23 and low carbon density region 24. The carbon concentration profile of gate oxide layer 12 is similar to that of the third reference gate oxide layer (i.e., gate oxide layer 12), as shown in FIG.

[0124] The gate electrode layer 13 faces the source region 26, the body region 8, and the drift region 9, with the gate oxide layer 12 sandwiched therebetween. The gate electrode layer 13 may contain at least one of copper, aluminum, and conductive polysilicon.

[0125] A channel CH of the MISFET is formed in a region of the body region 8 facing the gate electrode layer 13 with the gate oxide layer 12 sandwiched therebetween. An interface region 25 is formed at the boundary surface of the SiC semiconductor layer 2 that contacts the gate oxide layer 12.

[0126] An interlayer insulating layer 31 is formed on the first main surface 3. The interlayer insulating layer 31 covers the planar gate structure 62. The interlayer insulating layer 31 has contact holes 32 that expose the source region 26 and the contact region 27.

[0127] A source electrode 33 is formed on the interlayer insulating layer 31. The source electrode 33 extends from above the interlayer insulating layer 31 into the contact hole 32. The source electrode 33 is connected to the source region 26 and the contact region 27 within the contact hole 32. A drain electrode 34 is connected to the second main surface 4 of the SiC semiconductor layer 2.

[0128] Fig. 9 is a process diagram illustrating an example of a method for manufacturing the semiconductor device 51 shown in Fig. 8. Figs. 10A to 10L are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 51 shown in Fig. 8.

[0129] 10A, SiC semiconductor layer 2 is prepared (step S11 in FIG. 9). SiC semiconductor layer 2 is formed through a step of preparing SiC semiconductor substrate 5 and a step of forming SiC epitaxial layer 6 on the main surface of SiC semiconductor substrate 5. SiC epitaxial layer 6 is formed by epitaxially growing SiC from the main surface of SiC semiconductor substrate 5.

[0130] 10B, p-type body region 8 is formed in a surface layer portion of first main surface 3 (step S12 in FIG. 9). The step of forming body region 8 includes a step of introducing p-type impurities into the surface layer portion of first main surface 3. The p-type impurities may be introduced into the surface layer portion of first main surface 3 of SiC semiconductor layer 2 by ion implantation using ion implantation mask 71.

[0131] Next, referring to FIG. 10C, + An n-type source region 26 is formed in a surface portion of the body region 8 (Step S12 in FIG. 9). The step of forming the source region 26 includes a step of doping an n-type impurity into the surface portion of the body region 8. The n-type impurity may be doped into the surface portion of the body region 8 by ion implantation using an ion implantation mask 72.

[0132] Next, referring to FIG. 10D, p + A p-type contact region 27 is formed (Step S12 in FIG. 9). The step of forming the contact region 27 includes a step of doping a p-type impurity into a surface layer portion of the body region 8. The p-type impurity may be doped into the surface layer portion of the body region 8 by ion implantation using an ion implantation mask 73.

[0133] The order of the steps of forming the body region 8, the source region 26, and the contact region 27 is merely an example and is not limited to the above order. The order of the steps of forming the body region 8, the source region 26, and the contact region 27 may be changed as necessary.

[0134] Next, referring to FIG. 10E, a gate oxide layer 12 is formed on the first main surface 3 (step S13 in FIG. 9). The gate oxide layer 12 is formed by an oxidation treatment method (more specifically, a thermal oxidation treatment method). In this step, the first main surface 3 is oxidized at a temperature of 1000° C. or higher, thereby forming a gate oxide layer 12 having a thickness of 20 nm or higher.

[0135] For example, by oxidizing the first main surface 3 at a temperature of 1150°C for about 20 hours, a gate oxide layer 12 having a thickness of about 90 nm is formed. Also, by oxidizing the first main surface 3 at a temperature of 1300°C for about 40 minutes, a gate oxide layer 12 having a thickness of about 60 nm is formed.

[0136] The oxidation process may include a dry oxidation process or a wet oxidation process. In this embodiment, the gate oxide layer 12 is formed by the dry oxidation process. Of course, the gate oxide layer 12 may be formed by a CVD (Chemical Vapor Deposition) process instead of the oxidation process.

[0137] Immediately after the gate oxide layer 12 is formed, dangling species and carbon atoms exist in the interface region 25 of the SiC semiconductor layer 2 that contacts the gate oxide layer 12. In FIG. 10E, the dangling species are simply indicated by "X" and the carbon atoms are simply indicated by "C." The dangling species and carbon atoms are one cause of interface defects in the interface region 25. In the presence of the dangling species and carbon atoms, excellent channel mobility cannot be obtained.

[0138] Next, referring to Figure 10F, a nitrogen atom introducing step is performed to introduce nitrogen atoms into the gate oxide layer 12 (Step S14 in Figure 9). The nitrogen atom introducing step is also called a post-deposition annealing step or a post-oxidation annealing step.

[0139] The nitrogen atom introduction step may be performed at a temperature of 1000°C to 1400°C (for example, about 1250°C) for 1 minute to 600 minutes. The nitrogen atom introduction step includes a step of performing an annealing treatment in a gas atmosphere containing nitrogen atoms. This atmosphere does not contain phosphorus atoms.

[0140] In this embodiment, the nitrogen-containing gas is a mixed gas obtained by diluting NO (nitric oxide) gas, which contains nitrogen and oxygen atoms, with an inert gas. The inert gas may include at least one of N2 (nitrogen) gas, Ar (argon) gas, and He (helium) gas. The content of the inert gas in the mixed gas may be 5% or more and 20% or less (for example, about 10%).

[0141] In this process, nitrogen atoms in NO (nitric oxide) gas are introduced into the gate oxide layer 12. These nitrogen atoms bond with dangling species present in the interface region 25 of the SiC semiconductor layer 2. In FIG. 10F, the nitrogen atoms are indicated by "N."

[0142] In this process, oxygen atoms in the NO (nitric oxide) gas are also introduced into the gate oxide layer 12. These oxygen atoms react with carbon atoms in the gate oxide layer 12. These oxygen atoms also react with carbon atoms present in the interface region 25. As a result, the carbon atoms in the gate oxide layer 12 and the carbon atoms present in the interface region 25 become CO (carbon monoxide) or CO2 (carbon dioxide).

[0143] In this manner, in this step, the interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., the interface region 25) can be nitrogen-terminated with nitrogen atoms. Also, in this step, carbon atoms can be desorbed from the gate oxide layer 12 and the interface region 25. Therefore, the interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., the interface region 25) can be reduced.

[0144] Referring to FIG. 10G, after the nitrogen atom introduction step, an oxygen atom introduction step is further performed to introduce oxygen atoms into the gate oxide layer 12 (step S15 in FIG. 9). The oxygen atom introduction step includes a step of performing an annealing treatment in a low oxygen partial pressure atmosphere diluted with a mixed gas containing an inert gas. The inert gas may contain a rare gas, nitrogen atoms, etc. This atmosphere does not contain phosphorus atoms.

[0145] The oxygen partial pressure in the low oxygen partial pressure atmosphere may be 0.1 Pa or more and 10 Pa or less. The oxygen atom introduction step may be carried out at a temperature of 800°C or more and 1500°C or less (for example, about 1300°C) for 1 minute or more and 600 minutes or less. The pressure of the mixed gas may be 0.1 atmospheres or more and 2 atmospheres or less (for example, about 1 atmosphere).

[0146] In this step, oxygen atoms in O2 (oxygen) gas are introduced into the gate oxide layer 12. The oxygen atoms react with carbon atoms in the gate oxide layer 12. The oxygen atoms also react with carbon atoms present in the interface region 25.

[0147] As a result, the carbon atoms in the gate oxide layer 12 and the interface region 25 become CO (carbon monoxide) or CO2 (carbon dioxide). As a result, the carbon atoms can be desorbed from the gate oxide layer 12 and the interface region 25.

[0148] This makes it possible to further reduce interface defects between the SiC semiconductor layer 2 and the gate oxide layer 12 (i.e., in the interface region 25). In particular, in an atmosphere with an oxygen partial pressure of 0.1 Pa or more and 10 Pa or less, oxidation of the interface region 25 can be suppressed and carbon atoms can be appropriately desorbed from the interface region 25.

[0149] 10H, a base electrode layer 74 that serves as a base for gate electrode layer 13 is formed on first main surface 3 (step S16 in FIG. 9). Base electrode layer 74 may contain polysilicon or aluminum. Base electrode layer 74 may be formed by a CVD method.

[0150] 10I, a mask 75 having a predetermined pattern is formed on the base electrode layer 74. The mask 75 covers the region of the base electrode layer 74 where the gate electrode layer 13 is to be formed.

[0151] Next, unnecessary portions of the base electrode layer 74 are removed. The unnecessary portions of the base electrode layer 74 may be removed by an etching method (e.g., wet etching) using a mask 75. In this way, the gate electrode layer 13 is formed.

[0152] Next, referring to Fig. 10J, an interlayer insulating layer 31 is formed on the first main surface 3 (step S17 in Fig. 9). The interlayer insulating layer 31 may contain silicon oxide. The interlayer insulating layer 31 may be formed by a CVD method.

[0153] 10K, a mask 76 having a predetermined pattern is formed on the interlayer insulating layer 31 (step S18 in FIG. 9). The mask 76 may be a resist mask containing a photosensitive resin. The mask 76 has openings 77 that expose areas where the contact holes 32 are to be formed.

[0154] Next, unnecessary portions of the interlayer insulating layer 31 are removed. The unnecessary portions of the interlayer insulating layer 31 may be removed by etching (e.g., wet etching) using the mask 76. This forms the contact holes 32. After the contact holes 32 are formed, the mask 76 is removed.

[0155] 10L, the source electrode 33 is formed on the first main surface 3, and the drain electrode 34 is formed on the second main surface 4 (step S19 in FIG. 9). Through the steps including those described above, the semiconductor device 51 is manufactured.

[0156] As described above, the semiconductor device 51 according to this embodiment has the same structure as the semiconductor device 1, except that it has the planar gate structure 62 instead of the trench gate structure 10. Therefore, the semiconductor device 51 and the method for manufacturing the semiconductor device 51 can also achieve the same effects as those described for the semiconductor device 1 and the method for manufacturing the semiconductor device 1.

[0157] 11 is a cross-sectional view showing a region in which a trench-gate MISFET is formed in a semiconductor device 81 according to a third embodiment of the present invention. In the semiconductor device 1 according to the first embodiment, it has been explained that the gate oxide layer 12 may be formed to a uniform thickness. Also, in the semiconductor device 1 according to the first embodiment, it has been explained that the gate oxide layer 12 may be formed by a CVD method in the step of FIG. 3G.

[0158] The semiconductor device 81 according to the third embodiment is an example of the semiconductor device 1 including a gate oxide layer 12 formed by a CVD method. In the following, structures corresponding to those described in the semiconductor device 1 are denoted by the same reference numerals and will not be described again.

[0159] 11, in this embodiment, the gate oxide layer 12 is formed by a CVD method and is formed into a film with a uniform thickness that covers the sidewalls and bottom wall of the gate trench 11. That is, the first thickness T1 of the gate oxide layer 12 is approximately equal to the second thickness T2 of the gate oxide layer 12 (T1=T2 (T1≈T2)).

[0160] The first thickness T1 being approximately equal to the second thickness T2 means that the first thickness T1 has a value within ±10% of the second thickness T2 (T2×0.9≦T1≦T2×1.1). Of course, under the condition that the gate oxide layer 12 is formed by a CVD method, the first thickness T1 may be greater than the second thickness T2 (for example, T1>T2×1.1) or less than the second thickness T2 (for example, T1 <T2×0.9)であってもよい。

[0161] 3A to 3N, the semiconductor device 81 is manufactured by the same manufacturing method as the semiconductor device 1. Also, as shown in Fig. 4, the carbon concentration profile of the gate oxide layer 12 of the semiconductor device 81 is similar to the carbon concentration profile of the third reference gate oxide layer (i.e., the gate oxide layer 12).

[0162] As described above, the semiconductor device 81 and the method for manufacturing the semiconductor device 81 can also achieve the same effects as those described for the semiconductor device 1 and the method for manufacturing the semiconductor device 1.

[0163] Although the present invention has been described above with reference to certain preferred embodiments, it is possible to embody the invention in other forms.

[0164] For example, in each of the above-described embodiments, an example has been described in which the oxygen atom introducing step (step S6 in FIG. 2 and step S15 in FIG. 9) is performed after the nitrogen atom introducing step (step S5 in FIG. 2 and step S14 in FIG. 9). However, in each of the above-described embodiments, only the oxygen atom introducing step (step S6 in FIG. 2 and step S15 in FIG. 9) may be performed without performing the nitrogen atom introducing step (step S5 in FIG. 2 and step S14 in FIG. 9).

[0165] In the above-described embodiments, examples have been described in which the nitrogen atom introduction step (step S5 in FIG. 2 and step S14 in FIG. 9) and the oxygen atom introduction step (step S6 in FIG. 2 and step S15 in FIG. 9) are performed on the gate oxide layer 12. However, the nitrogen atom introduction step (step S5 in FIG. 2 and step S14 in FIG. 9) and the oxygen atom introduction step (step S6 in FIG. 2 and step S15 in FIG. 9) may also be performed on an SiO layer other than the gate oxide layer 12.

[0166] The SiO2 layer other than the gate oxide layer 12 may include an SiO2 layer for region isolation, such as a LOCOS (Local Oxidation Of Silicon) layer. In addition, an SiO2 layer formed by oxidizing the first main surface 3 or an SiO2 layer formed on the first main surface 3 by a CVD method is also suitable as the SiO2 layer other than the gate oxide layer 12.

[0167] The technical idea of ​​performing the nitrogen atom introduction process (step S5 in FIG. 2 and step S14 in FIG. 9) and the oxygen atom introduction process (step S6 in FIG. 2 and step S15 in FIG. 9) to remove carbon atoms from the gate oxide layer 12 (SiO2 layer) and the interface region 25 can be expected to be somewhat effective on insulating layers containing inorganic insulators other than SiO2.

[0168] Examples of insulating layers containing inorganic insulators other than SiO include a SiN (silicon nitride) layer, an AlO (aluminum oxide) layer, and an ONO layer. The ONO layer has a layered structure including a SiO layer, a SiN layer, and a SiO layer stacked in this order on the first main surface 3 of the SiC semiconductor layer 2. That is, in each of the above-described embodiments, the gate oxide layer 12 may include a SiN layer, an AlO layer, an ONO layer, or the like instead of or in addition to SiO.

[0169] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0170] In each of the above embodiments, n + Instead of the SiC semiconductor substrate 5, + A type SiC semiconductor substrate 5 may be employed. + The SiC semiconductor substrate 5 functions as a collector region of an IGBT (Insulated Gate Bipolar Transistor). In this case, in each of the above-described embodiments, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

[0171] This specification does not limit any combination of the features shown in the first to third embodiments. The first to third embodiments can be combined in any manner and in any form. In other words, the features shown in the first to third embodiments can be combined in any manner and in any form.

[0172] This application corresponds to Patent Application No. 2018-005735 filed with the Japan Patent Office on January 17, 2018, the entire disclosure of which is incorporated herein by reference.

[0173] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0174] 1...semiconductor device, 2...SiC semiconductor layer, 5...SiC semiconductor substrate, 6...SiC epitaxial layer, 12...gate oxide layer (SiO2 layer), 13...gate electrode layer, 21...connected surface of gate oxide layer, 22...non-connected surface of gate oxide layer, 23...carbon density gradually decreasing region, 24...low carbon density region, 25...interface region, 51...semiconductor device, 81...semiconductor device

Claims

1. 1.0 x 10 ２２ cm －３ a SiC semiconductor layer having a carbon density of at least 1000 nm; a SiO.sub.2 film formed on the SiC semiconductor layer, the SiO.sub.2 film having a connection surface in contact with the SiC semiconductor layer and a non-connection surface located opposite the connection surface; ２ Layers and The SiO ２ The SiO ２ a carbon density decreasing region in which the carbon density gradually decreases toward the non-connected surface of the layer; The SiO ２ The layer is formed on the surface of the non-connecting surface of the layer, and the thickness is 1.0 × 10 １９ cm －３ and a low carbon density region having a carbon density of:

2. The low carbon density region is ２ 2. The semiconductor device according to claim 1, wherein the low carbon density region occupies a proportion equal to or greater than the proportion of the thickness of the layer between the connection surface and the non-connection surface.

3. 3. The semiconductor device according to claim 1, wherein the low carbon density region has a thickness equal to or greater than the thickness of the gradually decreasing carbon density region.

4. The carbon density of the carbon density decreasing region is 1.0×10 １９ cm －３ Gradually decrease to The low carbon density region is 1.0×10 １９ cm －３ 4. The semiconductor device according to claim 1, wherein the semiconductor device has a carbon density of less than 1000 .mu.m.

5. The SiO ２ The nitrogen atom density on the connection surface side of the layer is ２ 5. The semiconductor device according to claim 1, wherein the nitrogen atom density is higher than that of the non-connection surface side of the layer.

6. In the SiC semiconductor layer, ２ The energy level from the conduction band edge is in the range of 0.2 eV to 0.5 eV, and the energy level is 4.0×10 １１ eV －１ ・cm －２ 6. The semiconductor device according to claim 1, further comprising an interface region having an interface state density of not more than 1000 .mu.m.sup.

2.

7. The SiO ２ The layer is 9.0 MV cm －１ 7. The semiconductor device according to claim 1, wherein the breakdown field strength is equal to or greater than 100 Ω / s.

8. The SiO ２ The semiconductor device according to any one of claims 1 to 7, wherein the layer has a thickness of 20 nm or more.

9. the SiC semiconductor layer includes a SiC semiconductor substrate and a SiC epitaxial layer formed on the SiC semiconductor substrate; The SiO ２ 9. The semiconductor device according to claim 1, wherein a layer is formed on the SiC epitaxial layer.

10. The SiC epitaxial layer has a thickness of 1.0×10 １５ cm －３ Above 1.0 x 10 １７ cm －３ 10. The semiconductor device according to claim 9, wherein the semiconductor device has an n-type impurity concentration of:

11. The SiO ２ The semiconductor device according to any one of claims 1 to 10, further comprising an electrode facing the SiC semiconductor layer with a layer sandwiched therebetween.

12. a trench is formed in the SiC semiconductor layer, The SiO ２ 11. The semiconductor device according to claim 1, wherein the layer is formed along an inner wall surface of the trench.

13. The SiO ２ 13. The semiconductor device according to claim 12, wherein the thickness of the layer varies depending on the portion covering the inner wall surface of the trench.

14. The SiO ２ The semiconductor device according to claim 12 or 13, further comprising an electrode embedded in the trench with the layer sandwiched therebetween.

15. In the SiC semiconductor layer, ２ 15. The semiconductor device according to claim 1, further comprising an electrode formed on a surface opposite to the surface on which the layer is formed.

16. The semiconductor device according to any one of claims 1 to 15, wherein the SiC semiconductor layer includes a 4H-SiC single crystal and includes a main surface having an off angle of 10° or less with respect to a <11-20> direction from a [0001] plane of the 4H-SiC single crystal.

Images