Semiconductor device

Abstract

To provide a transistor including an oxide semiconductor and capable of a high-speed operation and provide a highly reliable semiconductor device including the transistor.SOLUTION: A semiconductor device comprises an oxide semiconductor layer including a pair of low-resist regions and a channel formation region and provided on an electrode layer buried in a groove in a base insulation layer. The channel formation region is formed at a position overlapping a gate electrode layer having a sidewall on lateral walls. The groove has a deeper region and a shallower region, the sidewall overlaps the shallower region and connection with wiring overlaps the deeper region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a technology for miniaturizing semiconductor integrated circuits. In addition to silicon semiconductors, semiconductor integrated circuits are also made up of compound semiconductors. Examples of such elements include a semiconductor device using an oxide semiconductor and a manufacturing method thereof. Regarding.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor devices have been developed and are used as LSIs, CPUs, and memories. A CPU is a semiconductor integrated circuit (at least transistors and It is a collection of semiconductor elements that have a memory and on which electrodes that serve as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, e.g., printed circuit boards. It is mounted on a wiring board and used as one of the components in various electronic devices.

[0005] Silicon-based semiconductor materials are semiconductor materials that can be used in transistors used in semiconductor circuits. For example, in Patent Document 1, in order to achieve high integration, A structure has been proposed that shortens the distance between the contact and the substrate, thereby reducing the resistance between them. There are.

[0006] In addition to silicon, oxide semiconductors are also attracting attention as materials other than silicon. For example, Transistors were fabricated using zinc oxide and In-Ga-Zn oxide as oxide semiconductors. The technology used for switching elements of pixels in display devices is disclosed in Patent Documents 2 and 3. It has been disclosed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-327617 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0008] The channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories is shortened. By reducing the size of the transistors, we can increase the operating speed of the circuits. One of the objects is to reduce power consumption.

[0009] According to one embodiment of the present invention, a transistor including an oxide semiconductor and capable of high-speed operation and a method for manufacturing the same are provided. Another object of the present invention is to provide a method for manufacturing a semiconductor device including the transistor. One object is to provide a body device and a method for manufacturing the same. [Means for solving the problem]

[0010] By removing impurities that act as electron donors (donors) in the oxide semiconductor, it is possible to obtain intrinsic or substantially oxide semiconductors, which are fully intrinsic semiconductors and have a larger energy gap than silicon semiconductors Using transistors in which the channel formation region is formed in the body, A semiconductor integrated circuit is fabricated.

[0011] Contact resistance occurs between the oxide semiconductor and the conductive layer. It is necessary to ensure sufficient contact area.

[0012] Therefore, a conductive layer in contact with the upper surface of the oxide semiconductor layer and a conductive layer in contact with the lower surface of the oxide semiconductor layer are formed. By providing a sufficient contact area, contact resistance can be reduced.

[0013] One aspect of the present invention disclosed in this specification is a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor device including a semiconductor substrate. an oxide semiconductor layer on the gate insulating layer; and an oxide semiconductor layer on the gate insulating layer. A gate electrode layer overlapping the conductor layer and a sidewall on the side of the gate electrode layer, and an insulating layer A trench having a deep region and a shallow region, and a conductive region in the trench, and the sidewall is a shallow The semiconductor device is characterized in that it overlaps with the region.

[0014] In the above structure, the conductive layer may be in contact with the sidewall and the oxide semiconductor layer. Both are characteristics.

[0015] In the above structure, an interlayer insulating layer is further provided on the gate electrode layer, and a gate insulating film is provided on the interlayer insulating layer. The wiring has a conductive type region and is electrically connected to the deep region. It is one.

[0016] In the above structure, the conductive region is a shallow region having a first width in the channel length direction. and a deep region having a second width in the channel length direction. .

[0017] Also, a semiconductor device that has multiple semiconductor integrated circuits mounted in one package to increase integration. A so-called MCP (Multi Chip Package) may also be used.

[0018] When mounting a semiconductor integrated circuit on a circuit board, it may be mounted face up. Alternatively, a flip chip configuration (face down configuration) may be used.

[0019] The manufacturing method is also one aspect of the present invention, and the configuration thereof includes forming a first insulating film on a first electrode layer. A first planarization process is performed to expose the upper surface of the first electrode layer. A second electrode layer is formed in contact with the second electrode layer, a second insulating film is formed on the second electrode layer, and A second planarization treatment is performed to expose the upper surface of the second electrode layer, and the oxide semiconductor film is formed in contact with the upper surface of the second electrode layer. a gate insulating layer is formed on the oxide semiconductor film; a gate electrode layer and a gate insulating layer are formed on the gate insulating layer; and forming an insulating film covering the upper surface of the gate electrode layer, the insulating film overlapping the second electrode layer and A sidewall is formed in contact with a side surface of the electrode layer, and the gate electrode layer and the sidewall are covered. a conductive film is formed on and in contact with the oxide semiconductor film; and a portion of the conductive film overlapping with a gate electrode layer is formed on the oxide semiconductor film. This is a method for manufacturing a semiconductor device, in which a third planarization treatment is performed to remove the insulating portion. [Effects of the Invention]

[0020] The channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories is shortened. When the oxide semiconductor layer is thinned, the contact resistance of the oxide semiconductor layer is reduced, thereby increasing the operating speed of the circuit. Furthermore, it will achieve a reduction in power consumption. [Brief explanation of the drawings]

[0021] [Figure 1]1A and 1B are examples of a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 4] 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 5] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 6] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 8] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0023] (Embodiment 1) 1A and 1B are cross-sectional views and a top view of a transistor 420 as an example of a semiconductor device. 1A is a cross-sectional view of a transistor 420; 1(B) is a cross-sectional view taken along the XY line. Therefore, some of the components of the transistor 420 (for example, the insulating film 407, the insulating film 410, the interlayer The insulating film 415 and the like are omitted from the illustration.

[0024] The transistor 420 shown in FIGS. 1A and 1B is formed on a substrate 400 having an insulating surface. and a base insulating layer 436 and a metal oxide film embedded in the base insulating layer 436 and having at least one upper surface. The electrode layer 425a and the electrode layer 425b are exposed from the base insulating layer 436, and a pair of low resistance Regions 404a and 404b, and the channel sandwiched between the low resistance region 404a and the low resistance region 404b an oxide semiconductor layer 403 including a panel formation region 409; a gate insulating layer 402 and a gate insulating layer 403 formed on the channel forming region 409 via the gate insulating layer 402; and a sidewall insulating layer 412 provided on the side of the gate electrode layer 401. a, 412b, an insulating film 413 provided on the gate electrode layer 401, and a source electrode layer 40 an insulating film 410 provided on the insulating film 410; an interlayer insulating film 415 formed thereon, an insulating film 407 formed on the interlayer insulating film 415, and an insulating film 4 07, the source electrode layer 40 is formed through an opening provided in the interlayer insulating film 415 and the insulating film 410. 5a and the drain electrode layer 405b, respectively. and a second wiring layer 465b.

[0025] The interlayer insulating film 415 is provided to flatten the unevenness caused by the transistor 420. The height of the upper surface is approximately the same as that of the sidewall insulating layers 412a and 412b and the insulating film 410. The wall insulating layers 412a and 412b are also called sidewalls. The height of the upper surface of the drain electrode layer 405b is determined by the height of the interlayer insulating film 415, the sidewall insulating layer 412a, 12b and the upper surface of the insulating film 413, and the upper surface of the gate electrode layer 401. The height here refers to the height from the upper surface of the substrate 400.

[0026] 1, the electrode layer 425a and the electrode layer 425b are formed in a deep region in the base insulating layer 436. The sidewall insulating layers 412a and 412b are formed to fill the trench having a deep region and a shallow region. b overlaps with the shallow region. Also, the first wiring layer 465a and the second wiring layer 465b are provided at positions overlapping with the deep region. The wiring layer 465b is formed.

[0027] 1, the insulating film 407 is formed by the interlayer insulating film 415, the source electrode layer 405a, the drain electrode layer 405b, and the like. the inner electrode layer 405b, the sidewall insulating layers 412a and 412b, the insulating film 413, and the insulating film 410. It is set up as such.

[0028] Note that dopant is deposited on the oxide semiconductor film 403 in a self-aligned manner using the gate electrode layer 401 as a mask. The channel formation region 409 is sandwiched between the oxide semiconductor film 403 and the channel formation region 409. The resistivity of the dopant-containing low-resistance regions 404a and 404b is lower than that of the dopant-containing region 409. The dopant is an impurity that changes the conductivity of the oxide semiconductor film 403. The methods of introducing ions include ion implantation, ion doping, and plasma immersion ion implantation. For example, a ion implantation method can be used.

[0029] The channel formation region 409 is sandwiched between low resistance regions 404a and 404b in the channel length direction. The oxide semiconductor film 403 and the source electrode layer 40 in contact with a part of the upper surface of the oxide semiconductor film 403 5a and the drain electrode layer 405b, and the electrode layer 4 25a and electrode layer 425b, the transistor 420 has an on-characteristic (e.g., For example, the on-state current and field effect mobility are high, enabling high-speed operation and high-speed response.

[0030] The oxide semiconductor used for the oxide semiconductor film 403 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. The oxide semiconductor is used as a stabilizer for reducing oxygen vacancies in the oxide semiconductor. In addition to these, it is preferable to have gallium (Ga). It is preferable to have tin (Sn) as a stabilizer. ) as a stabilizer. It is also preferable that the stabilizer contains zirconium (Zr). It's nice.

[0031] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0032] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0033] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0034] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0035] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxides with atomic ratios of (=1 / 2:1 / 6:1 / 3) and their neighboring compositions Alternatively, an oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or is In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8). It is preferable to use a -Zn-based oxide or an oxide having a composition close to that.

[0036] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0037] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0038] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1) is close to the oxide composition by r, and a, b, and c are (aA) 2 +(bB ) 2 +(cC) 2 ≦r 2 For example, if r is set to 0.05, The same is true for other oxides.

[0039] The oxide semiconductor film 403 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0040] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0041] Here, CAAC (C Axis Aligned Crystal) means that the c axis of the oxide The three-dimensional structure is perpendicular to the surface on which the semiconductor film is formed or the surface thereof, and is perpendicular to the ab plane. It has a square or hexagonal atomic arrangement, and the metal atoms are layered or arranged in a direction perpendicular to the c-axis. This refers to a mixed phase structure of crystal and amorphous in which metal atoms and oxygen atoms are arranged in layers. In this multiphase structure, the CAACs may have different a-axis and b-axis directions. stomach.

[0042] CAAC Oxide Semiconductor (CAAC-OS:C Axis Aligned Crysta The thin film of a thin film oxide semiconductor is not a completely single crystal, but The CAAC-OS film is an oxide semiconductor film with a crystalline-amorphous mixed phase structure. The size of the crystals is estimated to be several nm to several tens of nm. Observation by Transmission Electron Microscope In the CAAC-OS film, the boundary between the amorphous phase and the CAAC phase is not necessarily clear. Furthermore, no crystal grain boundaries were observed in the CAAC-OS film. Since the CAAC-OS film does not have grain boundaries, the decrease in electron mobility due to grain boundaries is is less likely to occur.

[0043] Note that in the CAAC-OS film, the distribution of crystalline regions in the film does not need to be uniform. For example, when crystals grow from the surface side of the CAAC-OS film, the crystals grow near the surface of the CAAC-OS film. The proportion of crystalline material is higher near the surface where the film is formed, and the proportion of amorphous material is higher near the surface where the film is formed. There is.

[0044] The c-axis of the crystalline part of the CAAC is perpendicular to the surface on which the CAAC-OS film is formed or the surface. The shape of the CAAC-OS film (cross-sectional shape of the surface on which it is formed or cross-sectional shape of the surface) Therefore, the direction of the c-axis may be different. The direction of the CAAC-OS film is approximately perpendicular to the surface on which the film is formed. CAAC can be formed by performing a crystallization process such as heat treatment during or after film formation. It is done.

[0045] By using a CAAC-OS film, the electrical characteristics of a transistor can be improved by irradiating it with visible light or ultraviolet light. Since the fluctuation of the resistance is reduced, a highly reliable transistor can be obtained.

[0046] Note that part of oxygen contained in the oxide semiconductor film may be substituted with nitrogen.

[0047] The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). m or less), and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition The oxide semiconductor film 403 can be formed by a spat Film deposition is performed with multiple substrate surfaces set approximately perpendicular to the target surface. The sputtering equipment that performs this process is called the CP sputtering equipment (Columner Plasma Sputtering). The film may be formed using a heating system.

[0048] 2A to 2E and 3A to 3D show a semiconductor device having a transistor 420. An example of a method for manufacturing the device is shown below.

[0049] First, electrode layers 422a and 422b are formed on a substrate 400 having an insulating surface. 22a and 422b are, for example, Al, Cr, Cu, Ta, Ti, Mo, and W. Metal films containing the selected elements or metal nitride films containing the above elements (e.g. titanium nitride) Films such as molybdenum nitride film, tungsten nitride film, etc. can be used. A high melting point metal film such as Ti, Mo, W, etc. is applied to either or both of the upper and lower sides of a metal film such as u. or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) A laminated structure may also be used.

[0050] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as aluminoborosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. Also, silicon or silicon carbide substrates can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A substrate, an SOI substrate, or the like can also be used, and a semiconductor element is provided on such a substrate. may be used as the substrate 400.

[0051] Next, an insulating film 423 is formed to cover the electrode layers 422a and 422b. 2(A).

[0052] The insulating film 423 is formed by depositing silicon oxide, oxide film, or the like by plasma CVD or sputtering. Silicon nitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide It is formed using rubber, or a mixture of these materials.

[0053] Next, the insulating film 423 and the electrode layers 422a and 422b are cut (ground and polished). The grinding and polishing method is chemical mechanical polishing. Polishing (CMP) method can be suitably used.

[0054] Next, electrode layers 424a and 424b are formed to overlap the electrode layers 422a and 422b. The electrode layers 424a and 424b may be made of, for example, Al, Cr, Cu, Ta, Ti, Mo, A metal film containing an element selected from W, or a metal nitride film containing the above-mentioned element as a component ( Titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) can be used. A high melting point metal such as Ti, Mo, W is applied to one or both of the upper and lower sides of a metal film such as Al, Cu, etc. Metal films or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) It may also be configured by laminating a thin film (TEN film).

[0055] Next, an insulating film 426 is formed to cover the electrode layers 424a and 424b. 2(B). The boundary between the insulating film 423 and the insulating film 426 is shown by a dotted line. When using the insulating film, the boundary is no longer clear, so the dotted lines indicating the boundary are omitted in the following figures. The stack of the electrode layer 422a and the insulating film 426 is illustrated as a base insulating layer 436. If the same material is used for the electrode layers 422a and 422b and the electrode layers 424a and 424b, there will be no clear boundary. Therefore, the dotted lines indicating the boundaries are omitted in the following figures, and the electrode layers 422a, 422b and the electrode layer 42 The stack of layers 424a and 424b is shown as electrode layers 425a and 425b.

[0056] Next, the insulating film 426 and the electrode layers 424a and 424b are cut (ground and polished). The CMP method is used as the grinding and polishing method.

[0057] Next, the oxide semiconductor film 403 is formed over the base insulating layer 436 and the electrode layers 425a and 425b. do.

[0058] Note that in this embodiment, the oxide semiconductor film 403 is formed by a sputtering method. The target for this purpose is a composition ratio of In:Ga:Zn=3:1:2 [atomic ratio]. An In-Ga-Zn oxide film (IGZO film) is formed using an oxide target.

[0059] The oxide semiconductor film 403 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0060] The substrate is held in a film-forming chamber that is kept in a reduced pressure state, and the remaining moisture in the film-forming chamber is removed. The sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the target. In order to remove residual moisture in the deposition chamber, an oxide semiconductor film 403 is formed on the substrate. type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps It is preferable to use a turbo molecular pump with a cold trap as the exhaust means. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably compounds containing carbon atoms) Since gases such as impurities are exhausted, the impurities contained in the oxide semiconductor film 403 formed in the deposition chamber are The concentration of substances can be reduced.

[0061] The oxide semiconductor film 403 is formed by forming an oxide semiconductor film into island-like regions by a photolithography process. The insulating film can be formed by processing an oxide semiconductor film.

[0062] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0063] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. For example, an etching method used for wet etching of an oxide semiconductor film may be used. The cleaning solution can be a mixture of phosphoric acid, acetic acid, and nitric acid. O-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Dry etching using the Inductively Coupled Plasma (Inductively Coupled Plasma) etching method For example, an IGZO film can be etched by ICP etching. Etching conditions: etching gas (BCl3:Cl2 = 60 sccm, 20sccm), power supply power 450W, bias power 100W, pressure 1.9Pa), and It can be processed into

[0064] Further, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300°C or higher and 700°C or lower. The temperature should be below ℃ or below the distortion point of the substrate. The heat treatment should be carried out under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment apparatus, and an oxide semiconductor The film 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0065] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0066] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 to 700°C. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0067] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not contained. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than 1 ppm.

[0068] Note that the timing of heat treatment for dehydration or dehydrogenation is determined based on the time when the oxide semiconductor film is heated. The above-described step may be performed after the formation of the oxide semiconductor film 403 or after the formation of the island-shaped oxide semiconductor film 403.

[0069] The heat treatment for dehydration or dehydrogenation may be carried out multiple times, or may be carried out in combination with other heat treatments. You can sleep.

[0070] Further, after the dehydration or dehydrogenation treatment, the oxide semiconductor film 403 is heated to 10 ... oxygen radicals, oxygen atoms, or oxygen ions) are introduced to supply oxygen into the film. That's fine.

[0071] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. In the oxide semiconductor film, oxygen is released and the amount of oxygen is reduced. Oxygen vacancies exist in the areas where the oxide has been removed, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. Therefore, a donor level is generated.

[0072] Oxygen is introduced into the oxide semiconductor film 403 that has been subjected to dehydration or dehydrogenation treatment. By supplying the oxide semiconductor film 403, the oxide semiconductor film 403 is highly purified and electrically made i-type (intrinsic). The oxide semiconductor film 403 that has been highly purified and made electrically i-type (intrinsic) can be used. The transistor thus obtained has suppressed fluctuations in electrical characteristics and is electrically stable.

[0073] The oxygen introduction method includes ion implantation, ion doping, and plasma immersion. On-implantation methods, plasma treatment, etc. can be used.

[0074] In the step of introducing oxygen into the oxide semiconductor film 403, The ions may be introduced directly or through other films such as the gate insulating layer 402 into the oxide semiconductor film 40 3. When oxygen is introduced through another membrane, ion implantation, ion doping, etc. The method of plasma immersion ion implantation, etc. can be used. In the case where oxygen is directly introduced into the exposed oxide semiconductor film 403, plasma treatment or the like may be used. You can be there.

[0075] Oxygen is preferably introduced into the oxide semiconductor film 403 after dehydration or dehydrogenation treatment. However, there is no particular limitation thereto. Oxygen may be introduced into 3 multiple times.

[0076] Next, the gate insulating layer 402 is formed to cover the oxide semiconductor film 403 (see FIG. 2C). .

[0077] The thickness of the gate insulating layer 402 is set to 1 nm or more and 20 nm or less, and is formed by sputtering or MBE. The method, CVD method, pulsed laser deposition method, ALD method, etc. can be used as appropriate. The insulating layer 402 is formed by forming a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. Even if a film is formed using a sputtering device that forms a film in a set state, a so-called CP sputtering device, good.

[0078] The gate insulating layer 402 may be made of a silicon oxide film, a gallium oxide film, or an aluminum oxide film. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or an aluminum nitride film The gate insulating layer 402 can be formed using a silicon film. It is preferable that the gate insulating layer 402 contains oxygen in the film. It is preferred that there is at least a stoichiometric amount of oxygen present (in the bulk), e.g. For example, when a silicon oxide film is used as the gate insulating layer 402, SiO 2+α (just In this embodiment, the gate insulating layer 402 is made of SiO 2+α (Ta The silicon oxide film is used as the gate insulating layer 40. By using the oxide semiconductor film 403 as the oxide semiconductor film 2, oxygen can be supplied to the oxide semiconductor film 403, and the characteristics can be improved. Furthermore, the gate insulating layer 402 can be formed by adjusting the size and thickness of the transistor to be fabricated. It is preferable to form the gate insulating layer 402 in consideration of its step coverage.

[0079] The gate insulating layer 402 may be made of hafnium oxide, yttrium oxide, or hafnium. Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and high-k materials such as lanthanum oxide can be used to Furthermore, the gate insulating layer 402 may have a single layer structure or a stacked layer structure. It may also be a structure.

[0080] Next, a conductive film and an insulating film are stacked over the gate insulating layer 402. Etching is performed to form a stack of the gate electrode layer 401 and the insulating film 413 (see FIG. 2(C)). (see).

[0081] The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, aluminum, or the like. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as their main components The gate electrode layer 401 can be formed using a gold material. Semiconductor films such as element-doped polycrystalline silicon films, nickel silicide, etc. The gate electrode layer 401 may have a single layer structure or a stacked layer structure. The structure may also be used.

[0082] The insulating film 413 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. , aluminum oxynitride film, silicon nitride film, aluminum nitride film, silicon nitride oxide film An inorganic insulating film such as an aluminum nitride oxide film can be used for the insulating layer 413. The film can be formed by plasma CVD, sputtering, or the like.

[0083] Next, the oxide semiconductor film 403 is doped with a dopant using the gate electrode layer 401 and the insulating film 413 as masks. A punt 421 is introduced to form low resistance regions 404a and 404b (see FIG. 2(D)).

[0084] The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor film 403. The 421st group of elements includes group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Ant). Sb), boron (B), aluminum (Al), nitrogen (N), argon (Ar) , neon (Ne), indium (In), titanium (Ti), and zinc (Zn) One or more selected from the following can be used.

[0085] The dopant 421 is implanted through other films (e.g., the gate insulating layer 402) to The dopant 421 can also be introduced into the oxide semiconductor film 403. Ion implantation, ion doping, plasma immersion ion implantation Methods such as these can be used.

[0086] The dopant 421 introduction process is performed by adjusting the injection conditions such as the acceleration voltage and the dose amount, and the film through which the dopant 421 passes. In this embodiment, phosphorus is used as the dopant 421. The phosphorus ions are implanted by ion implantation using the dopant 421. is 1 x 10 13 ions / cm 2 5x10 or more 16 ions / cm 2 The following would suffice.

[0087] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0088] The dopant 421 may be introduced while the substrate 400 is heated.

[0089] Note that the treatment of introducing the dopant 421 into the oxide semiconductor film 403 may be performed multiple times. A plurality of types of dopants may be used.

[0090] After the introduction of the dopant 421, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be performed.

[0091] In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The implantation conditions for phosphorus (P) ions are an acceleration voltage of 30 kV and a dose of 1.0 × 1 0 15 ions / cm 2 Let's say.

[0092] When the oxide semiconductor film 403 is a CAAC-OS film, the introduction of the dopant 421 In this case, a heat treatment is performed after the introduction of the dopant 421. This allows the crystallinity of the oxide semiconductor film 403 to be restored.

[0093] By the above process, low resistance regions 404a and 404b are formed on either side of the channel forming region 409. An oxide semiconductor film 403 is formed by the above-mentioned steps.

[0094] Next, an insulating film is formed on the gate electrode layer 401 and the insulating film 413, and the insulating film is etched. Then, sidewall insulating layers 412a and 412b are formed. The edge layers 412a and 412b are used as a mask to form the gate electrode layer 401 and the sidewall insulating layers 412a and 412b. The gate insulating layer is etched except for the region overlapping with 412b to form the gate insulating layer 402. (See Figure 3(A)).

[0095] The sidewall insulating layers 412a and 412b are formed using the same material and method as the insulating film 413. In this embodiment, a silicon oxynitride film formed by a CVD method is used. .

[0096] Next, an oxide semiconductor film 403, a gate insulating layer 402, a gate electrode layer 401, and a sidewall insulating layer On the insulating film 413 and the insulating film 412a and 412b, a source electrode layer and a drain electrode layer (and A conductive film is formed to form a layer (including wiring formed in the same layer).

[0097] The conductive film is made of a material that can withstand subsequent heat treatment. The conductive film used is selected from Al, Cr, Cu, Ta, Ti, Mo, and W, for example. Metal films containing the above elements, or metal nitride films containing the above elements (titanium nitride film, Molybdenum nitride film, tungsten nitride film, etc.) can be used. A high melting point metal film such as Ti, Mo, W, etc. is placed on either the top or bottom of any metal film or both. These metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) are stacked It may also be configured as follows.

[0098] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After forming the island-shaped conductive film 445 by etching, the resist mask is removed. In this etching step, the conductive film 445 on the gate electrode layer 401 is not removed.

[0099] When a tungsten film having a thickness of 30 nm is used as the conductive film, the conductive film is etched as follows: For example, the tungsten film is etched by dry etching (etching conditions: The gas (CF4:Cl2:O2 = 55sccm:45sccm:55sccm, power supply voltage The tungsten island was formed under the conditions of a power of 3000 W, a bias power of 140 W, and a pressure of 0.67 Pa. A film may be formed.

[0100] An insulating film 410 and an insulating film 446 are stacked on the island-shaped conductive film 445 to form an interlayer insulating film (FIG. 3(B)).

[0101] The insulating film 410 is made of a highly dense inorganic insulating film (typically an aluminum oxide film), It may be a layer or a laminate, and preferably contains at least an aluminum oxide film.

[0102] The insulating film 446 can be formed using a material and a method similar to those of the insulating film 413. The insulating film 446 is formed to a thickness that can flatten the unevenness caused by the transistor 420. In this embodiment, a silicon oxynitride film is formed to a thickness of 300 nm by the CVD method.

[0103] Next, the insulating film 446 and the conductive film 445 are polished by chemical mechanical polishing. The insulating film 446, the insulating film 410, and the conductive film 445 are partly removed so that the ...13 is exposed.

[0104] By this polishing treatment, the insulating film 446 is processed into an interlayer insulating film 415, and the insulating film 446 is formed on the gate electrode layer 401. The conductive film 445 is removed, and the source electrode layer 405a and the drain electrode layer 405b are formed. .

[0105] In this embodiment, the insulating film 446, the insulating film 410, and the conductive film 445 are removed by chemical mechanical etching. Although a polishing method was used, other cutting (grinding, polishing) methods may also be used. In the process of removing the conductive film 445 on the substrate 01, cutting (grinding, polishing) such as chemical mechanical polishing is performed. In addition to polishing, etching (dry etching, wet etching) and plasma treatment For example, after the removal process by chemical mechanical polishing, dry etching may be performed. The flatness of the treated surface is improved by using a sputtering method or plasma treatment (reverse sputtering, etc.). It is also possible to combine cutting (grinding, polishing) with etching, plasma treatment, etc. In this case, the order of the steps is not particularly limited. This may be appropriately set depending on the material, film thickness, and surface irregularities.

[0106] In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are gate electrodes. The insulating layer 412a is provided on the side of the outer electrode layer 401, and the insulating layer 412b is provided on the side of the outer electrode layer 401. The insulating layer 412a covers the side surfaces of the sidewall insulating layers 412a and 412b up to a position slightly lower than the upper end. The source electrode layer 405a and the drain electrode layer 405b are formed by removing the conductive film 445. As shown in this embodiment, the sidewall insulating layers 412a and 4 12b, the shape may be recessed in the film thickness direction from the polished surface of the insulating film 413. However, depending on the conditions of the polishing process, the source electrode layer 405a and the drain electrode layer 405 In some cases, the upper end of the insulating layer 412b may be substantially aligned with the upper end of the sidewall insulating layers 412a and 412b.

[0107] Through the above steps, the transistor 420 of this embodiment is manufactured (see FIG. 3C).

[0108] By such a manufacturing method, the source electrode layer 405a or the drain electrode layer 405b and the oxide The distance between the gate electrode layer 401 and the region (first contact region) where the semiconductor film 403 is in contact with the gate electrode layer 401 is In addition, the distance between the electrode layers 425a and 425b and the oxide semiconductor film 403 can be reduced. It is also possible to shorten the distance between the region where the gate electrode layer 401 comes into contact with the gate electrode layer 401 (second contact region). Therefore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film The resistance between the gate electrode layer 401 and the region where the gate electrode layer 403 contacts the first contact region is reduced. This makes it possible to slightly improve the on-state characteristics of the transistor 420.

[0109] In addition, the gate electrode layer in the step of forming the source electrode layer 405a and the drain electrode layer 405b In the step of removing the conductive film 445 on the layer 401, a part of the insulating film 413 or the insulating film 4 Alternatively, the entire gate electrode layer 13 may be removed. Also, an upper portion of the gate electrode layer 401 may be removed. The transistor structure that exposes the gate electrode layer 401 is not provided with other wiring or It is useful in integrated circuits where semiconductor elements are stacked.

[0110] A highly dense inorganic insulating film (typically aluminum oxide) is formed on the transistor 420 as a protective insulating film. A thin film (aluminum film) may be provided.

[0111] In this embodiment, the insulating film 413, the source electrode layer 405a, the drain electrode layer 405b, the side electrode layer 405a, and the An insulating film 412 is formed on the wall insulating layers 412a and 412b, the insulating film 410, and the interlayer insulating film 415. 07 (see Figure 3(D)).

[0112] The insulating film 407 may be a single layer or a multilayer, and preferably contains at least an aluminum oxide film. I wish.

[0113] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. This can be done.

[0114] Besides the aluminum oxide film, the insulating films 407 and 410 are typically silicon oxide films. an inorganic insulating film such as a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film; Also, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, etc. can be used. aluminium oxide film, lanthanum oxide film, barium oxide film, or metal nitride film (e.g., aluminum nitride A film (aluminum film) can also be used.

[0115] In this embodiment, the insulating films 407 and 410 are made of aluminum oxide by sputtering. The aluminum oxide film is formed at a high density (film density 3.2 g / cm 3 Above, preferably is 3.6g / cm 3 By using a voltage of 100 V or more, the transistor 420 can have stable electrical characteristics. The film density can be measured by Rutherford backscattering spectroscopy (RBS). d Backscattering Spectrometry) and X-ray reflectivity measurement It can be measured by X-Ray Reflection (XRR).

[0116] The insulating films 407 and 410 provided over the oxide semiconductor film 403 are made of an oxide material. The aluminum chloride membrane does not allow impurities such as hydrogen and moisture, and oxygen to pass through the membrane. It has a high blocking effect.

[0117] 1A, the insulating film 410, the interlayer insulating film 415, and the insulating film 407 are covered with a source electrode. and a wiring layer 435a in the opening. 435a and 435b are formed. By connecting it to elements, various circuits can be configured.

[0118] The wiring layer 435a and the wiring layer 435b are connected to the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b. The layer 405b can be formed using the same material and method as the layer 405b. For example, Al a metal film containing an element selected from the group consisting of Cr, Cu, Ta, Ti, Mo, and W, or Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements In addition, a metal film such as Al or Cu may be used as the upper or lower side. On both sides, a high melting point metal film such as Ti, Mo, W, or a metal nitride film of these metals (titanium nitride) A laminated structure of a silicon nitride film, a molybdenum nitride film, and a tungsten nitride film may also be used.

[0119] (Embodiment 2) In this embodiment, the transistor described in Embodiment 1 is used, and the transistor is used in a state where power is not supplied. However, an example of a semiconductor device that can retain memory contents and has no limit on the number of times it can be written is: The semiconductor device of this embodiment mode will be described with reference to the drawings. The transistor 420 described in Embodiment 1 is used.

[0120] FIG. 4 shows an example of the configuration of a semiconductor device. FIG. 4(A) shows a cross-sectional view of the semiconductor device, and FIG. 4(B) shows a cross-sectional view of the semiconductor device. 4(B) shows a plan view of the semiconductor device, and FIG. 4(C) shows a circuit diagram of the semiconductor device. FIG. 4A corresponds to the cross sections taken along lines C1-C2 and D1-D2 in FIG. 4B.

[0121] The semiconductor device shown in FIGS. 4A and 4B has a transistor using a first semiconductor material in the lower part. a transistor 160 and a transistor 162 made of a second semiconductor material on top of it; The transistor 162 has the same structure as the transistor 420 described in Embodiment 1. It can be said that:

[0122] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used can easily operate at high speed. The properties of the charge storage capacitor allow it to retain charge for a long period of time.

[0123] The transistor 162 is a transistor including an oxide semiconductor and has a small off-state current. By using this transistor, it is possible to retain stored data for a long period of time. In other words, no refresh operation is required, or the frequency of refresh operation is extremely low. Therefore, it is possible to reduce the power consumption of the semiconductor memory device. can.

[0124] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. Therefore, the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, The specific configuration of the is not necessarily limited to that shown here.

[0125] The transistor 160 in FIG. 4A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on the substrate 100, and a an impurity region 120 provided in the semiconductor substrate; and a metal compound region 124 in contact with the impurity region 120. A gate insulating layer 108 is provided on the channel forming region 116, and and a gate electrode layer 110. In the figure, the source electrode However, for convenience, we refer to such a state as a transistor. In this case, the source is sometimes called the The source electrode and drain electrode are sometimes referred to as the source electrode and drain region. In this specification, the term "source electrode" may include a source region.

[0126] An element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. An insulating layer 130 is provided to cover the transistor 160. To achieve this, the transistor 160 is provided with a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, In this case, a sidewall insulating layer is provided on the side surface of the gate electrode layer 110, and the impurity concentration is different. The impurity region 120 may include a region.

[0127] The transistor 162 illustrated in FIG. 4A is a transistor in which an oxide semiconductor is used for a channel formation region. The oxide semiconductor layer 144 is a low-resistance region 144a, a low-resistance region 14 The low-resistance region 144a includes a conductive layer 143a and a channel forming region 144c. The low resistance region 144b is formed on and in contact with the conductive layer 143b. The formation region 144c is in contact with the insulating layer 154 sandwiched between the conductive layer 143a and the conductive layer 143b. It is formed by

[0128] In the manufacturing process of the transistor 162, the gate electrode 148, the insulating film 137, and the sidewall insulating film 138 are formed. a step of removing the conductive film provided on the edge layers 136a and 136b by chemical mechanical polishing; The electrode layers 142a and 142b functioning as a source electrode layer and a drain electrode layer are formed using the above-mentioned SiO 2 film. Complete.

[0129] Therefore, the transistor 162 has an electrode layer that functions as a source electrode layer or a drain electrode layer. The contact regions 142a and 142b are in contact with the oxide semiconductor layer 144, and the gate Since the distance to the electrode 148 can be shortened, the electrode layers 142a and 142b and the oxide semiconductor The resistance between the contact area with the conductor layer 144 and the gate electrode 148 is reduced. As a result, the on-characteristics of the transistor 162 can be improved.

[0130] On the transistor 162, an insulating film 149, an interlayer insulating film 135, and an insulating film 150 are formed as a single layer or In this embodiment, the insulating film 149 and the insulating film 150 are formed of a laminated film. The aluminum oxide film is made of high density aluminum oxide (film density 3.2 g / cm 3 End , preferably 3.6 g / cm 3 By setting the voltage to 0 V or more, a stable Electrical properties can be imparted.

[0131] The conductive layer 143a and the insulating layer 143b are connected via the insulating film 149, the interlayer insulating film 135, and the insulating film 150. The conductive layer 153 is provided in the overlapping region, and the conductive layer 143a and the insulating film 149 are The interlayer insulating film 135, the insulating film 150, and the conductive layer 153 constitute a capacitance element 164. That is, the conductive layer 143a functions as one electrode of the capacitor element 164, and The electrode layer 153 functions as the other electrode of the capacitor 164. Alternatively, the capacitor 164 may not be provided. , may be provided above the transistor 162.

[0132] An insulating film 152 is provided over the transistor 162 and the capacitor 164. On the insulating film 152, a transistor 162 and a wiring for connecting other transistors are provided. The wiring 156a is provided between the insulating film 149 and the interlayer insulating film 13. 5, the insulating film 150, the insulating film 152, etc., are formed in the openings formed through the electrodes. The wiring 156b is electrically connected to the insulating film 149 and the interlayer insulating film 135. , and conductive electrodes formed in openings formed in the insulating film 150 and the insulating film 152. It is electrically connected to layer 143b.

[0133] In FIGS. 4A and 4B, the transistor 160 and the transistor 162 are The source region of the transistor 160 is provided so as to overlap at least a part of the Preferably, the drain region is provided so as to partially overlap the oxide semiconductor layer 144. In addition, the transistor 162 and the capacitor 164 are at least For example, the conductive layer 153 of the capacitor 164 is provided so as to partially overlap with the At least a part of the gate electrode layer 110 of the transistor 160 is overlapped therewith. By adopting such a planar layout, the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0134] Next, an example of a circuit configuration corresponding to FIGS. 4A and 4B is shown in FIG. 4C.

[0135] In FIG. 4C, the first wiring (1st Line) and the source voltage of the transistor 160 The electrode is electrically connected to the second wiring (2nd Line) and the gate of the transistor 160. The third line and the drain electrode are electrically connected. The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode of the fourth transistor 162. The wiring (4th Line) and the gate electrode layer of the transistor 162 are electrically connected. The gate electrode layer of the transistor 160 and the source layer of the transistor 162 are One of the source electrode and the drain electrode is electrically connected to the other electrode of the capacitor 164. The fifth wiring (5th Line) and the other electrode of the capacitor element 164 are electrically connected. There are.

[0136] In the semiconductor device illustrated in FIG. 4C, the potential of the gate electrode layer of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: .

[0137] The writing and retention of data will be described. First, the potential of the fourth wiring is set to the potential of the transistor 1. The potential is set to a level at which the transistor 62 is turned on, thereby turning on the transistor 162. The potential of the third wiring is connected to the gate electrode layer of the transistor 160 and the capacitor 164. That is, a predetermined charge is given to the node FG. Here, the charge that gives two different potential levels (hereafter referred to as Low level) is Then, the fourth The potential of the wiring is set to a potential at which the transistor 162 is turned off. By turning off the node FG, the charge applied to the node FG is held (held).

[0138] Since the off-state current of the transistor 162 is extremely small, the gate electrode layer of the transistor 160 The charge is retained for a long time.

[0139] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, Then, when an appropriate potential (read potential) is applied to the fifth wiring, the charge held in the node FG Generally, the transistor 160 is an n-channel In this case, the node FG (which can also be referred to as the gate electrode of the transistor 160) The apparent threshold voltage V when a high level charge is applied to th_H is node F Apparent threshold voltage V when a low-level charge is applied to G th_L become lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is in the "on" state. Therefore, the potential of the fifth wiring is V th_H and V th_L By setting the potential V0 between the two, the potential applied to the node FG For example, if a high level charge is applied during writing, The potential of the fifth wire is V0 (>V th_H ), transistor 160 is "on" When a low level charge is applied, the potential of the fifth wire becomes V0( <V th_L ), transistor 160 remains in the "off state." By checking the potential of the second wiring, the stored data can be read out.

[0140] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 160 is in the "off state" regardless of V th_H Alternatively, a lower potential may be applied to the fifth wiring regardless of the state of the gate electrode layer. The potential at which transistor 160 is "on," i.e., V th_L Larger power Just give the position to the fifth wire.

[0141] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0142] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0143] In the transistor 162, the low-resistance region 144a of the oxide semiconductor layer is The conductive layer 143a embedded in the layer and the electrode layer 142a are in contact with each other and electrically connected to each other. It is possible to reduce contact resistance and achieve excellent electrical characteristics (e.g., high on-current characteristics). Therefore, the transistor 162 can be applied as a By doing so, it is possible to achieve high performance of the semiconductor device. Since the transistor is highly reliable, the reliability of the semiconductor device can be improved.

[0144] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0145] (Embodiment 3) In this embodiment mode, the transistor described in Embodiment 1 is used, and a A semiconductor device that can retain memory contents even in a difficult situation and has no limit on the number of times it can be written. The configuration different from that shown in the second embodiment will be described with reference to FIGS. 5 and 6. Note that the semiconductor device of this embodiment is the same as the transistor 162 described in Embodiment 1. The transistor 162 is configured by using the transistor shown in Embodiment 1. Any of the transistor structures can be applied.

[0146] FIG. 5(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 5(B) shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 5(A) will be explained, followed by the semiconductor device shown in FIG. The semiconductor device shown in B) will be described below.

[0147] In the semiconductor device shown in FIG. 5A, the bit line BL and the source electrode of the transistor 162 The drain electrode is electrically connected to the word line WL and the gate of the transistor 162. The electrode layer is electrically connected to the source electrode or drain electrode of the transistor 162. The first terminal of the capacitor 254 is electrically connected to the first terminal of the capacitor 254 .

[0148] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long time. It is possible to retain it.

[0149] Next, data is written and held in the semiconductor device (memory cell 250) shown in FIG. The following explains how to do this.

[0150] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. The transistor 162 is turned on. As a result, the potential of the bit line BL is changed to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal (write). By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the capacitance element 254 is held (held).

[0151] Since the off-state current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitive element) can be held for a long period of time.

[0152] Next, the reading of information will be described. When the transistor 162 is turned on, the floating The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0153] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and the capacitance before charge redistribution is If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is Therefore, if the potential of the first terminal of the capacitance element 254 takes two states, V1 and V0 (V1>V0), Then, the potential of the bit line BL when the potential V1 is maintained is (=CB×VB0+C×V1) / (CB+C) is the potential of the bit line BL when the potential V0 is maintained (=CB×VB0 +C×V0) / (CB+C)).

[0154] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0155] As described above, in the semiconductor device illustrated in FIG. 5A, the off-state current of the transistor 162 is extremely small. Therefore, the charge stored in the capacitance element 254 can be maintained for a long time. In other words, refresh operations are not required, or the frequency of refresh operations can be reduced. Since it is possible to make the power consumption extremely low, it is possible to reduce the power consumption sufficiently. Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0156] Next, the semiconductor device shown in FIG. 5B will be described.

[0157] The semiconductor device shown in FIG. 5B has the memory cell 2 shown in FIG. 5A as a memory circuit on the upper part. 50, and a memory cell array 251a and a memory cell array 251b, In addition, the memory cell array 251a and the memory cell array 251b are required to operate. The peripheral circuit 253 includes a memory cell array 251a and a memory It is electrically connected to the recell array 251b.

[0158] By using the configuration shown in FIG. 5B, the peripheral circuit 253 is connected to the memory cell array 251a In addition, since it can be provided directly under the memory cell array 251b, the semiconductor device can be made smaller. It is possible.

[0159] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can also be used. Alternatively, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. be.

[0160] In the semiconductor device shown in FIG. 5B, the memory cell array 251a and the memory cell array The example shows a configuration in which two memory cell arrays 251b are stacked. The number of memory cell arrays is not limited to this. is also good.

[0161] Next, the specific configuration of the memory cell 250 shown in FIG. 5(A) will be described with reference to FIG. 6. conduct.

[0162] 6 shows an example of the configuration of the memory cell 250. FIG. 6(A) shows a plan view of the memory cell 250. 6(A) and FIG. 6(B) is a cross-sectional view taken along line AB in FIG. 6(A).

[0163] The transistor 162 shown in FIGS. 6A and 6B has the same structure as that described in Embodiment 1. It can be configured as one.

[0164] As shown in FIG. 6B, the transistor 162 is provided over the electrode 502 and the electrode 504. The electrode 502 is a wiring that functions as the bit line BL in FIG. The electrode 504 is provided in contact with the low resistance region of the transistor 162. ) serves as one electrode of the capacitor 254, and the low resistance region of the transistor 162 In the transistor 162, a region overlapping with the electrode 504 is provided The electrode 506 functions as the other electrode of the capacitor 254 .

[0165] As shown in FIG. 6A, the other electrode 506 of the capacitor 254 is connected to a capacitor line 508. The gate insulating layer 146 is electrically connected to the oxide semiconductor layer 144. The port electrode 148 is electrically connected to a word line 509 .

[0166] FIG. 6C shows a cross-sectional view of a connection portion between the memory cell array and the peripheral circuit. The peripheral circuit includes, for example, an n-channel transistor 510 and a p-channel transistor 51 2. The n-channel transistor 510 and the p-channel transistor 511 may be included. The semiconductor material used for the transistor 512 is a semiconductor material other than an oxide semiconductor (silicon By using such materials, the transistors included in the peripheral circuits can be This allows the transistor to operate at high speed.

[0167] By adopting the planar layout shown in FIG. 6(A), the area occupied by the semiconductor device can be reduced. Therefore, high integration can be achieved.

[0168] As described above, the memory cells formed in multiple layers on the upper side are transistors using oxide semiconductors. The transistor is made of a highly purified and intrinsic oxide semiconductor. Since the off-state current of a transistor is small, it is possible to retain the stored contents for a long period of time by using it. In other words, the frequency of refresh operations can be reduced significantly. Therefore, the power consumption can be reduced sufficiently. As shown in FIG. 1B, the electrode 504, the oxide semiconductor layer 144, the gate insulating layer 146, and the electrode 506 are stacked to form the film.

[0169] In this way, transistors using materials other than oxide semiconductors (in other words, transistors with sufficiently high speed operation) The peripheral circuits are made up of transistors that can be operated with an oxide semiconductor. In a broader sense, it is a transistor with a sufficiently small off-state current. This makes it possible to realize a semiconductor device with unprecedented features. By forming the gate and memory circuits in a stacked structure, the integration of the semiconductor device can be increased.

[0170] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0171] (Fourth embodiment) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, an An example of application to a portable device such as a child book will be described with reference to FIGS.

[0172] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following: The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: do.

[0173] In a normal SRAM, one memory cell is made up of transistors 801 to 808 as shown in FIG. It consists of six transistors, X decoder 807 and Y decoder 808. It is driven by transistor 808. 4 and transistor 806 form an inverter, enabling high speed operation. The memory cell is composed of six transistors, which has the disadvantage of requiring a large cell area. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. stomach.

[0174] On the other hand, in a DRAM, the memory cell is made up of a transistor 811, a storage It is composed of a storage capacitor 812, which is driven by an X decoder 813 and a Y decoder 814. Each cell is composed of one transistor and one capacitor, and has a small area. The memory cell area of ​​RAM is usually 10F 2 However, DRAM is always refreshed. It requires a memory card and consumes power even when not being rewritten.

[0175] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Before and after , and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0176] A block diagram of the portable device is shown in Figure 8. The portable device shown in Figure 8 includes an RF circuit 901, an analog base station, and a a digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply circuit 905, application processor 906, flash memory 910, display controller controller 911, memory circuit 912, display 913, touch sensor 919, voice The display 913 is a display unit 9 14, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 9 09. Generally, the memory circuit 912 is configured with an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment in this portion, it is possible to write information. High speed read / write, long-term memory retention, and low power consumption. It is possible.

[0177] FIG. 9 shows a display memory circuit 950 using the semiconductor device described in the previous embodiment. The memory circuit 950 shown in FIG. 954, a switch 955 and a memory controller 951. The memory circuit is connected to a signal line from the image data (input image data), the memory 952, and the memory 9 The display controller 53 reads and controls the data (stored image data) stored in the The display controller 956 receives a signal from the display controller 956. Play 957 is connected.

[0178] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then 955 and a display controller 956 to a display 957. , will be displayed.

[0179] If there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. The display controller 956 reads the data from the memory 952 via the switch 955. It is revealed.

[0180] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This reading is then followed by the next new image data being stored in the memory. This continues until the data is stored in the library 952.

[0181] In this way, the memory 952 and the memory 953 alternately write and receive image data. By reading out the data, the display 957 displays the data. The memory 52 and the memory 953 are not limited to being separate memories, but may be divided into one memory. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, it is possible to write and read information at high speed and retain data for a long period of time. Moreover, power consumption can be reduced sufficiently.

[0182] Figure 10 shows a block diagram of an electronic book. , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard a card 1006, a memory circuit 1007, a touch panel 1008, a display 1009, It is configured by a display controller 1010.

[0183] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The memory circuit 1007 has the function of temporarily storing the contents of a book. For example, when a user is reading an e-book, they can mark (change the display color) a specific part. If you want to make changes to the text (such as highlighting, underlining, making text bold, or changing the font), It has the function of temporarily storing and retaining information specified by the user. If the data is to be stored for a long period of time, it may be copied to the flash memory 1004. By adopting the semiconductor device described in the above embodiment, it is possible to write information High speed read / write, long-term memory retention, and low power consumption. It is possible.

[0184] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. A portable device with reduced noise is realized.

[0185] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0186] 100 boards 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode layer 116 Channel formation region 120 Impurity region 124 Metal compound area 130 Insulating layer 135 Interlayer insulating film 136a Sidewall insulating layer 136b Sidewall insulating layer 137 Insulating Film 142a Electrode layer 142b Electrode layer 143a Conductive layer 143b Conductive layer 144 Oxide semiconductor layer 144a Low resistance area 144b Low resistance region 144c Channel formation region 146 Gate insulating layer 148 gate electrodes 149 insulating film 150 insulating film 152 insulating film 153 Conductive Layer 154 Insulating Layer 156a Wiring 156b Wiring 160 transistors 162 transistors 164 Capacitor 250 memory cells 251a Memory Cell Array 251b memory cell array 253 Peripheral Circuits 254 Capacitor 400 boards 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor film 404a Low resistance area 404b Low resistance region 405 Electrode layer 405a Electrode layer 405b Electrode layer 407 Insulating Film 409 Channel formation region 410 insulating film 412a Sidewall insulating layer 412b Sidewall insulating layer 413 Insulating Film 415 Interlayer insulating film 420 transistors 421 Dopant 422a Electrode layer 422b Electrode layer 423 Insulating Film 424a Electrode layer 424b Electrode layer 425a Electrode layer 425b Electrode layer 426 Insulating Film 436 Undercoat insulation layer 445 Conductive Film 446 Insulating Film 502 Electrode 504 Electrode 506 Electrode 508 Capacitance Line 509 Word Line 510 n-channel transistor 512 p-channel transistor 801 transistors 803 Transistor 804 transistor 805 transistor 806 Transistor 807 X Decoder 808 Y decoder 811 Transistor 812 holding capacity 813 X Decoder 814 Y decoder 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 memory 953 memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

1. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a semiconductor device in which one of a source electrode and a drain electrode of the first transistor is electrically connected to one electrode of the capacitor element, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source electrode and a drain electrode of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitor element; the third conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film functions as one electrode of the capacitor element, a region of the first conductive film that does not overlap with the oxide semiconductor film and the third conductive film has a region that overlaps with the fifth conductive film with the insulating film interposed therebetween; Semiconductor device.

2. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to one electrode of the capacitor element; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source electrode and a drain electrode of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitor element; the third conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film functions as one electrode of the capacitor element, a region of the first conductive film that does not overlap with the oxide semiconductor film and the third conductive film has a region that overlaps with the fifth conductive film with the insulating film interposed therebetween; Semiconductor device.

3. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a semiconductor device in which one of a source electrode and a drain electrode of the first transistor is electrically connected to one electrode of the capacitor element, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source electrode and a drain electrode of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitor element; the third conductive film has a region in contact with the oxide semiconductor film, the fourth conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film functions as one electrode of the capacitor element, a region of the first conductive film that does not overlap with the oxide semiconductor film and the third conductive film has a region that overlaps with the fifth conductive film with the insulating film interposed therebetween; Semiconductor device.

4. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to one electrode of the capacitor element; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film having a region overlapping with a channel formation region of the second transistor and electrically connected to one of a source electrode and a drain electrode of the first transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region disposed above the first conductive film with an insulating film interposed therebetween and functioning as the other electrode of the capacitor element; the third conductive film has a region in contact with the oxide semiconductor film, the fourth conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region in contact with the first conductive film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the third conductive film is spaced apart from the second conductive film in a plan view; the fourth conductive film is spaced apart from the second conductive film in a plan view; the first conductive film functions as one electrode of the capacitor element, a region of the first conductive film that does not overlap with the oxide semiconductor film and the third conductive film has a region that overlaps with the fifth conductive film with the insulating film interposed therebetween; Semiconductor device.

Images