Display device

Abstract

To provide a display device capable of improving the display quality.SOLUTION: A display device in an embodiment includes a substrate, a pixel circuit disposed above the substrate, an insulating layer covering the pixel circuit and including a contact hole, a lower electrode disposed above the insulating layer and connected to the pixel circuit through the contact hole; an upper electrode facing the lower electrode; an organic layer positioned between the lower electrode and the upper electrode and including a light-emitting layer; a rib formed of an inorganic insulating material, disposed on the lower electrode, and having an opening overlapping with the lower electrode; and a partition wall disposed above the rib. The organic layer is in contact with the lower electrode through the opening. In a plan view, the partition wall overlaps with the entire contact hole.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] Generally, pixel circuits are covered with an insulating layer made of organic material, and the lower electrode is connected to the pixel circuit through a contact hole in this insulating layer. If elements placed on the insulating layer are deformed by the contact hole, display defects may occur. Therefore, to improve display quality, it is necessary to design the layout of various elements taking the contact holes into consideration. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of improving display quality. [Means for solving the problem]

[0006] A display device according to one embodiment includes a substrate, a pixel circuit disposed above the substrate, an insulating layer covering the pixel circuit and having a contact hole, a lower electrode disposed above the insulating layer and connected to the pixel circuit through the contact hole, an upper electrode facing the lower electrode, an organic layer positioned between the lower electrode and the upper electrode and including a light-emitting layer, a rib formed of an inorganic insulating material and disposed on the lower electrode, the rib having an opening overlapping the lower electrode, and a partition wall disposed above the rib. The organic layer is in contact with the lower electrode through the opening. The partition wall overlaps the entire contact hole in a plan view. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels according to an embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view showing an enlarged portion of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a part of a manufacturing process of a display device according to an embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of a display device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction, the direction along the Y axis is referred to as the second direction, and the direction along the Z axis is referred to as the third direction. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a red subpixel SP1 (first subpixel), a green subpixel SP2 (second subpixel), and a blue subpixel SP3 (third subpixel). The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display elements 20 are organic light-emitting diodes (OLEDs) that function as light-emitting elements. For example, the subpixel SP1 includes a display element 20 that emits light in the red wavelength region, the subpixel SP2 includes a display element 20 that emits light in the green wavelength region, and the subpixel SP3 includes a display element 20 that emits light in the blue wavelength region.

[0018] Fig. 2 is a diagram showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP1 and SP2 are aligned in the second direction Y. Furthermore, subpixels SP1 and SP2 are aligned in the first direction X with subpixel SP3.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0021] In the display area DA, ribs 5 and partition walls 6 are arranged. The ribs 5 have openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, opening AP2 is larger than opening AP1, and opening AP3 is larger than opening AP2.

[0022] The partitions 6 overlap the ribs 5 in a plan view. The partitions 6 have a plurality of first partitions 6x extending in the first direction X and a plurality of second partitions 6y extending in the second direction Y. The plurality of first partitions 6x are respectively arranged between the openings AP1 and AP2 adjacent to each other in the second direction Y and between two openings AP3 adjacent to each other in the second direction Y. The second partitions 6y are respectively arranged between the openings AP1 and AP3 adjacent to each other in the first direction X and between the openings AP2 and AP3 adjacent to each other in the first direction X.

[0023] 2, the first partition 6x and the second partition 6y are connected to each other. As a result, the partition 6 as a whole has a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition 6 has openings in the subpixels SP1, SP2, and SP3, similar to the rib 5.

[0024] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each overlapping with aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with aperture AP3. In the example of FIG. 2, the outer shapes of the upper electrode UE1 and the organic layer OR1 are the same, the outer shapes of the upper electrode UE2 and the organic layer OR2 are the same, and the outer shapes of the upper electrode UE3 and the organic layer OR3 are the same.

[0025] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 20 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 20 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 20 of the subpixel SP3.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0027] The contact holes CH1 and CH2 entirely overlap with the first partition wall 6x between the openings AP1 and AP2 adjacent to each other in the second direction Y. The contact hole CH3 entirely overlaps with the first partition wall 6x between the two openings AP3 adjacent to each other in the second direction Y.

[0028] 2, the lower electrode LE1 has a protrusion PR1 protruding toward the lower electrode LE2, and the lower electrode LE2 has a protrusion PR2 protruding toward the upper electrode LE1. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0029] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11. Although not shown in the cross-section of FIG. 3, the contact holes CH1, CH2, and CH3 described above are provided in the insulating layer 12.

[0030] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. The rib 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0031] The partition wall 6 includes a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61 in FIG. 3. Such a shape of the partition wall 6 can also be said to be an overhanging shape.

[0032] The organic layer OR1 shown in FIG. 2 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 shown in FIG. 2 also includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. As shown in FIG. 3, the first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a portion of the rib 5. The second organic layer OR1b is located on the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0033] The organic layer OR2 shown in FIG. 2 includes a first organic layer OR2a and a second organic layer OR2b that are spaced apart from each other. The upper electrode UE2 shown in FIG. 2 also includes a first upper electrode UE2a and a second upper electrode UE2b that are spaced apart from each other. As shown in FIG. 3, the first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located on the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts a side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0034] The organic layer OR3 shown in FIG. 2 includes a first organic layer OR3a and a second organic layer OR3b that are spaced apart from each other. The upper electrode UE3 shown in FIG. 2 also includes a first upper electrode UE3a and a second upper electrode UE3b that are spaced apart from each other. As shown in FIG. 3, the first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts the side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0035] Sealing layers 71, 72, and 73 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer 71 continuously covers the first upper electrode UE1a, the side surfaces of the lower portion 61, and the second upper electrode UE1b. The sealing layer 72 continuously covers the first upper electrode UE2a, the side surfaces of the lower portion 61, and the second upper electrode UE2b. The sealing layer 73 continuously covers the first upper electrode UE3a, the side surfaces of the lower portion 61, and the second upper electrode UE3b.

[0036] 3, the second organic layer OR1b, the second upper electrode UE1b, and the sealing layer 71 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, and the sealing layer 73 on the partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, and the sealing layer 72 on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, and the sealing layer 73 on the partition wall 6.

[0037] The sealing layers 71, 72, and 73 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. Furthermore, the sealing layer 14 is covered with a resin layer 15.

[0038] The insulating layer 12 and the resin layers 13 and 15 are made of an organic material. The rib 5 and the sealing layers 14, 71, 72, and 73 are made of an inorganic material such as silicon nitride (SiNx). The thickness of the rib 5 made of an inorganic material is sufficiently smaller than the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of the rib 5 is 200 nm or more and 400 nm or less.

[0039] The lower portion 61 of the partition wall 6 is electrically conductive. The upper portion 62 of the partition wall 6 may also be electrically conductive.

[0040] The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or may have a laminated structure of a metal material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, and UE3 may be formed of a transparent conductive material such as ITO.

[0041] When the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, UE3, the lower electrodes LE1, LE2, LE3 correspond to anodes and the upper electrodes UE1, UE2, UE3 correspond to cathodes. Also, when the potential of the upper electrodes UE1, UE2, UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, LE3, the upper electrodes UE1, UE2, UE3 correspond to anodes and the lower electrodes LE1, LE2, LE3 correspond to cathodes.

[0042] Each of the organic layers OR1, OR2, and OR3 includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order.

[0043] The subpixels SP1, SP2, and SP3 may further include capping layers for adjusting the optical properties of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3. Such capping layers may be provided between the upper electrode UE1 and the sealing layer 71, between the upper electrode UE2 and the sealing layer 72, and between the upper electrode UE3 and the sealing layer 73, respectively.

[0044] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the first upper electrodes UE1a, UE2a, and UE3a in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 included in the subpixels SP1, SP2, and SP3, respectively.

[0045] When a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0046] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0047] Fig. 4 is a schematic plan view showing an enlarged view of the vicinity of the subpixel SP1 in Fig. 2. Of the region surrounded by a chain line showing the outline of the upper electrode UE1 and the organic layer OR1, the portions overlapping with the partition wall 6 correspond to the second upper electrode UE1b and the second organic layer OR1b described above. Furthermore, of the region surrounded by the chain line, the portions located inside the second upper electrode UE1b and the second organic layer OR1b correspond to the first upper electrode UE1a and the first organic layer OR1a described above.

[0048] The second upper electrode UE1b and the second organic layer OR1b surround the first upper electrode UE1a, the first organic layer OR1a, and the opening AP1. Similarly, the second upper electrode UE2b and the second organic layer OR2b shown in FIG. 3 surround the first upper electrode UE2a, the first organic layer OR2a, and the opening AP2. Furthermore, the second upper electrode UE3b and the second organic layer OR3b shown in FIG. 3 surround the first upper electrode UE3a, the first organic layer OR3a, and the opening AP3.

[0049] In this embodiment, the entire contact hole CH1 overlaps with the first partition wall 6x. The contact hole CH1 is located between the organic layers OR1 and OR2 (or between the upper electrodes UE1 and UE2) in the second direction Y.

[0050] The first partition 6x overlapping the contact hole CH1 has a width Wx1 in the second direction Y. The first partition 6x not overlapping the contact hole CH1 (the upper first partition 6x in the drawing) has a width Wx2. Each second partition 6y has a width Wy in the first direction X. In the example of FIG. 4, the width Wx1 is larger than the width Wx2 and the width Wy (Wx1>Wx2, Wy). For example, the width Wy is the same as the width Wx2.

[0051] The lower electrode LE1 has a first side S11 and a second side S12 parallel to the first direction X, and a third side S13 and a fourth side S14 parallel to the second direction Y. The first side S11 is located between the contact hole CH1 and the opening AP1 and overlaps with the first partition wall 6x at the bottom in the figure. The protrusion PR1 protrudes from the first side S11 toward the lower electrode LE2 and overlaps with the contact hole CH1. In the example of FIG. 4, the second side S12 does not overlap with the partition wall 6. Furthermore, most of the third side S13 and the fourth side S14 do not overlap with the partition wall 6 either.

[0052] The first partition wall 6x overlapping the contact hole CH1 also overlaps the entire contact hole CH2. The contact hole CH2 is located between the organic layers OR1 and OR2 (or between the upper electrodes UE1 and UE2) in the second direction Y. The contact holes CH1 and CH2 are aligned in the first direction X. The lower electrode LE2 has a first side S21 overlapping the first partition wall 6x. Most of the other sides of the lower electrode LE2 do not overlap the partition wall 6, similar to the sides S12, S13, and S14 of the lower electrode LE1. The protrusion PR2 protrudes from the first side S21 toward the lower electrode LE1 and overlaps the contact hole CH2. Although not shown in FIG. 4, the lower electrode LE3 also has one side adjacent to the contact hole CH3 overlapping the first partition wall 6x, and most of the other sides do not overlap the partition wall 6.

[0053] Fig. 5 is a schematic cross-sectional view of the display device DSP taken along line VV in Fig. 4. In this figure, the substrate 10, resin layers 13 and 15, and sealing layer 14 shown in Fig. 3 are omitted.

[0054] The contact hole CH1 penetrates the insulating layer 12. The protrusion PR1 of the lower electrode LE1 is in contact with the conductive layer CL included in the circuit layer 11 through the contact hole CH1. The conductive layer CL corresponds to, for example, the source electrode or drain electrode of the driving transistor 3 shown in FIG.

[0055] The lower portion 61 of the first partition 6x (partition 6) has side surfaces 61a and 61b. The first upper electrode UE1a is in contact with a portion of the side surface 61a. The other portion of the side surface 61a is covered with a sealing layer 71. Similarly, the first upper electrode UE2a is in contact with a portion of the side surface 61b. The other portion of the side surface 61b is covered with a sealing layer 72.

[0056] The upper portion 62 of the first partition wall 6x has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b. In the example of Fig. 5, a sealing layer 71 covers the lower surface of the end portion 62a, and a sealing layer 72 covers the lower surface of the end portion 62b.

[0057] The second organic layers OR1b, OR2b located on the first partition 6x are spaced apart in the second direction Y. Similarly, the second upper electrodes UE1b, UE2b located on the first partition 6x are spaced apart in the second direction Y. Furthermore, the end 71a of the sealing layer 71 and the end 72a of the sealing layer 72 are each located on the first partition 6x and are spaced apart in the second direction Y.

[0058] In this embodiment, the rib 5 is sufficiently thinner than the insulating layer 12, so that the rib 5 is recessed above the contact hole CH1, forming a recess RS1. Furthermore, the first partition wall 6x disposed on the rib 5 is also recessed above the contact hole CH1, forming a recess RS2.

[0059] The side surface 61a is located outside the recessed portion RS1. That is, the lower portion 61 covers the entire inner surface of the recessed portion RS1 and also covers the flat upper surface of the rib 5 around the recessed portion RS1.

[0060] The side surface 61a is located between the contact hole CH1 and the opening AP1 in the second direction Y. The side surface 61b is located between the contact hole CH2 and the opening AP2 (see FIG. 4) in the second direction Y.

[0061] Here, define the distance between the side surface 61a and the contact hole CH1 (the opening on the lower surface of the insulating layer 12) as D1, the distance between the side surface 61b and the contact hole CH1 (the above-mentioned opening) as D2, and the width of the contact hole CH1 (the above-mentioned opening) in the second direction Y as Wc.

[0062] The distance D1 is, for example, 2.0 μm or more, preferably 4.5 μm or more. The width Wc is, for example, 3 μm or more and 5 μm or less. In the example of FIG. 5, the width Wc is larger than the distance D1, and the distance D2 is larger than the width Wc (D1 < Wc < D2). However, it is not limited to this. For example, the distance D1 may be larger than the width Wc.

[0063] The cross-sectional structure in the vicinity of the contact holes CH2 and CH3 is the same as the cross-sectional structure in the vicinity of the contact hole CH1 shown in FIG. 5. That is, the distance between the contact holes CH2 and CH3 and the side surfaces 61a and 61b of the first partition wall 6x overlapping them is, for example, 2.0 μm or more, preferably 4.5 μm or more.

[0064] Here, an example of the effect achieved by this embodiment will be described using FIGS. 6 and 7. FIG. 6 is a schematic cross-sectional view showing a part of the manufacturing process of the display device DSP. When forming the organic layer OR1, first, the base material thereof is vapor-deposited on the entire display area DA. At this time, the material is divided into the first organic layer OR1a and the second organic layer OR1b by the partition wall 6. Subsequently, the material serving as the base of the upper electrode UE1 is vapor-deposited on the entire display area DA. At this time, the material is divided into the first upper electrode UE1a and the second upper electrode UE1b by the partition wall 6. <0​​Furthermore, a sealing layer 71 is formed on the first upper electrode UE1a and the second upper electrode UE1b, and a resist R is formed on the sealing layer 71 in areas where the first organic layer OR1a, the second organic layer OR1b, the first upper electrode UE1a, and the second upper electrode UE1b should ultimately remain. Subsequent etching removes portions of the first organic layer OR1a, the second organic layer OR1b, the first upper electrode UE1a, the second upper electrode UE1b, and the sealing layer 71 that are not covered with the resist R.

[0066] 7 is a schematic cross-sectional view of a display device according to a comparative example, illustrating the same manufacturing process as in FIG. 6. In this comparative example, the first partition 6x does not entirely overlap the contact hole CH1. As a result, the side surface 61a of the lower portion 61 is located inside the recess RS1 of the rib 5.

[0067] In the structure of the comparative example, the end 62a of the upper portion 62 faces upward compared to the structure of FIG. 6, so the organic layer OR1 and the upper electrode UE1 may not be separated by the first partition 6x. In this case, when resist R is formed and etching is performed, the end of the organic layer OR1 constituting the display element is exposed from the upper electrode UE1 and the sealing layer 71. In general, the organic layer OR1 has low resistance to moisture. Therefore, if moisture penetrates into the organic layer OR1 through the exposed end, display defects may occur.

[0068] In contrast, in this embodiment, the entire contact hole CH1 overlaps with the first partition wall 6x. Therefore, it is possible to divide the organic layer OR1 into the first organic layer OR1a and the second organic layer OR1b even in the vicinity of the contact hole CH1. In this case, the end of the first organic layer OR1a is well covered by the first upper electrode UE1a and the sealing layer 71, suppressing moisture penetration into the first organic layer OR1a. As a result, display defects are suppressed, and the display quality of the display device DSP is improved.

[0069] As described above, if the distance D1 between the side surface 61a and the contact hole CH1 is 2.0 μm or more, the shape of the first partition 6x in the vicinity of the side surface 61a is sufficiently stable. If the distance D1 is 4.5 μm or more, the shape becomes even better.

[0070] Although attention is focused on the organic layer OR1 in FIGS. 5 and 6, the same effect can be obtained for the organic layers OR2 and OR3.

[0071] 2 and 4, when the width Wx1 of the first partition 6x overlapping with the contact holes CH1, CH2, CH3 is larger than the width Wx2 of the other first partitions 6x and the width Wy of the second partition 6y, it becomes easier to ensure a sufficient distance between the contact holes CH1, CH2, CH3 and the side surface of the lower portion 61. From another perspective, since the widths of the first partition 6x and the second partition 6y that do not overlap with the contact holes CH1, CH2, CH3 are reduced, it becomes possible to increase the areas of the openings AP1, AP2, AP3.

[0072] 2 and 4, the contact holes CH1 and CH2 can be arranged in the first direction X. This makes it possible to reduce the width Wx1 of the first partition wall 6x while ensuring a sufficient distance between the contact holes CH1 and CH2 and the side surface of the lower portion 61.

[0073] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0074] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0075] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0076] DSP...display device, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, UE1, UE2, UE3...upper electrode, OR1, OR2, OR3...organic layer, CH1, CH2, CH3...contact hole, 1...pixel circuit, 5...rib, 6...partition wall, 10...substrate, 61...lower part, 62...upper part, 71, 72, 73...sealing layer.

Claims

1. A substrate; a pixel circuit disposed above the substrate; an insulating layer covering the pixel circuit and having a contact hole; a lower electrode disposed above the insulating layer and connected to the pixel circuit through the contact hole; an upper electrode facing the lower electrode; an organic layer located between the lower electrode and the upper electrode and including a light-emitting layer; a rib formed of an inorganic insulating material, disposed on the lower electrode, and having an opening overlapping the lower electrode; a partition wall disposed on the rib, the organic layer is in contact with the lower electrode through the opening; the partition wall overlaps the entire contact hole in plan view; Display device.

2. The partition wall includes a lower portion disposed on the rib and an upper portion disposed on the lower portion and having an end portion protruding from a side surface of the lower portion. The display device according to claim 1 .

3. the side surface of the lower portion is located between the contact hole and the opening. The display device according to claim 2 .

4. the distance between the side surface and the contact hole in a plan view is 2.0 μm or more; The display device according to claim 3 .

5. The upper electrode is in contact with the side surface.

5. The display device according to claim 2.

6. The lower portion is electrically conductive. The display device according to claim 5 .

7. a sealing layer formed of an inorganic material and covering the upper electrode, the side surface, and the top portion; 7. The display device according to claim 5 or 6.

8. the lower electrode has a first side located between the contact hole and the opening in a plan view, and a protrusion protruding from the first side and overlapping with the contact hole in a plan view; The display device according to any one of claims 1 to 7.

9. The partition wall surrounds the opening in a plan view.

9. The display device according to claim 1.

10. The thickness of the rib is smaller than the thickness of the partition wall. The display device according to any one of claims 1 to 9.

11. the rib and the partition wall each have a recess located above the contact hole; The display device according to any one of claims 1 to 10.

12. a first subpixel, a second subpixel, and a third subpixel, each of which includes the pixel circuit, the contact hole, the lower electrode, the upper electrode, the organic layer, and the opening; the first subpixel and the third subpixel are aligned in a first direction, the first subpixel and the second subpixel are aligned in a second direction intersecting the first direction, the partition includes a first partition disposed between the opening of the first subpixel and the opening of the second subpixel, and a second partition disposed between the opening of the first subpixel and the opening of the third subpixel. The display device according to claim 1 .

13. a width of the first partition wall in the second direction is larger than a width of the second partition wall in the first direction; The display device according to claim 12.

14. the contact hole of the first subpixel overlaps with the first partition wall in a plan view; The display device according to claim 12 or 13.

15. the contact hole of the second subpixel overlaps with the first partition wall in a plan view and is aligned with the contact hole of the first subpixel in the first direction; The display device according to claim 14.

16. the contact hole of the first subpixel is located between the organic layer of the first subpixel and the organic layer of the second subpixel in the second direction.

16. The display device according to any one of claims 12 to 15.

17. each of the first subpixel and the second subpixel includes a sealing layer covering the upper electrode; the sealing layer of the first subpixel and the sealing layer of the second subpixel are spaced apart in the second direction; 17. A display device according to any one of claims 12 to 16.

18. the partition wall includes a lower portion disposed on the rib and an upper portion disposed on the lower portion and having an end portion protruding from a side surface of the lower portion; the lower portion and the upper portion comprise different materials; The display device according to claim 1 .

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