Cascading of atomic operations

Abstract

Cascading the atomic operation includes each thread of a plurality of threads receiving a request to perform an atomic operation, the plurality of threads including a plurality of thread subsets, each thread corresponding to a local memory, the local memory of the thread subset being accessible by the thread subset and inaccessible to remaining threads of the plurality of threads; each thread subset generating a plurality of intermediate results by performing the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results into a shared memory accessible to all threads in the plurality of threads.

Description

[Background technology]

[0001] When multiple threads need to perform atomic operations on the same range (memory region), the atomic operations must be performed in a memory region accessible to each thread. A shared memory, such as a shared cache, can be used as the range of the atomic operations because each thread has access to the shared cache. However, performance degrades as the number of threads and atomic operations being performed increases due to the distance of the shared cache from the die or core that executes the threads. [Brief description of the drawings]

[0002] [Figure 1] FIG. 2 is a block diagram of an example processor for cascaded execution of atomic operations in accordance with some embodiments. [Diagram 2] FIG. 2 is a diagram of an example execution of cascaded execution of atomic operations in accordance with some embodiments. [Diagram 3] FIG. 2 is a block diagram of an exemplary computer for cascaded execution of atomic operations in accordance with some embodiments. [Figure 4] 1 is a flowchart of an example method for cascaded execution of atomic operations in accordance with some embodiments. [Diagram 5] 5 is a flow chart of a variation of the method of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] Various processes or software applications have multiple threads each perform an atomic operation. For example, the execution of the same atomic operation across multiple threads is used to generate histograms or performance metrics of the running threads or computing system. These atomic operations target the same range or region of memory. Therefore, the range of the atomic operation must be accessible to all threads that perform the atomic operation.

[0004] A shared memory, such as a shared cache, can be used as a scope for atomic operations because each thread has access to the shared cache, but performance degrades as the number of threads and atomic operations executed increases due to the distance of the shared cache from the die or core that executes the threads.

[0005] To that end, this specification describes various embodiments for cascaded execution of atomic operations. In some embodiments, a method for cascaded execution of atomic operations includes receiving, by each thread of a plurality of threads, a request to perform an atomic operation, where the plurality of threads includes a plurality of thread subsets, each thread corresponding to a local memory, the local memory for the thread subset being accessible by the thread subset and inaccessible to the remainder of the threads in the plurality of threads, generating, by each thread subset, a plurality of intermediate results by performing the atomic operation in the local memory corresponding to the thread subset, and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

[0006] In some embodiments, each thread subset executes on each core of the multiple cores, and the local memory for each thread subset includes a cache implemented on the respective core. In some embodiments, the shared memory includes a shared cache. In some embodiments, the shared cache includes a last level cache. In some embodiments, the method further includes evicting, for each intermediate result of the multiple intermediate results, a cache line and a tag indicating an opcode for the atomic operation. In some embodiments, aggregating the multiple intermediate results includes performing, in the shared memory, one or more other atomic operations based on the tag. In some embodiments, generating the multiple intermediate results includes initializing a cache line in the local memory corresponding to each thread subset.

[0007] This specification also describes various embodiments of a processor for cascaded execution of atomic operations, such processors performing steps including receiving a request for each thread of a plurality of threads to perform an atomic operation, the plurality of threads including a plurality of thread subsets each corresponding to a local memory, the local memory for the thread subset being accessible by the thread subset and inaccessible to the remainder of the threads in the plurality of threads, generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset, and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

[0008] In some embodiments, each thread subset executes on each core of the multiple cores, and the local memory for each thread subset includes a cache implemented on the respective core. In some embodiments, the shared memory includes a shared cache. In some embodiments, the shared cache includes a last level cache. In some embodiments, the process further includes evicting, for each intermediate result of the multiple intermediate results, a cache line and a tag indicating an opcode for the atomic operation. In some embodiments, aggregating the multiple intermediate results includes performing, in the shared memory, one or more other atomic operations based on the tag. In some embodiments, generating the multiple intermediate results includes initializing a cache line in the local memory corresponding to each thread subset.

[0009] Also described herein are various embodiments of an apparatus for cascaded execution of atomic operations, comprising a computer memory and a processor operatively coupled to the computer memory to perform steps including receiving a request for each thread of a plurality of threads to perform an atomic operation, the plurality of threads including a plurality of thread subsets each corresponding to a local memory, the local memory for the thread subset being accessible by the thread subset and inaccessible to the remainder of the threads in the plurality of threads, generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset, and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

[0010] In some embodiments, each thread subset executes on each core of the multiple cores, and the local memory for each thread subset comprises a cache implemented on the respective core. In some embodiments, the shared memory comprises a shared cache. In some embodiments, the shared cache comprises a last level cache. In some embodiments, the process further includes, for each intermediate result of the multiple intermediate results, evicting a cache line and a tag indicating an opcode for the atomic operation. In some embodiments, aggregating the multiple intermediate results includes performing one or more other atomic operations in the shared memory based on the tag.

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description includes embodiments in which the first and second features are formed in direct contact, and also includes embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "back," "front," "top," "bottom," and the like are used herein to facilitate descriptions that describe the relationship of one element or feature to another element(s) or feature(s), as shown in the figures. Similarly, terms such as "front" and "back" or "top" and "back" are used herein to more easily identify various components and to identify those components as being on opposite sides of another component, for example. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures.

[0012] FIG. 1 is a block diagram of a non-limiting exemplary processor 100. The exemplary processor 100 may be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, parallel accelerators (e.g., graphics processing units (GPUs), machine learning accelerators, cryptocurrency mining accelerators), and the like. The processor 100 includes multiple cores 102a-102n. Each core 102a-102n is an independently operated processing unit that loads and executes program instructions. Each core 102a-102n executes one or more threads 104a-104n. Each thread 104a-104n is an independently managed process and sequence of instructions. A thread or group of threads executing on a single core is referred to as a thread subset. Such a thread subset is restricted to access memory local to the core and to access memory local to other cores. 1, each thread subset 105a-105n includes one or more threads of the multiple threads 104a-104n and executes on a different processor core 102a-102n. The threads of the thread subset 105a-105n executing on a given core 102a-102n execute simultaneously (e.g., in parallel) with other threads executing on the core 102a-102n. For example, when the core 102a executes the thread subset 105a including multiple threads, the multiple threads execute in parallel on the core 102a.

[0013] Each core 102a-102n also includes a portion of local memory 106a-106n. The local memory 106a-106n for a given core 102a-102n includes memory that is accessible to the thread subset 105a-105n executing on that core 102a-102n, but is inaccessible to any other thread subset 105a-105n executing on another core 102a-102n. For example, the local memory 106a on the core 102a is accessible to the threads of the thread subset 105a executing on the core 102a, but is inaccessible to the thread subset 105n executing on the core 102n. Similarly, the local memory 106n on the core 102n is accessible to the threads of the thread subset 105n executing on the core 102n, but is inaccessible to the threads of the thread subset 105a executing on the core 102a. In some embodiments, the local memory 106a includes a cache, such as an L2 cache. Thus, each of the thread subsets 105a-105n executes on a respective core 102a-102n and corresponds to a respective local memory 106a-106n. The processor 100 also includes a shared memory 108. The shared memory 108 is a portion of memory accessible to all of the threads 104a-104n, and therefore all of the thread subsets 105a-105n. In some embodiments, the shared memory 108 includes a shared cache, such as a last level cache.

[0014] The processor 100 also includes a controller 110. The controller 110 processes commands to read data from and write data to memory, including the local memories 106a-106n and the shared memory 108. As such, the controller 110 provides or issues commands to the local memories 106a-106n and the memory 108 to perform certain operations, such as atomic operations, in the target memories. By way of example, the controller 110 may include a memory controller, a cache controller, or other controller as may be appreciated.

[0015] A request is received (e.g., by the controller 110) for each thread 104a-104n to perform an atomic operation. For example, an operating system or an executing software application may require each thread 104a-104n to perform an atomic operation in order to generate a histogram or other metric that describes the performance of the threads 104a-104n. An atomic operation is an operation that is performed independently of other processes and is not subject to interruption (e.g., an operation that can be performed atomically). Such atomic operations include, for example, add, subtract, increment, decrement, minimum function, maximum function, and other atomic operations as may be appreciated.

[0016] The atomic operations performed by each thread 104a-104n are directed to the same range or region of memory. For example, if the atomic operation is an increment operation (e.g., adding one to a previously stored value), then each atomic operation is directed to increment the same value stored in memory. In some embodiments, since each thread 104a-104n is directed to perform an atomic operation on the same range of memory, each atomic operation is directed to apply to a portion of the shared memory 108. For example, in some embodiments, each thread 104a-104n is directed to perform an atomic operation on a portion of memory (e.g., main memory or addressable memory) cached in the shared memory 108. In other embodiments, each thread 104a-104n is directed to perform an atomic operation on a portion (e.g., a cache line) of the shared memory 108 that does not necessarily reflect or correspond to a portion of the main memory or addressable memory.

[0017] In some embodiments, the request is embodied as a single command. In other embodiments, the request is embodied as multiple commands or requests. For example, a scheduler or other component of the operating system executes or issues, for each thread 104a-104n, a respective command or instruction to perform the atomic operation.

[0018] Instead of each thread 104a-104n directly executing the atomic operation in the shared memory 108, each thread 104a-104n executes the atomic operation in its respective local memory 106a-106n. For example, the threads of thread subset 105a execute the atomic operation on a portion of local memory 106a. In this example, if the atomic operation is an increment operation, then each thread of thread subset 105a increments the same value in local memory 106a. In some embodiments, prior to executing the atomic operation, a portion of each local memory 106a-106n is initialized (e.g., by controller 110). In embodiments in which local memory 106a-106n is a cache, the initialized portion of memory includes a cache line. In some embodiments, initializing the portion of memory includes storing a default value (e.g., zero or another default value) in the portion of memory. For example, in some embodiments, initializing the portion of memory includes storing zeros in the entire cache line in the cache line of local memory 106. In some embodiments, the default value depends on the type of atomic operation being performed. For example, for an increment or ADD operation, the default value is zero. As another example, if the atomic operation is a minimum operation (e.g., unsigned minimum (UMIN) or signed minimum (SMIN)), the default value is the maximum possible positive value that can be stored in a cache line. As a further example, if the atomic operation is a maximum operation (e.g., unsigned maximum (UMAX) or signed maximum (SMAX)), the default value is the minimum possible negative value that can be stored in a cache line. Thus, the first atomic operation is applied to an initialized zero value, and subsequent atomic operations are applied to the result of the previously applied atomic operation.

[0019] In some embodiments, after a given thread of thread subset 105a-105n performs an atomic operation in local memory 106a-106n, the portion of local memory 106a-106n (e.g., a cache line) on which the atomic operation was performed is tagged with an indication of the atomic operation (e.g., an opcode for the atomic operation). If other threads of other thread subsets 105a-105n perform the atomic operation on the same portion of memory (e.g., the same cache line), the tag is preserved or remains unchanged.

[0020] After each thread 104a-104n of the thread subset 105a-105n performs an atomic operation in the local memory 106a-106n, each local memory 106a-106n stores intermediate results based on the execution of the atomic operation. These intermediate results are then aggregated in the shared memory 108 to generate a result for the request (e.g., a result reflecting the execution of the atomic operation by all threads 104a-104n). In some embodiments, the intermediate results are copied from the local memories 106a-106n to the shared memory 108. For example, in some embodiments, after each thread 104a-104n performs an atomic operation in the local memory 106a-106n, cache lines from the local memories 106a-106n that store the intermediate results are evicted from the local memories 106a-106n to the shared memory 108. In some embodiments, cache lines from local memories 106a-106n are evicted to shared memory 108 with a tag indicating the atomic operation performed in local memory 106a-106n. For example, in some embodiments, the tag indicates the opcode for the atomic operation. Thus, after evicting a cache line from local memory 106a-106n to shared memory 108, shared memory 108 stores each intermediate result from local memory 106a-106n. In some embodiments, if the evicted cache line contains any data or bytes that were not accessed or modified by thread 104a-104n prior to the eviction, a byte mask is included in the evicted cache line to prevent modification of those bytes in shared memory 108.

[0021] In some embodiments, aggregating the intermediate results in the shared memory 108 includes performing one or more atomic operations in the shared memory 108 to generate a result. In some embodiments, the one or more atomic operations performed in the shared memory 108 correspond to an opcode of the atomic operation indicated in the tag provided with the evicted cache line. As an example, if the atomic operation is an add operation, the intermediate results in the shared memory 108 are added together using an atomic add operation to generate a result. In some embodiments, the one or more atomic operations performed in the shared memory 108 are based on, but do not match, the opcode of the atomic operation indicated in the tag provided with the evicted cache line. As an example, if an increment atomic operation was performed in the local memories 106a-106n, an add atomic operation is performed in the shared memory 108 to sum the intermediate results.

[0022] In some embodiments, if performing an atomic operation causes a cache line in the local memory 106a-106n to be tagged with the opcode of the atomic operation, the tag is used to determine whether the particular cache line should be evicted to the shared memory 108. As an example, assume that a first thread 104a-104n performs an atomic operation (e.g., an ADD operation) in the local memory 106a-106n and tags the cache line with the ADD tag. Assume that a second thread 104a-104n performs another ADD operation directed to the same cache line in the local memory 106a-106n. In some embodiments, the opcode of the atomic operation performed by the second thread 104a-104n is compared to the tag of the cache line. If the tag matches the opcode of the atomic operation, the second thread 104a-104n performs the ADD operation in the local memory 106a-106n. If the opcode differs from the tag, the cache line along with the tag is evicted to the shared memory 108 and the atomic operation is performed as if it were a cache miss (as the previously stored cache line is evicted). For example, if the atomic operation is a READ operation, the line from the shared memory 108 is read into the local memories 106a-106n. As another example, if the atomic operation is an unsigned minimum (UMIN) operation, the line in the local memories 106a-106n is initialized with an appropriate value (e.g., the largest positive value).

[0023] Those skilled in the art will appreciate that the techniques described herein provide advantages over performing atomic operations directly in the shared memory 108. For example, performing atomic operations in the shared memory 106a-106n allows for concurrent execution of atomic operations across the cores 102a-102n, as opposed to sequentially executing each atomic operation in the shared memory 108. Additionally, because the local memories 106a-106n are located on the respective cores 102a-102n, the atomic operations are performed more quickly in the local memories 106a-106n as compared to performing them in the shared memory 108.

[0024] Although the techniques disclosed herein are described with respect to threads 104a-104n executing on respective cores 102a-102n, those skilled in the art will appreciate that these techniques are also applicable to threads 104a-104n executing on separate dies, where each die includes a respective local memory 106a-106n.

[0025] FIG. 2 illustrates an example execution of cascaded execution of atomic operations according to some embodiments of the present disclosure. The example of FIG. 2 includes cores 202a and 202b. Cores 202a and 202b are similar to cores 102a-102n described in FIG. 1. Core 202a is executing thread subset 205a including threads 204a, 204b, and 204c, and core 202b is executing thread subset 205b threads 204d, 204c, and 204e. Core 202a includes a local cache 206a (e.g., local memory 106a-106n), and core 202b includes a local cache 206b (e.g., another local memory 106a-106n). Threads in thread subset 205a can access local cache 206a but cannot access local cache 206b. Similarly, threads in thread subset 205b can access local cache 206b, but cannot access local cache 206a. A request is received (e.g., by controller 110, not shown) to perform an atomic operation to add "1" by all threads 204a-204f. In some embodiments, a cache line in each of local caches 206a, 206b is initialized by setting all values ​​in the cache line to zero.

[0026] After the cache lines in each of local caches 206a, 206b are initialized, threads 204a-204f perform atomic add operations on the initialized cache lines. In other words, threads 204a-204c of thread subset 205a perform atomic add operations on the initialized cache lines of local cache 206a, and threads 204d-204f of thread subset 205b perform atomic add operations on the initialized cache lines of local cache 206b. Thus, each of local caches 206a, 206b stores an intermediate result "3" that reflects three executions of the atomic add operation.

[0027] Each of the local caches 206a, 206b evicts a respective cache line storing the intermediate result to the shared cache 208 (e.g., the shared memory 108). In some embodiments, the cache line is evicted with a tag indicating the opcode for the atomic add operation. After the cache line is evicted, the atomic add operation is performed in the shared cache 208 to add the intermediate results received from the evicted cache line, thereby producing a final result of "6", which is equivalent to each of the six threads 204a-204f performing an atomic add operation in the shared cache 208.

[0028] In some embodiments, the processor 100 of FIG. 1 is implemented in a computer 300. For example, the processor 100 is implemented as at least one processor 302. In addition to the at least one processor 302, the computer 300 of FIG. 3 includes random access memory (RAM) 304 that is connected to the processor 302 and other components of the computer 300 via a high speed memory bus 306 and a bus adapter 308. An operating system 310 is stored in the RAM 304. Although the operating system 310 in the example of FIG. 3 is shown in RAM 304, many components of such software are typically also stored in non-volatile memory, such as data storage 312, e.g., a disk drive or the like.

[0029] 3 includes a disk drive adapter 316 coupled to processor 302 and other components of computer 300 via expansion bus 318 and bus adapter 308. Disk drive adapter 316 connects non-volatile data storage to computer 300 in the form of data storage 312. Such disk drive adapters include Integrated Drive Electronics (IDE) adapters, Small Computer System Interface (SCSI) adapters, and others as would occur to one of ordinary skill in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disk drive, an electrically erasable programmable read-only memory (also known as "EEPROM" or "flash" memory), a RAM drive, or the like, as would occur to one of ordinary skill in the art.

[0030] The example computer 300 of Figure 3 includes one or more input / output ("I / O") adapters 320. I / O adapters provide user-oriented input / output through software drivers and computer hardware for controlling output to a display device, such as a computer display screen, and user input from user input devices 322, such as a keyboard and mouse. The example computer 300 of Figure 3 includes a video adapter 324, which is an example of an I / O adapter specifically designed for graphics output to a display device 326, such as a display screen or computer monitor. Video adapter 324 is connected to processor 302 via a high-speed video bus 328, bus adapter 308, and frontside bus 330, which is also a high-speed bus.

[0031] The example computer 300 of Figure 3 includes a communications adapter 332 for data communications with other computers and with a data communications network. Such data communications may occur serially through an RS-232 connection, through an external bus such as a Universal Serial Bus ("USB"), through a data communications network such as an IP data communications network, and / or in any other manner as would occur to one skilled in the art. The communications adapter 332 implements the hardware level of data communications by which one computer sends data communications directly to another computer or over a data communications network. Such communications adapters 332 include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0032] For further explanation, FIG. 4 sets forth a flowchart illustrating an exemplary method for cascaded execution of atomic operations according to an embodiment of the present disclosure. The method of FIG. 4 may be implemented, for example, in the processor 100. The method of FIG. 4 includes each thread 104a-104n of the plurality of threads 104a-104n receiving 402 a request to perform an atomic operation. Each thread 104a-104n executes on one of the plurality of cores 102a-102n. In other words, the plurality of threads 104a-104n includes a plurality of thread subsets, each thread subset executing on a respective core 102a-102n. Since each core 102a-102n includes a respective local memory 106a-106n, each thread subset corresponds to a local memory 106a-106n, and the local memory 106a-106n for a thread subset is accessible to the thread subset and is not accessible to other threads 104a-104n outside the thread subset. In some embodiments, the local memory 106a-106n includes a local cache, such as an L2 cache.

[0033] 4 also includes generating 404, by each thread subset, a plurality of intermediate results by performing atomic operations in a local memory 106a-106n corresponding to the thread subset. As described above, each thread subset executes on a respective core 102a-102n that includes a local memory 106a-106n. Instead of performing the atomic operations in a shared memory 108, such as a shared cache, accessible to all threads 104a-104n, the threads 104a-104n perform the atomic operations in their accessible local memories 106a-106n. The result of each thread subset performing the atomic operations in the local memories 106a-106n is the intermediate result.

[0034] In some embodiments, generating 404 the multiple intermediate results includes initializing 406 a cache line in a local memory 106a-106n corresponding to each thread subset. In some embodiments, each local memory 106a-106n includes a cache implemented on the respective core 102a-102n. Thus, in order for threads 104a-104n on a given core 102a-102n to perform atomic operations in the cache, the cache line is initialized. For example, the cache line is zeroed such that all data in the cache line is equal to zero. Then, a first atomic operation is performed on the initialized value, and each subsequent atomic operation is performed on the result of the preceding atomic operation. In some embodiments, the default value depends on the type of atomic operation being performed. For example, for an increment or ADD operation, the default value is zero. As another example, if the atomic operation is a minimum operation (e.g., unsigned minimum (UMIN) or signed minimum (SMIN)), the default value is the maximum possible positive value that can be stored in the cache line. As a further example, if the atomic operation is a maximum operation (eg, unsigned maximum (UMAX) or signed maximum (SMAX)), the default value is the smallest possible negative value that can be stored in a cache line.

[0035] 4 also includes generating 408 a result for the request by aggregating multiple intermediate results in the shared memory 108 that are accessible to all threads 104a-104n in the multiple threads 104a-104n. For example, the intermediate results are copied or moved to the shared memory 108. The intermediate results are then aggregated in the shared memory 108 by performing one or more atomic operations in the shared memory 108 on the intermediate results.

[0036] For further explanation, FIG. 5 illustrates a flow chart showing a variation of the exemplary method of FIG. 4. The method of FIG. 5 differs from FIG. 4 in that it also includes evicting 502 a cache line and a tag indicating an opcode for an atomic operation for each intermediate result of the plurality of intermediate results. If the local memories 106a-106n include a local cache, the intermediate results are stored in a particular cache line. As described above, each local memory 106a-106n includes in a cache line the intermediate results based on the atomic operations executed in the local memory 106a-106n by the corresponding thread subset. By evicting the cache line to the shared memory 108, the intermediate results are moved to the shared memory 108 for aggregation. The cache line is evicted with a tag indicating an opcode for the atomic operation used to generate the intermediate result.

[0037] In the method of FIG. 5, generating 408 a result includes performing 504 one or more other atomic operations in shared memory 108 based on the tag. The one or more other atomic operations are performed in shared memory 108 to aggregate the intermediate results into a final result. In some embodiments, the atomic operation performed on the intermediate results matches the atomic operation of the opcode for the tag. As an example, if the tag indicates an add operation, an add operation is performed on the intermediate results to sum them into a final result. In some embodiments, the atomic operation performed on the intermediate results is based on, but does not match, the atomic operation of the opcode for the tag. As an example, if the tag indicates a decrement operation (e.g., subtract by one), a subtract operation is performed on the intermediate results to aggregate them into a final result.

[0038] In light of the above discussion, the reader will recognize that advantages of cascaded execution of atomic operations include improved performance of a computing system by providing accelerated parallel execution of atomic operations in local memory prior to aggregation in shared memory.

[0039] Exemplary embodiments of the present disclosure are described primarily in the context of a fully functional computer system for cascaded execution of atomic operations. However, a reader skilled in the art will recognize that the present disclosure may be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tapes, and others as would occur to one skilled in the art. A person skilled in the art will readily recognize that any computer system with suitable programming means is capable of executing the steps of the method of the present disclosure embodied in a computer program product. A person skilled in the art will also recognize that, although some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless within the scope of the present disclosure.

[0040] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present disclosure.

[0041] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination of the above. As used herein, a computer-readable storage medium should not be construed as being an electromagnetic wave, such as an electric wave or other freely propagating electromagnetic wave, propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or a transitory signal per se, such as an electrical signal transmitted through a wire.

[0042] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network can include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing / processing device.

[0043] The computer readable program instructions for carrying out the operations of the present disclosure can be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions can be executed completely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to individualize the electronic circuitry to implement aspects of the present disclosure.

[0044] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer readable program instructions.

[0045] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may be stored on a computer readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner such that the computer readable storage medium having instructions stored thereon comprises an article of manufacture including instructions that perform aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0046] Furthermore, the computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operation steps to be performed on the computer, other programmable apparatus, or other device to generate a computer-implemented process such that the instructions executing on the computer, other programmable apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0047] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative embodiments, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flow diagrams, as well as combinations of blocks in the block diagrams and / or flow diagrams, may be executed by a dedicated hardware-based system that performs the specified functions or acts, or executes a combination of dedicated hardware and computer instructions.

[0048] It will be understood from the above description that modifications and changes can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A processor for cascading atomic operations, comprising: The controller receiving a request for performing an atomic operation in each thread of a plurality of threads, the plurality of threads including a plurality of thread subsets each corresponding to a local memory, the local memory of a thread subset being accessible by the thread subset and inaccessible to remaining threads in the plurality of threads; generating a plurality of intermediate results by performing, in the local memory corresponding to each subset of threads, the atomic operation; generating a result for the request by aggregating the intermediate results into a shared memory accessible to all threads in the plurality of threads; The method is configured to carry out a process comprising: Processor.

2. each subset of threads executes on a respective core of the plurality of cores, and the local memory for each subset of threads includes a cache implemented on the respective core; The processor of claim 1 .

3. the shared memory includes a shared cache; The processor of claim 1 .

4. the shared cache includes a last level cache; The processor of claim 3.

5. the steps including, for each intermediate result of the plurality of intermediate results, evicting a cache line and a tag indicating an opcode for the atomic operation. The processor of claim 1 .

6. aggregating the intermediate results includes performing one or more other atomic operations in the shared memory based on the tags. The processor of claim 5.

7. generating the intermediate results includes initializing cache lines in the local memory corresponding to each thread subset; The processor of claim 2.

8. 1. A method for cascading atomic operations, comprising: receiving a request for performing an atomic operation in each thread of a plurality of threads, the plurality of threads including a plurality of thread subsets each corresponding to a local memory, the local memory of a thread subset being accessible by the thread subset and inaccessible to remaining threads in the plurality of threads; generating a plurality of intermediate results by performing, in the local memory corresponding to each subset of threads, the atomic operation; generating a result for the request by aggregating the intermediate results into a shared memory accessible to all threads in the plurality of threads. method.

9. each subset of threads executes on a respective core of the plurality of cores, and the local memory for each subset of threads includes a cache implemented on the respective core; 9. The method of claim 8.

10. the shared memory includes a shared cache; 9. The method of claim 8.

11. the shared cache includes a last level cache; The method of claim 10.

12. for each intermediate result of the plurality of intermediate results, evicting a cache line and a tag indicating an opcode for the atomic operation.

9. The method of claim 8.

13. aggregating the intermediate results includes performing one or more other atomic operations in the shared memory based on the tags.

13. The method of claim 12.

14. generating the intermediate results includes initializing cache lines in the local memory corresponding to each thread subset; 10. The method of claim 9.

15. 1. An apparatus for cascading atomic operations, comprising: Computer memory; a processor operably coupled to the computer memory; The processor, receiving a request for performing an atomic operation for each thread of a plurality of threads, the plurality of threads including a plurality of thread subsets each corresponding to a local memory, the local memory of a thread subset being accessible by the thread subset and inaccessible to remaining threads in the plurality of threads; generating a plurality of intermediate results by performing, in the local memory corresponding to each subset of threads, the atomic operation; generating a result for the request by aggregating the intermediate results into a shared memory accessible to all threads in the plurality of threads; The method is configured to carry out a process comprising: Device.

16. each subset of threads executes on a respective core of the plurality of cores, and the local memory for each subset of threads includes a cache implemented on the respective core; 16. The apparatus of claim 15.

17. the shared memory includes a shared cache; 16. The apparatus of claim 15.

18. the shared cache includes a last level cache; 20. The apparatus of claim 17.

19. the steps including, for each intermediate result of the plurality of intermediate results, evicting a cache line and a tag indicating an opcode for the atomic operation.

16. The apparatus of claim 15.

20. aggregating the intermediate results includes performing one or more other atomic operations in the shared memory based on the tags.

20. The apparatus of claim 19.

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