Voltage converter with average input current control and input-to-output isolation - Patents.com

Abstract

A voltage converter (100) having a voltage input and a voltage output, the voltage converter (100) includes first and second transistors (M1, ISO FET) and an average current control circuit (130). The first transistor (M1) has a first control input and a first current terminal and a second current terminal. The first current terminal is adapted to be coupled to a switch node. The second transistor (ISO FET) has a second control input and a third current terminal and a fourth current terminal. The third current terminal is adapted to be coupled to an inductor (El). The average current control circuit (130) is coupled to the third current terminal and the fourth current terminal. The average current control circuit (130) is configured to determine an average current level of a current flowing through the second transistor (ISO FET) and control a voltage on the first control input of the first terminal based on the determined average current level.

Description

[Technical field]

[0001] Many types of voltage regulators are available. One type is a switching regulator, in which the duty cycle of one or more switching transistors is controlled based on a feedback signal to regulate the regulator's output voltage. One type of switching regulator is a boost converter, which produces a regulated output voltage that is greater than the input voltage. Summary of the Invention

[0002] In one example, a voltage converter has a voltage input and a voltage output. The voltage converter includes a first transistor, a second transistor, and an average current control circuit. The first transistor has a first control input, a first current terminal, and a second current terminal. The first current terminal is adapted to be coupled to a switch node. The second transistor has a second control input, a third current terminal, and a fourth current terminal. The third current terminal is adapted to be coupled to an inductor. The average current control circuit is coupled to the third current terminal and the fourth current terminal. The average current control circuit is configured to determine an average current level of a current flowing through the second transistor and control a voltage on the first control input of the first terminal based on the determined average current level. [Brief description of the drawings]

[0003] [Figure 1] 1 is a schematic diagram of a boost voltage converter according to an example.

[0004] [Diagram 2] 2 is a more detailed schematic diagram of the boost voltage converter of FIG. 1 according to an example.

[0005] [Diagram 3] 4 is a timing diagram illustrating the operation of a boost voltage converter during normal operation (when the output voltage is greater than the input voltage) according to an example.

[0006] [Figure 4] 4 is a timing diagram illustrating the operation of a boost voltage converter during start-up or an output short condition (when the output voltage is less than the input voltage) in accordance with an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A boost voltage converter converts an input voltage to a higher output voltage. In some applications of boost voltage converters, the input power source to the boost voltage converter has a relatively small input current limit. For example, some peripheral devices (e.g., barcode readers, cameras, etc.) receive operating power from a Universal Serial Bus (USB) Type-C cable. USB Type-C is only capable of carrying relatively low power to the peripheral device (e.g., 5V at 500 milliamps (mA)). For such limited input current power sources, it may be advantageous to control the average input current to efficiently use the input current. A boost voltage converter in which a control regulation circuit regulates the peak or valley input current may not be able to efficiently utilize the full but limited input current capability of the power source. The boost voltage converter described herein has a control circuit that controls the average (DC) input current. The described boost voltage converter also provides control for start-up or output short circuit conditions.

[0008] FIG. 1 is a schematic diagram of a boost voltage converter 100 according to an example. The boost voltage converter 100 includes an input (VIN) and an output (VOUT). During operation, VOUT is greater than VIN. However, during start-up or when VOUT is shorted to ground, VOUT is less than VIN. The boost voltage converter 100 includes an inductor L1, a switching transistor M1, and a Schottky diode D1. The current through the inductor L1 is labeled IL. The switching transistor M1 in this example is an n-type metal oxide semiconductor field effect transistor (NMOS transistor). When M1 is on, the current IL flows through the inductor L1 and energy is stored in the inductor L1 in its magnetic field. When M1 is off, the current IL decreases. The energy of the magnetic field also decreases to maintain the flow of current toward VOUT (to which the load is coupled). The inductor voltage polarity reverses with M1 off, therefore, VIN is in series with the inductor voltage and these two voltages add together to provide the larger VOUT voltage, charging the output capacitor Cout through Schottky diode D1.

[0009] The boost voltage converter 100 of FIG. 1 also includes an ISO Contains an isolation transistor (e.g., an NMOS transistor) denoted as FET. Inductor L1 and ISO The connection node between the FET is labeled VP and the ISO The connection node between the FET and Schottky diode D1 is labeled the switch node (SW). The drain of M1 is coupled to SW and the source of M1 is coupled to ground. When M1 is on, SW is pulled low to approximately ground. When M1 is off, SW is pulled high to approximately VOUT.

[0010] The boost voltage converter 100 also includes an ISO FET control circuit 120, an average current control circuit 130, a transconductance amplifier 102, a voltage-to-current (V2I) converter 104, and a PWM circuit 106. The FET control circuit 120 is During normal operation, the FET operates in its linear region. Turn on the FET. ISO Since the FET operates in its linear region, the ISO The FET represents a resistance between VP and SW, and therefore acts as a sense resistor to generate a voltage between its drain and source that is proportional to IL. The average current control circuit 130 supplies a current (IAVG SNS) and controls the compensation (COMP) signal to the PWM circuit 106. The SNS is used to control the duty cycle of the MI. If the average level of IL increases, the average current control circuit 130 responds by decreasing the duty cycle of the PWM circuit 106 to decrease the average level of IL. If the average level of IL decreases, the average current control circuit 130 responds by increasing the duty cycle of the PWM circuit 106 to increase the average level of IL. The operation of FET control circuit 120 and average current control circuit 130 is further described below.

[0011] Resistors R1 and R2 are coupled in series between VOUT and ground to generate a scaled down version of VOUT on a feedback node (FB) at the negative input of a transconductance amplifier 102. The positive input of the transconductance amplifier is coupled to a reference voltage VREF. The output of the transconductance amplifier is a compensation signal COMP, which is converted to a current by V2I 104. The current from V2I 104 flows through resistor Rs, which converts the current to a voltage, which is coupled to the positive input of a PWM circuit 106. The negative input of the PWM circuit 106 is coupled to the drain of ML. When M1 is on, current flows through M1, and because of its drain-source resistance, a voltage (albeit relatively low) proportional to the current through inductor L1 is generated on the drain of M1. The drain voltage of M1 is therefore the current sense signal (ISNS).

[0012] The ISO FET control circuit 120 includes a VMAX circuit 122 coupled to an ISO FET driver 124. The VMAX circuit includes one or more comparators. The input signals to the VMAX circuit 122 are VIN and VOUT. The VMAX circuit 122 generates two output control signals VMAX and VOUT VMAX is a voltage approximately equal to the greater of VIN and VOUT. That is, VMAX is approximately equal to VOUT during normal operation when VOUT is greater than VIN, and VMAX is approximately equal to VIN during start-up or VOUT short-circuit conditions (when VIN is greater than VOUT). VMAX and VOUT HI is ISO The control signal for turning on M1 is provided to the FET driver 124. ON and LSD ON is also provided as an input signal to ISO FET driver 124. Both VP and SW are also coupled to ISO FET driver 124. An example implementation of ISO FET driver 124 is shown in Figure 2 and described in more detail below.

[0013] 1, the average current control circuit 130 includes a high side (HSD) current sense circuit 132, a current reference circuit ILIM ("ILIM" refers to both the current reference circuit and the magnitude of the current it generates), a current amplifier 134, a resistor R4, a capacitor C2, and a transistor M2. Transistor M2 in this example is a p-type metal oxide semiconductor field effect transistor (PMOS transistor). When the input current to the current amplifier 134 is labeled ERR, the output of the HSD current circuit 132 is a current IAVG that is proportional to the average IL current. It is a social networking site. If SNS is greater than ILIM, ERR is This is a positive current that is the difference between SNS and ILIM flowing into the current amplifier 134. If SNS is less than ILIM, ERR flows in the opposite direction (i.e., from current amplifier 134 through ILIM to ground) and the sum of ERR and IAVG The sum of SNS is equal to ILIM in this state. Current amplifier 134 is an inverting current amplifier whose output controls the gate of M2. When the average IL current increases, the voltage on the gate of M2 turns M2 on harder, pulling COMP lower, to decrease the duty cycle of M1 and therefore decrease IL. When the average IL current decreases, the voltage on the gate of M2 also increases, turning M2 off further, allowing COMP to increase the duty cycle of M1 and therefore increase IL.

[0014] 2, the ISO FET driver 124 includes a diode D2, a Zener diode Z2, a PMOS transistor MP, switches S1 and S2 (both of which are transistors), a NOR gate 208, and an inverter 210. HI is coupled to one input of an inverter 208, and an LSD ON is coupled to the other inverter input. The output of NOR gate 208 is coupled to S2 and controls the on / off state of S2. The output of NOR gate 208 is coupled to the input of inverter 210 and the output of inverter 210 is coupled to S1 and controls the on / off state of S1. Thus, when S1 is on, S2 is off and when S2 is on, S1 is off.

[0015] When on (closed), S1 supplies the bootstrap voltage BOOT to ISO The ISO FET is connected to the gate of the FET. BOOT is generated by a bootstrap circuit (not shown) and is a predetermined voltage that exceeds the voltage of SW. In one example, BOOT is 5V greater than SW. The source of the FET is coupled to SW. When S1 is turned on, ISO The gate-source voltage (Vgs) of the FET is the BOOT voltage. In the example where BOOT is SW+5V, when S1 is on, ISO The Vgs of the FET is 5V.

[0016] The VMAX122 responds by lowering VOUT HI is forced to a logic "1". If one input of the NOR gate is a logic "1", the output of the NOR gate is a logic "0", thereby turning S2 off. However, the logic 0 from NOR gate 208 is inverted to a logic 1 by inverter 210, thereby turning S1 on. ISO The FET is on, operates in the linear region, and acts as a current sensing resistor that senses the inductor current (IL).

[0017] With further reference to FIG. 2, the HSD current sense circuit 132 includes a sense transistor (SNS The current mirror 202 includes, for example, a pair of PMOS transistors functioning as a current mirror. The current flowing through M3 is IAVG As SNS, it is mirrored to ILIM and current amplifier 134 via M4.

[0018] Social Media The source of the FET is coupled to SW and to the BOOT voltage. The source of the FET is ISO The inverting (-) input of OP1 is connected to the source of the FET and SW. The non-inverting (+) input of OP1 is connected to the drain of the FET. It is connected to the drain of the FET. The drain of the FET is coupled to node VP. Since the voltage difference between the inverting and non-inverting inputs of the operational amplifier is approximately 0 V, SNS The drain of the FET is also approximately equal to VP. When M1 is on, ISO The FET operates in the linear region as described above. FETs also operate in the linear region. SNS FETs are smaller transistors (the dimension refers to the ratio of channel width (W) to channel length (L)). If their source, drain, and gate have the same voltage, then SNS The current through the FET is It is proportional to the current through the FET (IL), but smaller than it. SNS The current through the FET is labeled as I21 in Figure 2. Current mirror 202 provides the current I21 through M3 and through the SNS_FET to SW.

[0019] The current mirror 202 also Mirror I21 to the ILIM / current amplifier 134 via M4 as SNS. The current amplifier includes a current mirror 230 formed by two NMOS transistors M4 and M5. Current source I20 provides the same current in one embodiment. IAVG If SNS is greater than ILIM, the excess current (IAVG The difference between SNS and ILIM flows into the drain of M4 along with I20. In one embodiment, the mirror ratio of current mirror 230 is 1:1, so the current that flows through M4 also flows through M5. Therefore, IAVG When SNS is greater than ILIM, the drain current of M5 is greater than I20, and therefore current flows out of the gate of M2, thereby discharging the gate of M2, which pulls COMP lower. Conversely, IAVG If SNS is less than ILIM, the drain current of M5 is less than I20 and excess current (I20 less than the drain current of M5) flows into the gate of M2, thereby charging that gate and bringing M2 closer to the fully off state, thereby allowing COMP to increase.

[0020] 3 is a timing diagram illustrating the operation of the boost voltage converter during normal operation where VOUT is greater than VIN. The timing diagram shows sample waveforms of inductor current IL, ISO The Vgs of the FET, the voltage of SW, and the BOOT voltage are included. When M1 is on, the inductor current IL increases as shown at 301. In one example, the BOOT voltage is 5V greater than the SW voltage, so the ISO The Vgs of the FET is 5V whether M1 is on or off. When M1 is on, the SW voltage is about 0V (as shown at 303) and therefore the BOOT voltage is about 5V as shown at 304. When M1 is off, IL decreases as shown at 302 and the SW voltage jumps to nearly VOUT as shown at 305 and therefore the BOOT voltage increases to VOUT+5V as shown at 306.

[0021] During the start-up process, VIN will be greater than VOUT. If VOUT is shorted to ground, VIN will also be greater than VOUT. In response to VIN being greater than VOUT, VMAX122 will HI is set to logic 0. VOUT If HI is 0, the output of NOR gate 208 is LSD It is the logical inversion of ON. LSD When ON is 1, M1 is turned on and LSD When ON is 0, M1 is off. Therefore, M1 is on (LSD When M1 is ON (when M1 is 1), the output of NOR gate 208 is 0, which turns off S2 and turns on S1 through inverter 210. Alternatively, when M1 is ON, S1 is also ON, which causes the BOOT voltage to be equal to ISO Conversely, when VIN is greater than VOUT and M1 is off (LSD_ON is 0), the output of NOR gate 208 is 1, which turns S2 on and S1 off. Alternatively, when M1 is off, S2 is on (S1 is off) and ISO The gate of the FET is coupled to SW through resistor R5. By controlling the gate voltage of the FET, ISO at Vgs which regulates the current through the FET to approximately equal IL (which decreases when M1 is off) To operate the FET in the saturation region, a control loop is created in this configuration, which is described further below.

[0022] When VIN is greater than VOUT, VOUT HI is 0 and the control loop operates according to two phases. One phase has M1 on (LSD ON is 1). The other phase is when M1 is off (LSD When M1 is on, SW is approximately equal to ground and LSD ON is 1 and the output of NOR gate 208 is 0. As a result, S2 is off and S1 is on. When S1 is on, the BOOT voltage is It is coupled to the gate of the FET.

[0023] When M1 is off, LSD ON is 0. VOUT HI and LSD When both ON and S1 are 0, the output of the NOR gate is 1, which closes S2 and, through inverter 210, opens S1. In this configuration, ISO The gate of the FET is coupled to SW through resistor R5. The gate of MP is VMAX (the greater of VIN or VOUT). If VIN is greater than VOUT, then VMAX is VIN, and therefore the gate of MP is VIN. ISO The Vgs voltage of the FET decreases with the resistance of R5 as a load, hence the ISO The drain-source on-resistance of the FET increases. The VP voltage increases when the inductor current does not change (the loop response is fast, so the inductor current generally does not change). When the VP voltage rises above VIN due to the forward voltage drop of diode D2 plus the Vgs of MP, the MP transistor starts to conduct and its source current flows through R5, causing the ISO Increase the Vgs of the FET. Therefore, MP, R5, and ISO The combination of FETs forms a negative feedback loop. VP is approximately equal to the voltage on the gate of MP(VIN) plus the Vgs of MP plus the forward voltage drop across diode D2. ISO The FET operates in the saturation region with Vgs in the range of approximately 1-2V.

[0024] 4 is a timing diagram illustrating the operation of the boost converter during operation when VOUT is less than V. The timing diagram shows sample waveforms of the inductor current IL, ISO The diagram includes the FET Vgs, the SW voltage, and the BOOT voltage. When M1 is on, the inductor current IL increases as shown at 401. In the above example, the BOOT voltage is 5V greater than the SW voltage. When M1 is on, the SW voltage is about 0V (as shown at 403), and therefore the BOOT voltage is about 5V, as shown at 404. When M1 is off, S1 is off and S2 is on as explained above. IL decreases as shown at 402. The SW voltage jumps to nearly VOUT as shown at 405, and therefore the BOOT voltage increases to VOUT+5V as shown at 406. ISO The Vgs of the FET is approximately equal to 5V when M1 is on and S1 is closed as shown at 407, but decreases to 1-2V as shown at 408, as controlled by the control loop described above.

[0025] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (a) in a first example, device A is coupled to device B by a direct connection when device A generates a signal that controls device B to perform an action, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A when intervening component C does not change the functional relationship between device A and device B.

[0026] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or the termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0027] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0028] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-type metal oxide silicon field effect transistor ("MOSFET") may be substituted for an n-type MOS FET with little or no change to the circuit. Also, other types of transistors (such as bipolar junction transistors (BJTs)) may be used.

[0029] The circuits described herein are reconfigurable to include additional or different components to provide at least partially similar functionality to that available prior to the component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0030] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of the present description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Modifications may be made to the described examples and other examples are possible within the scope of the present claims.

[0031] Modifications may be made to the described embodiments, and other embodiments are possible, within the scope of the invention.

Claims

1. 1. A voltage converter having a voltage input and a voltage output, an inductor having a first terminal coupled to the voltage input and a second terminal; a first transistor having a first control input, a first current terminal, and a second current terminal; a second transistor having a second control input, a third current terminal coupled to the second terminal of the inductor, and a fourth current terminal; an average current control circuit coupled to the third current terminal and the fourth current terminal, the current control circuit including a current sensing circuit having a first input coupled to the third current terminal and a second input coupled to the fourth current terminal; determining an average current level of the current flowing through the second transistor; controlling a voltage on a first control input of the first transistor based on the determined average current level. the average current control circuit configured as follows: , a voltage converter.

2. 2. A voltage converter according to claim 1, a current amplifier having an input coupled to the output of the current sensing circuit; a third transistor having a third control input, a fifth current terminal, and a sixth current terminal; Further comprising: A voltage converter configured such that the voltage on the fifth current terminal controls the voltage on the first control input.

3. 3. A voltage converter according to claim 2, A voltage converter wherein the current amplifier is an inverting current amplifier.

4. 2. A voltage converter according to claim 1, The average current control circuit a third transistor having a third control input, a fifth current terminal coupled to the fourth current terminal, and a sixth current terminal; an operational amplifier having a first input coupled to the sixth current terminal and a second input coupled to the third current terminal; The voltage converter further comprises:

5. 2. A voltage converter according to claim 1, 11. The voltage converter, further comprising: a transistor driver having a first driver terminal coupled to the third current terminal, a second driver terminal coupled to the fourth current terminal, a first driver control input, a second driver control input, and a driver output coupled to the second control input.

6. 6. A voltage converter according to claim 5, a control circuit having a first control output coupled to the first driver control input and a second control output coupled to the second driver control input, generating a voltage on said first control output equal to the greater of the voltages on said voltage input and said voltage output; generating a digital control signal on said second control output indicative of which of said voltage input and said voltage output has a greater voltage; a control circuit configured to:

7. 7. A voltage converter according to claim 6, The transistor driver a logic circuit having an input that is the second driver control input; a third transistor having a third control input being the first driver control input, a fifth current terminal, and a sixth current terminal providing the driver output coupled to the second current terminal; a first switch coupled to the logic circuit, the first switch configured to switch a boot voltage to the second control input in response to a first signal from the logic circuit; a second switch coupled to the logic circuit, the second switch configured to couple the boot voltage to the fourth current terminal in response to a second signal from the logic circuit; , a voltage converter.

8. 8. A voltage converter according to claim 7, The voltage converter, wherein the logic circuit includes a logic gate having a first logic gate input that is the second driver control input and a second logic gate input that is coupled to the first control input.

9. 2. A voltage converter according to claim 1, A voltage converter, wherein the voltage converter is a boost voltage converter.

10. 1. A voltage converter having a voltage input and a voltage output, a first transistor having a first control input, a first current terminal, and a second current terminal; a second transistor having a second control input, a third current terminal adapted to be coupled to the inductor, and a fourth current terminal; an average current control circuit coupled to the third current terminal and the fourth current terminal, the current control circuit including a current sensing circuit having a first input coupled to the third current terminal and a second input coupled to the fourth current terminal; determining an average current level of the current flowing through the second transistor; controlling a voltage on a first control input of the first transistor based on the determined average current level. the average current control circuit configured as follows: , a voltage converter.

11. 11. A voltage converter according to claim 10, a current amplifier having an input coupled to the output of the current sensing circuit; a third transistor having a third control input, a fifth current terminal, and a sixth current terminal; Further comprising: A voltage converter configured such that the voltage on the fifth current terminal controls the voltage on the first control input.

12. 11. A voltage converter according to claim 10, The average current control circuit a third transistor having a third control input, a fifth current terminal coupled to the fourth current terminal, and a sixth current terminal; an operational amplifier having a first input coupled to the sixth current terminal and a second input coupled to the third current terminal; The power converter further comprises:

13. 11. A voltage converter according to claim 10, a transistor driver having a first terminal coupled to the third current terminal, a second terminal coupled to the fourth current terminal, a first driver control input, a second driver control input, and a driver output coupled to the second control input.

14. 11. A voltage converter according to claim 10, a first logic gate having an output; a second logic gate having an input coupled to the output of the first logic gate; a first switch having a control input coupled to the output of the second logic gate, the first switch being configured to couple a voltage to a second control input of the second transistor when closed; a second switch having a control input coupled to the output of the first logic gate, the second switch being configured to couple the voltage to a fourth current terminal of the second transistor when closed; The voltage converter further comprises:

15. 1. A boost converter having a converter input and a converter output, an inductor having a first terminal coupled to the voltage input and a second terminal; a first transistor having a first control input, a first current terminal, and a second current terminal; an isolation transistor having a second control input, a third current terminal coupled to the second terminal of the inductor, and a fourth current terminal; an average current control circuit coupled to the third current terminal and the fourth current terminal, determining an average current level of current flowing through the isolation transistor; controlling a voltage on a first control input of the first transistor based on the determined average current level. the average current control circuit configured as follows: an isolation transistor driver having a first driver terminal coupled to the third current terminal, a second driver terminal coupled to the fourth current terminal, a first driver control input, a second driver control input, and a driver output coupled to the second control input; Including, a boost converter.

16. 16. The boost converter of claim 15, a current amplifier having an output; The boost converter, wherein the average current control circuit includes a current sensing circuit coupled to the current amplifier.

17. 17. The boost converter of claim 16, The boost converter further includes a transconductance amplifier having an output coupled to the output of the current amplifier.

18. 16. The boost converter of claim 15, responsive to the voltage on the converter input being less than the voltage on the converter output, the isolation transistor driver has a first mode of operation when the first transistor is on and a second mode of operation when the first transistor is off, the first mode of operation causing the isolation transistor driver to turn on the isolation transistor and the second mode of operation causing the isolation transistor driver to adjust the voltage on the second control input of the isolation transistor based on the voltage on the third current terminal.

19. 16. The boost converter of claim 15, The boost converter, wherein the isolation transistor is an n-type metal oxide semiconductor field effect transistor.

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