Out-of-Audio (OOA) Switching Voltage Regulators

Abstract

The control circuit (410) includes a timeout circuit (414) configured to receive a first control signal. The timeout circuit (414) asserts a timeout output signal on a timeout circuit output in response to expiration of a time period following assertion of the first control signal. A counter circuit (416) has an input coupled to the timeout circuit output and has a counter circuit output. In response to assertion of the first control signal, the counter circuit (416) selectively increments an output count value on the counter circuit output in response to the timeout output signal having a first logic state or decrements an output count value on the counter circuit output in response to the timeout output signal having a second logic state. A comparison circuit (420) has a control input coupled to the counter circuit output. The comparison circuit (420) adjusts a magnitude of a reference signal in response to the output count value from the counter circuit (416).

Description

[Technical field]

[0001] A voltage regulator receives an input voltage and generates a regulated output voltage. One type of voltage regulator includes a switching voltage regulator. A switching regulator includes one or more transistors that are switched on and off. Under relatively heavy load conditions (higher output current), the switching frequency exceeds the upper limit of human hearing. The upper limit of human hearing is generally considered to be about 20 KHz. Under lighter load conditions (lower output current levels), the switching regulator can maintain regulation of the output voltage by reducing the switching frequency. If the switching frequency is within the range of human hearing (e.g., below 20 KHz), such electrical switching noise can result in audio noise in a system having a speaker. For example, an audible noise can be heard through an automobile's infotainment system, which includes a voltage regulator. Summary of the Invention

[0002] In at least one example, a control circuit for a voltage converter includes a timeout circuit that receives a first control signal. The timeout circuit asserts a timeout output signal upon expiration of a predetermined time period following assertion of the first control signal. The control circuit includes a counter circuit having an input coupled to the timeout circuit output and a comparator circuit output. When the first control signal is asserted, the counter circuit increments an output count value on the counter circuit output in response to the timeout output signal being in a first logic state or decrements an output count value on the counter circuit output in response to the timeout output signal being in a second logic state. A control input of the comparator circuit couples to the counter circuit output. The comparator circuit adjusts a reference signal in response to the output count value from the counter circuit. [Brief description of the drawings]

[0003] [Figure 1]FIG. 2 is a schematic diagram of a buck converter in one example.

[0004] [Diagram 2] 2 is a timing diagram illustrating the operation of the buck converter of FIG. 1 in one example.

[0005] [Diagram 3] 2 is an inductor current waveform illustrating a possible instability problem in the Buck converter of FIG. 1.

[0006] [Figure 4] FIG. 1 is a schematic diagram of a buck converter having a timeout circuit, a counter circuit, and a zero-crossing comparator in another example for solving the instability problem.

[0007] [Diagram 5] FIG. 5 is a schematic diagram illustrating an implementation of a timeout circuit, a counter circuit, and a zero-crossing compare of the buck converter of FIG. 4 in one example.

[0008] [Figure 6] FIG. 2 is a schematic diagram illustrating a particular exemplary implementation of a timeout circuit;

[0009] [Figure 7] 5 is a timing diagram illustrating the operation of the buck converter of FIG. 4 in one example.

[0010] [Figure 8] 5 includes waveforms illustrating the operation of the buck converter of FIG. 4 to maintain a switching frequency above the upper frequency range of human hearing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Herein, we describe an example of a buck converter that reduces or eliminates switching noise that can appear as audio noise. However, the principles described herein are also relevant to other types of switching regulators, such as boost converters, buck-boost converters, etc. The example converters described herein operate to maintain switching frequencies above the upper limit of human hearing (e.g., above about 20 KHz). Therefore, such switching voltage regulators are referred to as "out-of-audio" regulators (converters).

[0012] FIG. 1 shows an example of a buck converter 100 that includes a high-side (HSD) transistor coupled to a low-side (LSD) transistor at a switch node (SW). The transistors are shown in FIG. 1 as field effect transistors (FETs) and are therefore labeled HSD FET and LSD FET. The series combination of the HSD and LSD FETs is between an input voltage VIN and ground. One terminal of an inductor L1 is coupled to the SW node, and the other inductor terminal provides a regulated output voltage (VOUT) and is also coupled to an output capacitor COUT. Control logic 110 controls the on and off states of the HSD and LSD FETs, thereby generating a square wave on the SW node with a duty cycle implemented by the control logic. Driver 102 converts the digital control signals (HSON and LSON) from the control logic 110 into appropriate voltages for the gates of the HSD and LSD FETs to turn them on and off. The magnitude of VOUT is a function of VIN and the duty cycle implemented by the control logic 110. A load 125 may be coupled to the inductor L1 and therefore receives VOUT from the converter. A zero-crossing (ZC) comparator 120 outputs a signal indicative of the inductor current IL (SW SNS) is compared to ground to determine when the inductor current reaches 0 amperes. SNS is from a current sensor 119. The current sensor 119 may include a sense resistor whose voltage is proportional to the current. Alternatively, the current sensor 119 may include a sense FET coupled in parallel with the LSD FET to generate a voltage proportional to the current through the LSD FET. A resistor divider formed by R1 in series with R2 between VOUT and ground provides a feedback voltage (VFB) proportional to VOUT. A comparator 122 uses VFB as a proxy for VOUT, compares VFB to a reference (VREF), and generates a LOOPRAW signal to the control logic 110 indicating that VOUT is above or below a threshold voltage (VREF). The LOOPRAW signal is provided to the control logic 110 and is used by the control logic 110 to determine when VOUT (VFB) has dropped to a threshold level and then turn on the HSD FET to boost VOUT to a higher voltage.

[0013] Buck converter 100 provides a regulated level of VOUT through a wide range of load currents. As the load's current needs decrease, control logic 110 dynamically adjusts the timing control of the HSD and LSD FETs to maintain the regulated level of VOUT. At higher load conditions, control logic 110 operates in continuous conduction mode (CCM) where the HSD and LSD FETs are toggled on and off continuously and alternately. In this mode, the LSD transistor turns on when the HSD FET turns off, then the LSD FET turns off and the HSD FET turns back on, and so on (with a small "dead time" between switching to avoid shoot-through current conditions). Current flows continuously through inductor L1 during CCM. At lighter load conditions (e.g., the load goes into a sleep state), the control logic may enter discontinuous conduction mode (DCM). At some point during each switching cycle in DCM, neither the HSD FET nor the LSD FET is on.

[0014] FIG. 2 is a timing diagram illustrating a type of DCM, pulse skipping mode (PSM), for the control logic at even lower load levels. A pulse event 211 is shown on the left side of the timing diagram. For this pulse event, the control logic 110 first turns on the LSD FET, which reduces IL, as shown at 202. Turning on the LSD FET also discharges the SW node, reducing VOUT, as shown at 205. When VOUT (or its proxy, VFB) falls below VREF, the comparator 122 asserts LOOPRAW (e.g., low) (206). The control logic 110 responds to the low assertion of LOOPRAW by turning off the LSD FET and turning on the HSD FET for a predetermined period of time. Turning on the HSD FET causes both IL and VOUT to increase, as shown at 202 and 204, respectively. Upon expiration of the predetermined period of time that the HSD FET is on, the control logic 110 turns off the HSD FET and turns on the LSD FET. When the LSD FET turns on, IL decreases towards 0 amp as shown at 203. VOUT also begins to decrease as shown at 207.

[0015] ZC comparator 120 determines when IL reaches 0 amps (time 208 in FIG. 2) and asserts its ZERO CROSS output signal (e.g., logic high). Control logic 110 responds to the assertion of ZERO CROSS by turning off the LSD FET. At that time (time 208), both the HSD FET and the LSD FET are off and IL remains at 0 amps until the next pulse event 213. When the HSD FET turns off, V also decreases (207). Control logic 110 includes a timer that determines when the elapsed time from when ZC comparator 120 detects a zero crossing (i.e., IL reaches 0 amps) reaches a predetermined period of time approximately equal to the period of the upper frequency limit of human hearing. If the upper limit is 20 KHz, then the period of a 20 KHz waveform is 50 microseconds. Thus, the timer in control logic 110 determines when approximately 50 microseconds have elapsed since the zero crossing event occurred.

[0016] Comparator 122 compares VREF to VFB. When the initial value of VFB falls below VREF or a timer expires (as determined by control logic 110), control logic 110 responds by initiating another pulse event to occur. When the LOOPRAW output of comparator 122 causes control logic 110 to initiate the next pulse event, the pulse event is not initiated by turning on the LSD FET. Instead, the pulse event begins by turning on the HSD FET. However, if a timer in the control logic expires before LOOPRAW is asserted, control logic 110 initiates the next pulse event by turning on the LSD FET. FIG. 2 shows that both pulse events 211 and 213 begin by turning on the LSD FET to discharge VOUT. Pulse events 211 and 213 are examples of three-phase pulse events in which the LSD FET is turned on, then the HSD FET is turned on, then the LSD FET is turned on again. If the initial LSD FET on phase is not implemented, the resulting pulse event is a two-phase pulse event in which the HSD FET is turned on first, followed by the LSD FET.

[0017] As mentioned above, the timer period is configured to be approximately equal to the period of a 20 KHz signal, which is generally considered the upper frequency range of human hearing. Therefore, the control logic 110 ensures that another pulse event will be initiated when VFB falls too low (below VREF), but to avoid an audio signal, the control logic 110 ensures that the pulse event occurs quickly enough to ensure that it occurs at a rate faster than 20 KHz and therefore above the audible frequency range.

[0018] However, FIG. 3 illustrates the stability problems associated with the out-of-audio PSM approach described above. As described above, some pulse events are three-phase pulse events (e.g., pulse event 301) that begin by turning on the LSD FET to partially discharge VOUT. There may be a minimum amount of on-time for the LSD FET. This minimum on-time may allow VOUT to discharge to a lower level than would otherwise be desired. If VOUT begins at a lower level during the phase in which both FETs are turned off, the next pulse event will be initiated by VREF falling below VREF (comparator 122) and will occur sooner than it would otherwise. Thus, it takes less time for VFB to fall below VREF than if VOUT had not first been over-discharged. This shorter inter-pulse event elapsed time is shown in FIG. 3 between pulse events 301 and 302 as time T31. Pulse event 302 is a two-phase pulse event and therefore does not begin with the VOUT discharge phase. As a result, VOUT is boosted to a higher voltage compared to when VOUT is first discharged by turning on the LSD FET. The next pulse event 303 is another three-phase pulse event initiated by the control logic 110 due to its internal timer (e.g., 50 microseconds) expiring before VFB reaches VREF. Therefore, the elapsed time (T32) between pulse events 302 and 303 is greater than T31. In some cases, such as shown in FIG. 3, the control logic 110 alternates between three-phase pulse events (e.g., pulse events 301 and 303) and two-phase pulse events (e.g., pulse event 302). As a result, the pulse events do not occur at a periodic rate. Although the converter reduces switching noise in the audible frequency range, it is unstable in this state.

[0019] FIG. 4 is a circuit diagram of an example buck converter 400 that addresses the above-mentioned problems, being an out-of-band converter that does not have the instability problems of the buck converter 100. In this example, the buck converter 400 includes an HSD FET coupled to an LSD FET between VIN and ground. One terminal of an inductor L1 is coupled to a switch node (SW), and the other inductor terminal provides a regulated output voltage (VOUT) from the buck converter 400 and is also coupled to an output capacitor COUT. A load 125 may be coupled to the inductor L1 to receive VOUT from the converter. A control logic 410 controls the on and off states of the HSD and LSD FETs, thereby generating a square wave on the SW node with a particular duty cycle. The control logic 410 is different from the control logic 110 of FIG. 1 (described below).

[0020] A ZC comparator 420 is also included, but as will be described below, the ZC comparator 420 differs from the ZC comparator 120 of Figure 1. The ZC comparator 420 outputs a signal SN SNS is compared to an internally generated reference signal of ZC comparator 420 to determine when the inductor current reaches 0 amperes. SNS is from the current sense circuit 119. A resistor divider formed by R1 in series with R2 provides a feedback voltage (VFB) that is proportional to VOUT. Comparator 122 compares VFB to a reference (VREF) and generates a LOOPRAW signal to control logic 410 that indicates VOUT has fallen below a threshold level.

[0021] The control logic 410 includes a PWM circuit 412, a timeout circuit 414, and a counter circuit 416. The output signal from the counter circuit 416 is a ZC control signal 450 that is provided to a control input 421 of a ZC comparator 420. As will be described below, the ZC control signal 450 controls the ZC comparator 420 to generate a SW The ZC comparator 120 adjusts the reference signal for comparison with the SNS. In Figure 4, SNS is compared to a fixed reference (ground), whereas SW The reference signal to which the SNS signal is compared can be dynamically adjusted by control logic 410. Having fine control over the magnitude of the reference signal in ZC comparator 420 helps to eliminate problems caused by the minimum on-time of the LSD FET, thereby helping to avoid the instability problems mentioned above.

[0022] The PWM circuit 412 of the control logic 410 generates an HSON signal 411 to the driver 102. In response to the logic state of the HSON signal 411, the driver 102 generates the appropriate voltage to turn the HSD FET on or off. Similarly, the control logic 410 generates an LSON signal 412 to cause the driver 102 to generate the appropriate voltage to turn the LSD FET on or off. The HSON signal 411 is also coupled to a timeout circuit 414. The output of the timeout circuit 414 is coupled to a counter circuit 416 and provides a TIMEOUT signal 415 to the counter circuit 416. The timeout circuit 414 generates the TIMEOUT signal 415 after a fixed period of time after the PWM circuit 412 turns the HSD FET off. After the fixed period of time, the period of time is approximately the length of the period of the 20 KHz signal (e.g., approximately 50 microseconds). When the PWM circuit 412 controls the HSON 411 to turn on the HSD FET, the counter 416 increments its output count value (ZC CTL 450) if the TIMEOUT signal 415 indicates the expiration of the timeout circuit's time period (e.g., 50 microseconds). In other words, if more than 50 microseconds (or whatever time is set in the timeout circuit 414) have elapsed since the last pulse event by the time the PWM circuit 412 determines it is time for the next pulse event, the counter 416 increments its count value. If less than 50 microseconds (or whatever time is set in the timeout circuit 414) have elapsed since the last pulse event by the time the PWM circuit 412 determines it is time for the next pulse event, the counter 416 decrements its count value. The output count value from the counter 416 is the ZC CTL 450, which in one example is an m-bit binary value (m is 1 or greater). In one example, m is 2, therefore ZC CTL 450 is a 2-bit binary value.

[0023] 5 is a schematic diagram of the timeout circuit 414, counter 416, and ZC comparator 420. The timeout circuit 414 in this example includes a NOR gate 502, an AND gate 504, and one or more cascaded flip-flops 506, 508. Each flip-flop has a Q output and a Qbar (logical inverse of Q) output. The flip-flops are cascaded with the Qbar output of one flip-flop coupled to the clock input of the next flip-flop in the chain. The Qbar output of each flip-flop is also coupled to its data (D) input. Each flip-flop also has an active-low enable input. First, the flip-flops are disabled, which causes their Q output to be 0 and their Qbar output to be 1. Each Qbar output is coupled to a respective D input, so that when the flip-flop is disabled, a logic 1 is present at the D input of each flip-flop. A logic 1 on the D input of a flip-flop propagates to its Q output when the respective flip-flop is enabled and then clocked.

[0024] The output of NOR gate 502 is coupled to the clock input of the first flip-flop in the chain flip-flop 506 in this example. The output of AND gate 504 is coupled to the enable inputs of flip-flops 506, 508. A clock (CLK) is provided to one input of NOR gate 502. In one example, CLK has a frequency in the range of 250 KHz to 2 MHz. The Q output of the last flip-flop in the chain (flip-flop 508 in this example) provides the TIMEOUT signal 415. The TIMEOUT signal 415 is provided to the other input of NOR gate 502. One input of AND gate 504 receives an enable (EN) signal (active low) and the other input of AND gate 504 receives an HSD_OFF signal. In this example, the HSD_OFF signal is asserted low when the HSD_FET is off, otherwise HSD_OFF is high. In one example, PWM circuit 412 generates the EN and HSD_OFF signals.

[0025] The timeout circuit 414 is enabled and starts counting pulses of CLK when EN and HSD_OFF are asserted low by the PWM circuit 412. Initially, TIMEOUT 415 is low, so the output of NOR gate 502 toggles between high and low logic levels inversely related to the high and low assertions of CLK. Thus, the falling edge of CLK causes flip-flop 506 to change state. The frequency of CLK and the number of flip-flops are application specific to measure a defined period of time (e.g., 50 microseconds). The cascaded arrangement of flip-flops 506, 508 is a multi-stage timer. The first flip-flop 506 is clocked by the output signal from NOR gate 502. TIMEOUT is initially 0, so the output of NOR gate 502 to the clock input of the first flip-flop 506 has a rising edge upon the falling edge of CLK. Because the D input of flip-flop 506 is a logic 1 (because Qbar is initially a logic 1), when it is clocked, the Q output of the first flip-flop 506 becomes a logic 1 and the Qbar output of the first flip-flop 506 becomes a logic 0. The Qbar output of flip-flop 506 is provided to the D input of the first flip-flop. On the next falling edge of CLK, the first flip-flop 506 is clocked again, this time causing the Q output of the first flip-flop 506 to become a 0 and its Qbar to become a 1.

[0026] This rising edge of Qbar of flip-flop 506 then clocks the next flip-flop in the chain, thereby forcing the Q output of the second flip-flop to a logic 1 state. The Qbar output of the second flip-flop becomes a logic 0 and is clocked through the D input of the second flip-flop as the Qbar output of the first flip-flop again changes from 0 to 1. The frequency of the Q output of the second flip-flop is therefore 1 / 2 the frequency of the Q output of the first flip-flop 506. This process continues until the last flip-flop in the chain asserts TIMEOUT 415 on its Q output to a logic 1 state. The Q output of each flip-flop in the chain is 1 / 2 the frequency of the Q output of the preceding flip-flop. When TIMEOUT 415 is asserted high by the last flip-flop in the chain, the output of NOR gate 502 is frozen at a logic low level, thereby stopping the chain of flip-flops from continuing to change states and freezing TIMEOUT 415 at a logic high level.

[0027] The counter circuit 416 includes an AND gate 518 and an up / down counter 520. The up / down counter has an input (IN), a clock input, and an output. The count value output from the up / down counter 520 is an m-bit ZC CTL signal. On every rising edge of its clock input (which is the output from AND gate 518), up / down counter 520 increments its output count value if TIMEOUT 415 is 1, or decrements its output count value if TIMEOUT 415 is 0. The input signals to AND gate 518 are HSON 411 and a blanking signal (BLANK) 517 (BLANK 517 is inverted as an input to AND gate 518). Assuming BLANK 517 is a logic low, upon a low-to-high transition of HSON 411, up / down counter 520 will count ZC 411 in response to TIMEOUT 415 being high or low, respectively. When BLANK 517 is logic high, the up / down counter 520 increments or decrements its output count value ZC CTL is prevented from incrementing or decrementing. Thus, BLANK 517 and AND gate 518 act to gate off HSON 411, preventing up / down counter 520 from counting. This function serves the purpose of hysteresis, described below.

[0028] Assuming BLANK 517 is low, when HSON 411 is asserted high to turn on the HSD FET, up / down counter 520 increments its count value upon receiving a high assertion of TIMEOUT signal 415. This condition means that the amount of time that has elapsed since the occurrence of the previous pulse event to the next pulse event has exceeded the time period set in timeout circuit 414, which means that the frequency of the pulses is less than, for example, 20 KHz. Conversely, when HSON 411 is asserted high to turn on the HSD FET, up / down counter 520 decrements its count value upon receiving a low assertion of TIMEOUT signal 415. This condition means that the amount of time that has elapsed since the occurrence of the previous pulse event to the next pulse event is less than the time period set in timeout circuit 414, which means that the frequency of the pulses is greater than, for example, 20 KHz.

[0029] Because counter 520 is an up-down counter, the counter output may increment and decrement too quickly on edge conditions such as TIMEOUT being high one cycle, low the next cycle, then high the next cycle. Using BLANK 517 to prevent counter 520 from changing its count value advantageously introduces hysteresis into the converter. Figure 6, described below, provides an example implementation for the generation of BLANK 517.

[0030] Continuing to refer to FIG. 5, the ZC comparator 420 includes a comparator 530, one or more current sources 531 and 532, switches SW1 and SW2 for each respective current source, and a resistor R3. Although two current sources are shown in this example, in other implementations there may be more than two current sources. In the example of FIG. 5, the current sources are binary weighted. Current source 531 generates a unit current (I1), current source 532 generates a current that is twice the unit current (2×I1). A third current source (if included) generates a current that is four times the unit current (4×I1), and so on. Each of the bits of the ZC CTL 450 is coupled to one of the switches. For example, bit 0 of the ZC CTL 450 is coupled to SW1 (associated with unit current source 531) and bit 1 is coupled to SW2. Therefore, the binary value of ZC CTL 450 controls which switch in ZC comparator 420 is open or closed. When SW1 is closed, a unitary current I1 from current source 531 flows through resistor R3. When SW2 is closed, a 2×I1 current from current source 532 flows through resistor R3. When both switches are closed, a current of 3×I1 flows through resistor R3. With two binary weighted current sources 531 and 532, four possible current values ​​are possible through resistor R3: zero current (zero crossing threshold is zero), I1, 2×I1, and 3×I1. Additional levels of current are possible with additional binary weighted current sources. The voltage developed across resistor R3 is the IL current sense signal (SW SNS) is a reference voltage PREF, which is compared by comparator 530.

[0031] Although the ZC comparator 420 is called a "zero crossing" comparator, the reference signal is configurable, so that the ZC comparator 420 is SNS is compared to a configurable reference signal (not necessarily equal to 0 volts). Thus, ZC comparator 420 has a configurable reference value that is controlled by ZC CTL 450 from counter circuit 416. If TIMEOUT 415 is asserted high when HSON 411 is asserted high (and BLANK is high), counter 520 increments (up or down) the binary value of ZC CTL to change the configuration of switches SW1 and SW2 in ZC comparator 420, thereby increasing the value of SW SNS increases the magnitude of the reference signal (PREF) against which it is compared. If TIMEOUT 415 is still logic low when HSON 411 is asserted high (and BLANK is high), then counter 520 does not change the value of ZC CTL 450, and therefore the voltage magnitude of the PREF reference signal remains unchanged.

[0032] FIG. 6 is a specific example of a timeout circuit 414 that includes three flip-flops 606, 607, 608, and therefore includes a three-stage timer. FIG. 7 is a corresponding timing diagram. In this example, the frequency of CLK is 250 KHz. The signal from the Q output of flip-flop 606 is labeled Q1. The signal from the Q output of flip-flop 607 is labeled Q2. The signal from the Q output of flip-flop 608 is TIMEOUT 415. As shown in FIG. 7, Q1 changes from 0 to 1 at 701 in response to the falling edge of CLK. Q1 changes back to 0 at the next falling edge of CLK, as shown at 702. Q2 changes from 0 to 1 at 703 in response to the falling edge of Q1, 702. Q2 changes back to 0 during the next falling edge of Q1, as shown at 704. The TIMEOUT signal 415 is asserted high at 705 in response to the falling edge of Q2, 704.

[0033] The timeout circuit 414 in this example also includes an AND gate 610 to generate BLANK. Three signals are coupled to respective inputs of the AND gate 610. One signal is CLK. The second signal is Q1, and the third signal is Q2. The BLANK signal in this example is asserted by the AND gate 610 when both the first two flip-flops 606 and 607 are clocked and upon the next high assertion of CLK. Therefore, BLANK is asserted high before TIMEOUT 415 is asserted high. When BLANK is asserted high, the counter 520 (FIG. 5) is prevented from advancing its count value. In one example, BLANK prevents the up / down counter 520 from counting within a relatively short period of time before the expiration of the full time period of the timeout circuit (e.g., 50 microseconds) to introduce hysteresis. In one example, BLANK is asserted high for 5-10 microseconds before TIMEOUT is asserted high. The PREF reference signal is not allowed to change once BLANK is asserted high.

[0034] FIG. 8 shows example waveforms illustrating the operation of the buck converter 400. The waveforms include 801-804. Waveform 801 is the inductor current IL. Waveform 802 illustrates the load current (current into the load 125). The load current waveform 802 illustrates a heavier load condition (albeit a light load at about 15 mA) and a lighter load condition 811 (about 8 mA). Waveform 803 represents the switching frequency of the converter. Waveform 804 represents the ZC CTL signal 450, which advances its value every cycle (807) until the switching frequency exceeds 20 KHz and settles at about 21.75 KHz (above the range of human hearing), as shown at 805. Each time the value of ZC CTL advances, a PG The GND reference signal further increases, which causes the reference comparison signal for the ZC comparator 420 to change.

[0035] Once the target frequency is reached, the ZC CTL advance stops and the switching frequency remains at approximately 21.75 KHz. Upon moving to a lighter load condition 811, the switching frequency drops sharply at 806, but the control logic 410 continues to increase the PG The ZC CTL value is again advanced (807) to further reduce the magnitude of the GND reference signal. The switching frequency is responded to by increasing (809) back to approximately 21.75 KHz.

[0036] At 820, the load current increases, which causes the switching frequency to increase, as shown at 821. Counter 520 responds by decrementing the value of ZC CTL, as described above. ZC comparator 420 responds by increasing the magnitude of its PG GND reference signal, resulting in a decrease in the switching frequency (813).

[0037] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (A) in a first example, device A is coupled to device B by a direct connection, where device A generates a signal that controls device B to perform an action, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, and device B is controlled by device A via a control signal generated by device A.

[0038] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that task or function by a manufacturer at the time of manufacture, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the configuration and / or layout of hardware components, via the device's interconnections, or via a combination thereof.

[0039] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or the termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0040] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0041] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-type metal oxide silicon field effect transistor ("MOSFET") may be substituted for an n-type MOS FET with little or no modification to the circuit. Also, other types of transistors may be used, such as bipolar junction transistors (BJTs).

[0042] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0043] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of this description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Modifications may be made to the exemplary embodiments described and other embodiments are possible that are within the scope of the present claims.

[0044] Modifications may be made to the illustrative embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. A circuit comprising: a control circuit having an input, a pulse width modulation (PWM) circuit having an output; a logic circuit having an input coupled to the output of the PWM circuit and an output; a counter circuit having an input coupled to the output of the logic circuit and an output; the control circuit including: a comparator circuit having a reference input coupled to an output of said counter circuit and an output coupled to an input of said control circuit; The circuit includes:

2. The circuit of claim 1, The circuit further includes a high-side transistor having a control terminal coupled to an output of the PWM circuit.

3. The circuit according to claim 2, The circuit further includes a current sensor having a first terminal coupled to the first current terminal of the high-side transistor and a second terminal coupled to the second input of the comparator circuit.

4. A circuit according to claim 1, The counter circuit comprises an up / down counter.

5. The circuit of claim 1, the logic circuit is configured to assert a timeout signal at an output of the logic circuit in response to the expiration of a period of time following the PWM circuit asserting a control signal to turn off a first transistor.

6. The circuit of claim 5, The circuit, wherein the logic circuit includes a multi-stage timer.

7. The circuit of claim 5, The counter circuit receiving the time-out signal on an input of the counter circuit; In response to assertion of the control signal, selectively incrementing an output count value on an output of the counter circuit in response to the timeout signal having a first logic state; selectively decreasing the output count value on the output of the counter circuit in response to the timeout signal having a second logic state; A circuit configured as follows.

8. The circuit of claim 1, The circuit, wherein the comparator circuit is configured to adjust a reference signal at the reference input in response to a value at the output of the counter circuit.

9. The circuit of claim 1, the comparator circuit a comparator having said reference input; a first current source; a first switch having a control terminal coupled to an output of the counter circuit, the first switch being configured to couple the first current source to the reference input; a second current source; and a second switch having a control terminal coupled to an output of the counter circuit, the second switch being configured to couple the second current source to the reference input; The circuit includes:

10. The circuit of claim 9, the first switch is further configured to operate in response to a first bit of a value at the output of the counter circuit; The circuit, wherein the second switch is further configured to operate in response to a second bit of a value at the output of the counter circuit.

11. The circuit of claim 9, The circuit, wherein the first and second switches are further configured to close separately or together in response to the value of a signal at the output of the counter circuit.

12. A system comprising: a driver circuit having a first input and a second input; a control circuit having an input, a gate control circuit having a first output coupled to a first input of the driver circuit and a second output coupled to a second input of the driver circuit; a timer circuit element having an input coupled to a first output of the gate control circuit, a first output, and a second output, the timer circuit element configured to provide a first control signal to the first output and a blanking control signal to the second output; a logic circuit having an input coupled to the first output of the timer circuit element and an output; the control circuit including: a comparator circuit having a reference input coupled to an output of the logic circuit and an output coupled to an input of the control circuit, the comparator circuit being configured to adjust a reference signal at the reference input in response to a signal at the output of the logic circuit; Including, the system.

13. The system of claim 12, the logic circuit includes a counter circuit having a first input coupled to a first output of the timer circuit element, a second input coupled to a second output of the timer circuit element, and an output coupled to a reference input of the comparator circuit.

14. The system of claim 13, The counter circuit an up / down counter having a first input coupled to a first output of said timer circuitry, a clock input, and an output coupled to a reference input of said comparator circuit; a logic gate having a first input coupled to a first output of said gate control circuit, a second input coupled to a second output of said timer circuitry, and an output coupled to a clock input of said up / down counter; Including, the system.

15. The system of claim 14, the up / down counter is configured to prevent counting in response to a first logic state of the blanking control signal, and the up / down counter is responsive to a transition in the first control signal for a second logic state of the blanking control signal.

16. The system of claim 12, The system wherein the gate control circuit includes a pulse width modulation (PWM) circuit.

17. The system of claim 13, The system wherein the timer circuitry includes a multi-stage timer.

18. The system of claim 12, the comparator circuit a comparator having said reference input; a first switch; a first current source coupled in series with the first switch between a voltage supply terminal and a reference input of the comparator; a second switch; a second current source coupled in series with the second switch between the voltage supply terminal and a reference input of the comparator; Including, the system.

19. The system of claim 13, the timer circuitry is further configured to generate the first control signal in response to the expiration of a period of time following the gate control circuit asserting a control signal to turn off a high-side transistor.

20. The system of claim 19, The time period is about 50 microseconds or less.

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