Magnetoresistive memory device

Abstract

The present invention relates to a magnetoresistive memory device (100) including a memory array (10) including at least one bit line (BL) and at least one source line (SL, SLB), each of which provides a magnetic tunnel junction (2) for selectively connecting the bit line (BL) and associated with a plurality of memory cells (1), each of which includes at least one selection transistor (RT). The memory array also includes peripheral blocks configured to apply a first voltage (Vread) higher than a ground voltage (Vss) to the bit lines (BL) and to apply a second voltage (VSL) higher than the first voltage (Vread) to at least one source line (SL, SLB). The state stored in the selected cell (1) is detected by sensing a current flowing in the bit line (BL) using a sense amplifier (SA) associated with at least one bit line (BL) in the peripheral block.

Description

[Technical field]

[0001] The present invention relates to magnetoresistive memory devices. [Background technology]

[0002] Typically, a magnetoresistive memory cell of a magnetic memory device includes a magnetic tunnel junction structure 2 including a thin dielectric layer 2a sandwiched between a ferromagnetic free layer 2b and a ferromagnetic pinned layer 2c. The dielectric layer 2a forms a tunnel barrier layer between the pinned layer 2c and the free layer 2b. The magnetization orientation of the ferromagnetic pinned layer 2c is fixed, for example, perpendicular to the substrate. The magnetization orientation of the free layer 2b is switchable in the perpendicular axis to one of parallel or anti-parallel states with respect to the magnetization orientation of the pinned layer 2b. The free layer can include a material selected from the list of Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd, or other suitable ferromagnetic materials. The pinned layer 2c can include a material selected from the list of Fe, Co, Ni, FeCo, CoNi, CoFEB, FeB, FePt, FePd, or other suitable ferromagnetic materials. Finally, the dielectric layer 2a may include MgO, Al2O3, or other suitable dielectric material.

[0003] The resistance between the pinned layer 2c and the free layer 2b depends on the actual state of the magnetization orientation of the free layer. When the free layer 2b and the pinned layer 2c have parallel magnetizations, the magnetic tunnel junction exhibits a relatively lower electrical resistance, and with antiparallel magnetizations, the magnetic tunnel junction exhibits a relatively higher electrical resistance. Thus, the switchable relative magnetization orientation of the free layer 2b defines two states of the memory cell 1, which respectively represent the "0" and "1" values ​​of an information bit.

[0004] In a read operation according to the current state of the art, a select signal turns on the read transistor, passing a read current through the magnetic tunnel junction 2. By sensing this read current, it is possible to identify the electrical resistance of the magnetic tunnel junction, which, as described above, depends on the relative orientations of the magnetizations of the fixed and free layers 2c and 2b, and thus the state stored in the memory cell.

[0005] 1a to 1c illustrate the read operation of such a magnetoresistive memory cell according to various well-known configurations. In FIG. 1a, a bit line BL is connected to a first side of a magnetic tunnel junction (MTJ) 2 of a spin-orbit torque (SOT) memory cell. In this regard, the MTJ 2 is on a SOT layer as is well known in the art. The MTJ is also arranged between two source lines SL and SLB, which are selectively connected to a second side of the MTJ opposite the first side through respective select transistors RT. These two select transistors RT are controlled through their respective gates through a select line WL. The select transistors (here NMOS transistors) have their respective sources S connected to source lines SL, SLB and their drains D connected to one side of the MTJ 2. For the avoidance of doubt, it is recalled here that for an NMOS transistor, the source is defined as the electrode receiving the lowest potential (of the two electrodes located on each side of the channel) and the drain is defined as the electrode receiving the highest potential. To read the state stored in the MTJ 2, the select line WL is set to connect the two source lines SL, SLB to the second side of the MTJ 2. A read voltage Vread is applied to the bit line BL and thus to the first side of MTJ2. The two source lines SL, SLB are set to ground. With the transistors polarized in this way, a read current flows from the bit line BL through the MTJ to each of the source lines SL, SLB. As explained above, this read current is sensed to determine the state stored in MTJ2.

[0006] FIG. 1b shows another conventional configuration of memory cells including a SOT memory cell including MTJ2 during a read operation. In this configuration, a source line SL is selectively connected to a first side of the magnetic tunnel junction 2 through a single select transistor RT. The select transistor RT is controlled through a first select line WL connected to its gate. The select transistor RT has its drain D connected to the side of MTJ2 and its source S connected to a source line BL. The second side of MTJ2 is connected to a bit line BL. The source line SL is further selectively connected to a second side of the MTJ through a write select transistor WT whose state is determined by a second select line WL'. During a read operation, the first select line WL is set to close the read select transistor RT and the second select line WL' is set to open the write select transistor WT. A read voltage Vread is applied to the bit line BL and thus to the second side of MTJ2. The source line SL is set to ground. As a result, a read current flows from the bit line BL to the source line SL through MTJ2. As explained above, this read current is sensed to determine the state stored in MTJ2.

[0007] FIG. 1c shows a further conventional configuration of a memory cell during a read operation, this time involving a spin transfer torque (STT) memory cell including a MTJ2. In this configuration, a source line SL is selectively connected to a first side of the magnetic tunnel junction 2 through a select transistor RT. The select transistor RT is controlled to be open or closed through a select line WL connected to its gate. The second side of the MTJ2 is connected to a bit line BL. The select transistor has its source connected to the source line SL and its drain connected to one side of the MTJ2. During a read operation, the select line is set to close the select transistor RT. A read voltage Vread is applied to the bit line BL and thus to the first side of the MTJ2. The source line SL is set to ground. As a result, a read current flows through the MTJ2 from the bit line BL to the source line SL. As explained above, this read current is sensed to determine the state stored in the MTJ2.

[0008] FIG. 1d illustrates the polarization state of the select transistor RT during a read operation in the various prior art configurations shown in FIGS. 1a to 1c.

[0009] In a conventional magnetoresistive memory device, memory cells are arranged in an array, with a number of memory cells arranged along a single bit line that runs across one direction of the array to define a column of memory cells. A memory cell in a column that is to be read is connected to the bit line BL by setting a select line WL high, i.e., closing a select transistor RT. The other memory cells in the column are disconnected from the bit line BL by setting the select line WL low.

[0010] By way of illustration, FIG. 2 illustrates such a column of memory cells according to the configuration of FIG. 1a.

[0011] In all configurations depicted in Figures 1a to 1c, the read voltage Vread applied to the bit line BL must be kept relatively low to remain below the breakdown voltage of the junction, and the magnitude of the read current Ion flowing across the MTJ2 must be limited below the write current threshold of this MTJ2. The read current Ion flowing through the selected memory cell is supplemented by a leakage current Ioff flowing through each of the unselected memory cells in the column. Generally, the number of unselected memory cells in a column is significant, exceeding 100, and the read current Ion of a single selected memory cell is necessarily limited, which may make it difficult to distinguish the actual state of this selected memory cell from the current sensing of the source lines SL, SLB.

[0012] It is noted that the ratio Ion / Ioff of the selection transistor RT depends on the source-drain voltage Vds of that transistor. The lower the source-drain voltage Vds, the lower this ratio. In the present application, this voltage corresponds to the read voltage Vread, which must be limited in order to control the read current below the threshold of the write current of the MTJ. Furthermore, limiting the read voltage is generally favorable to favor the tunnel magnetoresistance effect of the MTJ2 and to improve the reliability of the read operation by providing a better resistance difference between the parallel and antiparallel states of the MTJ2. As a result, in the current state-of-the-art memory arrays, the Ion / Ioff ratio is relatively low. In such current state-of-the-art memory arrays, the accumulated leakage current from unselected memory cells can be of the same order of magnitude (or even exceed) the read current Ion flowing in the selected memory cell. Also, the leakage current increases with temperature, so that even if the number of memory cells associated with a bit line is limited, the accumulation of the leakage current Ioff can mask the read current Ion and affect the reliability of the read operation.

[0013] For example, simulation results showed that in the configuration shown in FIG. 1a, where the select transistor RT is an NMOS transistor, the read current Ion could reach 10 microamperes, but the leakage current Ioff could reach 332 nA, thus resulting in an Ion / Ioff ratio of about 30.

[0014] In a particular configuration such as that shown in FIG. 1a or 1c, the select transistor RT also drives a write current for writing to a given cell in the MTJ2. This write current exhibits a relatively high magnitude, on the order of 100 microamperes or more in the case of SOT, and the dimensions of the select transistor RT must be set to allow driving such a current in a write operation while having a size as small as possible to keep the memory array within reasonable dimensions. This makes it attractive to design the select transistor RT with a relatively small threshold voltage, which allows more current to flow through the transistor with all other dimensional parameters and polarization being the same. However, a relatively lower threshold voltage tends to result in a relatively higher level of leakage current.

[0015] As a result, known magnetoresistive memory arrays and memory cells exhibit relatively poor reliability (particularly limited read margins) and relatively high power consumption. Summary of the Invention [Problem to be solved by the invention]

[0016] Large scale integration of magnetoresistive memory devices requires improvements to the configurations proposed in the current state of the art outlined above. Generally speaking, the invention aims to propose a method for reading the state stored in selected cells of a magnetoresistive memory array, which is more reliable than the prior art methods. The invention also aims to propose a memory device arranged to implement such a method. A memory device according to the invention may exhibit reduced power consumption and / or reduced dimensions when compared to memory devices according to the current state of the art. [Means for solving the problem]

[0017] To this effect, the present invention relates to a method for reading a state stored in a selected memory cell of a magnetoresistive memory device, the magnetoresistive memory device comprising: a memory array including a plurality of memory cells, at least one bit line associated with each of the plurality of memory cells, and at least one source line associated with each of the plurality of memory cells, each memory cell providing a magnetic tunnel junction associated with at least one select transistor selectively connecting the at least one bit line, the magnetic tunnel junction, and the at least one source line to define a read path, the select transistor including a source connected to the bit line via the magnetic tunnel junction, and a drain connected to the source line; a peripheral block including a sense amplifier associated with at least one bit line for determining a read current flowing along a read path; Includes:

[0018] According to the present invention, the method comprises the steps of: applying a first voltage to the bit lines, the first voltage being higher than a ground voltage, and applying a second voltage to at least one source line, the second voltage being higher than the first voltage; applying a read current to a read path from at least one source line to a bit line; sensing a current through a bit line to detect a state stored in a selected cell; Includes:

[0019] According to a non-limiting feature of the method, the second voltage is a power supply voltage of the memory device. Conveniently, the selection transistor is an NMOS transistor. Conveniently, the method also includes applying a gate voltage to the gate of the selection transistor, the gate voltage being selected to limit the voltage applied across the magnetic tunnel junction.

[0020] According to another aspect, the present invention relates to a method for polarizing select transistors associated with a plurality of unselected memory cells of a memory array of a memory device, each memory cell of the memory array including a magnetic tunnel junction, the method including applying a first voltage to a source of the select transistor, the first voltage being higher than a ground voltage, and applying a second voltage to a drain of the select transistor, the second voltage being higher than the first voltage (Vread).

[0021] According to a further aspect, the present invention provides a method for producing a method for treating a pulmonary circulation comprising the steps of: a memory array including a plurality of memory cells, at least one bit line associated with each of the plurality of memory cells, and at least one source line associated with each of the plurality of memory cells, each memory cell providing a magnetic tunnel junction associated with at least one select transistor selectively connecting the at least one bit line, the magnetic tunnel junction, and the at least one source line to define a read path, the select transistor including a source connected to the bit line via the magnetic tunnel junction, and a drain connected to the source line; A peripheral block, applying a first voltage to the bit lines, the first voltage being higher than a ground voltage, and applying a second voltage to at least one source line, the second voltage being higher than the first voltage; activating at least one select transistor of a selected memory cell to pass a read current through the read path from at least one source line to a bit line; and a peripheral block associated with at least one bit line and configured to sense the state stored in the selected cell by sensing a current through the bit line using a sense amplifier of the peripheral block; The present invention relates to a magnetoresistive memory device including:

[0022] According to a further non-limiting feature of the present invention, the select transistor is an NMOS transistor; the peripheral control block includes a multiplexer disposed between a plurality of bit lines of the memory array and the sense amplifier; the multiplexer includes a plurality of PMOS transistors each providing a source and respectively connected by their sources to a plurality of bit lines; Each PMOS transistor includes a gate connected to a control signal provided by a main control block, the control signal defining a first voltage on a bit line; either alone or in any technically feasible combination. [Brief description of the drawings]

[0023] Many other features and advantages of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings.

[0024] [Figure 1a] 1A-1C are diagrams illustrating polarization during a read operation of a magnetoresistive memory cell according to various known configurations. [Figure 1b] 1A-1C are diagrams illustrating polarization during a read operation of a magnetoresistive memory cell according to various known configurations. [Figure 1c]1A-1C are diagrams illustrating polarization during a read operation of a magnetoresistive memory cell according to various known configurations. [Figure 1d] 1A-1C are diagrams illustrating polarization during a read operation of a magnetoresistive memory cell according to various known configurations. [Diagram 2] FIG. 1b is an illustrative representation of a column of memory cells according to the configuration of FIG. 1a. [Diagram 3] FIG. 1 is a diagram illustrating a memory device according to the present invention. [Figure 4a] 1A-1C are diagrams illustrating polarization according to the present invention during a read operation of magnetoresistive memory cells according to various configurations; [Figure 4b] 1A-1C are diagrams illustrating polarization according to the present invention during a read operation of magnetoresistive memory cells according to various configurations; [Figure 4c] 1A-1C are diagrams illustrating polarization according to the present invention during a read operation of magnetoresistive memory cells according to various configurations; [Figure 4d] 1A-1C are diagrams illustrating polarization according to the present invention during a read operation of magnetoresistive memory cells according to various configurations; [Diagram 5] FIG. 3C is an illustrative representation of a column of memory cells according to the configuration of FIG. 3C. [Figure 6] FIG. 2 is a representation of a column control block according to one embodiment. [Figure 7] FIG. 2 is a diagrammatic representation of a sense amplifier according to one embodiment. [Figure 8] 2 is a flow chart illustrating a method according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] To keep the presentation simple, only elements relevant to the description of the invention have been included in the figures. A memory device benefiting from the proposed reading method may include further elements not included in the figures. In particular, in this disclosure, the method of writing a memory cell has not been described in detail, although the method operates according to the current state of the art.

[0026] Overview of magnetoresistive memory devices. FIG. 3 shows a magnetoresistive memory device 100 according to the present invention.

[0027] In this memory device 100, a number of memory cells 1, for example representing a configuration according to one of the configurations represented in FIGS. 4a to 4c, are provided in rows and columns to form a memory cell array 10.

[0028] Each memory cell 1 of the array 10 presents a magnetic tunnel junction 2. The magnetic tunnel junction of the memory cell 1 includes a magnetic free layer, the magnetization orientation of which defines the state of the memory cell 1. The characteristics of the memory cell 1 were recalled in the introductory part of the present application with reference to figures 1a to 1c and will not be repeated here for the sake of brevity, but these characteristics apply fully to the memory cells 1 of the memory array according to the invention. The memory cells may in particular be of the SOT or STT type.

[0029] The memory array 10 also includes bit lines BL and source lines SL disposed along each column of the memory cells 10. Select lines WL are disposed along each row of the memory cell array 10.

[0030] More specifically, in the magnetic memory array 10 according to the invention, a bit line BL and at least one source line SL, SLB are associated with a plurality of memory cells. Each memory cell provides a magnetic tunnel junction 2 and at least one select transistor RT selectively connecting the bit line BL, the magnetic tunnel junction 2 and the at least one source line SL, SLB to define a read path through the magnetic tunnel junction 2. The select transistor RT is controlled by select lines WL, WLR. Preferably, the select transistor is an NMOS transistor, which is generally smaller in size than a PMOS transistor.

[0031] The memory device 100 according to the invention also includes peripheral blocks that can be configured from a main control block 4, a row control block RCB, and a column control block CCB. The column control block CCB includes a source line driver and a bit line driver CCB_D that set voltages on the source lines SL, SLB, and bit lines BL, respectively. The column control block CCB also includes sense amplifiers that are connected (or connectable) to the respective bit lines BL to sense the current flowing in the respective bit lines BL. The row control block RCB includes a row driver RCB_D that sets voltages on the respective select lines WL, WLR, effectively selecting one of the memory cells of at least one column of the array in combination with the column control block CCB.

[0032] A row of memory cells (or multiple memory cells within a row) can be read collectively by activating corresponding select lines WL, WLR by row drivers RCB_D of row control block RCB so that a read current flows in the respective bit lines BL-source lines SL, and by activating bit lines BL and source lines SL, SLB by respective column drivers CCB_D of column control block CCB, as described in more detail below. Sense amplifiers in column control block CCB associated with the bit lines measure the read currents and determine the states stored in the respective memory cells. In certain embodiments, the sense amplifiers can be shared among multiple bit lines, for example through a multiplexer.

[0033] Typically, all column drivers CCB_D are activated simultaneously to read respective data from at least one memory cell of a selected row, although this conventional mode of operation is not required.

[0034] The peripheral block's main control block 4 coordinates read and write operations (not described in this disclosure). More specifically, the main control block 4 generates control signals for the drivers of the column driver CCB_D and row driver RCB_D to achieve the sequence of steps required to perform an intended read operation of a given row of cells. In the case where a bit line BL multiplexer is present, some control signals generated by the main control block can also be addressed to such a multiplexer to selectively connect sense amplifiers to selected bit lines BL of the memory array 10.

[0035] The control block 4 may be configured to implement a finite state machine or more generally to generate appropriate control signals, as will be described in more detail in the remainder of this disclosure. The input / output data can then be stored / retrieved from a magnetic memory device.

[0036] Method for reading a stored state in a selected memory cell - Patents.com In accordance with the present invention, and referring to FIG. 8, a method for reading the state of a selected memory cell of a memory device 100 includes: a first step S1 of applying a first voltage Vread to the bit lines, the first voltage Vread being higher than the ground voltage Vss, and a step S2 of applying a second voltage VSL to at least one source line, the second voltage VSL being higher than the first voltage Vread; Step S3 of passing a read current of a read path from the source line to the bit line; Step S4 of sensing a read current to detect the state stored in the selected cell; Includes:

[0037] Figures 4a to 4c are further illustrations of this method, in particular the polarization of the select transistor RT for the three memory cell configurations of Figures 1a to 1c described in the introductory part of this disclosure, the description of which is not reproduced here for the sake of brevity.

[0038] The source line SL (and the first and second source lines SL, SLB in FIG. 4a) can be shorted to the power supply voltage Vdd of the memory device 100, and the bit line BL is set to a first positive voltage Vread lower than the power supply voltage Vdd. However, the present invention is not limited to selecting the second voltage VSL to be the power supply Vdd, and more generally, the second voltage can be freely selected as long as it exceeds the first voltage Vread.

[0039] As a result, when a cell is selected using the select line WL by closing the select transistor RT, a read path is formed and current flows from the source line SL (from the first and second source lines SL, SLB in the configuration of Figure 4a) to the bit line BL through MTJ2.

[0040] This first voltage Vread is controlled with respect to a second voltage (Vdd in the illustrated example) such that the current Ion flowing through the read path is less than the write threshold voltage of this cell. Figure 5 illustrates this, but also shows a leakage current Ioff flowing through the unselected memory cells from the source lines SL, SLB to the bit line BL.

[0041] The state stored in a selected memory cell is detected by sensing the current flowing in a bit line BL using a sense amplifier in a column decoder block CCB connected to that bit line BL.

[0042] According to the invention and as illustrated in the diagrams of Figures 4a, 4b, 4c, 4d and 5, the select transistor RT, which is typically an NMOS transistor as described above, comprises a gate connected to a select line WL, a source connected to a bit line BL via MTJ2, and a drain connected to a source line SL. Thus, the polarization of the select transistor RT according to the invention is opposite to that of the select transistor RT according to the prior art.

[0043] The polarization of the selection transistor RT of the unselected memory cell according to the invention is particularly advantageous. A first voltage Vread applied to the source of the selection transistor RT is higher than the ground voltage, inducing a substrate bias effect in this transistor RT. As a result, the threshold voltage of the selection transistor RT polarized according to the invention is higher than the threshold voltage of the selection transistor RT polarized according to the state of the art. Also, for unselected memory cells, the gate of the selection transistor RT is set to the ground voltage, and the gate voltage Vgs with respect to the source is negative. As a result of these two aspects, the leakage current Ioff flowing through the unselected selection transistor RT is reduced without any change in the dimensions or configuration of the selection transistor. In addition, and importantly, the polarization of the selection transistor RT for the selected memory cell makes it possible to control the voltage applied to MTJ2 by ​​the voltage applied to the gate G through the selection line WL. The selection transistor RT during the read operation is in follower mode. This means that the voltage of the source is equal to the voltage applied to the gate shifted by the threshold voltage. Thus, in the configuration depicted in the figure, the voltage applied to the gate directly controls the voltage of MTJ2. The arrangement according to the invention prevents overvoltages that can degrade the MTJ by controlling the voltage on the select line WL.

[0044] In other words, the method for reading the state stored in a selected memory comprises applying a voltage to the gate G of the select transistor RT, this voltage being selected to limit the voltage applied across the magnetic tunnel junction 2.

[0045] Simulations have shown that, in the configurations and polarizations shown in Figures 4a to 4c, the NMOS select transistor RT can exhibit a read current Ion of 10 microamperes, a leakage current Ioff of 20 picoamperes, and thus an Ion / Ioff ratio of more than 500000. If we recall that in the configurations and polarizations of the prior art, this ratio was calculated to be about 30, which is almost 2000 times smaller for the same read current Ion.

[0046] As a result, the leakage current Ioff flowing through each unselected memory cell is significantly reduced and does not significantly mask the read current Ion flowing in the read path of the selected memory cell, even if all of these currents are summed in the bit line BL and the sense amplifier SA associated with the column of memory cells.

[0047] In other words, the present invention proposes an inventive polarization of a number of select transistors RT respectively associated with a number of unselected memory cells 1 in a cell string of a memory array 10. The method includes applying a first voltage Vread higher than a ground voltage Vss to the source of the select transistor RT, applying a ground voltage to the gate of the select transistor, and applying a second voltage VSL higher than the first voltage Vread to the drain of the select transistor RT. This approach reduces the leakage current of those unselected memory cells.

[0048] According to a particular advantageous embodiment represented in Fig. 6, the sense amplifiers SA of the column control block CCB are shared between several bit lines. The control block CCB contains a multiplexer MUX arranged between the memory array 10 and the sense amplifiers SA. The multiplexer MUX receives control signals MUXCTRL1...MUWCTRLn from the main control block which select the columns of the memory array, more precisely the bit lines BL, which are to be electrically connected to the inputs SA_IN of the sense amplifiers SA. The column control block CCB usually contains several multiplexers associated to several sense amplifiers so as to enable a simultaneous reading of several memory cells 1 from the memory array 10, which are arranged along the same row of the memory array 10.

[0049] Control signals MUXCTRL1...MUWCTRLn provided to the multiplexers MUX are sent to multiplexer transistors, typically PMOS transistors, each connected between a bit line BL and an input of a sense amplifier SA.

[0050] 6, the selected multiplexer transistor operates as a source follower, which means that the source of this transistor (connected to the bit line BL of the memory cell 1 to be read) is controlled to be equal to the voltage applied to its gate plus its threshold voltage. The multiplexer MUX not only makes it possible to select a selected column of cells 1 in the array 10, but also forms a bit line driver that applies a first voltage Vread to the bit line BL of the selected column.

[0051] FIG. 7 illustrates a possible sense amplifier SA circuit that accommodates the principles of the present disclosure, and in particular the relatively low voltage available at the sense amplifier input SA_IN, i.e., the drain of the multiplexer transistor.

[0052] The sense amplifier of Fig. 7 comprises two inputs, a first input SA_IN for receiving a read current I flowing on a bit line BL associated with the memory cell intended to be read, and a second input SA_REF for receiving a reference current I'. The reference current I' can be provided by a current flowing on a bit line BL associated with a reference memory cell. The sense amplifier SA of Fig. 7 also comprises an output SA_OUT providing the state of the read cell 1.

[0053] The sense amplifier SA consists of multiple current mirrors CM, which replicate the read current I and the reference current I' in parallel branches. In the output branch, the output of the sense amplifier SA_OUT is driven to the supply voltage VDD if the reference current I' is greater than the read current I, or to the ground voltage VSS if the read current I is greater than the reference current I'.

[0054] Those skilled in the art can understand and effect other variations to the disclosed embodiments from a study of the drawings, the disclosure, and the appended claims in practicing the claimed invention.

[0055] In particular, the proposed polarization of the select transistor can be applied to any memory cell configuration, for example not only configurations including a single bit line as shown in the figure, but also other configurations including multiple bit lines per cell.

Claims

1. A method for reading a state stored in a selected memory cell (1) of a magnetoresistive memory device (100), comprising: A memory array (10) including a plurality of memory cells (1), at least one bit line (BL) associated with each of the plurality of memory cells, and at least one source line (SL, SLB) associated with each of the plurality of memory cells, each memory cell (1) providing a magnetic tunnel junction (2) associated with at least one selection transistor (RT) for selectively connecting the at least one bit line (BL), the magnetic tunnel junction (2) and the at least one source line (SL, SLB) to define a read path, the selection transistor (RT) including a source connected to the bit line (BL) via the magnetic tunnel junction (2) and a drain connected to the source line (SL); a peripheral block (4, CCB, RCB) containing a sense amplifier (SA) associated with said at least one bit line (BL) for determining a read current flowing along said read path; The method includes: applying a first voltage (Vread) higher than a ground voltage to the bit line (BL) and a second voltage (VSL) higher than the first voltage (Vread) to the at least one source line (SL, SLB); A read current is applied to the read path from the at least one source line (SL, SLB) to the bit line (BL); detecting the state stored in the selected cell (1) by sensing the current through the bit line (BL); The method includes:

2. 2. The method of claim 1, wherein the second voltage is a power supply voltage (Vdd) of the memory device (100).

3. The method of claim 1 , wherein the select transistor is an NMOS transistor.

4. 4. The method of claim 1, wherein the method comprises applying a gate voltage to a gate of the select transistor, the gate voltage being selected to limit the voltage applied across the magnetic tunnel junction (2).

5. A magnetoresistive memory device (100), comprising: A memory array (10) including a plurality of memory cells (1), at least one bit line (BL) associated with each of the plurality of memory cells, and at least one source line (SL, SLB) associated with each of the plurality of memory cells, each memory cell (1) providing a magnetic tunnel junction (2) associated with at least one selection transistor (RT) for selectively connecting the at least one bit line (BL), the magnetic tunnel junction (2) and the at least one source line (SL, SLB) to define a read path, the selection transistor (RT) including a source connected to the bit line (BL) via the magnetic tunnel junction (2) and a drain connected to the source line (SL); A peripheral block, applying a first voltage (Vread) higher than a ground voltage (Vss) to the bit line (BL) and applying a second voltage (VSL) higher than the first voltage (Vread) to the at least one source line (SL, SLB); activating the at least one select transistor (RT) of a selected memory cell (1) to pass a read current through the read path from the at least one source line (SL, SLB) to the bit line (BL); and a peripheral block associated with the at least one bit line (BL) and configured to detect the state stored in the selected cell (1) by sensing the current flowing in the bit line (BL) using a sense amplifier (SA) of the peripheral block; A magnetoresistive memory device (100) comprising:

6. The magnetoresistive memory device (100) of claim 5, wherein the select transistor is an NMOS transistor.

7. The magnetoresistive memory device (100) of claim 5 or claim 6, wherein the peripheral control block includes a multiplexer (MUX) disposed between a plurality of bit lines (BL) of the memory array (10) and the sense amplifiers (SA).

8. The magnetoresistive memory device (100) of claim 7, wherein said multiplexer (MUX) comprises a plurality of PMOS transistors each providing a source and connected by their sources to said plurality of bit lines (BL), respectively.

9. 9. The magnetoresistive memory device (100) of claim 8, wherein each PMOS transistor includes a gate connected to a control signal provided by a main control block, said control signal defining said first voltage (Vread) on said bit line (BL).

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