Quantum Circuit Buffering

Abstract

One or more systems, devices, computer program products, or computer-implemented methods of use provided herein, or combinations thereof, relate to maximizing the use of a physical qubit layout of a quantum computer. The system may include a memory storing computer-executable components and a processor executing the computer-executable components stored in the memory, where the computer-executable components may include an identification component that identifies a quantum circuit, and a scheduler component that maps the quantum circuit to a physical qubit layout. In an embodiment, the scheduler component may combine multiple quantum circuits by including the quantum circuit in a composite circuit, and map the composite circuit to a physical qubit layout. In an embodiment, the acquisition component may assign the quantum circuit to a temporary storage bucket, and may identify whether the temporary storage bucket meets a threshold at which the scheduler component may begin analyzing the quantum circuit.

Description

[Technical field]

[0001] The present invention relates to quantum computing systems, and in particular to maximizing the use of the physical qubit layout of a quantum computer. [Background technology]

[0002] Quantum computing generally utilizes quantum mechanical phenomena to perform computational and information processing functions. Quantum computing can be viewed in contrast to classical computing, which typically uses transistors to operate on binary values. That is, while classical computers can operate on bit values ​​that are either 0 or 1, quantum computers can operate on quantum bits (qubits), which contain superpositions of both 0 and 1. Quantum computing has the potential to solve problems that are impossible or time-consuming to solve on classical computers due to their computational complexity.

[0003] At scale, a quantum computing cloud service provider may run millions of quantum jobs for its users over the course of a year. Each quantum job may involve the execution of one or more quantum programs on a physical logic circuit. The physical, real-world quantum logic circuit controlled by the quantum system may contain multiple qubits.

[0004] If a qubit state can only exist (or be coherent) for a limited amount of time, the purpose of the operation of a quantum logic circuit (e.g., including one or more qubits) can be to reduce the time of operation or to increase the speed of operation, or both. The time spent operating the quantum logic circuit can unnecessarily reduce the available time for operation on one or more qubits. This can be due to the coherence time of one or more qubits that can be used before decoherence of one or more qubits. For example, in one or more cases, the qubit state can be lost in less than 100-200 microseconds. Furthermore, operations on qubits typically introduce some error, such as some degree of decoherence and / or some degree of quantum noise, further impacting the availability of the qubits. Quantum noise refers to noise due to the discrete and / or stochastic nature of quantum interactions. Device designs that extend the lifetime of quantum states and extend the coherence time can be desirable.

[0005] Also, at large scale, the large number of quantum jobs may pressure each quantum program to execute quickly, i.e., increased execution speed may correlate directly or indirectly, or both, with maximizing system usage, minimizing users having to wait for measurement results, or minimizing unwanted consumption of classical computational resources, or a combination thereof. Summary of the Invention

[0006] The following presents a summary intended to provide a basic understanding of one or more embodiments described herein. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, or computer program product, or combination thereof, facilitates a process for maximizing the use of physical qubits of a real-world physical qubit layout of a quantum computer.

[0007] According to an embodiment, a system may include a memory that stores computer-executable components and a processor that executes the computer-executable components stored in the memory, where the computer-executable components may include an identification component that identifies a quantum circuit and a scheduler component that maps the quantum circuit to a physical qubit layout.

[0008] According to another embodiment, a computer-implemented method may include identifying, by a system operably coupled to a processor, a quantum circuit; and mapping, by the system, the quantum circuit to a physical circuit layout.

[0009] According to yet another embodiment, a computer program product that facilitates a process for buffering one or more quantum circuits may comprise a computer readable storage medium having program instructions embodied therein, the program instructions being executable by a processor to cause the processor to identify, by the processor, a quantum circuit and map, by the processor, the quantum circuit to a physical qubit layout.

[0010] An advantage of the foregoing systems, computer-implemented methods, or computer program products, or combinations thereof, can generally be an increase in the overall throughput of a quantum system employing such embodiments, as compared to the operation of one quantum program at a time. Indeed, the utilization of physical qubits can be increased both by increasing the number of qubits and by increasing the available coherence time utilized of one or more qubits in such a quantum system.

[0011] In one or more embodiments, an acquisition component can acquire quantum circuits and assign the quantum circuits to temporary storage buckets. In this manner, an overall organization system for the quantum circuits being manipulated can be employed.

[0012] In one or more embodiments, the acquisition component may identify whether the temporary storage buckets meet a threshold such that the scheduler component may begin analyzing the quantum circuits from the temporary storage buckets. In this manner, processing power associated with the quantum circuit mapping to the physical qubit layout may be limited to a state when a sufficient amount of quantum circuits have been identified, located, or acquired, or a combination thereof, to maximize use of the physical qubit layout. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate a process for buffering one or more quantum circuits in accordance with one or more embodiments described herein. [Diagram 2] FIG. 1 illustrates a block diagram of another example non-limiting system that can facilitate a process for buffering one or more quantum circuits in accordance with one or more embodiments described herein. [Diagram 3]FIG. 3 illustrates three general plots of basic uses of a physical qubit layout based on quantum circuit buffering performed by the non-limiting system of FIG. 2 in accordance with one or more embodiments described herein. [Figure 4] FIG. 1 illustrates a schematic diagram of an exemplary generation of a quantum circuit mapping in accordance with one or more embodiments described herein. [Diagram 5] FIG. 5 illustrates a process flow for facilitating quantum circuit buffering based on the schematic of FIG. 4 in accordance with one or more embodiments described herein. [Figure 6] FIG. 1 illustrates a process flow for facilitating the organization of a quantum circuit in accordance with one or more embodiments described herein. [Figure 7] FIG. 1 illustrates a process flow for facilitating buffering of one or more quantum circuits in accordance with one or more embodiments described herein. [Figure 8] FIG. 1 illustrates a block diagram of an example non-limiting operating environment that can facilitate one or more embodiments described herein. [Figure 9] FIG. 1 illustrates a block diagram of an exemplary non-limiting cloud computing environment in accordance with one or more embodiments described herein. [Figure 10] FIG. 2 illustrates a block diagram of an example non-limiting abstract model layer in accordance with one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The following detailed description is merely an example and is not intended to limit the embodiments, or the application and / or utilization of the embodiments. Furthermore, there is no intention to be bound by any express or implied information presented in the above "Summary of the Invention" section or "Description of the Preferred Embodiments" section. One or more embodiments are now described with reference to the drawings, in which like reference numerals are utilized to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various instances without these specific details.

[0015] As used herein, a quantum circuit can be a series of operations, such as gates, performed on a series of real-world physical qubits for the purpose of obtaining one or more qubit measurements. The operation of a quantum circuit can be facilitated by, for example, a waveform generator that generates one or more physical pulses, or other waveforms, or frequencies, or a combination thereof, to alter one or more states of one or more physical qubits. The altered states can be measured, and thus one or more computations are performed.

[0016] Different quantum circuits may require different resources. For example, one quantum circuit may use half of the total number of physical qubits in the quantum logic circuit of each quantum system. Another quantum circuit may use a different half, or even a different portion, of the available physical qubits of the same quantum system. That is, for physical qubit layouts of many qubits, typically 10 or more qubits, operation of one quantum circuit at a time may waste processing power, available qubits, or available qubit coherence, or a combination thereof. Fewer than all qubits may be used, leaving multiple qubits idle.

[0017] Because quantum processors and quantum systems are scarce and expensive resources, such waste may be underutilized and may have adverse effects on both users and administrators of the quantum system. In other words, each quantum processor may contain a fixed number of qubits that it supports, but the quantum circuits that may be performed on the fixed number of qubits may vary in complexity and size. If a quantum circuit does not use the full power of a quantum processor, one or more qubits may remain unused, and therefore it may be desirable to facilitate the process of buffering one or more quantum circuits.

[0018] This buffering may include collecting quantum circuits, mapping and / or remapping such quantum circuits onto the physical qubit layout of the quantum system, and executing such quantum circuits in a specified order, where one or more quantum circuits may be executed at least partially concurrently with one another. Furthermore, one or more such quantum circuits may be executed multiple times (e.g., multiple shots may be executed), and the shot of one quantum circuit being operated may overlap with the operation of one, two, or even more multiple other quantum circuits (or their shots) being operated on the same physical qubit layout.

[0019] The buffering decision may be based on one or more of several factors, including the proposed number of qubits to use, the number of shots to execute, the number of gates (e.g., swap gates) used, the execution time of the quantum circuit compared to the coherence time of the qubits used, the length / depth of the circuit, the time of the quantum circuit in the queue, hardware constraints, the level of the user entity or customer, or the like, or a combination thereof. That is, one or more thresholds may be used that are based on the quantum circuit, based on hold time, or based on the entity requesting the operation, or a combination thereof. One or more such thresholds may be used simultaneously, and the threshold criteria may be dynamically and selectively changed. In this way, the most efficient use of the quantum system may be effected while providing a quantified level of fairness to the user entity requesting use of the quantum system. Indeed, such balancing may be desirable in cases where the physical qubit layout exceeds 10 or more qubits, even including 1000 or more qubits.

[0020] Described herein are one or more embodiments of a system, computer-implemented method, or computer program product, or combination thereof, that can take into account one or more deficiencies of existing techniques for optimizing the execution of multiple quantum circuits on one or more quantum systems. Generally, one or more embodiments of a system, computer-implemented method, or computer program product, or combination thereof, that can facilitate a process of buffering (e.g., acquiring, analyzing, or mapping, or a combination thereof) one or more quantum circuits against one or more physical qubit layouts, are provided. Additionally, training of a model, such as a machine learning (ML) model, used to balance such operation of the quantum circuits after each iteration to continually improve upon the use of the physical qubit layouts according to the requirements of the quantum program for the use of the quantum system having the physical qubit layouts may be facilitated.

[0021] One or more embodiments are now described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. As used herein, the terms "entity," "requesting entity," and "user entity" can refer to machines, devices, components, hardware, software, smart devices, or humans, or combinations thereof. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various instances without these specific details.

[0022] Additionally, the embodiments shown in one or more figures described herein are merely illustrative, and as such, the architecture of the embodiments is not limited to the systems, devices, and / or components shown herein, nor to any particular order, connection, or coupling of any of the systems, devices, and / or components shown herein. For example, in one or more embodiments, a non-limiting system described herein, such as non-limiting system 100 and / or 200 as shown in Figures 1 and 2 or both, can further comprise, be associated with, be coupled to, or be a combination of one or more computer and / or computation-based elements described herein with reference to an operating environment, such as the operating environment 800 shown in Figure 8. In one or more described embodiments, the computer and / or computation-based elements can be used in connection with implementing one or more of the systems, devices, components, and / or computer-implemented operations shown or described in connection with Figures 1 and / or 2 or other figures described herein.

[0023] Referring initially generally to Figure 1, one or more embodiments described herein may include one or more devices, systems, or apparatus, or combinations thereof, that may facilitate quantum circuit buffering. For example, Figure 1 illustrates a block diagram of an example non-limiting system 100 that may employ a scheduler component that, in one or more embodiments, may use an ML model to balance the execution of multiple quantum circuits against multiple physical, real-world qubits of one or more physical qubit layouts of one or more quantum systems.

[0024] 1, a block diagram of an exemplary non-limiting system 100 that can facilitate such processes in accordance with one or more embodiments described herein is shown. Although reference is made herein to one or more processes, facilitation, and / or uses of non-limiting system 100, the descriptions provided both above and below herein may also relate to one or more other non-limiting systems described herein, such as non-limiting system 200, described in detail below.

[0025] 1, a non-limiting system 100 can include a quantum circuit buffering system 102. The quantum circuit buffering system 102 can include one or more components, such as a memory 104, a processor 106, a bus 105, an identification component 112, or a scheduler component 116, or combinations thereof. Generally, the quantum circuit buffering system 102 can facilitate obtaining one or more quantum circuits 113 based on receiving one or more quantum job requests 124. A determination of which one or more quantum circuits 113 to map and / or remap to a physical qubit layout 119 can be made using one or more balancing processes.

[0026] The identification component 112 may receive, transfer, download, or otherwise obtain, or a combination thereof, the quantum circuit 113 in response to receiving a quantum job request 124 to operate the quantum circuit 113 on the quantum system 101. A copy of the quantum circuit 113 may be temporarily stored inside and / or outside the quantum circuit buffering system 102.

[0027] The scheduler component 116 may map and / or remap the quantum circuit to the physical qubit layout 119 based on one or more factors of the quantum circuit 113. As used herein, mapping may include adapting the quantum circuit to the actual physical qubit layout 119 used, such as identifying the same and / or different qubits (compared to the qubits identified in the quantum circuit), adding and / or merging gates, adding one or more swap gates, or the like, or a combination thereof. Remapping may include a secondary mapping process that changes mapping settings, which may exist in the form of metadata or the like, for the obtained quantum circuit 113. For example, the quantum circuit 113 may be initially designed and / or otherwise constructed to run on one physical qubit layout that is different from the physical qubit layout 119 used. The one or more factors may include the proposed number of qubits to use, the number of shots to perform, the number of gates (e.g., swap gates) used, the execution time of the quantum circuit compared to the coherence time of the qubits used, the length / depth of the circuit, the time of the quantum circuit in the queue, hardware constraints, the level of the user entity or customer, or the like, or any combination thereof.

[0028] One or more aspects of the components (e.g., the identification component 112 and / or the scheduler component 116) may be used separately or in combination, such as to use one or more of the memory or processor of a system including the components, thereby facilitating generation of the constraint variables and / or influence mappings 115. That is, these components may use the processor 106 and / or the memory 104. Additionally and / or alternatively, the processor 106 may execute one or more program instructions to cause the processor 106 to perform one or more operations by these components.

[0029] An advantage of the foregoing systems, computer-implemented methods, and / or computer program products is that the overall throughput of a quantum system employing such embodiments can be generally increased as compared to the operation of one quantum program at a time. Indeed, the utilization of physical qubits can be increased both by increasing the number of qubits and by increasing the available coherence time utilized of one or more qubits in such a quantum system.

[0030] Referring now to FIG. 2, this figure illustrates a diagram of an example non-limiting system 200 that can facilitate quantum circuit buffering. For example, FIG. 2 illustrates a block diagram of an example non-limiting system 200 that can employ a scheduler component that, in one or more embodiments, can use an ML model to balance the execution of multiple quantum circuits for multiple physical real-world qubits of one or more physical qubit layouts of one or more quantum systems. Repetition of descriptions of similar elements and / or processes employed in each embodiment has been omitted for brevity. As previously indicated, the description for the embodiment of FIG. 1 can be applicable to the embodiment of FIG. 2. Similarly, the description for the embodiment of FIG. 2 can be applicable to the embodiment of FIG. 1.

[0031] In one or more embodiments, non-limiting system 200 can be a hybrid system and thus can include both quantum system 221 and one or more classical systems, such as classical-based quantum circuit buffering system 202. In one or more other embodiments, quantum system 221 can be separate from the classical systems, but can function in combination with the classical systems.

[0032] In such cases, one or more communications between one or more components of non-limiting system 200 (e.g., quantum system 221 and quantum circuit buffering system 202) may be facilitated by wired and / or wireless means, including, but not limited to, employing a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), or combinations thereof.Suitable wired or wireless technologies to facilitate communications include, but are not limited to, wireless fidelity (Wi-Fi), global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), worldwide interoperability for microwave access (WiMAX), enhanced general packet radio service (GPRS), third generation partnership project (3GPP) long term evolution (LTE), third generation partnership project 2 (3GPP2) ultra mobile broadband (UMB), high speed packet access (HSPA), Zigbee and other 802.XX wireless technologies and / or legacy communication technologies, BLUETOOTH®, Session Initiation Protocol (SIP), and / or other 802.XX wireless technologies. Protocol), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low power Wireless Area Networks), Z-Wave, ANT, ultra-wideband (UWB) standard protocols, or other proprietary and / or non-proprietary communications protocols.

[0033] In general, a quantum system 221 (e.g., a quantum computer system, a superconducting quantum computer system, or the like, or a combination thereof) may employ a quantum algorithm and / or quantum circuitry and may include computing components and / or computing devices for performing quantum operations and / or quantum functions on input data and generating results that may be output to an entity. A quantum circuit may comprise quantum bits (qubits), such as multi-bit quantum bits, physical circuit level components, higher level components, or functions, or a combination thereof. A quantum circuit may include physical pulses that may be structured (e.g., arranged or designed, or both) to perform a desired quantum function and / or quantum computation on data (e.g., input data and / or intermediate data derived from the input data) and generate one or more quantum results as output. A quantum result, e.g., a quantum measurement result 240, may be responsive to a quantum job request 224 and associated input data and may be based at least in part on the input data, the quantum function, or the quantum computation, or a combination thereof.

[0034] In one or more embodiments, quantum system 221 may include one or more quantum components, such as a quantum computing component 223, a quantum processor 226, a waveform generator 230, or a quantum logic circuit 228 including a plurality of qubits 227 (e.g., qubits 227A, 227B, or 227C, or a combination thereof), also referred to herein as qubit devices 227A, 227B, and 227C.

[0035] Quantum processor 226 can be any suitable processor. Quantum processor 226 can generate one or more instructions for controlling one or more processes of quantum computing component 223, or for controlling quantum logic circuit 228 and / or waveform generator 230.

[0036] Quantum operations component 223 can obtain (e.g., download, receive, retrieve, or the like, or a combination thereof) a quantum job request 224 that requests the execution of one or more quantum programs. Quantum operations component 223 can determine one or more quantum logic circuits, such as quantum logic circuit 228, to execute the quantum programs. Request 224 can be provided in any suitable format, such as text format, binary format, or another suitable format, or a combination thereof. In one or more embodiments, request 224 can be received by a component other than a component of quantum system 221, such as by a component of a classical system that is coupled to and / or in communication with quantum system 221.

[0037] The waveform generator 230 can perform one or more quantum processes, quantum computations, and / or quantum measurements to operate one or more quantum circuits on one or more qubits 227A, 227B, or 227C, or combinations thereof. For example, the waveform generator 230 can operate one or more qubit effectors, such as qubit oscillators, harmonic oscillators, pulse generators, or the like, or combinations thereof, to cause one or more pulses to stimulate and / or manipulate the state of one or more qubits 227A, 227B, or 227C, or combinations thereof, included in the quantum system 221. That is, the waveform generator 230, in combination with the quantum processor 226, or the like, can perform quantum logic circuit operations on multiple qubits 227 (e.g., qubits 227A, 227B, or 227C, or combinations thereof) of the quantum logic circuit 108. In response, the quantum operations component 223 may output one or more quantum job results, such as one or more quantum measurement results 240, in response to the quantum job request 224.

[0038] The quantum logic circuit 228 and some or all of the waveform generator 230 may be contained in a cryogenic environment generated by a cryogenic chamber 225, such as a dilution refrigerator. Indeed, signals may be generated by the waveform generator 230 in the cryogenic chamber 225 to affect one or more of the plurality of qubits 227. If the plurality of qubits 227 are qubit superconducting qubits, cryogenic temperatures, such as about 4K or less, may be used to facilitate the functioning of these physical qubits. Thus, elements of the quantum measurement circuit 230 also need to be constructed to perform at such cryogenic temperatures.

[0039] The quantum logic circuit 228, and therefore the quantum bits 227, may be configured by the quantum processor 226.

[0040] Limiting or preventing stray coupling between qubits or between qubits and couplers / buses or both, and minimizing crosstalk between qubits, may be achieved by a particular arrangement, such as a tiling (e.g., qubit layout), of multiple qubits 227 in quantum logic circuit 228.

[0041] The following / above description illustrates the operation of a single quantum program from a single quantum job request on a quantum logic circuit having a single configuration. This operation may include one or more readouts from the cryogenic environment electronics within the cryogenic chamber 225 by room temperature control / readout electronics outside the cryogenic chamber 225. However, the use of this configuration may be expanded, such that in one or more embodiments, two or more such configurations may be included in the quantum logic circuit 228. Such different configurations may be achieved by the same or different waveform generators. Furthermore, one or more processes described herein may be expanded, such as to additionally and / or alternatively include the execution of one or more quantum programs and / or quantum job requests in parallel with one another.

[0042] As shown in the figure, non-limiting system 200 may also comprise a classical computer portion, including quantum circuit buffering system 202. In general, quantum circuit buffering system 202 may comprise any suitable type of component, machine, device, facility, apparatus, or equipment, or combination thereof, that includes a processor and / or is capable of effective or operative communication with a wired or wireless network, or both, as shown in the figure. All such embodiments are contemplated. For example, quantum circuit buffering system 202 may comprise a server device, a computing device, a general purpose computer, a special purpose computer, a quantum computing device (e.g., a quantum computer), a tablet computing device, a handheld device, a server class computing machine and / or a database, a laptop computer, a notebook computer, a desktop computer, a mobile phone, a smartphone, a consumer device and / or a consumer appliance, an industrial device and / or a commercial device, a digital assistant, an internet enabled multimedia phone, a multimedia player, and / or another type of device and / or computing device, a combination thereof.Similarly, the quantum circuit buffering system 202 may be located and / or executed in any suitable device, such as, but not limited to, a server device, a computing device, a general-purpose computer, a special-purpose computer, a quantum computing device (e.g., a quantum computer), a tablet computing device, a handheld device, a server class computing machine and / or database, a laptop computer, a notebook computer, a desktop computer, a mobile phone, a smartphone, a consumer device and / or appliance, an industrial device and / or commercial device, a digital assistant, an Internet-enabled multimedia phone, a multimedia player, or another type of device and / or computing device, or a combination thereof.

[0043] Quantum circuit buffering system 202 may be associated with a cloud computing environment, such as being accessible via a cloud computing environment. For example, quantum circuit buffering system 202 may be associated with cloud computing environment 950, described below with reference to Figure 9, or with one or more functional abstraction layers (e.g., hardware and software layer 1060, virtualization layer 1070, management layer 1080, and / or workload layer 1090), described below with reference to Figure 10.

[0044] The operation of non-limiting system 200 and / or quantum circuit buffering system 202 is not limited to the use of a single quantum job result 240 or the use of a single quantum circuit 213. Rather, the operation of non-limiting system 200 and / or quantum circuit buffering system 202 is scalable. For example, non-limiting system 200 and / or quantum circuit buffering system 202 can facilitate the operation of multiple quantum circuits 213 at least partially concurrently with one another. Additionally, non-limiting system 200 and / or quantum circuit buffering system 202 can use one or more physical qubit layouts 219 based on one or more quantum logic circuits 228, such as the quantum logic circuits of a quantum processor, such as quantum processor 226.

[0045] In one or more embodiments, the quantum logic circuit 228 may be virtually separated into two or more virtual machines with distinct physical qubit layouts 219 based on the same quantum logic circuit of the same quantum processor or the same parent set of qubits.

[0046] Quantum circuit buffering system 202 may comprise multiple components, which may include memory 204, processor 206, bus 205, identification component 212, acquisition component 214, scheduler component 216, and / or training component 222. Like quantum circuit buffering system 102, quantum circuit buffering system 202 may be operated to facilitate the process of operation of multiple quantum circuits at least partially in parallel with one another.

[0047] One or more communications between one or more components of non-limiting system 200, or between external systems and non-limiting system 200, or both, may be facilitated by wired and / or wireless means, including, but not limited to, employing a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), or combinations thereof. Suitable wired or wireless technologies to facilitate communication include Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), High Speed ​​General Packet Radio Service (GPRS), Third Generation Partnership Project (3GPP) Long Term Evolution (LTE), Third Generation Partnership Project 2 (3GPP2) Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and / or legacy communication technologies, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low power Wireless Area Network (6LoWPAN) Networks), Z-Wave, ANT, Ultra-Wideband (UWB) standard protocols, or other proprietary and / or non-proprietary communications protocols, or combinations thereof.

[0048] The processor 206, memory 204, and bus 205 of the quantum circuit buffering system 202 will now be described.

[0049] For example, in one or more embodiments, quantum circuit buffering system 202 may comprise a processor 206 (e.g., a computer processing unit, a microprocessor, a classical processor, a quantum processor, or the like, or a combination thereof). In one or more embodiments, components associated with quantum circuit buffering system 202 may comprise components and / or instructions that are readable, writable, or executable by one or more computers and / or machines, or combinations thereof, as described herein with or without reference to one or more figures of one or more embodiments, and these components and / or instructions may be executed by processor 206 to facilitate execution of one or more processes defined by such components and / or instructions. In one or more embodiments, processor 206 may comprise an identification component 212, an acquisition component 214, a scheduler component 216, and / or a training component 222.

[0050] In one or more embodiments, the quantum circuit buffering system 202 may comprise a computer-readable memory 204 that may be operatively coupled to the processor 206. The memory 204 may store computer-executable instructions that, when executed by the processor 206, may cause the processor 206 and / or one or more other components of the quantum circuit buffering system 202 (e.g., the identification component 212, the acquisition component 214, the scheduler component 216, and / or the training component 222) to perform one or more operations. In one or more embodiments, the memory 204 may store the computer-executable components (e.g., the identification component 212, the acquisition component 214, the scheduler component 216, and / or the training component 222).

[0051] The quantum circuit buffering system 202 and / or components thereof described herein are communicatively, electrically, operatively, optically, or otherwise, or a combination thereof, coupled to each other via a bus 205 and perform and / or are coupled to the functions of the non-limiting system 200, the quantum circuit buffering system 202, and / or one or more components thereof, and / or one or more components coupled thereto. The bus 205 may include one or more of a memory bus, a memory controller, a peripheral bus, an external bus, a local bus, a quantum bus, or another type of bus that may employ one or more bus architectures, or a combination thereof. One or more of these examples of the bus 205 may be employed to implement one or more embodiments described herein.

[0052] In one or more embodiments, quantum circuit buffering system 202 may be coupled (e.g., communicatively, electrically, operatively, optically, or similarly functionally, or a combination thereof) to one or more external systems (e.g., an electrical output generating system not shown, one or more output targets, an output target controller, or the like, or a combination thereof), sources, or devices (e.g., classical or quantum computing devices, or both, communication devices, or the like, or a combination thereof), such as via a network. In one or more embodiments, one or more of the components of non-limiting system 200 may reside in the cloud and / or may reside locally in a local computing environment (e.g., at a designated location).

[0053] In addition to the aforementioned processor 206 and / or memory 204, the quantum circuit buffering system 202 may comprise one or more computer and / or machine readable, writable, and / or executable components and / or instructions that, when executed by the processor 206, can facilitate performance of one or more operations defined by such components and / or instructions.

[0054] Referring now to additional components of the quantum circuit buffering system 202, generally, a quantum circuit that is received and / or obtained may be stored in a bucket. The bucket 215 may be a storage unit used for temporary storage of the quantum circuit 213 or for copying the quantum circuit 213. The bucket 215 may be included in the memory 204 or may be separate from the memory 204, or both. When compiling the quantum circuit 213 into a composite circuit 217, the bucket 215 may not "populate" with the quantum circuit 213. In one or more embodiments, the bucket 215 may be used to temporarily store the composite circuit 217. The composite circuit 217 may be a quantum circuit composed of multiple smaller quantum circuits 213, thus allowing for maximizing the use of the quantum logic circuit 228. After one or more count / shot operations of the quantum circuit 213 and / or composite circuit 217, such quantum circuit 213 and / or composite circuit 217 may be removed from the temporary storage bucket 215. That is, the storage bucket 215 may be used as an organization system for the quantum circuit buffering system 202.

[0055] Further, generally, when a bucket 215 is ready, the circuits 213 in the bucket 215 may be combined and / or compiled into a composite circuit 217 and may be mapped and / or remapped to a physical qubit layout 219 that may be based on at least a portion of the qubits 227 of the quantum logic circuit 228. Generally, as described in further detail below, a bucket 215 may be ready when a certain percentage of the qubits of the physical qubit layout 219 are used, or based on time, or both. Multiple buckets 215 may be used, such as to increase utilization of the quantum system 221 (e.g., of the quantum logic circuit 228).

[0056] For example, with brief reference to FIG. 3, as shown in plots 300, 320, and 350, different quantum circuits A, B, or C, or combinations thereof, may be executed in a single iteration of a quantum system. Different quantum circuits may use various resources, such as different numbers of qubits, or qubits with specific hardware connections to each other, or both. In plot 300, circuits A and B may be executed in succession, using at least one same qubit of the same quantum logic circuit, etc. In plot 320, circuits A and B may be executed simultaneously with each other, for different qubits of the same quantum logic circuit, etc. In plot 350, circuits B and C may be executed in succession, and may be executed together simultaneously with circuit A, for different qubits of the same quantum logic circuit, etc. (e.g., circuit B / C vs. circuit A). Additionally, in conjunction with plot 350, different circuits A, B, and C may each be executed multiple times, in succession, in multiple shots, etc. In this manner, multiple quantum measurement results may be obtained to account for the variance of the various shots.

[0057] Now referring to the identification component 212, the identification component can identify a quantum circuit 213, such as based on a quantum job request 224. The quantum job request 224 can be provided in any suitable format, such as text, binary, or the like, or a combination thereof. The quantum circuit 213 can be included in the quantum job request 224, or can be stored internally and / or externally to the quantum circuit buffering system 202 and / or the non-limiting system 200.

[0058] The acquisition component 214 may receive, download, transfer, upload, or otherwise acquire quantum circuits 213, or a combination thereof. The acquisition component 214 may assign quantum circuits 213 to buckets 215. In one or more embodiments, the acquisition component 214 may determine that a bucket 215 is ready for analysis by the scheduler component 216. The ready state may be based on meeting one or more thresholds such that the scheduler component 216 may begin analyzing quantum circuits 213 from a ready bucket 215. This initial threshold may be based on any one or more of the number of qubits used, or the amount of time a bucket has been at least partially full and awaiting further processing. In one or more other embodiments, the initial threshold may be based on any one or more of the number of qubits to use, the number of shots to perform, the number of gates (e.g., swap gates) used, the execution time of the quantum circuit compared to the coherence time of the qubits used, the length / depth of the circuit, the time of the quantum circuit in the queue, hardware constraints, the level of the user entity or customer, or the like, or combinations thereof.

[0059] Scheduler component 216 may generally facilitate the mapping and / or re-mapping of quantum circuits stored in buckets to one or more physical qubit layouts 219. Physical qubit layouts 219 may be stored internally and / or externally to quantum circuit buffering system 202 and / or non-limiting system 200. Physical qubit layouts 219 may be dynamically changed, such as by quantum system 221, based on the current state of qubits 227 of quantum logic circuit 228.

[0060] As indicated above, scheduler component 216 may compile composite circuit 217 including the quantum circuit and at least one other quantum circuit that are executed together on physical qubit layout 219. The mapping performed by scheduler component 216 may be based at least in part on the number of gates used by scheduler component 216 to perform the mapping compared to the number of gates of quantum circuit 213 prior to execution of the mapping. The mapping performed by scheduler component 216 may be based at least in part on a comparison of the execution time of the quantum circuit compared to the coherence time of physical qubit layout 219. Such coherence times may be based on past activity or may be based on individual qubit coherence, or both. A threshold based on the number of shots may, in one or more embodiments, eliminate various overheads, such as from otherwise additional initialization of equipment, qubits, and / or associated components of a quantum system across multiple quantum program jobs (e.g., each of which may require the operation of one or more quantum circuits).

[0061] In one or more embodiments, the remapping can include adding additional gates, such as swaps, to fit the quantum circuit 213 to the physical qubit layout 219. Adding gates may lengthen the composite circuit 217, but may also allow a smaller quantum circuit 213 to run efficiently on a larger quantum system (e.g., containing more qubits than are used by any one quantum circuit 213) and / or may reduce the number of swap gates used. In one example, a 5 qubit quantum circuit compiled for a 5 qubit machine may contain many swaps due to connectivity (e.g., hardware connectivity). If the same quantum circuit were compiled for a larger machine with better connectivity, the number of swaps may be reduced.

[0062] If multiple buckets 215 are used by the quantum circuit buffering system 202, the scheduler component 216 may analyze one or more buckets 215, such as each bucket 215, in any suitable order (or one or more buckets 215 simultaneously, or both) to find a combination of quantum circuits 213 to use. A combination of quantum circuits 213 can be quantum circuits from a single bucket 215 or from multiple buckets 215.

[0063] In one or more embodiments, a similar process may be used when a single large bucket is used. In such an example, one or more quantum circuits 213 may be selected, such as by heuristic techniques, to form a composite circuit 217. Any one or more of the thresholds discussed above may be used.

[0064] In one or more embodiments, the scheduler component 216 may perform the mapping and / or remapping using one or more algorithms, i.e., historical data of the quantum circuits used and the corresponding utilized mappings may be used as inputs to the algorithms.

[0065] In one or more embodiments, the scheduler component 216 can perform the mapping and / or remapping using a machine learning (ML) model. That is, historical data of used quantum circuits and corresponding utilized mappings can be used to train the ML model. The ML model can be further trained, such as by a training component 222, such as after each iterative execution of the composite circuit 217 or after multiple shots of operation of the composite circuit 217 or portions thereof or both.

[0066] In one or more embodiments, scheduler component 216 may map one or more quantum circuits 213 and / or composite circuits 217 to physical qubit layout 219 while operating generally independent of physical qubit layout 219 other than the total number of available qubits in physical qubit layout 219. For example, scheduler component 216 may map without consideration of hardware connections or other connectivity and / or constraints between qubits in physical qubit layout 219.

[0067] Referring now to FIG. 4, a schematic diagram 400 of operations that may use the non-limiting system 200 and / or quantum circuit buffering system 202 of FIG. 2 is shown. Referring also to FIG. 5, a process flow 500 based on the schematic diagram 400 of FIG. 4 is shown. An explanation is provided in accordance with one or more embodiments described herein, such as the non-limiting system 200 of FIG. 2. Although the process flow 500 is explained in relation to the non-limiting system 200 of FIG. 2, the process flow 500 is also applicable to other systems described herein, such as the non-limiting system 100 of FIG. 1. Repetition of explanations of similar elements and / or processes employed in each embodiment is omitted for the sake of brevity.

[0068] At 502, the non-limiting method 500 may include receiving, by a system (e.g., quantum circuit buffering system 202), one or more quantum circuits (e.g., quantum circuit 413).

[0069] At 504, non-limiting method 500 may include determining, by a system (e.g., acquisition component 214 of quantum circuit buffering system 202), that a bucket (e.g., bucket 415) is ready to be analyzed based on one or more thresholds.

[0070] At 506, the non-limiting method 500 may include coupling, by a system (e.g., the scheduler component 216 of the quantum circuit buffering system 202), the quantum circuit (e.g., the quantum circuit 413) into a composite circuit (e.g., the composite circuit 417).

[0071] At 508, the non-limiting method 500 may include executing, by a system (e.g., non-limiting system 200), a composite circuit (e.g., composite circuit 417) on a quantum system (e.g., quantum system 421).

[0072] Referring now to Figure 6, a schematic diagram 600 is shown illustrating an example non-limiting method 600 that can facilitate determining bucket readiness in accordance with one or more embodiments described herein, such as the non-limiting system 200 of Figure 2. Although the non-limiting method 600 is described in relation to the non-limiting system 200 of Figure 2, the non-limiting method 600 can also be applicable to other systems described herein, such as the non-limiting system 100 of Figure 1. Repetition of descriptions of similar elements and / or processes employed in each embodiment has been omitted for the sake of brevity.

[0073] At 602, the non-limiting method 600 may include receiving, by a system (e.g., quantum circuit buffering system 202), one or more thresholds at an interface of an entity.

[0074] At 604, the non-limiting method 600 may include determining, by a system (e.g., the acquisition component 214 of the quantum circuit buffering system 202), that the bucket is ready to be analyzed based on one or more thresholds.

[0075] At 606, non-limiting method 600 may include modifying the decision by a system (e.g., acquisition component 214 of quantum circuit buffering system 202) based on availability of quantum bits in a quantum system (e.g., quantum system 221).

[0076] At 608, the non-limiting method 600 may include providing, by a system (e.g., an acquisition component 214 of the quantum circuit buffering system 202) an indication to a scheduler (e.g., a scheduler component 216 of the quantum circuit buffering system 202) that the bucket is ready for analysis.

[0077] Next, Figure 7 illustrates a flow diagram of an exemplary non-limiting method 700 that can facilitate generation of a decision policy in accordance with one or more embodiments described herein, such as the non-limiting system 200 of Figure 2. Although the non-limiting method 700 is described in relation to the non-limiting system 200 of Figure 2, the non-limiting method 700 is also applicable to other systems described herein, such as the non-limiting system 100 of Figure 1. Repetition of descriptions of similar elements and / or processes employed in each embodiment has been omitted for the sake of brevity.

[0078] At 702, the non-limiting method 700 may include identifying a quantum circuit by a system operably coupled to a processor (e.g., the identification component 212 of the quantum circuit buffering system 202).

[0079] At 704, the non-limiting method 700 may include acquiring, by a system (e.g., the acquiring component 214 of the quantum circuit buffering system 202), the quantum circuit and assigning, by the system, the quantum circuit to a temporary storage bucket.

[0080] At 706, the non-limiting method 700 may include identifying, by a system (e.g., the acquisition component 214 of the quantum circuit buffering system 202), whether the temporary storage bucket meets a threshold such that the system may proceed with analysis of the quantum circuit from the temporary storage bucket.

[0081] At 708, the non-limiting method 700 may include mapping, by a system (e.g., the scheduler component 216 of the quantum circuit buffering system 202), the quantum circuit to a physical circuit layout.

[0082] At 710, non-limiting method 700 may include mapping, by a system (e.g., scheduler component 216 of quantum circuit buffering system 202), the quantum circuit to a physical qubit layout based at least in part on one or more of: a number of shots of the quantum circuit performed, a number of gates used to perform the mapping compared to the number of gates of the quantum circuit before the mapping was performed, or a comparison of the execution time of the quantum circuit compared to a coherence time of the physical qubit layout.

[0083] At 712, non-limiting method 700 may include compiling, by a system (e.g., scheduler component 216 of quantum circuit buffering system 202), a composite circuit that includes the quantum circuit and at least one other quantum circuit, and mapping, by the system, the composite circuit to a physical qubit layout (e.g., physical qubit layout 219).

[0084] At 714, the non-limiting method 700 may include requesting execution of the composite circuit by a system (e.g., the scheduler component 216 of the quantum circuit buffering system 202).

[0085] At 716, non-limiting method 700 may include assigning, by a system (e.g., scheduler component 216 of quantum circuit buffering system 202), a first number of physical qubits of the physical qubit layout as first virtual machines based at least in part on the variables of the quantum circuit, and assigning, by the system (e.g., scheduler component 216 of quantum circuit buffering system 202), a second number of physical qubits of the physical qubit layout as second virtual machines, where the first number is less than the second number.

[0086] For ease of explanation, the computer-implemented methods and non-computer-implemented methods provided herein are depicted and / or described as a series of operations. It should be understood that the subject innovation is not limited by the operations depicted and / or by the order of operations, e.g., operations can occur in one or more orders, or simultaneously, or both, with other operations not presented and described herein. Moreover, not all depicted operations may be utilized to practice the computer-implemented methods and non-computer-implemented methods in accordance with the described subject matter. In addition, the computer-implemented methods and non-computer-implemented methods may alternatively be represented as a series of interrelated states or events via a state diagram. Furthermore, to facilitate transporting and transferring the computer-implemented methods to a computer, the computer-implemented methods described below and throughout this specification may be stored in an article of manufacture. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or computer-readable storage medium.

[0087] Systems and / or devices have been described (and / or further described) herein with respect to interactions between one or more components. Such systems and / or components may include those components or subcomponents designated therein, one or more of the designated components and / or subcomponents, or additional components, or combinations thereof. Subcomponents may be implemented as components that are communicatively coupled to other components rather than being included within a parent component. One or more components and / or subcomponents may be combined into a single component that provides a collective functionality. Components may interact with one or more other components not specifically described herein for brevity but known by those skilled in the art.

[0088] In summary, one or more systems, devices, computer program products, or computer-implemented methods of use, or combinations thereof, provided herein relate to maximizing the use of a physical qubit layout of a quantum computer. The system may include a memory storing computer-executable components and a processor executing the computer-executable components stored in the memory, where the computer-executable components may include an identification component that identifies a quantum circuit, and a scheduler component that maps the quantum circuit to a physical qubit layout. In one embodiment, the scheduler component may combine multiple quantum circuits by including the quantum circuit in a composite circuit, and map the composite circuit to a physical qubit layout. In one embodiment, the acquisition component may assign the quantum circuit to a temporary storage bucket and may identify whether the temporary storage bucket meets a threshold at which the scheduler component may begin analyzing the quantum circuit.

[0089] Generally, one or more systems, devices, computer program products, and / or computer-implemented methods of use provided herein can optimize the operation of an execution of a quantum circuit, such as by finding low-cost patterns using a library of physical qubit layout templates.

[0090] An advantage of the foregoing systems, computer-implemented methods, and / or computer program products is that the overall throughput of a quantum system employing such embodiments is generally increased as compared to the operation of one quantum program at a time. Indeed, the utilization of physical qubits may be increased both by increasing the number of qubits and by increasing the utilized available coherence time of one or more qubits in such a quantum system.

[0091] Another advantage is the employment of one or more thresholds that are based on quantum circuits, hold times, or based on the entity requesting the operation, or a combination thereof. One or more such thresholds may be used simultaneously, and the threshold criteria may be dynamically and selectively changed. In this manner, the most efficient use of the quantum system may be effected while providing a quantified level of fairness to the user entity requesting use of the quantum system. Indeed, such balancing may be desirable in cases where the physical qubit layout exceeds 10 or more qubits, such as including 1000 or more qubits.

[0092] Another advantage is that, compared to existing technologies, open access to quantum circuits can be restricted based on increasing qubit size and / or shot counts, so that smaller quantum circuits can be combined and run on larger quantum processors (which can, for example, comprise quantum logic circuits). This allows fewer but larger quantum systems to be maintained.

[0093] One or more embodiments described herein may, in one or more embodiments, essentially or intimately relate to computer technology and may not be implemented outside of a computing environment. For example, one or more processes performed by one or more embodiments described herein may facilitate the execution of programs and / or program instructions in a more efficient and even more executable manner, such as in connection with mapping and / or remapping quantum circuits to physical qubit layouts. Systems, computer-implemented methods, and / or computer program products that facilitate the execution of these processes are highly useful in the field of quantum computing and may not be implemented in the same executable manner outside of a computing environment in a sensible manner.

[0094] One or more embodiments described herein may employ hardware and / or software to solve highly technical problems that are not abstract and cannot be performed as a series of mental activities by a human. For example, a single human, or even thousands of humans, cannot efficiently balance multiple factors to efficiently, accurately, or effectively, or a combination thereof, map a large number of quantum circuits on a time scale that one or more embodiments described herein can facilitate this process. Furthermore, neither the human mind nor a human with pen and paper can efficiently balance multiple factors to electronically, efficiently, accurately, or effectively, or a combination thereof, on a time scale that is performed by one or more embodiments described herein.

[0095] In one or more embodiments, one or more of the processes described herein may be executed by one or more specialized computers (e.g., specialized processing units, specialized classical computers, specialized quantum computers, specialized hybrid classical / quantum systems, or another type of specialized computer, or a combination thereof) to perform defined tasks associated with one or more of the techniques described above. One or more embodiments and / or components of the embodiments described herein may be employed to solve new problems that arise due to advances in the aforementioned technologies, quantum computing systems, cloud computing systems, computer architectures, or another technique, or a combination thereof.

[0096] One or more embodiments described herein may be fully operable towards performing one or more other functions (e.g., fully powered, fully running, or another, or a combination thereof) while also performing one or more of the operations, such as quantum and / or non-quantum operations, that are described herein and / or not specifically described.

[0097] 8-10, additional background details are provided regarding one or more embodiments described herein in FIGS. 1-7.

[0098] FIG. 8 and the following discussion are intended to provide a brief general description of a suitable operating environment 800 in which one or more embodiments described in FIGS. 1-7 herein may be implemented. For example, one or more components and / or other aspects of the embodiments described herein may be associated with, such as implemented within, or accessible via, the operating environment 800. Additionally, while one or more embodiments are described above in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will recognize that one or more embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0099] Typically, program modules include routines, programs, components, data structures, or the like, or combinations thereof, that perform particular tasks and / or implement particular abstract data types. Furthermore, the methods described above can be practiced using other computer system configurations, including single or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, or the like, or combinations thereof, each of which may be operatively coupled to one or more associated devices.

[0100] A computing device typically includes a variety of media, which may include computer-readable storage media, machine-readable storage media, or communication media, or a combination thereof, and in this specification, the two terms are used differently from each other as follows. A computer-readable storage medium or machine-readable storage medium can be any available storage medium that can be accessed by a computer, and includes both volatile and non-volatile media, removable and non-removable media. By way of example, a computer-readable storage medium or machine-readable storage medium or both may be implemented in association with any method or technology for storage of information, such as, but not limited to, computer-readable and / or machine-readable instructions, program modules, structured and / or unstructured data.

[0101] A computer readable storage medium may include, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray disc (BD) or other optical disk storage or combinations thereof, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices or combinations thereof, solid state drives or other solid state storage devices, or other tangible and / or non-transitory media that may be used to store the identified information. In this regard, the terms "tangible" or "non-transient" in this specification, when applied to storage, memory, and / or computer-readable media, should be understood to exclude only propagating, ephemeral signals as modifiers, and not to disclaim any claim to all standard storage, memory, or computer-readable media that are not themselves merely propagating, ephemeral signals.

[0102] The computer-readable storage medium may be accessed by one or more local or remote computing devices for various operations on the information stored by the medium, for example, via access requests, queries, or other data retrieval protocols, or a combination thereof.

[0103] Communication media typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a data signal, such as a modulated data signal (e.g., carrier wave or other transport mechanism) and includes any information delivery or transport media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal or signals. By way of example, and not limitation, communication media may include wired media, such as a wired network or direct-wired connection, or wireless media, such as acoustic, RF, infrared, or other wireless media, or combinations thereof.

[0104] 8, an exemplary operating environment 800 for implementing one or more embodiments of the aspects described herein can include a computer 802 including a processing unit 806, a system memory 804, and / or a system bus 808. One or more aspects of the processing unit 806 can be applied to a processor, such as 106 and / or 206 of non-limiting systems 100 and / or 200. The processing unit 806 can be implemented in combination with a processor, such as 106 and / or 206, or as a replacement for these processors, or both.

[0105] Memory 804 can store components and / or instructions that can be read, written, or executed by one or more computers and / or machines, or a combination thereof, which, when executed by processing unit 806 (e.g., a classical processor, a quantum processor, or the like, or a combination thereof), can facilitate the performance of operations defined by the executable components and / or instructions. For example, memory 804 can store components and / or instructions that can be read, written, or executed by a computer or machine, or a combination thereof, which, when executed by processing unit 806, can facilitate the performance of one or more functions described herein in connection with non-limiting system 100, non-limiting system 200, or both, as described herein with or without reference to one or more figures of one or more embodiments.

[0106] The memory 804 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), or the like, or a combination thereof) and / or non-volatile memory (e.g., read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or the like, or a combination thereof), which may employ one or more memory architectures.

[0107] The processing unit 806 may include one or more types of processors and / or electronic circuitry (e.g., classical, quantum, or similar processors, or a combination thereof) that may implement components and / or instructions that may be stored in the memory 804 that may be readable, written, and / or executed by one or more computers and / or machines. For example, the processing unit 806 may perform one or more operations, including but not limited to, logic, control, input / output (I / O), arithmetic, and / or the like, that may be specified by components and / or instructions that may be readable, written, and / or executed by a computer and / or machine. In one or more embodiments, the processing unit 806 may be any of one or more commercially available processors. In one or more embodiments, the processing unit 806 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system on a chip (SOC), array processors, vector processors, quantum processors, or other types of processors, or combinations thereof. Examples of the processing unit 806 may be employed to implement one or more embodiments described herein.

[0108] A system bus 808 may couple system components, including but not limited to a system memory 804, to the processing unit 806. The system bus 808 may include one or more types of bus structures that may be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, or a local bus, or combinations thereof, using one or more of a variety of commercially available bus architectures. The system memory 804 may include a ROM 810 and / or a RAM 812. A basic input / output system (BIOS) may be stored in a non-volatile memory, such as a ROM, an erasable programmable read-only memory (EPROM), or an EEPROM, or combinations thereof, and the BIOS includes basic routines that help transfer information between elements within the computer 802, such as during start-up. The RAM 812 may include a high-speed RAM, such as a static RAM, for caching data.

[0109] The computer 802 may include an internal hard disk drive (HDD) 814 (e.g., EIDE, SATA), one or more external storage devices 816 (e.g., a magnetic floppy disk drive (FDD), a memory stick or flash drive reader, a memory card reader, or the like, or a combination thereof), and / or a drive 820 (e.g., a solid-state drive or optical disk drive that can read from or write to a disk 822, such as a CD-ROM disk, a DVD, a BD, or the like, or a combination thereof). Additionally and / or alternatively, if a solid-state drive is included, the disk 822 may not be included unless it is separate. Although the internal HDD 814 is shown as being within the computer 802, the internal HDD 814 may also be configured for use within an external suitable enclosure (not shown). Additionally, although not shown in operating environment 800, a solid state drive (SSD) may be used in addition to or in place of HDD 814. HDD 814, external storage device 816, and drive 820 may be connected to system bus 808 by HDD interface 824, external storage interface 826, and drive interface 828, respectively. HDD interface 824 for external drive implementations may include at least one or both of Universal Serial Bus (USB) interface technology and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technology. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0110] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. The drives and storage media of computer 802 accommodate the storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to various storage devices, it is understood that other types of storage media that can be read by a computer, whether currently existing or developed in the future, can also be used within the exemplary operating environment and / or any such storage media can include computer-executable instructions for performing the methods described herein.

[0111] A number of program modules, including an operating system 830, one or more applications 832, other program modules 834, and / or program data 836, may be stored in the drives and RAM 812. All or portions of the operating system, applications, modules, and / or data may be cached in RAM 812. The systems and / or methods described herein may be implemented using one or more commercially available operating systems and / or combinations of operating systems.

[0112] Computer 802 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment of operating system 830, and the emulated hardware may optionally be different than the hardware shown in FIG. 8. In a related embodiment, operating system 830 may include one of a number of virtual machines (VMs) hosted on computer 802. Additionally, operating system 830 may provide a runtime environment, such as the JAVA® runtime environment or the .NET framework, to application 832. The runtime environment is a consistent execution environment that may enable application 832 to run on any operating system that includes the runtime environment. Similarly, operating system 830 may support containers, and application 832 may be in the form of a container, which is a lightweight, standalone, executable software package that includes, for example, code, runtime, system tools, system libraries, and / or settings for the application.

[0113] Additionally, computer 802 may be enabled with a security module, such as a trusted processing module (TPM). For example, with a TPM, a boot component may hash the next boot component in time and wait for a match of the hash result with a protected value before loading the next boot component. This process may occur at any layer within the code execution stack of computer 802, for example, applied at the application execution level or at the operating system (OS) kernel level, or both, thereby enabling security at any level of code execution.

[0114] An entity may input and / or send commands and / or information to the computer 802 via one or more wired / wireless input devices (e.g., a keyboard 838, a touch screen 840, and / or a pointing device such as a mouse 842). Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote control, or a combination thereof, a joystick, a virtual reality controller or / and a virtual reality headset, a game pad, a stylus, an image input device (e.g., a camera), a gesture sensor input device, a visual movement sensor input device, an emotion or face detection device, a biometric input device (e.g., a fingerprint or iris scanner or / and), or the like, or a combination thereof. These and other input devices may often be connected to the processing unit 806 via an input device interface 844 which may be coupled to the system bus 808, but may also be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH® interface, or the like, or combinations thereof.

[0115] Alternatively and / or additionally, a monitor 846 or other type of display device may be connected to the system bus 808 via an interface, such as a video adapter 848. In addition to the monitor 846, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, or the like, or a combination thereof.

[0116] The computer 802 can operate in a networked environment using logical connections via wired and / or wireless communications to one or more remote computers, such as a remote computer 850. The remote computer 850 can be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment device, a peer device, or other common network node, or a combination thereof, and typically includes many or all of the elements described relative to the computer 802, although for simplicity only a memory / storage device 852 is shown. Additionally and / or alternatively, computer 802 may be communicatively coupled (e.g., communicatively, electrically, operatively, optically, or the like, or a combination thereof) to one or more external systems, sources, or devices (e.g., classical and / or quantum computing devices, communication devices, or the like, or a combination thereof) via a data cable (e.g., a High-Definition Multimedia Interface (HDMI), recommended standard (RS) 232, Ethernet cable, or the like, or a combination thereof).

[0117] In one or more embodiments, the network may include one or more wired and / or wireless networks, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN). For example, one or more embodiments described herein may be used in conjunction with wireless fidelity (Wi-Fi), global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), worldwide interoperability for microwave access (WiMAX), enhanced general packet radio service (enhanced GPRS), third generation partnership project (3GPP) long term evolution (LET), third generation partnership project 2 (3GPP2) ultra mobile broadband (UMB), high speed packet access (HSPA), Zigbee, and other 802.11b standards.XX The device may communicate with (and vice versa) one or more external systems, sources, or devices (e.g., computing devices) or any combination thereof using virtually any specified wired or wireless technology, including, but not limited to, wireless and / or legacy communication technologies, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, IPv6 over Low power Wireless Area Networks (6LoWPAN), Z-Wave, ANT, ultra-wideband (UWB) standard protocols, and / or other proprietary and / or non-proprietary communication protocols. In a related example, one or more embodiments described herein may include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, quantum hardware, a quantum processor, or the like, or a combination thereof), software (e.g., a set of threads, a set of processes, running software, a quantum pulse schedule, a quantum circuit, a quantum gate, or the like, or a combination thereof), or a combination of hardware or software or both, that facilitates the transfer of information between one or more embodiments described herein and an external system, source, or device (e.g., a computing device, a communication device, or the like, or a combination thereof).

[0118] The logical connections depicted in the diagram include wired / wireless connections to a local area network (LAN) 854 or larger networks, such as a wide area network (WAN) 856. LAN and WAN networking environments may be commonplace in offices and companies, facilitating enterprise-wide computer networks, such as intranets, all of which may connect to a global communications network, such as the Internet.

[0119] When used in a LAN networking environment, the computer 802 may be connected to the local network 854 via a wired and / or wireless communication network interface or adapter 858. The adapter 858 may facilitate wired and / or wireless communication with the LAN 854, which may also include a wireless access point (AP) disposed for communicating with the adapter 858 in a wireless mode.

[0120] When used in a WAN network environment, the computer 802 may include a modem 860 or may be connected to a communications server on the WAN 856 by other means for establishing communications over the WAN 856, such as via the Internet, or both. The modem 860, which may be a wired and / or wireless device that is internal and / or external, may be connected to the system bus 808 via the input device interface 844. In a network environment, program modules depicted relative to the computer 802 or portions thereof may be stored in a remote memory / storage device 852. The network connections shown are merely examples and one or more other means of establishing a communications link between the computers may be used.

[0121] When used in either a LAN or WAN network environment, the computer 802 may access a cloud storage system or other network-based storage system, such as, but not limited to, a networked virtual machine, that provides one or more aspects of information storage and / or processing in addition to or in place of the external storage device 816 as previously described, when used in either a LAN or WAN network environment. In general, a connection between the computer 802 and the cloud storage system may be established via the LAN 854 or the WAN 856, for example, by an adapter 858 or a modem 860, respectively. Upon connecting the computer 802 to an associated cloud storage system, the external storage interface 826 may manage the storage provided by the cloud storage system as well as other types of external storage, such as by using the adapter 858 or the modem 860, or both. For example, the external storage interface 826 may be configured to provide access to the cloud storage sources as if the cloud storage sources were physically connected to the computer 802.

[0122] The computer 802 may be operable to communicate with any wireless device or entity operatively disposed in wireless communication (e.g., a printer, a scanner, a desktop computer or portable computer or both, a portable data assistant, a communications satellite, a telephone, or any piece or location of equipment associated with a wirelessly detectable tag (e.g., a kiosk, a newsstand, a store shelf, or the like, or any combination thereof). This communication may include Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technologies. Thus, this communication may be of a predefined structure, similar to a conventional network, or may simply be an ad-hoc communication between at least two devices.

[0123] Example embodiments described herein may be used in conjunction with distributed computing environments (e.g., cloud computing environments) where certain tasks are performed by remote processing devices linked through a communications network, such as the distributed computing environment described below with respect to Figure 13. In a distributed computing environment, program modules may be located in local and / or remote memory storage devices.

[0124] For example, one or more embodiments or one or more components of embodiments described herein may employ one or more computational resources of cloud computing environment 950 described below with reference to FIG. 9 or with reference to one or more functional abstraction layers (e.g., quantum software, and / or the like) described below with reference to FIG. 10 to perform one or more operations in accordance with one or more embodiments described herein. For example, cloud computing environment 950, or one or more of functional abstraction layers 1060, 1070, 1080, or 1090, or combinations thereof, may include one or more classical computing devices (e.g., classical computers, classical processors, virtual machines, servers, or the like, or combinations thereof), quantum hardware, and / or quantum software (e.g., quantum computing devices, quantum computers, quantum processors, quantum circuit simulation software, superconducting circuits, and / or the like), that may be employed by one or more embodiments or components of embodiments described herein to perform one or more operations in accordance with one or more embodiments described herein. For example, one or more embodiments and / or components of embodiments described herein may use one or more such classical and / or quantum computing resources to execute one or more classical and / or quantum mathematical functions, calculations, or equations, or combinations thereof, computational and / or processing scripts, algorithms, models (e.g., artificial intelligence (AI) models, machine learning (ML) models, or similar models, or combinations thereof), or other operations in accordance with one or more embodiments described herein, or combinations thereof.

[0125] Although one or more embodiments described herein include detailed descriptions of cloud computing, it should be understood that implementation of the subject matter presented herein is not limited to a cloud computing environment. Rather, one or more embodiments described herein may be implemented in conjunction with any other type of computing environment now known or later developed.

[0126] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with the service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0127] The features are as follows:

[0128] On-Demand Self-Service: Cloud customers can automatically provision server time and computing power, such as network storage, as needed, without the need for unilateral, human interaction with the service provider.

[0129] Broad network access: Cloud capabilities are available over the network and can be accessed using standard mechanisms, facilitating usage by heterogeneous thin- or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0130] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model. Different physical and virtual resources are dynamically allocated and reallocated according to demand. There is a sense of location independence, consumers typically have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction they can specify the location (e.g. country, state, and / or data center).

[0131] Rapid Elasticity: Cloud capacity can be rapidly and elastically provisioned automatically in one or more cases, quickly scaled out, and quickly released to quickly scale in. Capacity available for provisioning can appear to consumers as unlimited and available for purchase in any quantity at any time.

[0132] Metered Services: Cloud systems leverage metering to automatically control and optimize resource usage at one or more levels of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and / or active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services utilized.

[0133] The service model is as follows:

[0134] SaaS (Software as a Service): The capability provided to the consumer is the use of the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, storage, or individual application functionality, or any combination thereof, except for the possibility of limited user-specific application configuration settings.

[0135] PaaS (Platform as a Service): The capability provided to a customer is to deploy applications that the customer creates or acquires, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The customer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, and / or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0136] Infrastructure as a Service (IaaS): The capability provided to a customer is the provisioning of processing, storage, network, or other basic computing resources, or a combination thereof, onto which the customer can deploy and run any software, which may include operating systems and applications. The customer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0137] The deployment model is as follows:

[0138] Private Cloud: This cloud infrastructure is operated solely for the organization. It can be managed by the organization or a third party and can exist on-premise or off-premise.

[0139] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community that has a shared concern (e.g., mission, security requirements, policy and / or compliance considerations). It can be managed by the organization or a third party and can exist on-premise or off-premise.

[0140] Public Cloud: This cloud infrastructure is available for use by general users or large industry organizations and is owned by an organization that sells cloud services.

[0141] Hybrid Cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain unique entities but are joined together by standardized or proprietary technologies that allow for the portability of data and applications (e.g., cloud bursting to balance the load between clouds).

[0142] A cloud computing environment is a service-oriented environment with an emphasis on statelessness, loose coupling, modularity, and / or semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0143] Additionally, the non-limiting system 100, and / or the exemplary operating environment 800, may be associated with or included in a data analysis system, a data processing system, a graph analysis system, a graph processing system, a big data system, a social network system, a voice recognition system, an image recognition system, a graphical modeling system, a bioinformatics system, a data compression system, an artificial intelligence system, an authentication system, a syntactic pattern recognition system, a medical system, a health monitoring system, a network system, a computer network system, a communication system, a router system, a server system, a high availability server system (e.g., a telecommunications server system), a web server system, a file server system, a data server system, a disk array system, a powered insertion board system, a cloud-based system, or the like, or any combination thereof. Accordingly, the non-limiting system 100, and / or the exemplary operating environment 800, may be employed using hardware and / or software to solve problems that are highly technical in nature that are not abstract and / or cannot be implemented as a series of mental activities by a human being.

[0144] Referring now to details of one or more aspects depicted in FIG. 9, an exemplary cloud computing environment 950 is illustrated. As depicted, the cloud computing environment 950 includes one or more cloud computing nodes 910 with which local computing devices used by the cloud consumers (e.g., a personal digital assistant (PDA) or cell phone 954A, a desktop computer 954B, a laptop computer 954C, or an automobile computer system 954N, or combinations thereof) can communicate. Although not depicted in FIG. 9, the cloud computing nodes 910 may further comprise a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, or the like, or combinations thereof) with which the local computing devices used by the cloud consumers can communicate. The cloud computing nodes 910 may communicate with each other. The nodes 910 may be physically or virtually grouped together in one or more networks (not depicted), such as in a private cloud, a community cloud, or a hybrid cloud, or combinations thereof, as previously described herein. This allows the cloud computing environment 950 to provide an infrastructure, platform, and / or SaaS that does not require cloud consumers to maintain resources on local computing devices. It is understood that the types of computing devices 954A-N illustrated in Figure 9 are intended to be exemplary only, and that the cloud computing node 910 and cloud computing environment 950 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0145] Referring now to details of one or more aspects depicted in FIG. 10, a set of functional abstraction layers is depicted, such as a set of functional abstraction layers provided by cloud computing environment 950 (FIG. 19). One or more embodiments described herein may be associated with a functional abstraction layer, such as accessible through one or more functional abstraction layers (e.g., hardware and software layer 1060, virtualization layer 1070, management layer 1080, and / or workload layer 1090) described below with reference to FIG. 10. It should be understood in advance that the components, layers, and / or combinations thereof depicted in FIG. 10 are intended to be illustrative only and that the embodiments described herein are not limited thereto. As depicted in the figure, the following layers and / or corresponding functions are provided:

[0146] The hardware and software layer 1060 may include hardware and software components. Examples of hardware components include mainframes 1061, Reduced Instruction Set Computer (RISC) architecture based servers 1062, servers 1063, blade servers 1064, storage devices 1065, and / or networks and / or network components 1066. In one or more embodiments, the software components may include network application server software 1067, quantum platform routing software 1068, and / or quantum software (not shown in FIG. 10).

[0147] The virtualization layer 1070 may comprise an abstraction layer that can provide virtual entities such as virtual servers 1071, virtual storage 1072, virtual networks including virtual private networks 1073, virtual applications and / or operating systems 1074, and / or virtual clients 1075.

[0148] In one example, the management layer 1080 can provide the functionality described below. Resource provisioning 1081 can provide dynamic procurement of computational and other resources that can be utilized to execute tasks within the cloud computing environment. Metering and pricing 1082 can provide cost tracking and / or billing and / or invoicing for the utilization of resources within the cloud computing environment. In one example, the resources can include one or more application software licenses. Security can provide identity verification of cloud consumers and / or tasks, as well as protection of data and / or other resources. User (or entity) portal 1083 can provide consumers and system administrators with access to the cloud computing environment. Service level management 1084 can provide allocation and / or management of cloud computational resources to meet required service levels. Service level agreement (SLA) planning and execution 1085 can provide advance provisioning and procurement of cloud computational resources in anticipation of upcoming demands and in accordance with SLAs.

[0149] The Workload Layer 1090 may represent examples of functionality available in a cloud computing environment. Non-limiting examples of workloads and functionality that may be provided from this layer include mapping and navigation 1091, software development and lifecycle management 1092, virtual classroom instructional delivery 1093, data analytics processing 1094, transaction processing 1095, or application transformation software 1096, or any combination thereof.

[0150] The embodiments described herein may be directed to one or more of a system, method, apparatus, or computer program product, or combinations thereof, at any possible level of technical detail of integration. The computer program product may include a computer readable storage medium that includes computer readable program instructions for causing a processor to execute aspects of one or more of the embodiments described herein. The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, a superconducting storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, or a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media may include portable floppy disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, or mechanically encoded devices such as punch cards or raised structures in grooves on which instructions are recorded, or any suitable combination of these. As used herein, computer readable storage media should not be construed as being signals that are themselves ephemeral, such as radio waves or other freely propagating electromagnetic waves or both, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable) or both, or electrical signals transmitted over wires, or combinations thereof.

[0151] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to each computing device / processing device, or to an external computer or external storage device, or both, over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). This network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing device / processing device receives the computer readable program instructions from the network and forwards those computer readable program instructions for storage on a computer readable storage medium within each computing device / processing device. The computer readable program instructions for carrying out the operations of one or more embodiments described herein can be source and / or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, and / or object-oriented programming languages ​​such as Smalltalk®, C++, and / or procedural programming languages ​​such as the “C” programming language and / or similar programming languages. The computer readable program instructions can be executed entirely on the computer, partially on the computer as a stand-alone software package, partially on the computer or partially on a remote computer, or both, or entirely on a remote computer or a server, or both, or combinations thereof.In the latter scenario, the remote computer may be connected to the computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or both, and / or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In one or more embodiments, to perform aspects of one or more embodiments described herein, electronic circuitry, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), or combinations thereof, may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0152] Aspects of one or more embodiments described herein are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to one or more embodiments described herein. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks included in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, or a combination thereof, to create a machine, such that the instructions, executed via a processor of the computer or other programmable data processing device, can create means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium and can instruct a computer, programmable data processing device, or other device, or a combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored can include a product including instructions that can perform aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. Computer readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device, or combination thereof, such that the instructions, executed on the computer, other programmable apparatus, or other device, or combination thereof, perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable operations to be performed on the computer, other programmable apparatus, or other device, or combination thereof, to generate a computer-implemented process.

[0153] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and / or operation of possible implementations of a system, computer-implementable method, or computer program product, or combination thereof, according to one or more embodiments described herein. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, or a combination thereof, including one or more executable instructions for implementing the specified logical function. In one or more alternative implementations, the functions shown in the blocks may occur in a different order than the order shown in the figures. For example, two blocks shown in succession may be executed substantially simultaneously or may be executed in reverse order, or both, depending on the functionality involved. It is also noted that each block of the block diagrams and / or flowchart illustrations, or combinations of blocks included in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system capable of performing the specified functions and / or operations, or one or more combinations of dedicated hardware and / or computer instructions and / or both.

[0154] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product executed on one or more computers, or both, those skilled in the art will recognize that one or more embodiments herein may also be implemented in combination with one or more other program modules. Typically, a program module includes routines, programs, components, data structures, or the like, or a combination thereof, that perform particular tasks and / or implement particular abstract data types. Furthermore, the computer-implemented methods described above may be practiced using other computer system configurations, including single-processor or multi-processor computer systems or both, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer and / or industrial electronics, or the like, or a combination thereof. The illustrated aspects may also be practiced in distributed computing environments, where tasks are performed by remote processing devices linked through a communications network. However, one or more aspects, if not all aspects, of one or more embodiments described herein may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0155] As used in this application, the terms "component", "system", "platform", "interface", or the like, or combinations thereof, can refer to or include a computer-related entity or an operable machine-related entity that includes one or more specific functions. The entities described herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. As an example, both an application running on a server and the server can be a component. One or more components can reside within a process and / or a thread of execution, and a component can be localized on one computer or distributed between two or more computers, or both. In another example, each component can execute from various computer readable media having various data structures stored thereon. A component may communicate via local and / or remote processes, such as according to signals containing one or more data packets (e.g., data from one component communicating with another component in a local or distributed system, or communicating with other systems via signals over a network such as the Internet, or both). As another example, a component may be a device having a specific function provided by mechanical parts operated by electrical or electronic circuits, and operated by software and / or firmware applications executed by a processor.In such cases, the processor may be internal and / or external to the device and may execute at least a portion of the software and / or firmware applications. As yet another example, the components may be devices that provide certain functionality through electronic components that do not include mechanical parts, and those electronic components may include a processor and / or other means for executing software and / or firmware that provides at least a portion of the functionality of the electronic components. In one aspect, the components may emulate the electronic components via a virtual machine, for example, in a cloud computing system.

[0156] In addition, the term "or" is intended to mean an inclusive or rather than an exclusive or. That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A, or X employs B, or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from the context to cover the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter described herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0157] As used herein, the term "processor" may refer to substantially any computational processing unit and / or device, including, but not limited to, a single-core processor, a single processor with software multithreaded execution capabilities, a multi-core processor, a multi-core processor with software multithreaded execution capabilities, a multi-core processor with hardware multithreading techniques, a parallel platform, or a parallel platform with distributed shared memory, or combinations thereof. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, or discrete hardware components, or any combination thereof, designed to perform the functions described herein. Additionally, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, or gates, or combinations thereof, to optimize space utilization and / or improve the performance of associated equipment. A processor may be implemented as a combination of computing processing units.

[0158] As used herein, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component relating to the operation and functionality of a component are used to refer to a "memory component," an entity embodied in a "memory," or a component comprising a memory. The memory and / or memory components described herein can be either volatile or non-volatile memory, or can include both volatile and non-volatile memory. Examples of non-volatile memory include, but are not limited to, read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can act as an external cache memory, for example. For example, RAM can be available in many forms, such as, but not limited to, synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), or Rambus dynamic RAM (RDRAM), or combinations thereof. Additionally, memory components described in systems and / or computer-implemented methods herein are intended to include memory including, but not limited to, these or any other suitable types of memory or both.

[0159] The foregoing includes merely examples of systems and computer-implemented methods. Of course, for purposes of describing one or more embodiments, it is not possible to describe every conceivable combination of components and / or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and / or permutations of one or more embodiments are possible. Furthermore, to the extent terms such as "including," "having," "possessing," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a similar manner to the term "comprising" as "comprising" is interpreted when used as a transitional term in the claims.

[0160] The description of one or more embodiments is presented for illustrative purposes, but is not intended to be exhaustive and is not limited to the embodiments described herein. Many changes and modifications that do not depart from the scope of the described embodiments will be apparent to those skilled in the art. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond the technology found in the market, or combinations thereof, or to allow other skilled in the art to understand the embodiments described herein, or both.

Claims

1. 1. A system comprising: a memory for storing computer-executable components; and a processor for executing the computer-executable components stored in the memory, the computer-executable components comprising: an identification component that identifies the quantum circuit; and a scheduler component that maps the quantum circuit to a physical qubit layout. Including, the system.

2. The computer executable components include:

10. The system of claim 1, further comprising an acquisition component that acquires the quantum circuit and assigns the quantum circuit to a temporary storage bucket.

3. 3. The system of claim 2, wherein the acquisition component identifies whether the temporary storage bucket meets a threshold such that the scheduler component initiates analysis of the quantum circuit from the temporary storage bucket.

4. 2. The system of claim 1 , wherein the scheduler component compiles a composite circuit that includes the quantum circuit and at least one other quantum circuit, and maps the composite circuit to the physical qubit layout.

5. 2. The system of claim 1, wherein the mapping performed by the scheduler component is based at least in part on a number of shots of the quantum circuit to be executed.

6. 2. The system of claim 1 , wherein the mapping performed by the scheduler component is based at least in part on a number of gates used by the scheduler component to perform the mapping compared to a number of gates of the quantum circuit before the mapping was performed.

7. 2. The system of claim 1 , wherein the mapping performed by the scheduler component is based at least in part on a comparison of an execution time of the quantum circuit compared to a coherence time of the physical qubit layout.

8. 2. The system of claim 1 , wherein based at least in part on variables of the quantum circuit, the scheduler component assigns a first number of physical qubits of the physical qubit layout as a first virtual machine, and wherein the scheduler component further assigns a second number of physical qubits of the physical qubit layout as a second virtual machine, the first number being less than or equal to the second number.

9. identifying, by a system operatively coupled to the processor, a quantum circuit; mapping said quantum circuit to a physical qubit layout by said system; 4. A computer-implemented method comprising:

10. obtaining the quantum circuit by the system; assigning, by the system, the quantum circuit to a temporary storage bucket; The computer-implemented method of claim 9 , further comprising:

11. 11. The computer-implemented method of claim 10, further comprising identifying, by the system, whether the temporary storage bucket meets a threshold such that the system may proceed with analyzing the quantum circuit from the temporary storage bucket.

12. compiling, by the system, a composite circuit that includes the quantum circuit and at least one other quantum circuit; mapping, by the system, the composite circuit onto the physical qubit layout; The computer-implemented method of claim 9 , further comprising:

13. 10. The computer-implemented method of claim 9, further comprising: mapping, by the system, the quantum circuit to the physical qubit layout based at least in part on one or more of: a number of shots of the quantum circuit performed, a number of gates used to perform the mapping compared to a number of gates of the quantum circuit before performing the mapping, or a comparison of a run-time of the quantum circuit compared to a coherence time of the physical qubit layout.

14. Based at least in part on variables of the quantum circuit, allocating, by the system, a first number of physical qubits of the physical qubit layout as a first virtual machine; allocating, by the system, a second number of physical qubits of the physical qubit layout as a second virtual machine; 10. The computer-implemented method of claim 9, further comprising: wherein the first number is less than or equal to the second number.

15. 1. A computer program product that facilitates a process for buffering one or more quantum circuits, the computer program product comprising a computer readable storage medium having program instructions embodied therein, the program instructions being executable by a processor, the processor comprising: identifying, by the processor, a quantum circuit; mapping, by the processor, the quantum circuit onto a physical qubit layout; A computer program product that causes

16. The program instructions are further executable by the processor to cause the processor to: obtaining, by the processor, the quantum circuit; assigning, by the processor, the quantum circuit to a temporary storage bucket; 16. The computer program product of claim 15, further comprising:

17. The program instructions are further executable by the processor to cause the processor to:

20. The computer program product of claim 16, further comprising: causing the processor to identify whether the temporary storage bucket meets a threshold such that the processor's analysis of the quantum circuit from the temporary storage bucket proceeds.

18. The program instructions are further executable by the processor to cause the processor to: compiling, by the processor, a composite circuit that includes the quantum circuit and at least one other quantum circuit; mapping, by the processor, the composite circuit onto the physical qubit layout; 16. The computer program product of claim 15, further comprising:

19. The program instructions are further executable by the processor to cause the processor to:

16. The computer program product of claim 15, further comprising: causing the processor to map the quantum circuit to the physical qubit layout based at least in part on one or more of: a number of shots of the quantum circuit performed; a number of gates used to perform the mapping compared to a number of gates of the quantum circuit before performing the mapping; or a comparison of a run-time of the quantum circuit compared to a coherence time of the physical qubit layout.

20. The program instructions are further executable by the processor to cause the processor to: Based at least in part on variables of the quantum circuit, allocating, by the processor, a first number of physical qubits of the physical qubit layout as a first virtual machine; allocating, by the processor, a second number of physical qubits of the physical qubit layout as a second virtual machine; 16. The computer program product of claim 15, wherein the first number is less than or equal to the second number.

Images