Low via resistance interconnect structure

Abstract

An interconnect structure is disclosed that includes a low via resistance via structure. The via structure includes a barrier layer on sidewalls and at a bottom of the via structure. The interconnect structure also includes a first metal layer. The interconnect structure further includes a second metal layer between the barrier layer and the first metal layer at the bottom of the via structure, the first metal layer and the second metal layer comprising different materials.

Description

[Technical field]

[0001] Certain aspects of the present disclosure relate generally to interconnects, and more particularly, to interconnect structures comprising low via resistance via structures. [Background technology]

[0002] Computing devices are becoming increasingly common in modern society. Early computers were the size of a room and used vacuum tubes to perform basic mathematical calculations. In contrast, modern computing devices are based on integrated circuits (ICs) that provide a variety of complex functions in a relatively small footprint. There is pressure from the market to provide more and more processing options in increasingly smaller products.

[0003] The continued advancement of IC functions in smaller footprints is putting stress on manufacturing capabilities. Current IC manufacturing processes utilize lithography to create ICs in the form of semiconductor dies. An IC may include an active semiconductor layer fabricated in a front-end process. The active semiconductor layer may include various semiconductor devices. An IC may also include an interconnect structure formed adjacent to the active semiconductor layer by a back-end process. The interconnect structure may include multiple metallization layers, each having metal lines disposed within the respective metallization layer to provide connections between different semiconductor devices and external interconnects. Vertical interconnect accesses (vias) may be disposed between the metallization layers to provide connections of the different metallization layers. Summary of the Invention

[0004] Some aspects of the present disclosure provide an interconnect structure for a semiconductor device. The interconnect structure may include a via structure, the via structure comprising a barrier layer on a sidewall and at a bottom of the via structure. The interconnect structure may also include a first metal layer. The interconnect structure may further include a second metal layer between the barrier layer and the first metal layer at the bottom of the via structure, the first metal layer and the second metal layer comprising different materials.

[0005] Some aspects of the present disclosure provide a method of fabricating an interconnect structure for a semiconductor device. The method may include forming a via opening on a first metal layer. The method may also include forming a second metal layer at a bottom of the via opening. The first metal layer and the second metal layer include different materials. The method may also include forming a barrier layer on the sidewalls and at the bottom of the via opening, with the second metal layer between the barrier layer at the bottom of the via opening and the first metal layer. The method may further include depositing a metal in the via opening.

[0006] This summary has outlined features and embodiments of the present disclosure so that the following detailed description may be better understood. Additional features and embodiments of the present disclosure are described below. Those skilled in the art will appreciate that this disclosure may be readily utilized as a basis for modifying or designing other equivalent structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. Features believed to be characteristic of the present disclosure, both as to its organization and method of operation, will be better understood when the following description is considered in conjunction with the accompanying drawings. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended to define the scope of the present disclosure. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an exemplary interconnect structure of a semiconductor device comprising a first metal layer and a second metal layer connected by a via structure having a low via resistance in accordance with some aspects of the present disclosure. [Figure 2A] 2 illustrates an exemplary fabrication process for the interconnect structure 100 of FIG. 1 according to some aspects of the present disclosure. [Figure 2B] 2 illustrates an exemplary fabrication process for the interconnect structure 100 of FIG. 1 according to some aspects of the present disclosure. [Diagram 3] 2 shows a flow chart illustrating an exemplary fabrication process for the interconnect structure 100 of FIG. [Figure 4] FIG. 1 is a block diagram illustrating an example wireless communication system in which an aspect of the present disclosure may be used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Several exemplary aspects of the present disclosure are described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0009] The detailed description set forth below, in conjunction with the accompanying drawings, is intended to describe various aspects and is not intended to represent the only manner in which the concepts described herein may be implemented. The "Description of Embodiments" includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010] FIG. 1 illustrates an exemplary interconnect structure of a semiconductor device comprising a first metal layer and a second metal layer connected by a via structure having a low via resistance according to some aspects of the present disclosure. An interconnect structure 100 is illustrated in FIG. 1. The interconnect structure 100 includes a first etch stop layer 102. As an example, the first etch stop layer 102 may include at least one of silicon carbonitride (SiCN) and aluminum nitride (AlN) with oxygen doped carbon (ODC). The interconnect structure 100 also includes a first dielectric layer 104 on the first etch stop layer 102. As an example, the first dielectric layer 104 may include carbon doped silicon oxide (SiCOH). The interconnect structure 100 also includes a first metal layer 106 in the first dielectric layer 104. As an example, the first metal layer 106 may include copper (Cu). The interconnect structure 100 also includes a first barrier layer 108 between the first dielectric layer 104 and the first metal layer 106. By way of example, the first barrier layer 108 may include a first tantalum nitride (TaN) layer between the first dielectric layer 104 and the first metal layer 106, and a first cobalt (Co) liner between the first TaN layer and the first metal layer 106. The interconnect structure 100 also includes a first cap layer 110 on the first metal layer 106. By way of example, the first cap layer 110 may include Co.

[0011] The interconnect structure 100 also includes a second etch stop layer 112 on the first dielectric layer 104 and on the first cap layer 110. By way of example, the second etch stop layer 112 can include at least one of SiCN and AlN with ODC. The interconnect structure 100 also includes a second dielectric layer 114 on the second etch stop layer 112. By way of example, the second dielectric layer 114 can include SiCOH. The interconnect structure 100 also includes a second metal layer 116 and a via structure 118 in the second dielectric layer 114. By way of example, the second metal layer 116 can include Cu. The via structure 118 is between the first metal layer 106 and the second metal layer 116. The via structure 118 includes a second barrier layer 120 on the sidewalls and bottom of the via structure 118 and a via metal in the via structure 118. As an example, the via metal may include Cu. The second barrier layer 120 is also on the sidewalls and bottom of the second metal layer 116. As an example, the second barrier layer 120 may include a second TaN layer between the second dielectric layer 114 and the via metal and between the second dielectric layer 114 and the second metal layer 116, and a second Co liner on the sidewalls of the via structure 118 and on the sidewalls and bottom of the second metal layer 116, between the second TaN layer and the via metal and between the second TaN layer and the second metal layer 116. At the bottom of the via structure 118, the second TaN layer may be between the first metal layer 106 and the via metal, and the second Co liner may be between the second TaN layer and the via metal.

[0012] The TaN layer may be formed by physical vapor deposition (PVD) at room temperature. PVD is a non-conformal deposition process. The thickness of the PVD TaN layer at the bottom of the via structure 118 is about twice the thickness of the PVD TaN layer on the sidewall of the via structure 118. Alternatively, the TaN layer may be formed by atomic layer deposition (ALD) at about 275° C.. ALD is a conformal deposition process. The thickness of the ALD TaN layer at the bottom of the via structure 118 is about the same as the thickness of the ALD TaN layer on the sidewall of the via structure 118. The thickness of the TaN layer at the bottom of the via structure 118 will affect the via resistance of the via structure 118. The thinner TaN layer at the bottom of the via structure 118 reduces the via resistance of the via structure 118 and improves the performance of the interconnect structure 100. Meanwhile, the PVD TaN layer has better adhesion with the Co liner compared to the ALD TaN layer. Therefore, to achieve both low via resistance and good adhesion with the Co liner, an ALD TaN layer can be combined with a PVD TaN layer to form a second TaN layer in the second barrier layer 120. For example, the second TaN layer can include an ALD TaN layer having a thickness of 16 angstroms (A) and a PVD TaN layer having a thickness of 10 A on the sidewalls of the via structure 118. At the bottom of the via structure 118, the second TaN layer can include an ALD TaN layer having a thickness of 16 A and a PVD TaN layer having a thickness of 20 A. Thus, at the bottom of the via structure 118, the second TaN layer can be about 36 A thick. On the other hand, if the second TaN layer only includes a PVD TaN layer having the same TaN layer thickness (26 A) on the sidewalls of the via structure 118, the thickness of the second TaN layer at the bottom of the via structure 118 is about 52 A, which is thicker than 36 A. Thus, combining an ALD TaN layer with a PVD TaN layer to form the second TaN layer provides both low via resistance and good adhesion with the Co liner. The second TaN layer can include an ALD TaN layer having a thickness of 11A-21A between the second dielectric layer 114 and the second Co liner, and a PVD TaN layer having a thickness of 5A-15A between the ALD TaN layer on the sidewalls of the via structure 118 and the second Co liner.At the bottom of the via structure 118, an ALD TaN layer may be between the first metal layer 106 and the second Co liner, and a PVD TaN layer may be between the ALD TaN layer and the second Co liner. The second Co liner may have a thickness of 20 A to 30 A. Because the first TaN layer does not contribute to the via resistance of the via structure 118, the first TaN layer may include only an ALD TaN layer, only a PVD TaN layer, or a combination of ALD and PVD TaN layers.

[0013] As mentioned above, ALD may be carried out at about 275° C. This temperature is -6 / K) and Cu(16.5×10 -6 10 / K), generates stress at the interface between the ALD TaN layer at the bottom of the via structure 118 and the Cu in the first metal layer 106. The generated stress can lead to the formation of voids at the interface and increased via resistance of the via structure 118. To avoid such stress, the interconnect structure 100 also includes a third metal layer 122 between the ALD TaN layer at the bottom of the via structure 118 and the first metal layer 106. By way of example, the third metal layer 122 has a thermal expansion coefficient of 7×10 -6The third metal layer 122 may include a metal material having a thermal expansion coefficient less than 1 / K, such as tungsten (W), molybdenum (Mo), chromium (Cr), osmium (Os), zirconium (Zr), hafnium (Hf), rhenium (Re), cerium (Ce), tantalum (Ta), ruthenium (Ru), iridium (Ir), and praseodymium (Pr). The third metal layer 122 may have a thickness less than 5 nanometers (nm). The top surface of the third metal layer 122 may be flush with or below the top surface of the second etch stop layer 112. The above-mentioned metal materials can be grown at room temperature and achieve good adhesion with Cu through metallic bonding. Because the above-mentioned metal materials have a similar thermal expansion coefficient to TaN, the adhesion of an ALD TaN layer on these metal materials is better than the adhesion of an ALD TaN layer on Cu. Thus, the third metal layer 122 creates less stress at the interface between the ALD TaN layer at the bottom of the via structure 118 and the Cu in the first metal layer 106. The third metal layer 122 helps to eliminate voids at the interface and reduce the via resistance of the via structure 118. The interconnect structure 100 further includes a second cap layer 124 on the second metal layer 116. As an example, the second cap layer 124 may include Co.

[0014] As described above, according to some aspects of the present disclosure, the combination of the ALD TaN layer and the PVD TaN layer at the bottom of the via structure 118, together with the third metal layer 122, reduces the via resistance of the via structure 118 and improves the performance of the interconnect structure 100.

[0015] 2A-2B illustrate an exemplary fabrication process for the interconnect structure 100 of FIG. 1 according to some embodiments of the present disclosure. In FIG. 2A, stage 200(1) includes forming trench and via openings 202 in an interconnect structure of a semiconductor device. As an example, the interconnect structure may include a first etch stop layer 204. The first etch stop layer 204 may include at least one of SiCN and AlN with ODC. The interconnect structure may also include a first dielectric layer 206 on the first etch stop layer 204. The first dielectric layer 206 may include SiCOH. The interconnect structure may also include a first metal layer 208 in the first dielectric layer 206. The first metal layer 208 may include Cu. The interconnect structure may also include a first barrier layer 210 between the first dielectric layer 206 and the first metal layer 208. The first barrier layer 210 may include a first TaN layer between the first dielectric layer 206 and the first metal layer 208, and a first Co liner between the first TaN layer and the first metal layer 208. The interconnect structure may also include a first cap layer 212 on the first metal layer 208. The first cap layer 212 may include Co. The interconnect structure may also include a second etch stop layer 214 on the first dielectric layer 206 and on the first cap layer 212. The second etch stop layer 214 may include at least one of SiCN and AlN with ODC. The interconnect structure may further include a second dielectric layer 216 on the second etch stop layer 214. The second dielectric layer 216 may include SiCOH. The trench and via opening 202 is formed in the second dielectric layer 216 through the second etch stop layer 214 and the first cap layer 212. The trench and via opening 202 extends into the first metal layer 208 to form a recess in the first metal layer 208. By way of example, the trench and via opening 202 may be formed by a dual damascene process.

[0016] 2A, stage 200(2) includes forming a second metal layer 218 on the first metal layer 208 at the bottom of the trench and via opening 202. By way of example, the second metal layer 218 may be formed of any of a variety of metals, including metals such as W, Mo, Cr, Os, Zr, Hf, Re, Ce, Ta, Ru, Ir, and Pr, with a 7×10 -6 The second metal layer 218 may include a metallic material having a thermal expansion coefficient less than 1 / K. The second metal layer 218 may have a thickness less than 5 nm. The top surface of the second metal layer 218 may be flush with or below the top surface of the second etch stop layer 214. As an example, the second metal layer 218 may be formed by selective deposition, such as electroless deposition, at room temperature and may achieve good adhesion with Cu in the first metal layer 208 via metallic bonding.

[0017] In FIG. 2B, stage 200(3) includes forming a second barrier layer 220 on the sidewalls of the trench and via openings 202 and on the second metal layer 218. As an example, the second barrier layer 220 may include a second TaN layer on the sidewalls of the trench and via openings 202 and on the second metal layer 218, and a second Co liner on the second TaN layer. The second TaN layer may be formed by ALD TaN having a thickness of 11A-21A, and then by PVD TaN having a thickness of 5A-15A on the sidewalls of the trench and via openings 202. A second Co liner may then be formed by chemical vapor deposition (CVD) on the PVD TaN. The second Co liner may have a thickness of 20A-30A.

[0018] As mentioned above, PVD is a non-conformal deposition process. The thickness of the PVD TaN layer on the second metal layer 218 is approximately twice the thickness of the PVD TaN layer on the sidewalls of the trench and via opening 202. ALD is a conformal deposition process. The thickness of the ALD TaN layer on the second metal layer 218 is approximately the same as the thickness of the ALD TaN layer on the sidewalls of the trench and via opening 202. The thickness of the second TaN layer on the second metal layer 218 will affect the via resistance. A thinner second TaN layer on the second metal layer 218 reduces the via resistance and improves the performance of the interconnect structure. Meanwhile, the PVD TaN layer has better adhesion with the Co liner compared to the ALD TaN layer. Therefore, a combination of ALD TaN and PVD TaN can be used to form the second TaN layer to achieve both low via resistance and good adhesion with the Co liner. Even though ALD is performed at about 275° C., less stress will be generated at the interface between the second TaN layer and the second metal layer 218 because the second metal layer 218 has a similar thermal expansion coefficient to TaN. The introduction of the second metal layer 218 between the second TaN layer and the first metal layer 208 helps to eliminate voids at the bottom of the trench and via openings 202 and reduce the via resistance. Thus, the performance of the interconnect structure will be improved.

[0019] 2B, stage 200(4) includes depositing a third metal in the trench and via openings 202. By way of example, the third metal may include Cu. Stage 200(4) also includes chemical mechanical polishing (CMP) of the third metal and the second dielectric layer 216. Stage 200(4) further includes forming a second cap layer 222 on the third metal. By way of example, the second cap layer 222 may include Co.

[0020] 3 shows a flow chart 300 illustrating an exemplary fabrication process for the interconnect structure 100 of FIG. 1. Block 302 includes forming a via opening on a first metal layer. Block 304 includes forming a second metal layer at the bottom of the via opening. Block 306 includes forming a barrier layer on the sidewalls and bottom of the via opening, with the second metal layer between the barrier layer and the first metal layer at the bottom of the via opening. Block 308 includes depositing metal in the via opening to form the interconnect structure 100.

[0021] Interconnect structures including low via resistance via structures according to some aspects disclosed herein may be provided or incorporated into any electronic device, examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, and drones.

[0022] FIG. 4 is a block diagram illustrating an example wireless communication system 400 in which an aspect of the present disclosure may be used. For illustrative purposes, FIG. 4 shows three remote units 420, 430, and 450 and two base stations 440. It will be appreciated that the wireless communication system may have more remote units and base stations. The remote units 420, 430, and 450 include integrated circuit (IC) devices 425A, 425C, and 425B that may include the disclosed interconnect structures. It will be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed interconnect structures. FIG. 4 shows forward link signals 480 from the base station 440 to the remote units 420, 430, and 450, and reverse link signals 490 from the remote units 420, 430, and 450 to the base station 440.

[0023] In FIG. 4, remote unit 420 is shown as a mobile phone, remote unit 430 is shown as a portable computer, and remote unit 450 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, handheld personal communication system (PCS) units, portable data units such as PDAs, fixed location data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading equipment, or other communication devices that store or retrieve data or computer instructions, or combinations thereof. Although FIG. 4 illustrates remote units according to some aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Some aspects of the present disclosure may be suitably utilized in many devices, including the disclosed interconnect structures.

[0024] The following numbered clauses describe example implementations.

[0025] Clause 1: An interconnect structure for a semiconductor device, comprising: a via structure having a barrier layer on a sidewall and a bottom of the via structure; a first metal layer; and a second metal layer between the barrier layer and the first metal layer at the bottom of the via structure, wherein the first metal layer and the second metal layer comprise different materials.

[0026] Clause 2. The interconnect structure of clause 1, wherein the barrier layer comprises tantalum nitride (TaN) and cobalt (Co).

[0027] Clause 3: The interconnect structure of clause 1 or clause 2, wherein the first metal layer comprises copper (Cu).

[0028] Clause 4: The second metal layer is 7×10 -6 4. The interconnect structure of any one of clauses 1 to 3, comprising a metallic material having a thermal expansion coefficient of less than 1 / K.

[0029] Clause 5. The interconnect structure of clause 4, wherein the metallic material comprises at least one of tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru).

[0030] Clause 6: The interconnect structure of any one of clauses 1 to 5, wherein the second metal layer has a thickness of less than 5 nanometers.

[0031] Clause 7: The interconnect structure of any one of clauses 1 to 6, further comprising a cap layer on the first metal layer.

[0032] Clause 8: The interconnect structure of clause 7, wherein the cap layer comprises Co.

[0033] Clause 9: The interconnect structure of clause 7 or clause 8, further comprising an etch stop layer on the cap layer.

[0034] Clause 10: The interconnect structure of clause 9, wherein a top surface of the second metal layer is coplanar with or below a top surface of the etch stop layer.

[0035] Clause 11: The interconnect structure of clause 9 or clause 10, wherein the etch stop layer comprises at least one of silicon carbonitride (SiCN) and aluminum nitride (AlN) with oxygen doped carbon (ODC).

[0036] Clause 12: A method of fabricating an interconnect structure for a semiconductor device, the method comprising: forming a via opening on a first metal layer; forming a second metal layer at a bottom of the via opening, the first metal layer and the second metal layer comprising different materials; forming a barrier layer on sidewalls and at a bottom of the via opening, the second metal layer being between the barrier layer at the bottom of the via opening and the first metal layer; and depositing metal in the via opening.

[0037] Clause 13: The method of clause 12, wherein the barrier layer comprises tantalum nitride (TaN) and cobalt (Co).

[0038] Clause 14: The method of clause 13, wherein the TaN in the barrier layer comprises TaN formed by atomic layer deposition (ALD) and physical vapor deposition (PVD).

[0039] Clause 15. The method of any one of clauses 12 to 14, wherein the first metal layer comprises copper (Cu).

[0040] Clause 16: The second metal layer is 7×10 -6 16. The method of any one of clauses 12 to 15, comprising a metallic material having a thermal expansion coefficient of less than 1 / K.

[0041] Clause 17. The method of clause 16, wherein the metallic material comprises at least one of tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru).

[0042] Clause 18: The method of any one of clauses 12 to 17, wherein the second metal layer is formed by electroless deposition.

[0043] Clause 19: The method of any one of clauses 12 to 18, further comprising forming a cap layer on the metal in the via opening.

[0044] Clause 20. The method of clause 19, wherein the cap layer comprises Co.

[0045] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with certain aspects of the disclosure herein may be implemented as electronic hardware, as instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The devices described herein may be utilized in circuits, hardware components, ICs, or IC chips, as examples. The memories disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may realize the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0046] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in any flow chart diagram, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0047] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and features disclosed herein. [Explanation of symbols]

[0048] 100 Interconnect Structure 102 First Etch Stop Layer 104 First Dielectric Layer 106 First Metal Layer 108 First Barrier Layer 110 First Cap Layer 112 Second etch stop layer 114 Second Dielectric Layer 116 Second Metal Layer 118 Via Structure 120 Second Barrier Layer 122 Third Metal Layer 124 Second Cap Layer 200 stages 202 via opening 204 First Etch Stop Layer 206 First Dielectric Layer 208 First Metal Layer 210 First Barrier Layer 212 First Cap Layer 214 Second Etch Stop Layer 216 Second Dielectric Layer 218 Second Metal Layer 220 Second Barrier Layer 222 Second Cap Layer 400 Wireless Communication System 420 Remote Unit 425A Device 425B Device 425C Device 430 Remote Unit 440 base station 450 Remote Unit 480 forward link signal 490 Reverse Link Signal

Claims

1. 1. An interconnect structure for a semiconductor device, comprising: a via structure comprising a barrier layer on the sidewalls and at the bottom of the via structure; a first metal layer; a second metal layer between the barrier layer and the first metal layer at the bottom of the via structure; wherein the first metal layer and the second metal layer comprise different materials.

2. 2. The interconnect structure of claim 1, wherein said barrier layer comprises tantalum nitride (TaN) and cobalt (Co).

3. The interconnect structure of claim 1 , wherein the first metal layer comprises copper (Cu).

4. The second metal layer is 7×10 －６ / K, 2. The interconnect structure of claim 1, wherein the metallic material comprises at least one of tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru).

5. 10. The interconnect structure of claim 1, wherein the second metal layer has a thickness of less than 5 nanometers.

6. The interconnect structure of claim 1 further comprising a cap layer on said first metal layer.

7. The interconnect structure of claim 6 wherein said cap layer comprises Co.

8. The interconnect structure of claim 6 further comprising an etch stop layer on said cap layer.

9. 9. The interconnect structure of claim 8, wherein a top surface of the second metal layer is coplanar with or below a top surface of the etch stop layer.

10. 10. The interconnect structure of claim 9, wherein the etch stop layer comprises at least one of silicon carbonitride (SiCN) and aluminum nitride (AlN) with oxygen doped carbon (ODC).

11. 1. A method for fabricating an interconnect structure for a semiconductor device, comprising: forming a via opening on the first metal layer; forming a second metal layer at a bottom of the via opening, the first metal layer and the second metal layer comprising different materials; forming a barrier layer on the sidewalls and at the bottom of the via opening, the second metal layer being between the barrier layer at the bottom of the via opening and the first metal layer; depositing metal within the via opening; A method comprising:

12. the barrier layer comprises tantalum nitride (TaN) and cobalt (Co); 12. The method of claim 11, wherein the TaN in the barrier layer comprises TaN formed by atomic layer deposition (ALD) and physical vapor deposition (PVD).

13. The method of claim 11 , wherein the first metal layer comprises copper (Cu).

14. The second metal layer is 7×10 －６ / K, The method of claim 11 , wherein the metallic material comprises at least one of tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru).

15. The method of claim 11 , further comprising forming a cap layer over the metal in the via opening.

Images