Highly selective and uniform dielectric etching

Abstract

Various embodiments herein relate to methods and apparatus for etching features in a substrate. The features are often etched in connection with the formation of DRAM or other memory devices. The features are etched in dielectric materials, which often include silicon oxide. The features are etched using a chemistry that includes a metal-containing gas, such as tungsten hexafluoride. Other metal-containing gases are typically used as deposition gases (e.g., to deposit metal-containing films), but may also be used during etching. Advantageously, including a metal-containing gas in the etch chemistry can increase the selectivity of the etch and / or improve feature-to-feature uniformity (e.g., LCDU).

Description

[Technical Field]

[0001] [Incorporated by reference] A PCT application is filed concurrently herewith as part of this application. Each application to which this application claims the benefit or priority of a concurrently filed PCT application is incorporated herein by reference in its entirety for all purposes.

[0002] Embodiments herein relate to methods and apparatus for fabricating semiconductor devices, and more particularly to methods and apparatus for etching high aspect ratio features in dielectric materials with high selectivity to mask materials that define the features. [Background technology]

[0003] One process commonly used in the fabrication of semiconductor devices is the formation of etched cylinders or other recessed features in dielectric materials. For example, such processes are commonly used in memory applications, such as the fabrication of dynamic random access memory (DRAM) structures. As the semiconductor industry advances and device dimensions shrink, such features become increasingly difficult to etch uniformly, especially for high aspect ratio cylinders with narrow widths and / or large depths.

[0004] The Background Art set forth herein is intended to present the contents of the present disclosure generally, and the inventions of the presently named inventors are not admitted expressly or impliedly as prior art to the present disclosure to the extent that they are described in this Background Art section and in a descriptive manner that does not constitute prior art at the time of filing. Summary of the Invention

[0005] Certain embodiments herein relate to methods and apparatus for etching features in dielectric materials on semiconductor substrates, for example, for the formation of memory structures.

[0006] One aspect of an embodiment of the present disclosure relates to a method for etching features in a substrate during fabrication of an electronic device. Such a method may include receiving a substrate on a substrate support in a reaction chamber, the substrate comprising a silicon- and oxygen-containing material beneath a mask layer having a pattern thereon, and etching features in the silicon- and oxygen-containing material by exposing the substrate to a plasma in the reaction chamber. The plasma may be generated from a plasma-generating gas comprising a metal-containing gas, one or more fluorocarbons, and oxygen. The plasma may be a capacitively coupled plasma, and the substrate may be biased. The capacitively coupled plasma may be generated at an RF power level of about 9 kW or less per substrate, or about 6 kW or less per substrate, with an excitation frequency of about 13 to 169 MHz. The substrate may be biased at an RF power level of about 40 kW or less per substrate, about 30 kW or less per substrate, or about 20 kW or less per substrate, with a bias frequency of about 50 kHz to 10 MHz. In some embodiments, the metal-containing gas is a metal-containing halide, such as a metal fluoride. Examples include tungsten hexafluoride, rhenium hexafluoride, molybdenum hexafluoride, tantalum pentafluoride, vanadium fluoride, and combinations thereof. In some embodiments, the metal-containing gas is a tungsten-containing gas, such as tungsten hexafluoride.

[0007] In certain embodiments, the capacitively coupled plasma is generated at an RF power level of about 0.2 kW or less per substrate. In certain embodiments, the capacitively coupled plasma is generated at an RF power level of about 0.1 kW or less per substrate. In certain embodiments, the substrate is biased at an RF power level of about 0.5 kW or less per substrate. In certain embodiments, the substrate is biased at an RF power level of about 0.3 kW or less per substrate. In certain embodiments, the excitation frequency is about 60 MHz and the bias frequency is about 400 kHz.

[0008] In some examples, the plasma generating gas comprises about 0.01-10% by volume of a metal-containing gas. In particular embodiments, the plasma generating gas comprises C4F8. In particular embodiments, the substrate support is maintained at a temperature of about -100-150°C or about -30-150°C while the substrate is exposed to the plasma.

[0009] In certain embodiments, the silicon-oxygen containing material comprises silicon oxide. In some embodiments, the mask layer comprises carbon, polysilicon, silicon nitride, silicon oxynitride, or a combination thereof.

[0010] In certain embodiments, the features have a critical dimension of about 200 nm or less. In some embodiments, the etching is performed at least in one direction by about 1 / 200 nm. -1 A plurality of features are formed having a feature density of at least about 0.3. In some embodiments, the features are etched with a silicon-oxygen-containing material-to-mask selectivity of at least about 0.3. In some embodiments, the etching forms a plurality of features, the plurality of features having local dimensional uniformity (defined as an integer multiple of the standard deviation or range of CDs [maximum CD - minimum CD]). In some cases, the specified range of LCDU values ​​corresponds to LCDU = sample standard deviation of CDs of the plurality of features (population of etched features). By way of example, LCDU may be about 200 Å or less, about 100 Å or less, about 50 Å or less, or about 20 Å or less, or about 15 Å or less, or about 10 Å or less, or about 5 Å or less.

[0011] In certain embodiments, the metal-containing gas dissociates in the plasma into metal-containing fragments and halogen-containing fragments (eg, fluorine-containing fragments).

[0012] In certain embodiments, the electronic device includes a memory device.

[0013] In many cases, the flow rate of the metal-containing gas in the plasma-generating gas is relatively low. For example, in some cases, the flow rate of the metal-containing gas (e.g., metal halide) in the plasma-generating gas may be about 20 sccm or less. In some cases, the flow rate of the metal-containing gas (e.g., metal halide) in the plasma-generating gas may be about 10 sccm or less. In certain cases, the flow rate of the metal-containing gas (e.g., metal halide) in the plasma-generating gas is about 2 sccm or less. Process gas flow rates and plasma power values ​​are listed for a single 300 mm wafer. For processing larger or smaller substrates, or for simultaneous processing of multiple substrates, these values ​​may be modified as needed.

[0014] This method can provide one or more benefits. For example, in various embodiments, the method provides an etch selectivity ratio of at least about 0.3, or at least about 1, where the selectivity ratio is defined as the etch rate of silicon oxide divided by the etch rate of the mask layer (wherein the mask comprises carbon, polysilicon, silicon nitride, silicon oxynitride, or a combination thereof).

[0015] In another aspect of an embodiment of the present disclosure, an apparatus for etching features in a dielectric material on a substrate during fabrication of a memory structure is provided. The apparatus includes a reaction chamber including an inlet for introducing process gases into the reaction chamber and an outlet for removing material from the reaction chamber, a substrate support, and a plasma source configured to provide a capacitively coupled plasma to the reaction chamber; and a controller configured to receive a substrate on the substrate support and expose the substrate to the plasma in the reaction chamber to cause etching of features in the dielectric material. The controller may be further configured to cause operation in which the plasma is generated from a gas including a metal-containing gas, one or more fluorocarbons, and oxygen, the plasma is a capacitively coupled plasma, a bias may be applied to the substrate, the capacitively coupled plasma is generated at an excitation frequency of about 13 to 169 MHz at an RF power level of about 9 kW per substrate or less, or about 6 kW per substrate or less, and the substrate is biased at an RF power level of about 40 kW per substrate or less, about 30 kW per substrate or less, or about 20 kW per substrate or less, and a bias frequency of about 50 kHz to 10 MHz.

[0016] These and other features are described below with reference to the associated drawings. [Brief explanation of the drawings]

[0017] [Figure 1A] The partially finished DRAM structure when features are etched into the dielectric material. [Figure 1B] The partially finished DRAM structure when features are etched into the dielectric material. [Figure 1C] The partially finished DRAM structure when features are etched into the dielectric material.

[0018] [Figure 2] Capped partial etch feature.

[0019] [Figure 3A]1 is a flowchart illustrating a method for etching features for a DRAM structure, according to certain embodiments.

[0020] [Figure 3B] 3B is a partially fabricated DRAM structure prior to the method of FIG. 3A. [Figure 3C] 3B is a partially finished DRAM structure after the method of FIG. 3A.

[0021] [Figure 4] 1 is a diagram of an etching system that may be used to perform etching of a substrate in accordance with certain embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0022] 1A-1C illustrate cross-sectional views of a semi-finished structure, such as a DRAM or other memory structure, represented as features 102 etched into a dielectric material layer 104 on a substrate 101. The figures are not drawn to scale. FIG. 1A shows the substrate 101 before etching begins. The substrate includes a patterned mask layer 106 covering the dielectric material layer 104. An underlayer 107 is provided below the dielectric material layer 104. In various embodiments, the patterned mask layer 106 may have a thickness of approximately 5-800 nm, and the dielectric material layer 104 may have a thickness of approximately 60 nm-1.5 μm. The mask material may be composed of carbon, polysilicon, silicon nitride, silicon oxynitride, combinations thereof, or another mask material known in the art. In some embodiments, the mask is composed of two or more sublayers, which may be of different materials. The dielectric material layer 104 typically includes a silicon-oxygen-containing material, such as silicon oxide (e.g., silicon dioxide). The underlayer 107 may be, for example, a silicon nitride layer. In some cases, the dielectric material layer 104 may be a material stack including one or more silicon oxide layers and one or more silicon nitride layers. The one or more silicon nitride layers may be relatively thin compared to the one or more silicon oxide layers. In a particular example, the dielectric material layer 104 includes an upper layer of silicon nitride and a lower layer of silicon oxide (the oxide is thicker than the nitride). In a similar example, the dielectric material layer 104 further includes a lower layer of silicon nitride, with a silicon oxide layer sandwiched between the upper and lower silicon nitride layers. The pitch between adjacent instances of the features 102 may be about 60 nm or less. In some embodiments, the feature density is about 1 / 60 nm -1 , or even denser. This corresponds to a center-to-center feature separation of 60 nm or less. The critical dimensions (e.g., diameters) of the features, including feature 102, may be about 200 nm or less (e.g., about 10-30 nm), or in some cases about 15-30 nm.

[0023] A substrate 101, as shown in FIG. 1A, is provided to a semiconductor processing apparatus for etching. A suitable apparatus is described below. After the substrate is introduced into the processing apparatus, a plasma is generated within the processing apparatus. The plasma may directly interact with the substrate, causing etching on the substrate. After a period of time, features 102 begin to form in the dielectric material layer 104, as shown in FIG. 1B. The patterned mask layer 106 is somewhat resistant to the etching conditions, but will undergo some etching / erosion during this process. Therefore, the patterned mask layer 106 shown in FIG. 1B is thinner than the patterned mask layer 106 shown in FIG. 1A.

[0024] FIG. 1C shows substrate 101 immediately after prolonged exposure to etching conditions has resulted in nearly complete removal of patterned mask layer 106. At this point, feature 102 is deeper than shown in FIG. 1B, but has not yet penetrated dielectric material layer 104. Because patterned mask layer 106 has been nearly completely removed, feature 102 is not etched any deeper. Further etching would substantially and unnecessarily erode dielectric material layer 104. FIGS. 1A-1C illustrate one of the problems frequently encountered when etching features. Often, various processing issues limit the thickness of the mask layer that can be used for a particular application. This limits the depth of features that can be formed using the patterned mask layer.

[0025] One approach to etching deeper holes without increasing the mask thickness is to increase the selectivity of the etching process. Selectivity is calculated as the ratio of the etch rate of the dielectric material to the etch rate of the mask material. For example, if the dielectric material etches three times faster than the mask material, the etching process has a selectivity ratio of 3:1. The selectivity of the etching process can be increased by increasing the etch rate of the dielectric material relative to the etch rate of the mask layer. Similarly, the selectivity can be increased by decreasing the etch rate of the mask layer relative to the etch rate of the dielectric material.

[0026] Several techniques are available for increasing the selectivity of an etching process. However, these techniques typically exhibit other drawbacks, such as increased capping. Capping, also known as etch stop, occurs when a recessed feature becomes blocked / clogged during the etching process. Once a feature is clogged, no further etching can be achieved for that feature. Figure 2 shows a clogged feature 202 during an etching process. The feature 202 is formed in a dielectric material layer 204 formed between an underlying layer 207 and a patterned mask layer 206. During etching, the etching chemistry interacts with the dielectric material layer 204 to remove the dielectric material and form a fluorocarbon-based polymer 208 that deposits on the sidewalls of the feature 202. Often, the fluorocarbon-based polymer 208 deposits near the top of the feature 202. If the deposition is excessive, it can cause the blockage / clogging problem shown in Figure 2.

[0027] Many techniques for increasing etch selectivity result in the formation of relatively large amounts of fluorocarbon-based polymers on or near the patterned mask layer. This has the desired effect of increasing selectivity by reducing the etch rate of the mask material. However, it can also have the undesirable effect of capping when there is excess fluorocarbon-based polymer. In practice, the tradeoff between selectivity and capping limits how deep high aspect ratio features can be etched in dielectric materials.

[0028] As the semiconductor industry aggressively shrinks feature density (e.g., pitch), tolerance for feature-to-feature variation decreases. Features may be dense holes, ovals (common in DRAM capacitor masks), or line-and-space patterns formed by multiple patterning methods or EUV lithography. Etching such dense features into dielectric layers (e.g., SiO2) is often limited not only by selectivity to the mask but also by high feature-to-feature variability, which can be expressed as a parameter called local dimension uniformity (LCDU). LCDU may be defined as a multiple of the sample standard deviation of the feature CD (typically 1x or 3x) or by the range of feature CDs (maximum CD minus minimum CD). Improving LCDU and increasing selectivity are becoming increasingly important. Examples of applications of the disclosed etching process include open and short contact applications in DRAM masks.

[0029] Surprisingly, the inventors have developed an etching method that improves both selectivity and LCDU. Such a method enables the formation of dense features while using relatively thin mask layers. Thus, the approach described herein is advantageous for both etching dense features without risk of capping the features and minimizing the amount of mask material required.

[0030] In certain embodiments, the process windows described herein provide an etch selectivity (dielectric:mask) of at least about 0.3, or at least about 1.0, or at least about 1.5. -1In certain cases defining a feature density of , the process window herein provides LCDU values ​​(with LCDU defined as the sample standard deviation of feature CD in a population of etched features) of up to about 200 Å, up to about 100 Å or less, up to about 50 Å, or up to about 20 Å, or up to about 15 Å, or up to about 10 Å, or up to about 5 Å. Note that useful LCDU values ​​may depend on the average dimension (e.g., CD) of holes or other features of interest. Generally, larger features exhibit larger LCDU values. In certain embodiments having feature CDs of up to about 20 nm, LCDU values ​​may be about 10 Å or less. In certain embodiments having feature CDs of about 200 nm or less, LCDU values ​​may be about 100 Å or less.

[0031] To form metal-based films using vapor deposition processes, metal fluorides are sometimes used in deposition gases. Traditionally, metal-containing gases have not been used in etching. The addition of metal-containing gases to etching chemistries, when provided at suitable flow rates and with suitable plasma conditions, increases the etch selectivity of dielectric materials (e.g., often silicon oxide) and / or reduces feature-to-feature non-uniformity. The present disclosure is not limited to a particular metal-containing gas. In various embodiments, the metal-containing gas comprises a metal-containing halide, such as a metal fluoride. In some embodiments, the metal-containing gas comprises a tetravalent metal fluoride, a pentavalent metal fluoride, or a hexavalent metal fluoride. Examples of metal fluorides include tungsten fluoride (e.g., tungsten hexafluoride), rhenium fluoride (e.g., rhenium hexafluoride and rhenium heptafluoride), molybdenum fluoride (e.g., molybdenum tetrafluoride, molybdenum pentafluoride, and molybdenum hexafluoride), tantalum fluoride (e.g., tantalum pentafluoride), vanadium fluoride (e.g., vanadium tetrafluoride and vanadium pentafluoride), and combinations thereof. In some embodiments, the metal-containing gas is a tungsten-containing gas, such as tungsten hexafluoride. In many embodiments, the metal-containing halide is a gas at the etching temperature, although one or more specific compounds may be used herein for purposes of discussion. Unless otherwise clear from the context, a description of a specific compound may extend to one or more other metal-containing gases (such as those listed above).

[0032] One factor why metal-containing gases are not typically used in etching chemistries, particularly for etching recessed features in DRAM devices, is that such features are not typically filled with metal or metal-containing materials. Therefore, any remaining metal (e.g., on the sidewalls or field areas of the feature) can be problematic in subsequent processing. Furthermore, such material would need to be removed before subsequent processing can occur.

[0033] FIG. 3A is a flowchart illustrating a method of etching features in a dielectric material, according to certain embodiments. The method of FIG. 3A is described with respect to the structure shown in FIGS. 3B and 3C. FIGS. 3B and 3C illustrate a partially fabricated memory structure when a feature 302 has been etched into a dielectric material layer 304 on a substrate 301. FIG. 3B illustrates the substrate 301 before etching begins, and FIG. 3C illustrates the substrate 301 after etching has been completed. The substrate may have the dimensions described above with respect to FIGS. 1A-1C. Similarly, the dielectric material layer 304 may have the structure / composition described with respect to the dielectric material layer 104 of FIGS. 1A-1C. The substrate 301 includes a patterned mask layer 306 on the dielectric material layer 304. An underlayer 307 is provided below the dielectric material layer 304. In certain examples, the patterned mask layer 306 is polysilicon and may have a thickness of about 40-1000 nm (e.g., about 50-100 nm). In other embodiments, patterned mask layer 306 is amorphous carbon and may have a thickness of about 50-1200 nm (e.g., about 100-250 nm). In some cases, other mask materials may be used. In some embodiments, dielectric material layer 304 includes silicon oxide, such as SiO2. In some such cases, dielectric material layer 304 is a (typically relatively thick) single layer of silicon oxide. In some cases, dielectric material layer 304 may include additional layers (e.g., one or more silicon nitride layers) that may be interleaved between thick silicon oxide layers. Underlayer 307 may be, for example, silicon nitride. The final etch depth is underlayer 307, as shown in FIG. 3C.

[0034] The method of Figure 3A begins in operation 351, where a substrate 301, as shown in Figure 3B, is provided to a reaction chamber of a semiconductor processing apparatus. Suitable apparatus are further described below. After the substrate is introduced into the reaction chamber, in operation 353, a plasma-generating gas is provided to the reaction chamber, a plasma is generated from the plasma-generating gas, and the plasma etches the dielectric material.

[0035] The composition of the etching process gas may vary within certain ranges. In some embodiments, the flow rate of the metal fluoride or other metal-containing gas may be at least about 0.1 sccm, or at least about 0.2 sccm, or at least about 0.5 sccm, or at least about 1 sccm. In these or other cases, the flow rate of the metal fluoride or other metal-containing gas may be about 20 sccm or less (e.g., about 10 sccm or less, or about 5 sccm or less, or about 2 sccm or less, or about 1 sccm or less).

[0036] The plasma-generating gas may also include one or more materials conventionally used to etch dielectric materials. Such materials typically include fluorocarbons and hydrofluorocarbons (e.g., C3F8, C4F8, C4F6, CH2F2, CH3F, CHF3, C5F8, C6F6, CF4, etc.). Such materials may also include oxidizers (e.g., O2, O3, CO, CO2, COS, etc.). The total flow rate of the plasma-generating gas may range from about 50 to 500 sccm in various cases. In some cases, one or more fluorocarbon sources may be mixed (before or after delivery to the reaction chamber) to provide, for example, a desired ratio of carbon and fluorine. The plasma-generating gas may also include one or more inert species. In various cases, a metal fluoride or other metal-containing gas may represent at least about 0.01%, or at least about 0.05%, or at least about 0.1%, or at least about 0.5%, or at least about 1% of the plasma-generating gas volumetric flow rate. In these or other cases, tungsten hexafluoride or other metal-containing gas may represent about 10% or less, or about 5% or less, or about 1% or less, or about 0.05% or less of the plasma-generating gas volumetric flow rate. x F y In some embodiments including a metal fluoride, the metal fluoride comprises about 0.01-10% by volume of the total process gas, or about 0.1-10% by volume of the total process gas. The process gas may be supplied to the processing chamber in a pulsed or non-pulsed manner.

[0037] In certain embodiments, the plasma generating gas may include about 0.1-15 sccm of a metal-containing gas, about 0-50 sccm of C4F6, about 0-70 sccm of C4F8, about 0-70 sccm of O2, and about 0-30 sccm of CH2F2.

[0038] In various cases, the following conditions may be used to generate the plasma: The plasma may be a capacitively coupled plasma. The plasma may be generated at an excitation frequency of about 13-169 MHz (e.g., about 40-100 MHz (e.g., 60 MHz in certain cases)) and a power level of about 10 kW or less per 300 mm substrate. In some cases, the power level is relatively low (e.g., about 0 W-9 kW, or about 0 W-6 kW, or about 0.2 kW or less, or about 0.1 kW or less (all per 300 mm substrate)). The plasma power may be pulsed or non-pulsed.

[0039] A bias may be applied to the substrate, for example, to promote a vertical etch rate. The bias may be applied to the substrate at a frequency of about 50 kHz to 10 MHz, or about 200 kHz to 4 MHz (e.g., about 400 kHz in certain cases), and at a power level of about 0 W to 40 kW per 300 mm substrate, about 0 W to 20 kW per 300 mm substrate, or about 1 to 20 kW per 300 mm substrate. In some cases, the power level used to apply the bias to the substrate is about 0.5 kW or less per 300 mm substrate, or about 0.3 kW or less per 300 mm substrate. The plasma power that applies the bias to the substrate may be pulsed or non-pulsed.

[0040] The pressure in the reaction chamber may be about 1-100 mTorr, or about 10-20 mTorr. In some cases, the pressure may remain relatively low during etching but may be increased to a higher pressure (e.g., 100-500 mTorr, or 300-500 mTorr, or 400-500 mTorr) for a cleaning operation to clean the interior walls of the reaction chamber. The substrate support on which the substrate is provided may be maintained (e.g., through heating and / or cooling) at a temperature of about -100-150°C, or about -30-100°C. In some cases, the substrate support is maintained at a temperature of at least about -20°C, or at least about 0°C, or at least about 20°C, or at least about 50°C, or at least about 60°C, or at least about 70°C. In these or other cases, the substrate support may be maintained at a temperature of about 150° C. or less, or about 120° C. or less, or about 100° C. or less, or about 80° C. or less, or about 50° C. or less, or about 20° C. or less, or about 0° C. or less, or about −20° C. or less, or about −50° C. These temperatures may relate to the controlled temperature of the substrate support while the substrate is exposed to the plasma.

[0041] After a period of time, features 302 begin to form in the dielectric material layer 304. After the features reach their final etch depth, as shown in FIG. 3C, the substrate 301 is removed from the reaction chamber in operation 355. Compared to conventional approaches, the method described with reference to FIGS. 3A-3C can form more uniformly dense and / or deep features without increasing the mask height. Including a metal fluoride or other metal-containing gas in the plasma generating gas improves the etch selectivity when provided at an appropriate flow rate and under appropriate plasma conditions. Advantageously, this improvement in selectivity does not increase the rate at which features are capped.

[0042] Device The methods described herein may be implemented by any suitable system and apparatus. Suitable apparatus include hardware for performing process operations and a system controller having instructions for controlling the process operations in accordance with the present embodiments. For example, in some embodiments, the hardware may include one or more process stations included in a processing tool.

[0043] FIG. 4 is a diagram of an embodiment of a system 400 illustrating the implementation of an etching process as described herein. The system 400 includes a host computer 402, a low frequency (LF) radio frequency (RF) generator, a high frequency (HF) RF generator, a matcher, and a plasma chamber 404. By way of example, the LFRF generator has an operating frequency of 400 kilohertz (kHz) or 2 megahertz (MHz). By way of example, the HFRF generator has an operating frequency of 13.56 MHz, or 27 MHz, or 60 MHz. Note that the operating frequency of the HFRF generator is greater than the operating frequency of the LFRF generator. The LFRF generator is an example of a primary generator, and the HFRF generator is an example of a secondary generator.

[0044] A matcher is a network of circuit components (e.g., inductors, capacitors, and resistors). For example, a matcher may include one or more shunt circuits and one or more series circuits. Each shunt circuit has one or more circuit components, and each series circuit has one or more circuit components. A first branch circuit including one or more shunt circuits, one or more series circuits, or a combination thereof is connected between the input 410 of the matcher and the output 414 of the matcher. A second branch circuit including one or more shunt circuits, one or more series circuits, or a combination thereof is connected between the input 412 and the output 414 of the matcher.

[0045] Examples of the host computer 402 include a desktop computer, a laptop computer, a controller, a tablet, and a smartphone. The host computer 402 includes a processor 406 and a memory device 408. The processor 406 is connected to the memory device 408. Examples of a processor as used herein include a microprocessor, an application specific integrated circuit (ASIC), a programmable logic device (PLD), an embedded microcontroller, and a central processing unit (CPU). Examples of a memory device as used herein include a read-only memory (ROM), a random access memory (RAM), a flash memory, a storage disk array, a hard disk, etc.

[0046] The plasma chamber 404 includes a substrate support 416, such as an electrostatic chuck (ESC). The ESC includes a lower electrode 418. The plasma chamber 404 further includes a showerhead 420 in which an upper electrode 422 is embedded. The lower electrode 418 and the upper electrode 422 are each made of a metal, such as aluminum or an aluminum alloy. The bottom surface of the showerhead 420 is positioned above and opposite the top surface of the substrate support 416. A substrate S is placed on the top surface of the substrate 416. An example of the substrate S is a semiconductor wafer having one or more partially fabricated integrated circuits thereon.

[0047] System 400 further includes a gas source 424 and, optionally, another gas source 426. Examples of gas sources include containers for storing one or more chemical compounds. For example, gas source 424 stores a metal-containing compound such as tungsten hexafluoride, while gas source 426 stores a fluorocarbon. To indicate that different compounds or groups of compounds may be used, the diagram shows "chemical A" and "chemical B." As another example, gas source 426 stores chemical B (fluorocarbon and nitrogen trifluoride). System 400 further includes a driver A and a driver B. Examples of drivers include one or more transistors. For example, the driver includes one or more field-effect transistors (FETs) connected to each other.

[0048] The LFRF generator has an output 428 connected to an input 410 via RF cable RFC1, which is connected to a first branch of the matching circuit 410. The HFRF generator also has an output 430 connected to an input 412 via RF cable RFC2, which is connected to a second branch of the matching circuit 410. The first and second branches are connected to each other and to an output 414. The output 414 is connected to a lower electrode 418 via an RF transmission line RFT. The upper electrode 422 is connected to a standard potential, such as ground.

[0049] The processor 406 is also connected to the LFRF generator via a transfer cable TC1 and to the HFRF generator via a transfer cable TC2. Examples of transfer cables include cables used for serial transfer of data, cables used for parallel transfer of data, and universal serial bus (USB) cables.

[0050] The gas source 424 is connected to the showerhead 420 via a gas supply line 432. The gas source 426 is also connected to the showerhead 420 via a gas supply line 434. Examples of the gas supply line include a gas duct and / or a gas pipe. The processor 406 is connected to a driver A and also to a driver B. The driver A is connected to a valve 436, which is connected to the gas supply line 432. For example, the valve 436 is installed inside the gas supply line 432. Similarly, the driver B is connected to a valve 437, which is connected to the gas supply line 434. Examples of the valve include a valve assembly. For example, the valve assembly includes a stationary valve plate and a movable valve plate. The movable valve plate slides relative to the stationary valve plate. The stationary valve plate has a plurality of openings. Another example of the valve assembly includes a solenoid valve.

[0051] The processor 406 generates a recipe signal having a recipe and provides it to the LFRF generator over the transfer cable TC1. An example of a recipe provided to the LFRF generator is the frequency and parameter levels of the LFRF signal 438 (e.g., a sinusoidal signal) generated by the LFRF generator. Upon receiving the recipe, the LFRF generator stores the recipe.

[0052] Similarly, the processor 406 generates a recipe signal having a recipe and provides it to the HFRF generator over the transfer cable TC2. An example of a recipe provided to the HFRF generator is the frequency and parameter levels of the HFRF signal 440 (e.g., a sinusoidal signal) generated by the HFRF generator. Upon receiving the recipe, the HFRF generator stores the recipe.

[0053] The processor 406 generates a trigger signal (e.g., a signal having a single digital pulse) and transmits the trigger signal to the LFRF generator via the transmission cable TC1, and also transmits the trigger signal to the HFRF generator via the transmission cable TC2.

[0054] In response to receiving the trigger signal, the LFRF generator generates an RF signal 438 and transmits the RF signal 438 through output 428 and RF cable RFC1 to input 410. Also, in response to receiving the trigger signal, the HFRF generator generates an RF signal 440 and transmits the RF signal 440 through output 430 and RF cable RFC2 to input 412.

[0055] A first branch of the matcher 414 receives an RF signal 438 through an input 410, and a second branch of the matcher 414 receives an RF signal 440 through an input 412. The matcher 414 modifies the impedance of the RF signals 438 and 440 to output first and second modified RF signals. The impedance of the RF signals 438 and 440 is modified by matching the impedance of a load connected to the output 414 with the impedance of a source connected to the inputs 410 and 412. Examples of loads include the RF transmission line RFT and the plasma chamber 404. Examples of sources include RF cables RFC1 and RFC2, and an LFRF generator and an HFRF generator. The matcher 414 further combines (e.g., sums or adds) the first and second modified RF signals to output a modified RF signal 442 at the output 414. The modified RF signal 442 is provided to the lower electrode 418 through the RF transmission line RFT.

[0056] Furthermore, when the modified RF signal 442 is provided to the plasma chamber 404, one or more chemical compounds, including a metal-containing gas, are supplied to the plasma chamber 404. For example, the processor 306 generates and sends a close drive signal to a driver A. Upon receiving the close drive signal, the driver A generates and provides a current signal to the valve 336 to close the valve 336. For example, when a current signal is provided to the valve 336 to close the valve 336, a field, such as a magnetic field, is generated to rotate the movable valve plate of the valve 336 relative to the stationary valve plate of the valve 336, closing all openings in the stationary valve plate. When the valve 336 is closed, the chemical A stored in the gas source 324 is not supplied to the showerhead 320 through the gas supply line 332. Thus, when the valve 336 is closed, the application of the chemical A to the plasma chamber 304 is stopped.

[0057] As another example, processor 306 generates and sends a full open drive signal to driver A. Upon receiving the full open drive signal, driver A generates and provides a current signal to valve 336 to fully open valve 336. For example, when a current signal is provided to valve 336 to fully open valve 336, a field, such as a magnetic field, is generated to rotate a movable valve plate of valve 336 relative to a stationary valve plate of valve 336, opening all openings in the stationary valve plate. When valve 336 is fully open, chemical A stored in gas source 324 is supplied to showerhead 320 through gas supply line 332.

[0058] As yet another example, processor 306 generates and transmits a partial-open drive signal to driver A. Upon receiving the partial-open drive signal, driver A generates a current signal and provides the current signal to valve 336 to partially open valve 336. For example, when a current signal is provided to valve 336 to partially open valve 336, a field, such as a magnetic field, is generated to rotate a movable valve plate of valve 336 relative to a stationary valve plate of valve 336, thereby opening at least one, but not all, openings, or a portion of the openings, of the stationary valve plate. When valve 336 is partially open, chemical A stored in gas source 324 is supplied in small amounts to showerhead 320 through gas supply line 332. For example, the amount of chemical A supplied in small amounts is substantially less than the amount of chemical A supplied when valve 336 is fully open. For another example, the amount of chemical A supplied is substantially less than the amount of chemical A supplied when valve 336 is 0.1 to 10% of the amount of chemical A supplied when valve 336 is fully open. Thus, when valve 336 is partially open, less chemical A is dispensed than when valve 336 is fully open.

[0059] Similarly, by way of example, processor 306 generates and sends a close drive signal to driver B. Upon receiving the close drive signal, driver B generates and provides a current signal to valve 337 to close valve 337. For example, when a current signal is provided to valve 337 to close valve 337, a field, such as a magnetic field, is generated to rotate a movable valve plate of valve 337 relative to a stationary valve plate of valve 337, closing all openings in the stationary valve plate. When valve 337 is closed, chemical B stored in gas source 326 is not supplied to showerhead 320 through gas supply line 334. Thus, when valve 337 is closed, dispensing of chemical B is stopped.

[0060] As another example, processor 306 generates and sends a full open drive signal to driver B. Upon receiving the full open driver signal, driver B generates and provides a current signal to valve 337, causing valve 337 to fully open. For example, when a current signal is provided to valve 337 to fully open it, a field is generated that causes a movable valve plate of valve 337 to rotate relative to a stationary valve plate of valve 337, opening all openings in the stationary valve plate. When valve 337 is fully open, chemical B stored in gas source 326 is supplied to showerhead 320 through gas supply line 334.

[0061] As yet another example, processor 306 generates and transmits a partial-open drive signal to driver B. Upon receiving the partial-open drive signal, driver B generates and provides a current signal to valve 337, causing valve 337 to partially open. For example, when a current signal is provided to valve 337 to partially open valve 337, a field, such as a magnetic field, is generated to rotate a movable valve plate of valve 337 relative to a stationary valve plate of valve 337, thereby opening at least one, but not all, openings, or a portion of the openings, of the stationary valve plate. When valve 337 is partially open, chemical B stored in gas source 326 is supplied in small amounts to showerhead 320 through gas supply line 334. For example, the amount of chemical B supplied in small amounts is substantially less than the amount of chemical B supplied when valve 337 is fully open. For another example, the amount of chemical B supplied is substantially less than the amount of chemical B supplied when valve 337 is fully open when the amount of chemical B is 0.1 to 10% of the amount of chemical B supplied when valve 337 is fully open. Thus, when valve 337 is partially open, less chemical B is dispensed than when valve 337 is fully open.

[0062] In some embodiments, a controller (implemented via or incorporating the processor and / or host computer of FIG. 4 , as appropriate) is part of a system that may be part of the above examples. Such systems may include semiconductor processing equipment with processing tools, chambers, processing platforms, and / or specific processing components (such as wafer pedestals and gas flow systems). These systems may be integrated with electronics for controlling pre-, during-, and post-processing operations of semiconductor wafers or substrates. These electronics may be referred to as “controllers” and may control various components or subcomponents of the system. Depending on the processing requirements and / or type of system, the controller may be programmed to control any of the processes disclosed herein, including process gas supply, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position operation settings, wafer transfer to and from the tool and other transport tools, and / or wafer transfer to and from load locks connected or coupled to the particular system.

[0063] Generally, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in firmware format that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various personalizations (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the operational parameters may be part of a recipe defined by a process engineer to accomplish one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer molds.

[0064] In some embodiments, the controller may be part of or connected to a computer integrated with or otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” that enables remote access of wafer processing, or may be all or part of a fab host computer system. The computer may enable remote access to the system to monitor the progress of manufacturing operations, examine the history of past fabrication operations, examine trends or performance metrics from multiple fabrication operations, and modify parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings that are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters are specific to the type of process to be performed and the type of tool to which the controller is connected or controlled. Thus, as noted above, the controller may be distributed, for example, by including one or more separate controllers networked together and cooperating toward a common purpose, such as the processes and controls described herein. An example of a controller distributed for such purposes would be one or more integrated circuits in the chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and in combination communicate with one or more integrated circuits that control the processes in the chamber.

[0065] Without limitation, exemplary systems may include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems related to or usable in the fabrication and / or manufacturing of semiconductor wafers.

[0066] As noted above, depending on the processing steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools installed throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0067] Additional Embodiments The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes for, for example, the fabrication or manufacture of semiconductor devices, displays, LEDs, solar panels, etc. Typically, although not necessarily, such tools / processes will be used or performed together in a common fabrication facility.

[0068] Lithographic patterning of films typically includes some or all of the following steps, each of which can be performed using several possible tools: (1) applying photoresist to a workpiece (e.g., a substrate with a silicon nitride film formed thereon) using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate, furnace, or other suitable curing tool; (3) exposing the photoresist to visible, UV, or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove it using a tool such as a wet bench or spray developer, thereby patterning it; (5) transferring the resist pattern to an underlying film or workpiece using a dry etching tool or a plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0069] It should be understood that the structures and / or techniques described herein are exemplary in nature and are susceptible to several variations, and therefore, the specific embodiments or examples should not be construed in a limiting sense. A particular procedure or method described herein may represent any number of one or more process steps. As such, various illustrated acts may be performed in the order described, in other orders, in parallel, or in some cases omitted. Similarly, the order of the processes described above may be changed. Certain descriptions are incorporated herein by reference. It is understood that any disclaimer or disclaimer in such descriptions does not necessarily apply to the embodiments described herein. Similarly, features described as required in such descriptions may be omitted in embodiments herein.

[0070] The subject matter of the present disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems, and configurations, as well as other features, functions, acts, and / or characteristics described herein, and all equivalents thereof.

[0071] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “semi-finished integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “semi-finished integrated circuit” can refer to a silicon wafer at any stage of the many integrated circuit fabrication stages. Wafers or substrates used in the semiconductor device industry are typically 200 mm, 300 mm, or 450 mm in diameter. The above description assumes, but is not limited to, that the embodiments are implemented on wafers. Workpieces may have various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize embodiments of the present disclosure include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like. Unless defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% of the associated value.

[0072] In the above description, several specific details are set forth to provide a thorough understanding of the present embodiments. Embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. While the embodiments of the present disclosure will be described in conjunction with specific embodiments, it will be understood that no limitation of the embodiments of the present disclosure is intended.

Claims

1. 1. A method of etching features in a substrate during the fabrication of an electronic device, comprising: receiving a substrate on a substrate support in a reaction chamber, the substrate comprising a silicon-oxygen containing material beneath a mask layer having a pattern thereon; Etching the features into the silicon-oxygen containing material by exposing the substrate to a plasma in the reaction chamber; the plasma is generated from a plasma generating gas comprising a metal-containing gas, one or more fluorocarbons, and oxygen; the plasma is a capacitively coupled plasma, the substrate is biased; the capacitively coupled plasma is generated at an excitation frequency of about 13-169 MHz at an RF power level of about 9 kW or less per substrate; A method comprising:

2. 2. The method of claim 1 , The method wherein the substrate is biased at a bias frequency between about 50 kHz and 10 MHz with an RF power level of about 40 kW or less per substrate while exposing the substrate to the plasma.

3. 2. The method of claim 1 , The method, wherein the capacitively coupled plasma is generated at an RF power level of about 0.2 kW or less per substrate.

4. 2. The method of claim 1 , The method, wherein the capacitively coupled plasma is generated at an RF power level of about 0.1 kW or less per substrate.

5. 2. The method of claim 1 , The method wherein the substrate is biased at an RF power level of about 0.5 kW or less per substrate.

6. 2. The method of claim 1 , The method wherein the substrate is biased at an RF power level of about 0.3 kW or less per substrate.

7. 2. The method of claim 1 , The method of claim 1, wherein the plasma generating gas comprises about 0.01 to 10 volume percent of a metal halide.

8. 2. The method of claim 1 , The plasma generating gas is 4 F 8 A method comprising:

9. 2. The method of claim 1 , The method, wherein the excitation frequency is about 60 MHz and the bias frequency is about 400 kHz.

10. 2. The method of claim 1 , The method wherein the substrate support is maintained at a temperature of about -100 to 150° C. while the substrate is exposed to the plasma.

11. 2. The method of claim 1 , The method of claim 1, wherein the silicon-oxygen containing material comprises silicon oxide.

12. 2. The method of claim 1 , The method, wherein the mask layer comprises carbon, polysilicon, silicon nitride, silicon oxynitride, or a combination thereof.

13. 2. The method of claim 1 , The method, wherein the features have a critical dimension of about 200 nm or less in at least one direction.

14. 2. The method of claim 1 , The etching is at least in one direction about 1 / 200 nm -1 forming a plurality of features having a feature density equal to or greater than 100 nm;

15. 2. The method of claim 1 , The method, wherein the features are etched with a selectivity ratio of the silicon-oxygen containing material to the mask of at least about 0.

3.

16. 2. The method of claim 1 , The method, wherein the etching forms a plurality of features, the plurality of features having a local dimensional uniformity (LCDU) of up to about 100 Å, where LCDU is the sample standard deviation of the CD of the plurality of etched features.

17. 2. The method of claim 1 , The method of claim 1, wherein the metal-containing gas comprises a metal fluoride.

18. 20. The method of claim 17, The method of claim 1, wherein the metal fluoride comprises rhenium hexafluoride, tungsten hexafluoride, molybdenum hexafluoride, tantalum pentafluoride, vanadium pentafluoride, and combinations thereof.

19. 2. The method of claim 1 , The method, wherein the electronic device includes a memory device.

20. 1. An apparatus for etching features in a dielectric material on a substrate, comprising: (a) a reaction chamber, comprising: an inlet for introducing a process gas into the reaction chamber; an outlet for removing materials from the reaction chamber; A substrate support; a plasma source configured to provide a plasma to the reaction chamber, the plasma being a capacitively coupled plasma; and (b) a controller, receiving the substrate on the substrate support; configured to expose the substrate to a plasma in the reaction chamber to etch the feature into the dielectric material; the plasma is generated from a plasma generating gas comprising a metal-containing gas, one or more fluorocarbons, and oxygen; the plasma is a capacitively coupled plasma, the substrate is biased; a controller, wherein the capacitively coupled plasma is generated at an excitation frequency between about 13-169 MHz at an RF power level of about 9 kW or less per substrate; An apparatus comprising:

21. 21. The apparatus of claim 20, The substrate is biased at a bias frequency of about 50 kHz to 10 MHz at an RF power level of about 40 kW or less per substrate.

22. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured to generate the capacitively coupled plasma at an RF power level of about 0.2 kW or less per substrate.

23. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured to cause the capacitively coupled plasma to be generated at an RF power level of about 0.1 kW or less per substrate.

24. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured to cause the substrates to be biased at an RF power level of about 0.5 kW or less per substrate.

25. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured to cause the substrate to be biased at an RF power level of about 0.3 kW or less per substrate.

26. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured such that the plasma generating gas comprises 0.01 to 10 volume percent of a metal halide.

27. 21. The apparatus of claim 20, The controller may further comprise a controller for controlling the plasma generating gas to be C 4 F 8 An apparatus configured to include:

28. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured to set the excitation frequency to about 60 MHz and the bias frequency to about 400 kHz.

29. 21. The apparatus of claim 20, The apparatus, wherein the controller is further configured to maintain the substrate support at a temperature of about -100 to 150° C. while the substrate is exposed to the plasma.

30. 21. The apparatus of claim 20, The apparatus, wherein the metal-containing gas comprises a metal fluoride.

31. 31. The apparatus of claim 30, The metal fluoride includes rhenium hexafluoride, tungsten hexafluoride, molybdenum hexafluoride, tantalum pentafluoride, and vanadium pentafluoride.

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