Two-stage solid-state matching

Abstract

The present disclosure describes a system, method, and apparatus for a two-stage solid-state matcher having a load side and a source side, a first coarse stage and a second high precision stage, the first coarse stage being coupled between the second high precision stage and the load side, the second high precision stage being coupled between the source side and an input of the first coarse stage, the first coarse stage comprising at least one switched variable reactance element, the first coarse stage being configured to map a load impedance connected to the load side to a first number of intermediate impedances at the input of the first coarse stage, and the second high precision stage being configured to map at least one of the intermediate impedances to a second number of input impedances at the source side.

Description

[Technical field]

[0001] (Claiming priority under 35 USC Section 119) This application for patent claims priority to Provisional Application No. 63 / 299,766, entitled "TWO-STAGE SOLID STATE MATCH," filed on January 14, 2022, which is assigned to the assignee hereof and expressly incorporated herein by reference.

[0002] Field of the Disclosure The present disclosure relates generally to power systems and, more particularly, but not by way of limitation, to impedance matching networks. [Background technology]

[0003] 2. Description of Related Art In the context of plasma processing, manufacturers use plasma processing chambers that utilize power (e.g., radio frequency (RF) power) to generate a plasma. To achieve efficient power transfer between the generator and the plasma load, an impedance matching network ("matching network") is often used to match the load impedance to a desired input impedance, typically (but not always) 50 Ω. The plasma load impedance may vary depending on variables such as generator frequency, power, chamber pressure, gas composition, and plasma ignition. The matching network accounts for these variations in the load impedance by varying a reactive element (e.g., a variable capacitor) to maintain the desired input impedance.

[0004] RF matching networks have utilized variable vacuum capacitors for many years, but solid-state matchers (SSMs), which include discrete capacitors that are switched on and off to modify the value of the capacitor within the SSM, are now an alternative technology that is gaining popularity because SSMs can be switched more quickly, and faster switching can allow for faster matching, which allows for better process control.

[0005] However, in some situations, it may be difficult to design an SSM with power handling and efficiency comparable to an equivalent vacuum variable capacitor-based matcher. Conventional approaches involving two variable reactance elements may fail to achieve similar performance to a vacuum variable capacitor matcher. Thus, there is a need for refined SSM topologies that can help improve the power handling and efficiency of SSMs.

[0006] A description provided in the Description of Related Art section should not be considered prior art merely because it is mentioned in or associated with this section. The Description of Related Art section may include information that describes one or more aspects of the present technology. Summary of the Invention [Means for solving the problem]

[0007] Summary of the Disclosure The following presents a simplified summary related to one or more aspects and / or embodiments disclosed herein. As such, the following summary should not be considered an extensive overview related to all envisioned aspects and / or embodiments, nor should the following summary be considered to identify key or critical elements related to all envisioned aspects and / or embodiments or to delimit the scope associated with any particular aspect and / or embodiment. Thus, the following summary has the sole purpose of presenting certain concepts related to one or more aspects and / or embodiments related to the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

[0008] Aspects of the present disclosure generally relate to systems, methods, and apparatus for solid-state matcher (SSM) circuits, and more specifically, for impedance matching networks with two or more stages, including at least a first stage for transforming a load impedance into an intermediate impedance and a second stage for transforming the intermediate impedance into a desired input impedance (e.g., 50Ω). In some embodiments, two of the stages may also be referred to as coarse and fine (or fine) stages, respectively (and even intermediate stages, etc., if there are more than two stages). The use of the first stage (or coarse matching stage) helps to limit the number of switches that need to handle very high voltages and currents to a small number (e.g., 3 kV and 60 A RMS values ​​and 20 switches), which helps to optimize the overall efficiency of the SSM circuit. Due to the limited number of switches, the initial impedance transformation is followed by a second stage for transforming the intermediate impedance into a target input impedance, e.g., 50Ω. In some embodiments, one or more other intermediate stages (e.g., a third stage, a fourth stage, etc.) may be employed between the first (coarse) stage and the second (high) stage.

[0009] In some implementations, the coarse stage contains the minimum number of elements required to transform the load impedance to the intermediate impedance, at which point the maximum voltage and current to match the intermediate impedance to the desired input impedance (e.g., 50Ω) is significantly reduced. In one exemplary implementation, illustrated in FIG. 9A, the load impedance is: [ka] With the load current varied at 100 V and the RMS load current being 60 A, the coarse (first) stage series element 922 may be exposed to an RMS voltage of 3,300 V, while the series variable reactance element in the precision (second) stage 910 may be exposed to an RMS voltage of 1,000 V. This represents a 3.3-fold reduction in voltage stress. Since losses may be proportional to the square of the voltage, other things being equal, this may equate to roughly a 10-fold reduction in losses. Similarly, the coarse (first) stage shunt element 930 may be exposed to an RMS voltage of 1,100 V, while the shunt variable reactance element (C VAR_2) may be subjected to an RMS voltage of 363V. This may represent roughly a three-fold reduction in voltage stress and a nine-fold reduction in losses. Similarly, the coarse series element 922 may be subjected to an RMS current of 60A, while the variable reactance element in the precision second stage 910 may experience a current of 9-47A. To illustrate why it is beneficial to subsequently use a precision stage after a coarse first stage, consider the predicted efficiency of 81.9% for 0.6+j21Ω, as shown in FIG. 11D. In this example, the RMS load current is 60A (the calculated efficiency is not current dependent, the specific current is used simply to illustrate the calculation), which means that 2,160W is delivered to the load and 478W is dissipated in the matcher (2,160 / (2,160+478)=0.819). To match this load to 50Ω, the coarse series element 922 reactance is set to -10Ω (i.e., an impedance of -j10Ω). The corresponding series resistance of the coarse series element 922 (corresponding to a reactance of -10Ω) is 0.116Ω (as will be shown later). This means that the power dissipated in the coarse series element 922 is [ka] This means that if a high precision first series element is used (rather than a coarse precision first stage followed by a high precision second stage), then approximately 7 divide by 7 reactance values ​​(i.e., reactances of -7, -4.7, -3.1, -2, -1.3, -0.9, and -0.6 if a sub-binary sequence such as taught in U.S. Pat. No. 10,623,012 is used) may be required to match the load impedance to the desired input impedance with the desired accuracy. The additional series resistance resulting from the 7 divide by values ​​may be approximately 0.07 Ω, assuming a similar design to reactance module 925 of FIG. 9A. The additional losses from these divide by 7 series elements may then be approximately 60 2×0.07=252W. The resulting efficiency of the matcher, if all other losses in the matcher are ignored, would be 2,160 / (2,160+418+252)=0.763. The efficiency would therefore be reduced from 81.9% to no more than 76.3%, i.e., a reduction in efficiency of 5.6%. As shown in FIG. 11D, this would reduce the best efficiency of the SSM below that of a comparable conventional matcher. As this embodiment illustrates, the use of a coarse first stage followed by a high-precision second stage is highly beneficial in the design of a high-efficiency SSM. U.S. Pat. No. 10,623,012 is incorporated herein by reference in its entirety.

[0010] A vacuum variable capacitor based matcher with a series inductor to match a capacitive load (e.g., 5-j30Ω) to a real input impedance (e.g., 50+j0Ω) may be limited by the inefficiency of the series inductor. For example, matching a reactance ranging from -50 to +50 to a 50Ω input impedance requires the series element reactance in the L-topology matcher to range from -50 to +75 (some reduction in range is possible by limiting the load resistance range, but not much). Assuming the variable capacitor can achieve a maximum reactance of -10Ω, a series inductor reactance of 85Ω is required. This limits the efficiency for all loads, regardless of whether inductance is required. According to aspects of the present disclosure, an SSM circuit with two or more stages, including at least a first coarse stage and a second finer stage, may help reduce this inefficiency by switching the inductor sections off when not needed.

[0011] In some embodiments, a second stage (or final stage) can be employed for final impedance matching to the target input impedance. In some cases, the second stage may utilize variable reactance elements (e.g., switched variable reactive elements, including variable inductors, variable capacitors, capacitive and / or inductive elements) with finer adjustment than the coarse first stage to precisely match the intermediate impedance to the target input impedance. For example, when the target input impedance is Z t Without adjusting the second stage, the coarse first stage may not be precise enough for many applications, e.g. [ka] So, the input impedance Z in While it may be possible to match only the first stage, by adjusting a variable reactance element in the second stage, e.g. [ka] It may be possible to ensure that

[0012] In some aspects, the techniques described herein relate to an apparatus that includes an impedance matching network having a load side and a source side, and a first coarse stage and a second high precision stage, where the first coarse stage is coupled between the second high precision stage and the load side, and the second high precision stage is coupled between the source side and an input of the first coarse stage, the first coarse stage including at least one switched variable reactance element, the first coarse stage configured to map a load impedance connected to the load side to a first number of intermediate impedances at the input of the first coarse stage, and the second high precision stage configured to map at least one of the intermediate impedances to a second number of input impedances at the source side.

[0013] In some aspects, the techniques described herein relate to an apparatus, wherein at least one switchable variable reactance element includes at least two reactances including an inductive reactance and a capacitive reactance, and the at least two reactances are configured to be switched on and off by the at least one switchable variable reactance element.

[0014] In some aspects, the techniques described herein relate to an apparatus wherein the second number exceeds the first number.

[0015] In some aspects, the techniques described herein relate to an apparatus, wherein the first number of intermediate impedances is less than or equal to 400.

[0016] In some aspects, the techniques described herein relate to an apparatus, wherein the second number of input impedances is at least 100,000.

[0017] In some aspects, the techniques described herein relate to an apparatus, wherein the at least one switched variable reactance element includes a plurality of switched variable reactance elements including at least a first switched variable reactance element and a second switched variable reactance element, wherein the first switched variable reactance element and the second switched variable reactance element each include at least two reactances of opposite sign configured to be switched on and off of individual ones of the first switched variable reactance element and the second switched variable reactance element, wherein the first switched variable reactance element is a coarse series element coupled to a load side, and the second switched variable reactance element is a coarse shunt element coupled between the coarse series element and the second high precision stage.

[0018] In some aspects, the techniques described herein relate to an apparatus, in which a coarse shunt element includes at least a first switch arranged in series with an inductive reactance and a second switch arranged in series with a capacitive reactance.

[0019] In some aspects, the techniques described herein relate to an apparatus, in which a coarse series element includes at least a first switch arranged in parallel with an inductive reactance and a second switch arranged in parallel with a capacitive reactance.

[0020] In some aspects, the techniques described herein relate to an apparatus, wherein the first coarse stage further includes a plurality of PIN diodes.

[0021] In some aspects, the techniques described herein relate to a method for operating a two-stage solid-state matcher, the method including the steps of determining a load impedance of a load coupled to the two-stage solid-state matcher; identifying a plurality of settings for a coarse first stage of the two-stage solid-state matcher; and, for each of the plurality of settings, calculating an intermediate impedance and an efficiency for the two-stage solid-state matcher when the respective setting is applied to the coarse first stage; identifying a target input impedance; and selecting a setting for the coarse first stage, the selecting step being based at least in part on the target input impedance, the intermediate impedance, and the efficiency, the selecting step further including applying the selected setting to the coarse first stage; and adjusting a high-precision second stage of the two-stage solid-state matcher to convert the intermediate impedance corresponding to the selected setting to the target input impedance.

[0022] In some aspects, the techniques described herein relate to a method, wherein selecting a setting for the coarse first stage includes identifying a subset of a plurality of settings, each setting in the subset corresponding to an intermediate impedance that is mappable to a target input impedance by the fine second stage, and identifying a selected setting from the subset of settings, the selected setting maximizing efficiency of the two-stage solid-state matcher.

[0023] In some aspects, the techniques described herein relate to a method, wherein the number of the plurality of settings is less than 400.

[0024] In some aspects, the techniques described herein relate to a method, wherein the coarse first stage includes at least one switched variable reactance element, the at least one switched variable reactance element including a first switch in parallel with a first reactance and a second switch in parallel with a second reactance, and setting the coarse first stage to a selected setting further includes determining a target reactance for the at least one switched variable reactance element, closing the first switch, and opening the second switch, wherein the first reactance has an opposite sign to that of the target reactance and the second reactance has the same sign as that of the target reactance.

[0025] In some aspects, the techniques described herein relate to a method, wherein a first stage of coarse accuracy includes at least one switched variable reactance element, the at least one switched variable reactance element including a first switch in series with a first reactance and a second switch in series with a second reactance, and setting the first stage of coarse accuracy to a selected setting includes determining a target susceptance for the at least one switched variable reactance element, opening the first switch, and closing the second switch, the first reactance having a susceptance with an opposite sign to that of the target susceptance, and the second reactance having a susceptance with the same sign as that of the target susceptance.

[0026] In some aspects, the techniques described herein relate to a non-transitory tangible computer readable storage medium encoded with processor readable instructions for implementing a method for switching two or more reactances on and off of a first stage of a two-stage solid-state matcher, the method including the steps of determining a load impedance of a load coupled to the two-stage solid-state matcher; and identifying a plurality of settings for the first stage of the two-stage solid-state matcher, the first stage including at least one switched variable reactance element, the at least one switched variable reactance element including two or more reactances, the two or more reactances being at least The method includes the steps of: selecting a setting for the first stage, both of which include a first reactance and a second reactance of opposite signs; selecting a setting for the first stage; and applying the selected setting to the first stage, the applying step including the steps of determining a target reactance for at least one switchable variable reactance element; switching off a first reactance of the two or more reactances, the first reactance having an opposite sign to the target reactance; and switching on a second reactance of the two or more reactances, the second reactance having the same sign as the target reactance.

[0027] In some aspects, the techniques described herein relate to a non-transitory tangible computer-readable storage medium, wherein the two or more reactances include at least one inductive reactance and at least one capacitive reactance, the first reactance being an inductive reactance and the second reactance being a capacitive reactance.

[0028] In some aspects, the techniques described herein relate to a non-transitory tangible computer-readable storage medium, wherein at least one switched variable reactance element includes a first switched variable reactance element, the first switched variable reactance element being a coarse series element, and a second switched variable reactance element, the second switched variable reactance element being a coarse shunt element, wherein the coarse series element and the coarse shunt element each include a plurality of reactances and a plurality of switches.

[0029] In some aspects, the techniques described herein relate to a non-transitory tangible computer readable storage medium, wherein the number of the plurality of settings is less than 400.

[0030] In some aspects, the techniques described herein relate to a non-transitory tangible computer-readable storage medium, wherein the first stage further includes a plurality of PIN diodes.

[0031] In some aspects, the techniques described herein relate to a non-transitory tangible computer-readable storage medium, wherein selecting a setting for the first stage includes identifying a subset of a plurality of settings, each setting in the subset corresponding to an intermediate impedance that is mappable to a target input impedance by a second stage of the two-stage solid-state matcher, and identifying a selected setting from the subset of settings, the selected setting maximizing efficiency of the two-stage solid-state matcher.

[0032] These and other features and characteristics of the present technology, as well as the method of operation and function of the associated elements of construction, and combination with economy of parts and manufacture, will become more apparent upon consideration of the following description and appended claims, with reference to the accompanying drawings, all of which form a part of this specification and in which like reference numerals designate corresponding parts in the various views. It is to be expressly understood, however, that the drawings are for purposes of illustration and description only and are not intended as a definition of the limits of the invention. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. [Brief description of the drawings]

[0033] Various objects and advantages of the present disclosure as well as a more complete understanding will become apparent and will be more readily understood by reference to the following detailed description and appended claims, when considered in conjunction with the accompanying drawings.

[0034] [Figure 1] FIG. 1 is a block diagram illustrating a two-stage solid-state matcher (SSM) comprising a coarse stage and a fine stage in accordance with various aspects of the present disclosure.

[0035] [Diagram 2] FIG. 2 is a block diagram illustrating sections that may be used in an impedance matching network in accordance with various aspects of the disclosure.

[0036] [Diagram 3] FIG. 3 is a block diagram illustrating sections that may be used in an impedance matching network in accordance with various aspects of the disclosure.

[0037] [Figure 4A] FIG. 4A is a block diagram illustrating sections that may be used in an impedance matching network in accordance with various aspects of the disclosure.

[0038] [Figure 4B] FIG. 4B is a block diagram illustrating sections that may be used in an impedance matching network in accordance with various aspects of the disclosure.

[0039] [Diagram 5] FIG. 5 is a block diagram illustrating cascaded sections that may be used in an impedance matching network in accordance with various aspects of the disclosure.

[0040] [Figure 6A] FIG. 6A illustrates a block diagram of a switched variable reactance element in accordance with various aspects of the disclosure.

[0041] [Figure 6B] FIG. 6B illustrates a block diagram of a switched variable reactance element in accordance with various aspects of the disclosure.

[0042] [Figure 7A] FIG. 7A illustrates a schematic diagram of an equivalent circuit for a PIN diode in an on-state in accordance with various aspects of the present disclosure.

[0043] [Figure 7B] FIG. 7B illustrates a schematic diagram of an equivalent circuit for a PIN diode in an off state in accordance with various aspects of the present disclosure.

[0044] [Figure 8A] FIG. 8A illustrates a schematic diagram of an impedance matching network in the prior art that connects a load to a generator.

[0045] [Figure 8B] FIG. 8B illustrates a schematic diagram of an impedance matching network in the prior art that connects a load to a generator.

[0046] [Figure 9A]FIG. 9A illustrates a circuit diagram of a two-stage solid-state matcher comprising a coarse stage and a high-precision or fine stage in accordance with various aspects of the present disclosure.

[0047] [Figure 9B] FIG. 9B depicts N PIN diodes coupled in parallel, which can be used to implement any of the switches of the switched variable reactance element in FIG. 9A, in accordance with various aspects of the disclosure.

[0048] [Figure 9C] FIG. 9C illustrates a switched variable reactance element having reactances of opposite signs in accordance with various aspects of the disclosure.

[0049] [Figure 10A] FIG. 10A illustrates efficiency as a function of coarse stage setting in accordance with various aspects of the present disclosure.

[0050] [Figure 10B] FIG. 10B illustrates intermediate impedance as a function of coarse stage setting in accordance with various aspects of the present disclosure.

[0051] [Figure 10C] FIG. 10C illustrates the medium load reflection coefficient as a function of the coarse stage setting in accordance with various aspects of the present disclosure.

[0052] [Figure 11A] FIG. 11A illustrates a Smith chart showing load reflection coefficients in accordance with various aspects of the present disclosure.

[0053] [Figure 11B] FIG. 11B illustrates a Smith chart showing an intermediate load reflection coefficient in accordance with various aspects of the present disclosure.

[0054] [Figure 11C]FIG. 11C illustrates a Smith chart showing input reflection coefficients in accordance with various aspects of the present disclosure.

[0055] [Figure 11D] FIG. 11D illustrates a conceptual graph showing efficiency versus load reactance for an impedance matching network utilizing a two-stage SSM and a vacuum variable capacitor design in accordance with various aspects of the present disclosure.

[0056] [Figure 12] FIG. 12 illustrates an example of a method for operating a multi-stage solid-state matcher network comprising at least a coarse stage and a fine stage in accordance with various aspects of the present disclosure.

[0057] [Figure 13] FIG. 13 illustrates an example of a method for operating a switched variable reactance element in accordance with various aspects of the disclosure.

[0058] [Figure 14] FIG. 14 illustrates an example of a method for operating a switched variable reactance element in accordance with various aspects of the disclosure.

[0059] [Figure 15] FIG. 15 illustrates a block diagram of a computer system that can be used to implement one or more aspects of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Detailed Description Prior to describing the embodiments in detail, it is convenient to define certain terms as used in this disclosure.

[0061] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0062] Preliminary Note: The flow charts and block diagrams in the following figures illustrate the functionality and operation of possible implementations of a multi-stage solid-state matcher (e.g., a two-stage solid-state matcher) according to various embodiments of the present disclosure. It should be noted that in some alternative implementations, the functions described in each block may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be performed substantially in parallel, or the blocks may sometimes be performed in the reverse order, depending on the functionality involved. For example, the operation of closing at least one switch in parallel with a reactance having an opposite sign to that of the target reactance may be interchanged or performed in parallel with the step of opening at least one switch in parallel with a reactance having the same sign as that of the target reactance.

[0063] 1, shown is an example of a power system 100 including a generator 104, a two-stage solid-state matcher (SSM) 102, and a load 106. In some embodiments, the load 106 may be a plasma load and the generator 104 may be a radio frequency (RF) generator. The two-stage SSM 102 has a load impedance Z L Matching input impedance Z 120 in 140, to which the generator 104 can efficiently deliver power. Because the matcher performs this function more efficiently than possible in the art, a greater percentage of the generator 104 power is delivered to the load. inA typical value for is 50 Ω, but this is not intended to be limiting. Non-50 Ω input impedances are also contemplated in different embodiments, such as 25 Ω, 37.5 Ω, 75 Ω, or even complex impedances such as 30+j40 Ω, which may sometimes be utilized to improve the stability of the power system 100 when the load is a non-linear (e.g., plasma) load. In some cases, a coaxial cable with a characteristic impedance of 50 Ω may be connected between the output of the generator 104 and the input of the SSM 102 without further transforming the impedance presented to the generator away from 50 Ω. When the load 106 is a plasma load, the load impedance Z L may depend on the amount of power delivered to the load. In other words, the load 106 may be an example of a nonlinear load. In the case of a plasma load, the load impedance may further depend on the pressure and / or properties of the gases and materials being processed in the plasma chamber. The two-stage SSM 102 adjusts the load impedance Z by switching reactive elements internal to the SSM 102 in and out of a matcher circuit, which will be further described in connection with FIGS. 6A, 6B, and 9A-14. L reacts to changes in

[0064] In some cases, the two-stage SSM 102 includes a first coarse stage 110 and a second fine or high-precision stage 108. The two-stage SSM 102 first uses the first or coarse stage 110 to calculate the load impedance Z L 120 is the intermediate impedance Z I 130. The high-precision second stage 108 then switches to the intermediate impedance Z I Target input impedance Z 130 in140. The coarse first stage 110 may comprise a sufficient number of switched reactance elements (e.g., shown as switched reactance elements 621, 622, 623 in FIG. 6A and / or switched reactance elements 661, 662, 663 in FIG. 6B) without exceeding the minimum number required to transform the load impedance 120 to the intermediate impedance 130. In some circumstances, the coarse first stage 110 may be exposed to high voltages and currents (e.g., RMS voltages and currents of 3,300V to 60A). Furthermore, by limiting the number of switched reactance elements in the coarse first stage 110, the electrical efficiency of the matching network 102 can be improved as compared to the prior art. The electrical efficiency or efficiency of the SSM 102 is improved by reducing the power leaving the matcher (i.e., the actual (v L i L * ) where v L 124 is a voltage vector at the output of the matching circuit, i L 122 is the matching box output current vector, i L * i L ) and the power going into the matcher (i.e., the actual (v in i in * ) where v in 144 is the voltage vector at the matcher input, i in 142 is the matching box input current vector, i in * i in The load impedance Z L Since the coarse first stage 110 can theoretically assume an infinite number of impedances, but the coarse first stage 110 can assume only a limited number of configurations (e.g., 90 different configurations), the coarse first stage 110 can calculate the load impedance (Z L ) 120 to the target input impedance 140 (e.g., a reflection coefficient as small as 0.3 when the target is <0.05). in -50| / |Z in+50|, with respect to a target input impedance of 50 Ω), the high-precision second stage 108 provides an intermediate impedance Z I 130 is the input impedance Z in It may be employed to convert to 140.

[0065] 2 illustrates a schematic diagram of a section 200 of an SSM that may be used in designing an impedance matching network according to various aspects of the present disclosure. As can be seen, section 200 comprises a source side 204, a load side 205, and a number of reactances X1 201, X2 202, and X3 203 coupled between source side 204 and load side 205. In FIG. 2 (and elsewhere in this disclosure), source side 204 is the side closer to a generator (e.g., RF generator 104 in FIG. 1), while load side 205 is the side closer to a load (e.g., plasma load 106 in FIG. 1). As shown, section 200 is a pi (Π) section in a ladder network, where Π refers to the arrangement of reactances X1 201, X2 202, and X3 203 in the shape of the Greek letter Π. In a power system, the shunt elements X1 201 and X3 203 may be connected to a common node 206, typically referred to as ground or earth ground. In a non-power application, the ends of the reactances X1 201 and X3 203 may be connected to different nodes (i.e., instead of connecting to the common node 206), and a second series element (not shown) may be connected between those two nodes. In such a case, the section of the network more closely resembles a ladder, with the rungs / legs of the ladder comprising the shunt elements X1 and X3, the first rail of the ladder comprising the series element X2, and the second rail of the ladder comprising a series element (not shown) connected between the bottom / lower ends of the shunt elements X1 and X3. In either case, the section 200 may be referred to as being part of a ladder network.

[0066] In some embodiments, different impedance matching topologies may be obtained from this π network, for example, by eliminating one or more of the reactances, selecting one or more of the reactances to be variable reactances, and / or selecting one or more of the reactances to be fixed reactances. Table 220, read in conjunction with Table 210, lists various examples of different impedance matching networks that may be derived from section 200. Table 220 lists 20 different examples of impedance matching networks that may be derived from section 200, but this is not intended to be limiting. Of the matching networks listed in column 1 of Table 220, configuration number 18, which includes a variable source-side shunt (i.e., variable X1 201) and a variable series element L matcher (i.e., variable X2 202), is commonly used in conventional impedance matching networks. In addition, configuration number 17, which includes a fixed series element (i.e., fixed X2 202) and a variable source and load side shunt π matcher (i.e., variable X1 202 and X3 203), is frequently used in conjunction with a fixed π matcher (i.e., configuration number 10, which includes fixed X1 201, X2 202, and X3 203) in a solid-state impedance matching network. Section 200 may be used alone or in combination with other sections in the design of either the coarse first stage 110 or the fine second stage 108 of the two-stage solid-state matcher 102.

[0067] In designing impedance matching networks for power systems, elements X1 201, X2 202, and X3 203 are typically reactances, not impedances that may include resistive parts that are large compared to the reactive parts, because the use of impedances that include resistive parts that are large compared to the reactive parts may lead to lossy networks that are typically not suitable for such applications. Typically, all real reactances have small resistive parts. For example, reactance X1 may ideally be a pure reactance with an impedance of -j1,000Ω, but in practice may be realized as an impedance of 2-j1,000Ω. The ratio of the magnitude of the imaginary part of an impedance or reactance (e.g., 1,000 when the impedance is 2-j1,000Ω) to the real part or resistance (e.g., 2 when the impedance is 2-j1,000Ω) may be referred to as the quality factor or "Q". In some cases, a capacitor may have a quality factor of several thousand, while a high quality inductor may have a Q of around 500.

[0068] 3 illustrates a schematic diagram of a section 300 of an SSM that may be used in designing an impedance matching network according to various aspects of the disclosure. As can be seen, section 300 may comprise a source side 304, a load side 305, and one or more reactance elements X4 301, X5 302, and X6 303 arranged between source side 304 and load side 305. Similar to FIG. 2, in FIG. 3, source side 304 is the side toward a generator (e.g., generator 104 in FIG. 1) and load side 305 is the side toward a load (e.g., load 106 in FIG. 1).

[0069] As shown, section 300 is a T-section of a ladder network, where "T" refers to an arrangement of reactance elements X4 301, X5 302, and X6 303 in the shape of the letter "T." Additionally (i.e., in addition to the example configurations already listed in table 220 of FIG. 2), one or more impedance matching topologies can be obtained or derived from the T-network (or section 300), shown in FIG. 3. Specifically, one or more impedance matching topologies or configurations may be obtained by selecting reactances (e.g., X3, X4, X5) to be varied and reactances to be left fixed, as further described in connection with Tables 320 and 310 below.

[0070] Table 320, read in conjunction with table 310, lists eight additional impedance matching networks that may be derived from T-section 300. Of the matching networks listed in column 1 of table 320, configuration number 26, which comprises a dual variable series element and fixed shunt element T-matcher (i.e., variable X4 and X6 and fixed X5), is sometimes used in conventional impedance matching networks. Section 300 may be used alone or in combination with other sections in the design of either the coarse first stage 110 or the fine second stage 108 of the two-stage solid-state matcher 102.

[0071] FIG. 4A illustrates a schematic diagram of a section 400-a that can be used in designing an impedance matching network. FIG. 4A serves to illustrate that some simple networks cannot be reduced to a ladder network of series (e.g., X2202 in FIG. 2, X4301 and X6303 in FIG. 3) and shunt (e.g., X1201 and X3203 in FIG. 2 and X5302 in FIG. 3) elements. FIG. 4B is a depiction of the same section 400 of FIG. 4A, showing that the inclusion of coupled inductors such as L1418, L2419, and L3420 with couplers K1408, K2409, and K3410 creates a three-port network N2411 that is connected to various nodes within section 400. Additionally, section 400 may include a two-port network 407, such as a section of a transmission line, or more than one series element (e.g., X7 and X9) connected across it to further prevent reduction of section 400 into a ladder network of series and shunt elements, X 10 406. Sections 400-a and 400-b may be used alone or in combination with other sections in the design of either the coarse first stage 110 or the fine second stage 108 of the two-stage solid-state matcher 102.

[0072] FIG. 5 illustrates a block diagram of a cascaded (or tandem) connection 500 of sections that may be used in designing an impedance matching network according to various aspects of the disclosure. As can be seen, FIG. 5 depicts a source side 504, a load side 505, and a number of cascaded sections (e.g., section 501, section 502, section 503, etc.) coupled between the source side 504 and the load side 505. Although other types of connections (e.g., series connections) between the various sections are also possible, the cascaded sections (e.g., sections 501, 502, 503, etc.) are more common in designing impedance matching networks for power systems. In some embodiments, each section 501, 502, ... 503 may be selected from the group consisting of sections 200, 300, 400-a, and / or 400-b of FIGs. 2, 3, 4A, and / or 4B, respectively. 5 may represent either the entire impedance matching network (e.g., the two-stage solid-state matcher 102 of FIG. 1) or a stage of the impedance matching network, such as the coarse first stage 110 or the fine second stage 108 of FIG. 1.

[0073] 6A illustrates a block diagram of a switched variable reactance element 600-a that may be used in designing an impedance matching network according to various aspects of the present disclosure. As can be seen, the switched variable reactance element 600-a includes a first terminal 630 and a second terminal 631. Furthermore, the variable reactance element 600-a includes reactances Y1, Y2, ... Y N 611, 612, ... 613 are switches S1, S2, ..., S N 601, 602, ..., 603. Closing a switch (e.g., switch S2 602) that is in series with a reactance (e.g., reactance Y2 612) adds the susceptance of that reactance to the total susceptance of the variable reactance element 600-a. In some embodiments, the variable reactance element 600-a also includes a fixed reactance Y F 614. In some cases, a fixed reactance Y F 614 is a switch (e.g., SN+1 ) is not arranged in series with the variable reactance element 600-a. The variable reactance element 600-a may be used as a variable reactance element in a section of an impedance matching network. In one non-limiting example, the variable reactance element X1 201 in the section 200 of FIG. 2 for configuration number 18 in table 220 may be implemented using the variable reactance element 600-a, described in connection with FIG. 6A. In turn, the section 200 of FIG. 2 containing the variable reactance element X1 201 may be used as either the coarse first stage 110 or the fine second stage 108 of the two-stage solid-state matcher 102 in the power system 100 of FIG. 1. In some cases, the coarse shunt element 930 in FIG. 9A is similar or substantially similar to the switched variable reactance element 600-a. The switched variable reactance elements 600-a may be used as series (e.g., X2 202 in FIG. 2, X4 and X6 in FIG. 3), shunt (e.g., X1 and X3 in FIG. 2, X5 in FIG. 3), or other (e.g., X 10 ) applications, it may be used as a variable reactance element.

[0074] 6B illustrates a block diagram of a switched variable reactance element 600-b that may be used in designing an impedance matching network according to various aspects of the present disclosure. As can be seen, the switched variable reactance element 600-b is coupled between (or comprises) a first terminal 670 and a second terminal 671. Furthermore, in the variable reactance element 600-b, reactances X1, X2, ... X N 651, 652, ... 653 are switches S1, S2, ..., S N 641, 642, ..., 643. Opening a switch (e.g., switch 641) that shunts a reactance (e.g., reactance 651) adds reactance to the total reactance of variable reactance element 600-b. In some embodiments, variable reactance element 600-b also includes a switch (e.g., switch SN+1 ) is not shunted by a fixed reactance X F 656. The variable reactance element 600-b may be used as a variable reactance element in a section of an impedance matching network, for example, as X1 201 in section 200 of FIG. 2 in the topology, with a variable reactance for X1, such as the L matcher listed as number 18 in table 220 of FIG. 2. In some cases, the coarse series element 922 in FIG. 9A is similar or substantially similar to the switched variable reactance element 600-b. The switched variable reactance element 600-b may be used as a series (e.g., X2 202 in FIG. 2, X4 and X6 in FIG. 3), shunt (e.g., X1 and X3 in FIG. 2, X5 in FIG. 3), or other (e.g., X in FIG. 4A) in either the coarse first stage 110 or the fine second stage 108 of the two-stage SSM 108 of FIG. 1. 10 ) applications, it may be used as a variable reactance element.

[0075] PIN Diode A PIN diode is an electrical device that has an undoped or lightly doped intrinsic (I) semiconductor region sandwiched between heavily doped regions and has a variety of uses, for example, as a switching device in impedance matching networks, particularly radio frequency (RF) matching networks. The "PIN" designation comes from the diode's three-part "sandwich" structure, i.e., a lightly doped intrinsic region (I) positioned between a heavily doped p-type semiconductor (P) and a heavily doped n-type semiconductor (N).

[0076] Generally, PIN diodes follow conventional diode behavior for low frequency input signals, but for higher frequency input signals, they behave as resistors in the forward bias or on state and as capacitors in the reverse bias or off state. Thus, PIN diodes are often utilized in radio frequency (RF) applications, for example, in attenuators and high speed switches where high isolation and low loss are desired. In some situations, PIN diodes can be turned on with a DC current that is a small fraction of the RF current being switched, and turned off by reverse biasing the PIN diode. PIN diodes are attractive switches because they combine low on-state resistance with very low off-state losses. In some cases, a PIN diode driver circuit can be used to turn PIN diodes on and off by conducting DC current through the PIN diode and applying a reverse bias voltage across the PIN diode, respectively.

[0077] In one implementation, PIN diodes are used in an impedance matching network configured to match the varying load impedance of a plasma load to a desired impedance (e.g., 50 Ω) into which a high-power RF generator can deliver power. In such an implementation, the PIN diodes serve to quickly modify the nature of the matching network by connecting or disconnecting a reactive component of the impedance matching network, typically a capacitor, switching the reactive element in and out of the network.

[0078] Turning now to FIG. 7A, which illustrates a model 700-a for a PIN diode in an on-state. In some embodiments, a PIN diode may be used as a switch in a variable reactance element (e.g., switches S1, S2, etc. in FIG. 6A and / or 6B) in accordance with various aspects of the present disclosure. PIN diodes may be used as switches in a variable reactance element because they act like a small resistor (e.g., 0.15 Ω) for RF current in the on-state and as a small capacitor (e.g., 4 pF) in the off-state. As seen in FIG. 7A, the PIN diode model 700-a includes an anode 710-a, a cathode 711-a, an inductor 701-a, and a resistor 702-a, where the inductor 701-a and the resistor 702-a appear in series. A typical value for the inductance of inductor 701-a in FIG. 7A may be about 1 nH, and a typical value for the resistance of resistor 702-a may be about 0.15 Ω.

[0079] FIG. 7B illustrates a model 700-b for a PIN diode in an off state. In the off state, the PIN diode model 700-b comprises an anode 710-b, a cathode 711-b, an inductor 701-b, a resistor 702-b, and a capacitor 703, where the inductor 701-b is connected in series with the parallel combination of the resistor and the capacitor. A typical value for the inductance of the inductor 701-b in FIG. 7B is about 1 nH, a typical value for the capacitor 703 is about 4 pF, and a typical value for the resistor 702-b is about 1.6 megaohms. The resistance of the resistor 702-b may depend on the frequency. The typical values ​​cited may be applied at a frequency of 13.56 MHz.

[0080] 8A and 8B depict a prior art power delivery system utilizing a single stage matching network and a fixed inductor. In some aspects, the illustrations of FIGS. 8A-B highlight some of the efficiencies of using a fixed inductor for an impedance matching network for a power delivery system, as is common in the prior art.

[0081] 8A illustrates a block diagram of a power delivery system 800-a in the prior art, comprising an impedance matching network 808 (e.g., an L-matching network) for matching a load 806 to a generator 804. In this example, the impedance matching network 808 includes an inductor (L), a variable capacitor (C), and a shunt B SH 832 and shunt B SH 832 includes a variable capacitor and an inductor.

[0082] FIG. 8B illustrates an equivalent circuit 800-b for the power delivery system 800-a of FIG. 8A. In some embodiments, an L-matching network, such as the impedance matching network 808 shown in FIG. L +R ind ≦50 (wherein R ind is the resistance of the inductor L), then the load impedance R L +jX L The dominant loss mechanism in this type of matcher is the resistance R of the inductor L. ind In one embodiment, the impedance matching network 808 may have a load resistance (R L ) values, and load reactance (X) from -50 to 50 Ω L ) may be designed to match the load 806 to an input impedance (e.g., 50Ω). The calculated total series reactance (X s 822) is [ka] X s is the inductor L, the capacitor C, and the load reactance X L Specifically, it consists of the sum of reactances X S 822 is the reactance (Xind ), the reactance of the capacitor (X cap ), and the reactance of the load (X L ) can be calculated as the sum of X S 822=X ind +X cap +X L As shown above, X s 2 is (R L +R ind ) is a quadratic function of (R L +R ind )=25, then 625 (i.e., 25 2 ) is reached. For this matching network topology, which utilizes capacitive shunt elements, the total series reactance X s can be chosen to have a positive value, so that X L =-50 and R L =25-R ind When X ind +X c = 75. The capacitance of the capacitor C is limited (for a vacuum variable capacitor, the typical limit is 2 nF, which corresponds to a reactance of -5.9 Ω at a typical RF frequency of 13.56 MHz for a plasma processing chamber), so X ind can be calculated to be at least 75 minus the maximum reactance of the capacitor, i.e., 75-(-5.9)=80.9Ω. X equal to or greater than 80.9Ω ind By using the reactance (X ind ) may be selected to be 85Ω. The quality factor Q of the inductor L may be 500 or about 500. As described above, the resistance R of the inductor ind is the quality factor Q and the reactance X ind In this embodiment, the resistance is R ind This can be calculated as R = 85 / 500 = 0.17Ω. indis the only lossy element in the impedance matching network (or if the resistance of other lossy elements is negligible compared to the resistance of the inductor), the load resistance (R L )=0.6Ω, then the efficiency of the matcher can be calculated to be 0.6 / (0.6+0.17) or approximately 78%.

[0083] FIG. 9A is a block diagram 900-a illustrating an example of a two-stage solid-state matcher 900 incorporating a first stage 920 (or coarse stage 920) and a second stage 910 (or fine / precise stage 910) in accordance with various aspects of the disclosure. The two-stage SSM 900 may be similar or substantially similar to the two-stage SSM 102 described above in connection with FIG. 1. As shown, the coarse first stage 920 includes a coarse series element 922 and a coarse shunt element 930, the coarse series element 922 comprising a series-connected reactance module 924 and a series-connected reactance module 926. The series-connected reactance module 924 comprises a plurality of reactance modules 925 (e.g., capacitive reactance modules). Similarly, the series-connected reactance module 926 comprises a plurality of reactance modules 927 (e.g., inductive reactance modules). In this example, there are two reactance modules 925 and six reactance modules 927, but this is not intended to be limiting. Different numbers of reactance modules (i.e., capacitive and inductive reactance modules) are contemplated in different embodiments. In some cases, the coarse series element 922 implements one or more aspects of the switched variable reactance element 600-b described above in connection with FIG. 6B. Additionally or alternatively, the coarse shunt element 930 implements one or more aspects of the switched variable reactance element 600-a described above in connection with FIG. 6A. It is also possible that in implementing the coarse shunt element 930, the coarse series element 922 may be implemented using one or more aspects of the switched variable reactance element 600-a as well as one or more aspects of the switched reactance element 600-b. For purposes of this disclosure, the term “switchable variable reactance element” may be used to refer to an element (e.g., coarse series element 922, coarse shunt element 930) that comprises multiple reactance modules (e.g., reactance modules 925, 927).Alternatively, the term "switchable variable reactance element" may refer to a reactance module (e.g., reactance module 925, reactance module 927) that includes at least a reactance and a switch, where the switch is arranged in parallel or series with the reactance.

[0084] In some cases, the coarse series element 922 and the coarse shunt element 930 each include multiple switched reactance elements. Specifically, the coarse series element 922 and the coarse shunt element 930 include a sufficient (necessarily sufficient) number of switched reactance elements. By "necessarily sufficient," we mean that the minimum number of switched reactance elements that covers the required reactance range is used without exceeding the maximum voltage or current that each switched reactance element can withstand. To illustrate this using one non-limiting example, assume that the series reactance elements that need to cover the reactance range from -30 to +55, the maximum load current is 60A, and the maximum voltage that each switched reactance module can withstand is 650V. Then, for the reactance of the design of the coarse series element 922, with the switched reactance modules 925 and 927 in series, the maximum absolute value that each switched reactance can contribute to the total reactance is 650 / 60 V / A or approximately 10.83 Ω. Furthermore, covering a reactance range of (55-(-30))=85 Ω with a 10.83 Ω limit means that a minimum of 85 / 10.83 or 7.84 modules may need to be used. Since the number of switched reactance modules is an integer, this means that the sufficient number of switched reactance modules required is eight for this example. Other factors, such as the ability of the precision second stage to match the intermediate impedance to the target input impedance, may dictate the use of more modules in the coarse stage than can be calculated by considering only the reactance range and maximum voltage and current. In this embodiment, the coarse series element 922 comprises eight switched reactance elements, namely, two reactance modules 925 (e.g., a first module having a -jX1 element and a second module having a -jX2 element, where X1 and X2 can be the same or different) and six reactance modules 927.In the illustrated embodiment, the series-connected reactance modules 926 include a first reactance module 927 having a jX3 element, a second reactance module 927 having a jX4 element, a third reactance module 927 having a jX5 element, a fourth reactance module 927 having a jX6 element, a fifth reactance module 927 having a jX7 element, and a sixth reactance module 927 having a jX8 element. The reactances X3-X8 may have the same or different values. In one non-limiting embodiment, X3-X8 may each be equal to 10.83. Additionally, in one non-limiting example, X1 and X2 may each be equal to 10 (i.e., the impedance of the reactance switched on and off of the coarse series reactance element 922 is j10.83 for six reactance modules 927 and -j10 for two reactance modules 925). In some examples, the coarse shunt element 930 may consist of more than three switched reactance elements (e.g., nine switched reactance elements), although only three are shown for simplicity.

[0085] In one non-limiting example, matching network 900 (or two-stage SSM 900) may be designed for a maximum RMS load current of 60 A. In this example, the peak RF voltage generated across a switched reactance element with a reactance of 10.83 Ω can be calculated to be an RMS voltage of approximately 650 V. In this example, 650 V may be the maximum RMS voltage that can be safely tolerated across the switched reactance module, such that fewer switched reactance elements cannot be used to achieve the same impedance range (i.e., if fewer switched reactance elements were used and the impedance range of the coarse series elements remained the same (e.g., ranging from -j30 to +j55 Ω), the absolute value of the reactance of each element would have to be increased above 10.83, but then multiplied by the higher absolute value of the reactance, 60 A would result in a voltage higher than 650 V across the switched reactance elements, which could damage the switched reactance module). In this embodiment, the high-precision stage 910 is connected to the intermediate impedance (the impedance at the source side of the coarse first stage 920, also Z I The minimum impedance range of the coarse series element 922 that allows matching the impedance of the coarse series element 922 (130) to 50 Ω at the source side 904 (generator side) of the high precision second stage 910 is −j30 to j55.

[0086] In some implementations, either the coarse shunt element 930 or the coarse series element 922 may be a fixed reactance. For example, if the coarse shunt element 930 is a fixed capacitance and the coarse series element 922 contains eight switched reactance elements (i.e., reactance modules 925, 927), the total number of useful configurations of the coarse first stage 920 is nine. 8There are x = 256 different configurations, but of those, only 9 result in distinctly different impedances of the coarse series element when the magnitudes of the reactances of the switched reactance elements are the same, as is the case here. Those configurations that result in distinctly different impedances of the switched reactance elements are "useful configurations" (slight differences in magnitudes, as a result of component tolerances or, for example, the use of -10 and 10.83 reactances, would result in more distinctly different impedances, but these slight deviations are not considered useful). As another example, the coarse series element 922 may contain eight switched reactance elements (i.e., reactance modules 925, 927) and the coarse shunt element 930 may contain nine switched reactance elements, as shown in FIG. 9A, for a total of (9+1) x (8+1) = 90 useful configurations. Note that only a small percentage of the total number of on / off combinations of switches in a switched reactance element are "useful configurations" since split reactances are not used in the coarse division. Instead, multiple reactances of the same absolute value may be used. For example, X1=X2, and X3=X4=X5=X6=X7=X8, and [ka] This means that the split reactance value can be calculated with the required accuracy by dividing the intermediate impedance (Z I This can be contrasted with the situation in the high precision second stage 910, where the impedance matching network is used to match the input impedance of [ka] With a return loss of better than 27 dB, which means that T(typically 50Ω). With this accuracy, to match a 0.6+jXΩ load (the load reactance X does not affect the required accuracy calculated here) to 50Ω, the L matcher may require an in-series reactance element accuracy of 0.241Ω. With an 85Ω reactance range, this means at least 85 / 0.241 or about 353 steps or 8 full value steps and 6 split reactance steps for the series reactance elements. The use of full value and split steps means that 14 switched reactance elements can be used in this embodiment, rather than 353 switched reactance elements if only full value switched reactance elements were used. Similar considerations apply to the shunt elements of the L matcher, typically requiring at least 353 steps of the high accuracy second stage (e.g., 910, 108). 2 This means that =124,609 configurations may be required in this exemplary application to achieve the specified accuracy, i.e., return loss better than 27 dB. Although an L-matcher is used as an example, similar considerations apply to other matcher topologies, and in general a large number of configurations (e.g., >125,000) may be required in the high-precision second stage to achieve the specified accuracy. While the coarse-precision first stage has 90 useful configurations in this example, the number of useful configurations in the high-precision second stage 910 may be significantly higher (e.g., >100,000; >500,000; 100,000-500,000; approximately 1 million, to name a few).

[0087] In some embodiments, switched reactance elements of opposite sign (e.g., -jX1, -jX2, jX3, jX4, etc., with X1, X2, ..., X8 all positive) may be used in the coarse first stage 920 to optimize the efficiency of the matching network compared to the prior art. As shown, the coarse series element 922 contains both capacitive (e.g., -X1, -X2Ω, with X1 and X2 both positive) and inductive (e.g., X3-X8Ω, with X3-X8 all positive) switched reactances. A fixed capacitive reactance 928 (e.g., -X9Ω reactance, where X9=10) may or may not be employed depending on the use case or application. An instance where a fixed reactance such as the -jX9 reactance 928 may be utilized is when the output may be exposed to a lower frequency RF signal and a fixed capacitive element such as the -jX9928 may be used to drop most of the lower frequency voltage across the fixed capacitive element. In some other cases, a fixed inductive element (e.g., 10 Ω, 10.83 Ω reactance) may be used, for example, when the output of the matcher is exposed to a high frequency RF signal. Such a condition may occur in a multi-frequency matcher.

[0088] In some cases, the efficiency of the matching network 900 is based on the reactances (e.g., -jX1, -jX2, jX3, jX4, etc.) of the switched reactance modules 924 and 926 and the losses (if applicable) of the switch 977. FIG. 9A illustrates the loss of resistors (e.g., resistors R1-R8, resistor R s_1 -R s_8 ) provides insight into the losses of the switched reactance modules 924 and 926. In some aspects, the resistance values ​​of the resistors shown in the switched reactance modules 924 and 926 are based at least in part on the reactance and switch properties. In other words, the efficiency of the matching network 900 is based at least in part on the reactance and switch properties of the switched reactance modules 924, 926.

[0089] In one non-limiting example, X1=X2=10. Additionally, each switch 977 in the two reactance modules 925 (or the -j10 switched reactance module 925) may be implemented using 16 PIN diodes in parallel. As depicted in FIG. 9B, the on-resistance R PIN_ON If I is about 0.15Ω, the resistor in series with the switch can be calculated as follows: [ka]

[0090] In this embodiment, the RF frequency is 13.56 MHz, and the equivalent parallel resistance of each PIN diode in the off state at 13.56 MHz is approximately 1.6 Megaohms. By using 16 PIN diodes in parallel, the resistance in parallel with the capacitor when the PIN diode is off is R PIN_OFF 1 / 16, i.e., approximately 1.6 / 16 megohms or 100 kΩ. In some embodiments, the reactance is created as a parallel combination of an inductor (e.g., having a reactance of 20 and a Q of 500) and a capacitor (e.g., having a reactance of -6.67). In such a case, the equivalent parallel resistance of the reactance created using both the capacitor and inductor may be lower (lossier) than the equivalent parallel resistance when only the capacitor is used alone (e.g., a 30 kOhm equivalent parallel resistance is achievable when using only the capacitor, with a reactance of -10). For example, using a value of 10 kOhm for the equivalent parallel resistance of the capacitors and inductors in parallel, and 100 kOhm for the equivalent parallel resistance of the PIN diodes in the off state (i.e., when 16 PIN diodes are in parallel with the capacitors when they are off), the total parallel resistance of the open switch (R P ) can be calculated as follows: [ka] The reason for using an inductor with a reactance of 20 in parallel with a capacitor with a reactance of -6.67, rather than just a capacitor with a reactance of -10, is that with this arrangement, the matcher 900 can be used in applications where the load side of the matcher may be exposed to high voltages at lower frequencies such as those encountered in dual or multi-frequency matching networks, albeit with slightly higher losses. For example, if the load side of the matcher 900 experiences 1 kV at 400 kHz and the matcher 900 is designed for use at 13.56 MHz, then the reactance of the -10 Ω reactance module 925 at 400 kHz is 0.952 Ω, while the reactance of the fixed -10 Ω reactance module 928 at 400 kHz is -339 Ω. With both capacitive reactance modules 925 switched into the coarse series element 922, the reactance of the series reactance module at 400 kHz is: [ka] And the current is [ka] So at 400kHz the voltage developed across the -10Ω reactance module 925 is only [ka] It is.

[0091] The resulting series model for the open switch is [ka] , i.e., a capacitive reactance (e.g., a reactance of -10) in series with a resistor (e.g., having a resistance of about 0.011 Ω). That is, X1=X2=10, and R1=R2=0.011 Ω, and R S_1 =R S_2In one non-limiting example, X3=X4=X5=X6=X7=X8=10.83 Ω, R3=R4=R5=R6=R7=R8=0.0224 Ω, and R S_3 =R S_4 =R S_5 =R S_6 =R S_7 =R S_8 = 0.015 Ω. In some embodiments, ten PIN diodes arranged in parallel may be used to implement each switch 977 of the reactance module 927. Using these example values, nine settings of the coarse series element 922 can be determined based on which reactances (e.g., -jX1, -jX2, jX3, etc.) are switched on or off in the impedance matching network. For example, a first setting may correspond to a scenario in which only the fixed capacitive reactance 928 (e.g., -j10 reactance) and two reactance modules 925, each having a -j10 reactance, are switched on. That is, six reactance modules 927 are switched off in the matching network. The reactance for the first setting can then be obtained by summing the three j10 reactances. Similarly, the second setting may correspond to a scenario in which only one of the two reactance modules 925 having a fixed capacitive reactance and a -j10 reactance is switched on, in which case the second setting corresponds to two -j10 reactances. Thus, the nine settings of the coarse series element 922 may comprise reactances of -30, -20, -10, 0.83, 11.67, 22.5, 33.33, 44.17, and 55 Ω. In addition, the corresponding series resistance of the coarse series element 922 may be calculated as shown in FIG. 9C. For example, for setting 1 (i.e., when the six reactance modules 927 are switched on in the impedance matching network), the corresponding series resistance of the coarse series element is calculated as resistances R1 and R2 and resistance R S_3 -R S_8 It is calculated as the sum of R1, R2, R S_3Using the example values ​​for R and R, the series resistance for the first setting can be calculated to be approximately 0.112 Ω. Similarly, the series resistance for the second setting can be calculated to be approximately 0.112 Ω. S_2 -R S_8 which gives a value of approximately 0.110 Ω. Thus, the nine settings of the coarse series element 922 may have resistances of 0.112, 0.110, 0.109, 0.116, 0.124, 0.131, 0.138, 0.146, and 0.153 Ω (an accurate calculation of the resistance when the switch is closed can be calculated by multiplying the admittance of the impedance (e.g., 1 / (R1-jX1￢)) by the admittance of the switch (e.g., 1 / R s_1 ), but the resistance is R s_1 The error in assuming that is extremely small. For example, [ka] 8A ) In all cases, the series resistance of the coarse series element is lower than that of the equivalent conventional matcher of FIG. 8A. A similar model for losses in the coarse shunt element 930 and the variable reactance element of the precision second stage 910 is applied and used to calculate the overall matching efficiency. For example, for the coarse precision shunt element 930 of Figure 9A, the shunt susceptances are calculated as 0.01, 0.0156, 0.0211, 0.0267, 0.0322, 0.0378, 0.0433, 0.0489, 0.0544, 0.06 siemens and the corresponding shunt conductances are calculated as 3.89, 14.21, 24.52, 34.84, 45.16, 55.48, 65.79, 76.11, 86.43, and 96.75 microsiemens based on the assumed nature of the reactive elements and switches used. For the variable reactance elements in the high precision second stage, the quality factors of both the fixed and variable reactance elements are assumed to be 500 based on an analysis of the design.

[0092] FIG. 10A illustrates a conceptual graph 1000-a showing the efficiency 1015 of a two-stage SSM as a function of settings for the first stage of the two-stage SSM in accordance with various aspects of the disclosure. Specifically, graph 1000-a shows the efficiency for the two-stage matcher 900 of FIG. 9A as a function of settings of the coarse first stage 920 for a load impedance of 0.6-j20Ω, including one or more of the settings of the coarse shunt element 930 and the coarse series element 922. In some cases, the electrical efficiency 1015 or SSM efficiency 1015 can be calculated as the ratio of the power leaving the matcher to the power entering the matcher. Note that FIG. 10A depicts only the settings of the coarse first stage 920 that can be mapped to a desired input impedance (e.g., 50Ω) by the precision second stage 910. In some cases, the number of settings as well as the configurations / values / variables corresponding to the settings may be based in part on the design of the high-precision second stage. In this example, there are four settings of the coarse series element 922 with corresponding settings of the coarse shunt element 930 that may be mapped to 50Ω by the high-precision second stage 910. Each of the settings of the coarse series element 922 (numbered 1-9 in this example) corresponds to one of the reactances of the series element 922 (e.g., −30Ω, −20Ω, −10Ω, 0.83Ω, 11.67Ω, 22.5Ω, 33.33Ω, 44.17Ω, and 55Ω). For example, a first setting (or setting 1) corresponds to a -30 Ω reactance of the series element 922 when the three -j10 reactance modules 925 and 928 are active / in use, a second setting (or setting 2) corresponds to a -20 Ω reactance of the series element when the -j10 reactance module 928 and one of the two -j10 reactance modules are active / in use, and so on.

[0093] In this example, the settings of the coarse shunt element 930 correspond to uniformly spaced susceptances of 0.01 to 0.06 Siemens. In some cases, the on and off nature of the switches and the quality factors of the capacitors in the coarse shunt 930 may be used to calculate the performance of the two-stage matcher (e.g., in terms of efficiency). The performance calculation is done by determining the currents and voltages in the circuit of the matcher 900, including the lossy nature of the various elements in the matcher, using standard circuit analysis techniques as known in the art, and then calculating the quantities of interest (e.g., input impedance and efficiency) from the determined voltages and currents. The precision second stage 910 is assumed to be a variable source-side shunt and variable series element L matcher (item number 18 in table 220 of FIG. 2). In one non-limiting example, the series element is a switched variable capacitor (C in FIG. 9A). VAR_1 ) in series with a fixed inductor (jX in FIG. 9A ) with reactance j and a Q of 500. 10 9A ) that has a Q of 500 and can be adjusted from 200 pF to 2 nF. The variable source side shunt element of the high precision second stage 910 may include a switched variable capacitor (C VAR_2 ). Using these example values, the settings of the coarse first stage 920 that result in the most optimal efficiency 1015 of the impedance matching network 900 are found, with the coarse series element 922 set to a setting of 7 (i.e., a reactance of 33.33 Ω) and the coarse shunt element 930 set to a setting of 10 (i.e., a susceptance of 0.06 Siemens).

[0094] FIG. 10B illustrates a load impedance Z L As a function of the setting of the first stage of the coarse accuracy for I 10 illustrates a conceptual graph 1000-b showing load impedance (Z L) is 0.6-j20Ω. FIG. 10B depicts only those settings (i.e., series and shunt settings) that can be mapped to, for example, 50Ω by the precision second stage. The setting configuration for the coarse series and shunt elements 922 and 930, respectively, that is conducive to achieving the most optimal efficiency (series setting=setting 7, corresponding to a reactance of 33.33Ω, shunt setting=setting 10, corresponding to a susceptance of 0.06 Siemens) corresponds to an intermediate impedance of 17.6+j71.8Ω.

[0095] FIG. 10C illustrates a Smith chart 1000-c in accordance with various aspects of the disclosure. The Smith chart 1000-c implements one or more aspects of the graph 1000-b discussed above in connection with FIG. 10B. Here, each intermediate load impedance (i.e., the impedance experienced at the source side of the coarse first stage, Z in FIG. 1) is I 130, etc.) is expressed as the load reflection coefficient for 50 Ω. The load reflection coefficient for an intermediate load impedance for 50 Ω is given by: (Z I -50) / (Z I +50). In addition, the intermediate load impedance for the impedance that results in the highest efficiency is also expressed as a function of the first stage setting of the coarse precision for the load impedance, where the load impedance is 0.6-j20Ω.

[0096] 11A, 11B, and 11C show Smith charts 1100-a, 1100-b, and 1100-c, respectively. Specifically, the Smith chart 1100 shows the load impedance (Z L ) and intermediate impedance (Z I ) and input impedance (Z IN 10A, 10B, and 10C, for a particular load impedance, there may be multiple settings for the coarse first stage 920 that allow the fine second stage 910 to map the intermediate impedance to 50 Ω on the source side of the matcher 900.

[0097] FIG. 11A shows the load reflection coefficient (Γ) for a source impedance (i.e., 0.6+jX, where reactance “X” ranges from −50 to 50) of 50Ω. L ) and the load reflection coefficient (Γ L ) is as follows, i.e. (Z L -50) / (Z L +50).

[0098] Figure 11B shows the intermediate load impedance reflection coefficient (Γ I ) I ), where the mid-load impedance reflection coefficient corresponds to the coarse first stage setting that results in the highest efficiency of the matcher 900. In some cases, the mid-load impedance reflection coefficient (Γ I ) is as follows, that is, (Z I -50) / (Z I +50).

[0099] Figure 11C shows the input reflection coefficient (Γ IN 1 ) at the source side of the matching circuit 900. in 140, etc.), and the input reflection coefficient (Γ IN ) is as follows, that is, (Z IN -50) / (Z IN +50).

[0100] In some embodiments, the desired input impedance is set to 50Ω for all load impedances, but this is not intended to be limiting. Other input impedances (e.g., 25Ω, 37.5Ω, 75Ω, to name a few) are also contemplated in different embodiments.

[0101] FIG. 11D illustrates a conceptual graph 1100-d depicting the efficiency of the impedance matching network 900 of FIG. 9 compared to the efficiency of the L-matcher 800-a in FIG. 8A (prior art). Here, the graph 1100-d shows the efficiency 1115 on the vertical axis (or y-axis) and the load reactance 1110 on the horizontal axis (or x-axis). Specifically, the graph 1100-d depicts the efficiency 1115 of the impedance matching network 900 of FIG. 9 as a function of the load reactance 1110 for a fixed load resistance (e.g., 0.6 Ω) as the load reactance 1110 is varied from −50 to 50. The two-stage SSM curve 1150 corresponds to the efficiency obtained when the setting that results in the most optimal efficiency of the matcher 900 is used for each impedance setting. Also shown (using the vacuum variable capacitor curve 1160) is the efficiency of the conventional L matcher 800-a of FIG. 8A. As can be seen, the two-stage solid-state matcher 900 of FIG. 9 helps to improve efficiency over a large portion of the reactance range compared to the prior art matching network. In some aspects, the two-stage solid-state matcher helps to optimize performance compared to the prior art impedance matching network (e.g., L matcher 800-a in FIG. 8A) by allowing a portion of the series inductor to be shorted (e.g., by closing one or more of the switches 977 in the switched reactance module 927 in FIG. 9), such as when a smaller inductor is employed in the matching network. In some cases, the two-stage SSM may short a portion of the series inductor instead of reducing the capacitance value of the capacitor (e.g., C of the impedance matching network 808 in FIG. 8A).

[0102] In some embodiments, the efficiency of the two-stage solid-state matcher may be further improved by using reactances of opposite signs in the switched reactance elements (e.g., switched reactance element 925 with a reactance of -10 and switched reactance element 927 with a reactance of 10.83). Specifically, the series resistance range of the coarse series element 922 (i.e., to achieve the same reactance range, such as -30 to 55) may be reduced by using reactances of opposite signs. Since the efficiency range is a function of the load resistance (e.g., 0.6 Ω) and the series resistance range, smaller resistance values ​​within the series resistance range may result in higher efficiency of the impedance matching network. In one non-limiting example, the series resistance may range from 0.185 to 0.198 Ω when only the coarse series element 922 uses switched capacitive reactance and fixed inductive reactance. Furthermore, the series resistance may range from 0.112 Ω to 0.153 Ω (using example values ​​described in connection with FIG. 9A) when both switched capacitance and switched inductive reactance are utilized in the coarse series element 922. By reducing the overall series resistance, efficiency may be improved. For example, when operating against a load resistance of 0.6 ohms, the efficiency range can be improved from about 0.75-0.76 to about 0.80-0.84. In other words, efficiency can be improved by about 0.09 (or 9%) when operating against a highly inductive load, and by about 0.04 (or 4%) when operating against a highly capacitive load.

[0103] In some cases, the efficiency of a two-stage solid-state matcher can be further improved by limiting the number of switched reactive elements in the coarse first stage.

[0104] FIG. 12 illustrates an example of a method 1200 for operating a two-stage solid-state matcher according to various aspects of the disclosure. In some embodiments, the two-stage solid-state matcher may be similar or substantially similar to the two-stage SSM described above in connection with FIG. 9. Additionally, the two-stage SSM may include a coarse first stage (e.g., the coarse first stage 920 in FIG. 9) and a high-precision second stage (e.g., the high-precision second stage 910 in FIG. 9). The second stage may be coupled between a source side (e.g., the source side 904) and the coarse first stage, while the coarse first stage may be coupled at one end to the load side 905 and at another end to the second stage.

[0105] At operation 1202, the method 1200 calculates a load impedance (Z L 9 ) in some embodiments. In some embodiments, the load impedance may be obtained directly through a sensor on the load side, such as load side 905 of the two-stage SSM in FIG. 9 . Alternatively, the load impedance may be obtained indirectly by measuring the impedance on the source side, such as source side 904 of the matcher in FIG. 9 , and combining the measured impedance information with information about the properties of the matcher 900 (e.g., using the 2-port admittance parameters of the matcher 900 for the particular settings of the variable reactance components in the matcher at the time the measurement of Y, i.e., the source-side impedance, is made, and port 1, i.e., the source-side port, to determine the load impedance Z L is the following, i.e. [ka] can be calculated as:

[0106] In some cases, operation 1204 may include matching one or more intermediate impedances (Z I ) and a corresponding matcher efficiency, where the calculating step is further based at least in part on the load impedance obtained in Operation 1202.

[0107] Next, operation 1206 determines whether a high-precision second stage of the impedance matching network is matched to an intermediate impedance (Z I ) to a target or desired input impedance (e.g., 50 Ω).

[0108] Operation 1208 includes applying one of the settings from the subset to the coarse first stage. In some cases, the setting selected from the subset in operation 1208 comprises a setting that maximizes an overall efficiency of the impedance matching network (or the two-stage SSM). Operation 1208 also includes utilizing the setting for the coarse first stage of the impedance matching network.

[0109] Finally, operation 1210 includes adjusting the precision second stage of the impedance matching network such that the intermediate impedance is mapped to the desired input impedance (eg, 50 Ω).

[0110] Although not shown, the method 1200 can be implemented in computer logic, such as a non-transitory tangible computer readable medium, encoded with instructions to perform the method 1200 for controlling high-precision and coarse-precision stages of an SSM, such as stages 108, 110 shown in FIG. 1, or stages 910, 920 shown in FIG. 9A.

[0111] FIG. 13 illustrates an example of a method 1300 for operating a switched reactance element in accordance with various aspects of the disclosure.

[0112] Method 1300 begins with determining a target reactance for the switched reactance elements (operation 1302). In some embodiments, the target reactance may be obtained as an output of operation 1208 of method 1200. For example, operation 1208 includes selecting and using a setting that maximizes the overall efficiency of the two-stage SSM, the setting being one of a number of settings that may be used to adjust a coarse first stage (e.g., 110 or 920) of the two-stage SSM. In some cases, the setting is associated with (or corresponds to) a reactance for the switched reactance elements in at least the coarse first stage of the two-stage SSM, as described above with respect to FIGS. 1 and 9.

[0113] Next, operation 1304 includes closing at least one switch in parallel with a reactance having an opposite sign to that of the target reactance. For example, when the target reactance is 11.67 Ω, a switch (e.g., a switch in module 924) in parallel with a −10 Ω reactance is closed.

[0114] Operation 1306 includes opening at least one switch in parallel with a reactance having the same sign as that of the target reactance, for example, when the target reactance is −20Ω, a switch (e.g., a switch in module 924) in parallel with a −10Ω reactance is opened.

[0115] Although not shown, the method 1300 can be implemented in computer logic, such as a non-transitory tangible computer readable medium, encoded with instructions to perform the method 1300 for controlling high-precision and coarse-precision stages of an SSM, such as stages 108, 110 shown in FIG. 1, or stages 910, 920 shown in FIG. 9A.

[0116] FIG. 14 illustrates another example of a method 1400 for operating a switched reactance element in accordance with various aspects of the disclosure.

[0117] In operation 1402, method 1400 includes determining a target susceptance for the switched reactance element. Similar to operation 1302 in FIG. 13, in some embodiments, the target susceptance may be obtained as an output of operation 1208 of method 1200. For example, operation 1208 includes selecting and using a setting that maximizes an overall efficiency of the two-stage SSM, the setting being one of a plurality of settings that may be used to adjust a coarse first stage of the two-stage SSM. In some cases, the setting is associated with (or corresponds to) a susceptance for the switched reactance element in the coarse first stage of the two-stage SSM.

[0118] Next, operation 1404 includes opening at least one switch in series with a susceptance having an opposite sign to that of the target susceptance.

[0119] Next, operation 1406 includes closing at least one switch in series with the susceptance having the same sign as that of the target susceptance.

[0120] Although not shown, the method 1400 can be implemented in computer logic, such as a non-transitory tangible computer readable medium, encoded with instructions to perform the method 1400 for controlling high-precision and coarse-precision stages of an SSM, such as stages 108, 110 shown in FIG. 1, or stages 910, 920 shown in FIG. 9A.

[0121] FIG. 15 illustrates a block diagram of a computer system 1100 that may be used to implement one or more aspects of the disclosure, including at least a method for operating a two-stage solid-state matcher (e.g., as described above in connection with FIG. 12). As shown, in this embodiment, a display 1512 and a non-volatile memory 1529 are coupled to a bus 1522, which is also coupled to a random access memory ("RAM") 1524, a processing portion 1526 (including N processing components), a field programmable gate array (FPGA) 1527, and a transceiver component 1528, including N transceivers. Although the components depicted in FIG. 15 represent physical components, FIG. 15 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 15 may be realized by common construction or distributed among additional physical components. Other existing and yet to be developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG. 15.

[0122] The display 1512 generally operates to provide a user interface for a user, and in some implementations, the display 1512 is realized by a touch screen display. For example, the display 1512 can be used to control and interact with the components described herein. In general, the non-volatile memory 1529 is a non-transient memory that functions to store (e.g., persistently store) data and machine-readable (e.g., processor-executable) code (including executable code associated with steps that effect the methods described herein). In some embodiments, for example, the non-volatile memory 1529 includes boot loader code, operating system code, file system code, and non-transient processor-executable code to facilitate execution of the methods described herein, such as methods 1200-1400 of FIGS. 12-14.

[0123] In some implementations, non-volatile memory 1529 may be realized by flash memory (e.g., NAND or ONENAND memory). In other embodiments, other memory types may be utilized as well. While some embodiments may execute code from non-volatile memory 1529, in other embodiments, executable code in non-volatile memory may typically be loaded into RAM 1524 and executed by one or more of the N processing components in processing portion 1526.

[0124] In operation, the N processing components associated with RAM 1524 may generally operate to execute instructions stored in non-volatile memory 1529 to implement the functionality of the two-stage SSM described herein. For example, non-transient processor-executable instructions for effecting the methods described herein may be persistently stored in non-volatile memory 1529 and executed by the N processing components associated with RAM 1524. The processing portion 1526 may include a video processor, a digital signal processor (DSP), a graphics processing unit (GPU), and other processing components.

[0125] Additionally, or in other embodiments, a field programmable gate array (FPGA) 1527 may be configured to effect one or more aspects of the methodologies described herein. For example, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1529 and accessed by FPGA 1527 (e.g., during power-up) to configure FPGA 1527.

[0126] The input component 1531 may generally operate to receive signals (e.g., target accuracy for the two-stage SSM, target input impedance, load impedance, to name a few). The output component 1532 may generally operate to provide one or more digital and / or analog signals (e.g., to a control module, PIN diode switches, etc.) to effect operational aspects of the two-stage SSM and / or other systems described herein. In some embodiments, the computer system 1500 may be configured to implement a method for switching on and off at least two reactances (e.g., of opposite signs, such as an inductive reactance and a capacitive reactance) of a plurality of switchable variable reactance elements employed in an impedance matching network.

[0127] The depicted transceiver component 1528 includes N transceiver chains that may be used to communicate with external devices (e.g., an external controller) over a wireless or wired network. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., Wifi, Ethernet, Profibus, etc.).

[0128] Methods 1200-1400, as well as other methods of the present disclosure, may include other steps or variations in various other embodiments. Some or all of any of methods 1200-1400 may be performed by or embodied in hardware in controlling other associated hardware, devices, systems, or products in performing, implementing, or embodying the various subject matter of the methods, and / or performed or executed by a measurement and control multiprocessor system-on-chip (MPSoC), which may include a controller, CPU, FPGA, system-on-chip (SoC), both a CPU and FPGA, and other elements together in one integrated SoC or other processing or computing device processing executable instructions.

[0129] As used herein, the recitation of "at least one of A, B, and C" is intended to mean "any of A, B, C, or any combination of A, B, and C." The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0130] Terms such as "first," "second," "third," and the like may be used herein to describe various elements, components, and / or sections, but it should be understood that these elements, components, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, or section from another element, component, or section. Thus, a first element, component, or section discussed below may also be referred to as a second element, component, or section without departing from the teachings of the present disclosure.

[0131] Spatially relative terms such as "below," "below," "below side," "down," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It should be understood that the spatially relative terms are intended to encompass different orientations of the circuitry in use or operation in addition to the orientation depicted in the figures. For example, if the circuitry of the figures were flipped over, elements described as being "below," or "below," or "below" the other elements or features would therefore be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both "upper" and "lower" orientations. The circuitry and power generating components may be oriented differently (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0132] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprising", as used herein, specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any combination of one or more of the associated listed items and may be abbreviated as " / ".

[0133] When an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, it is understood that it may be "directly on", "connected to", "coupled to", or "adjacent to" the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to", or "directly adjacent to" another element, there are no intervening elements present.

[0134] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant field and / or in the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

Claims

1. 1. An apparatus comprising: an impedance matching network having a load side and a source side; a first coarse precision stage and a second high precision stage, the first coarse precision stage being coupled between the second high precision stage and the load side, and the second high precision stage being coupled between the source side and an input of the first coarse precision stage; Equipped with the coarse first stage comprises at least one switched variable reactance element; the first coarse stage is configured to map a load impedance connected to the load side to a first number of intermediate impedances at an input of the first coarse stage; The apparatus, wherein the second precision stage is configured to map at least one of the intermediate impedances to a second number of input impedances at the source side.

2. 2. The apparatus of claim 1, wherein the at least one switchable variable reactance element comprises at least two reactances including an inductive reactance and a capacitive reactance, the at least two reactances being configured to be switched on and off by the at least one switchable variable reactance element.

3. The apparatus of claim 1 , wherein the second number is greater than the first number.

4. The apparatus of claim 1 , wherein the first number of intermediate impedances is less than or equal to 400.

5. 2. The apparatus of claim 1, wherein the second number of input impedances is at least 100,000.

6. The first coarse stage comprises: a coarse series element and a coarse shunt element, each of the coarse series element and the coarse shunt element comprising one or more switched variable reactance elements; the coarse series element is coupled to the load side; the coarse shunt element is coupled between the coarse series element and the second precision stage.

2. The apparatus of claim 1.

7. 7. The apparatus of claim 6, wherein the coarse shunt element comprises at least a first switch arranged in series with an inductive reactance and a second switch arranged in series with a capacitive reactance.

8. 7. The apparatus of claim 6, wherein the coarse series element comprises at least a first switch arranged in parallel with an inductive reactance and a second switch arranged in parallel with a capacitive reactance.

9. The apparatus of claim 6 , wherein the first coarse stage further comprises a plurality of PIN diodes.

10. 1. A method for operating a two-stage solid-state matcher, the method comprising: determining a load impedance of a load coupled to the two-stage solid-state matcher; identifying a plurality of settings for a coarse first stage of the two-stage solid-state matcher; calculating, for each of the plurality of settings, a mid-point impedance and an efficiency for the two-stage solid-state matcher when the respective setting is applied to the coarse first stage; Identifying a target input impedance; selecting a setting for the coarse first stage, the selecting being based at least in part on the target input impedance, the intermediate impedance, and the efficiency, the selecting further comprising applying the selected setting to the coarse first stage; adjusting a high precision second stage of the two-stage solid-state matching circuit to transform an intermediate impedance corresponding to the selected setting into the target input impedance; A method comprising:

11. Selecting a setting for the first stage of coarse precision comprises: identifying a subset of the plurality of settings, each setting in the subset corresponding to an intermediate impedance that is mappable to the target input impedance by the high accuracy second stage; identifying the selected setting from the subset of settings, the selected setting maximizing efficiency of the two-stage solid-state matcher; The method of claim 10, comprising:

12. The method of claim 10 , wherein the number of the plurality of settings is less than 400.

13. The coarse first stage comprises at least one switched variable reactance element, the at least one switched variable reactance element comprising a first switch in parallel with a first reactance and a second switch in parallel with a second reactance, and setting the coarse first stage to the selected setting further comprises: determining a target reactance for the at least one switchable variable reactance element; closing the first switch; opening the second switch; Including, the first reactance has an opposite sign to that of the target reactance, and the second reactance has the same sign as that of the target reactance. The method of claim 10.

14. The coarse first stage comprises at least one switched variable reactance element, the at least one switched variable reactance element comprising a first switch in series with a first reactance and a second switch in series with a second reactance, and setting the coarse first stage to a selected setting comprises: determining a target susceptance for the at least one switched variable reactance element; opening the first switch; closing the second switch; Including, the first reactance has a susceptance of opposite sign to that of the target susceptance, and the second reactance has a susceptance of the same sign as that of the target susceptance. The method of claim 10.

15. 1. A non-transitory tangible computer readable storage medium encoded with processor readable instructions for implementing a method for switching two or more reactances on and off in a first stage of a two-stage solid-state matcher, the method comprising: determining a load impedance of a load coupled to the two-stage solid-state matcher; identifying a plurality of settings for a first stage of the two-stage solid-state matcher, the first stage comprising at least one switched variable reactance element, the at least one switched variable reactance element comprising the two or more reactances, the two or more reactances including at least a first reactance and a second reactance of opposite signs; selecting a setting for the first stage; applying the selected settings to the first stage, said applying including: determining a target reactance for the at least one switchable variable reactance element; switching on and off a first reactance of the two or more reactances, the first reactance having an opposite sign to a sign of the target reactance; switching on a second of the two or more reactances, the second reactance having the same sign as a sign of the target reactance; Including, 16. A non-transitory tangible computer readable storage medium comprising:

16. 16. The non-transitory tangible computer-readable storage medium of claim 15, wherein the two or more reactances include at least one inductive reactance and at least one capacitive reactance, and wherein either the first reactance is an inductive reactance and the second reactance is a capacitive reactance, or the first reactance is a capacitive reactance and the second reactance is an inductive reactance.

17. 16. The non-transitory tangible computer readable storage medium of claim 15, wherein the number of the plurality of settings is less than 400.

18. 20. The non-transitory, tangible computer-readable storage medium of claim 15, wherein the first stage further comprises a plurality of PIN diodes.

19. Selecting a setting for the first stage includes:

16. The non-transitory tangible computer-readable storage medium of claim 15, further comprising identifying a subset of the plurality of settings, each setting in the subset corresponding to an intermediate impedance that is mappable to a target input impedance by a second stage of the two-stage solid-state matcher.

20. Selecting a setting for the first stage further includes:

20. The non-transitory tangible computer readable storage medium of claim 19, further comprising identifying, from the subset of settings, the selected setting, the selected setting maximizing an efficiency of the two-stage solid-state matcher.

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