Wireless transmission of coded samples using spread spectrum video transport.

Abstract

A wireless transmitter and antenna are provided on the transmitting side, and a receiver and antenna are provided on the receiving side. The transmitter receives samples from a video source via a media signal, permutes the input samples into input vectors, and encodes each input vector with reference to a set of orthogonal codes to generate analog SSVT signals per encoder. The wireless transmitter modulates the SSVT signals generated by the SSVT transmitter onto one or more carrier frequency signals. Once modulated, the carrier frequency signals are broadcast by an antenna. At the receiving side, the antenna receives the broadcast and provides the modulated carrier signals to a wireless receiver. In response, the wireless receiver demodulates the carrier frequency signals and generates corresponding analog SSVT signals, which are then decoded to reconstruct the input media samples into output vectors, and the decoded signals are then permuted into output samples that are sent to a video sink for display.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 299,137, filed January 13, 2022 (HYFYP011P), and U.S. Provisional Patent Application No. 63 / 317,757, filed March 8, 2020 (HYFYP011P2), the contents of which are incorporated herein by reference.

[0002] This application is also incorporated by reference into U.S. Patent Application No. 15 / 925,123, filed March 19, 2018 (Docket No. HYFYP001), U.S. Patent Application No. 16 / 494,901, filed September 17, 2019 (Docket No. HYFYP002), U.S. Patent Application No. 17 / 879,499, filed August 2, 2022 (Docket No. HYFYP003), U.S. Patent Application No. 17 / 686,790, filed March 4, 2022 (Docket No. HYFYP004AX1), U.S. Patent Application No. 17 / 887,849, filed August 15, 2022 (Docket No. HYFYP006), U.S. Patent Application No. 17 / 851,821, filed June 28, 2022 (Docket No. HYFYP007, the specification of U.S. patent application No. 63 / 421,062 (Docket No. HYFYP008P2), filed on October 31, 2022, the specification of U.S. patent application No. 63 / 280,017 (Docket No. HYFYP009P2), and the specification of U.S. patent application No. 63 / 391,226 (Docket No. HYFYP013P3), filed on July 21, 2022, are incorporated by reference.

[0003] The present invention relates generally to video and other media transport, and more particularly to encoding and decoding video media for wireless transmission between a video source and a video sink using discrete-time continuous amplitude electromagnetic (EM) signals. [Background technology]

[0004] High-definition video is typically produced in many different formats, including "720p", "1080i", "1080p", and more recently "4K". In reference to these formats, "i" refers to interlaced scan and "p" refers to progressive scan.

[0005] The amount of video data transmitted using any of the formats listed above is enormous. With "720p" the transmission rate is 1280 horizontal lines by 720 vertical lines (i.e. approximately 921,600 pixels) per frame with a typical refresh rate of 50 or 60 frames per second. The transmission of 1080i requires the transmission of 1920 horizontal lines by 540 vertical lines per field (i.e. 1,036,800 pixels per field) with two interlaced fields making up each frame and a refresh rate of 12.5 to 60 fields per second. The transmission of 1080p involves 1920 horizontal lines by 1080 vertical lines per frame (i.e. 2,073,600 pixels per frame) and a refresh rate of typically 30 to 60 frames per second. The transmission of 4K video involves 3840 horizontal lines by 2160 vertical lines per frame with a typical refresh rate of 30 or 60 frames per second.

[0006] Given the enormous amount of bandwidth required for the transmission of video, various types of video compression, such as MPEG, AVC, and HEVC, are commonly used. Problems with video compression include limited interoperability, increased implementation costs, added latency, increased vulnerability to data loss, and reduced image fidelity. As a result, some image quality is degraded when displaying "compressed video" versus "uncompressed or visually lossless video."

[0007] The magnitude of the above problems will only get worse in the near future. Consumer electronics companies are introducing 8K cameras and displays into the market. These 8K devices have a frame size of 7,680 horizontal and 4,320 vertical lines (i.e. 33,177,600 pixels per frame) and a refresh rate of either 120 frames per second or 240 frames per second. Thus, transmitting 8K video will significantly worsen the existing set of challenges. Furthermore, many of these applications (cameras, video, displays, headsets) will require wireless rather than wired connections.

[0008] Therefore, there is a need for a video transport system that can transmit high quality, high definition video wirelessly without the above drawbacks. Summary of the Invention [Means for solving the problem]

[0009] The present invention relates generally to video or other media transmission, and more particularly to encoding and decoding of video media transmitted wirelessly between a video source and a video sink by using improved spread spectrum direct sequence (SSDS) modulation.

[0010] In one embodiment, the invention is directed to an apparatus for wirelessly transmitting video media, including a Spread Spectrum Video Transport (SSVT) encoder configured to generate one or more electromagnetic signals, each representative of the video media. The one or more electromagnetic (EM) signals are generated by (a) distributing samples into one or more vectors, (b) applying a Direct Sequence Spread Spectrum (SSDS) code to the samples respectively distributed within the one or more vectors, (c) accumulating results from the application of the SSDS codes to the samples respectively distributed within the one or more vectors, and (d) generating one or more electromagnetic signals respectively from the results of the one or more vectors. The apparatus also includes a modulator configured to modulate the one or more electromagnetic signals respectively onto one or more carrier frequency signals, and an antenna configured to wirelessly broadcast the one or more electromagnetic signals respectively modulated onto the one or more carrier frequencies.

[0011] In another embodiment, the invention is directed to an apparatus for wirelessly receiving and decoding EM signals. The apparatus includes an antenna configured to receive a radio broadcast of one or more carrier frequencies having one or more electromagnetic signals modulated thereon, respectively; a demodulator configured to demodulate the one or more electromagnetic signals from the one or more carrier frequencies, respectively; and a decoder for decoding the demodulated one or more electromagnetic signals to recover samples encoded into the electromagnetic signals. The decoder decodes the electromagnetic signals by (a) applying a direct sequence spread spectrum (SSDS) code to the one or more electromagnetic signals that is the same as that used to encode the samples into the electromagnetic signals prior to the radio broadcast, and (b) generating one or more samples from the SSDS code applied to the one or more electromagnetic signals, respectively.

[0012] The invention and its advantages may best be understood by referring to the following description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a system diagram illustrating transmission of an electromagnetic (EM) video signal from a digital video source to a digital video sink by using spread spectrum video transport (SSVT) according to one embodiment of the present invention. [Figure 2A] 1 is a logical block diagram of a spread spectrum video transport (SSVT) transmitter and a SSVT receiver connected by a transmission medium according to one embodiment of the present invention. [Figure 2B] 4 is a diagram of one possible permutation of video signals into vectors that are then encoded for transmission according to one embodiment of the present invention. [Figure 3A] FIG. 2 is a logical block diagram of an SSVT transmitter in accordance with a non-exclusive embodiment of the present invention. [Figure 3B] FIG. 2 is a circuit diagram of an SSVT encoder according to one embodiment of the present invention. [Figure 4A] An example is given showing how signal samples (in this case analog values) are coded in an encoder and then transmitted over an electromagnetic path. [Figure 4B] A novel encoding technique is presented that can be applied to signal samples that are digital values. [Figure 4C] 4B illustrates decoding of an analog input level that has been encoded using the encoder of FIG. 4A. [Figure 4D1] The use of an analogue encoder and a corresponding analogue decoder is shown. [Figure 4D2] The use of a digital encoder and a corresponding analog decoder is shown. [Figure 4D3] 1 illustrates the use of a digital decoder to decode an encoded analog signal arriving over an electromagnetic path. [Figure 4E] 1 shows a simulation of a SSVT waveform transmitted over an electromagnetic path. [Figure 5A] FIG. 2 is a logical block diagram illustrating a SSVT receiver for demodulating P received EM level signals back to samples in accordance with one embodiment of the present invention. [Figure 5B] FIG. 2 is a logical block diagram illustrating another SSVT receiver for demodulating P received EM level signals back to samples in accordance with one embodiment of the present invention. [Figure 6] FIG. 2 is a logic diagram of N decoder tracks for demodulating one differential pair of EM level signals according to one embodiment of the present invention. [Figure 7] FIG. 2 is a circuit diagram of an exemplary encoder track circuit according to one embodiment of the present invention. [Figure 8A] 4 is a circuit diagram of another decoder circuit for decoding SSDS encoded samples of video media according to one embodiment of the present invention; [Figure 8B] 1 shows a passive multiply-accumulator decoder that implements a partially pipelined approach in which no multiplexers are required. [Figure 9] 8B is a timing diagram illustrating the operation of the decoder circuit of FIG. 8A according to one embodiment of the present invention. [Figure 10] 8B illustrates storage banks and control logic used within the decoder circuit of FIG. 8A according to one embodiment of the present invention. [Figure 11] 1 shows a block diagram of a wireless implementation of a transmission medium according to one embodiment of the present invention; [Figure 12A] 1 illustrates a wireless transmitter according to one embodiment of the present invention. [Figure 12B] 1 illustrates a wireless receiver according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] SSDS is a modulation scheme in which a signal (e.g., a series of electrical or electromagnetic values) within a particular bandwidth is intentionally spread by using orthogonal codes, resulting in a signal with a wider bandwidth. The wider bandwidth signal is then transmitted over a transmission medium. At the receiving end, the wider bandwidth signal is demodulated by using the same orthogonal codes used for modulation at the transmitting end. As a result, the original electrical or electromagnetic signal is recovered.

[0015] The present invention is directed to a circuit for encoding and decoding samples transmitted wirelessly between a video source and a video sink. In operation, a stream of time-sequenced video samples, including color values ​​and pixel-related information, is received from the video source and reconstructed for the video sink. As described in more detail below, the number and content of input video samples received from the video source depends on the operating color space of the video source. Regardless of which color space is used, each video sample represents a sensed or measured amount of light in a specified color space. Once the stream of input video samples is received, the input video samples are repeatedly (1) distributed by assigning the input video samples into encoder input vectors according to a predetermined permutation, and (2) encoded by applying SSVT modulation by applying an orthogonal code to each encoder input vector of the multiple encoder input vectors, to generate a plurality of composite EM signals having pseudo-noise characteristics. The EM signals are then (3) transmitted, such as wirelessly, over a transmission medium. At the receiving end, (4) the arriving EM signal is decoded by applying SSVT demodulation to reconstruct the samples into an output vector and by applying the same orthogonal code, and then (5) the output vector is collected by assigning the reconstructed video samples from the output vector to an output stream by using the inverse of a predefined permutation. As a result, a raw stream of time-series video samples including color and pixel-related information is conveyed from the video source to the video sink.

[0016] The following discussion describes the process of how video data is typically captured. Once captured, the video data can be transmitted to an analog video display for near real-time consumption. It is proposed herein that SSVT is used to wirelessly transmit video data from a video source (or storage device) to a video sink for display (or storage).

[0017] Video capture The following specification uses an example in which video samples are transmitted between a video source and a video sink using the novel video transport technique. Although pixel voltages are used herein as one type of sample, the technique may be used with voltages that represent a wide variety of other samples, such as signals from sensors (LIDAR values, audio values, tactile values, aerosol values, etc.), and the samples may represent values ​​other than voltages, such as currents.

[0018] FIG. 1 is a block diagram of a system 10 illustrating the transmission of electromagnetic (EM) signals from a video source to a video sink. Once captured, the video data is typically transmitted to a video display for near real-time consumption. Video source 12 includes an image sensor array 16 (possibly one or more analog-to-digital converters 18, an Image Signal Processor (ISP 20)), and a video streamer 21 responsible for generating a stream of video samples 22. Video source 12 may also optionally be connected to a video media storage device 24. The storage device may be either proximate to the location of image sensor array 16 or remote thereto. Video source 12 may be any device capable of capturing imaging information, such as, but not limited to, a video camera, an infrared imaging device, an ultrasound imaging device, a magnetic resonance imaging (MRI) device, a computed tomography device, or virtually any other type of imaging device capable of generating video information.

[0019] Image sensor 16 is any device (such as a planar array of photodiodes) capable of generating an electronic signal proportional to the amount of incident light. Each photodiode represents a pixel location in the planar array. The number of photodiodes in the planar array can vary widely and thus depends on the size of image sensor 16. Image sensor 16 can be of any size. As a result, the array of photodiodes generates a set of voltages that collectively represent a frame. As the image sensor is continually refreshing at a given frame rate, multiple sets of voltages, each representing a frame, are generated in succession one after the other. In operation, image sensor 16 continuously cycles through sensing intervals at a given refresh rate. During each sensing interval, each photodiode in the array generates a voltage for each pixel location that is inversely proportional to the number of photons incident on the photodiode.

[0020] For each pixel location, a photodiode is provided between a capacitor and ground. Just prior to the sensing interval, the capacitor is precharged. When sensing, the photodiode generates a current proportional to the amount of light received. If little or no light is sensed, little or no capacitor discharges to ground through the photodiode. Conversely, if a large amount of light is sensed, most of the voltage on the capacitor is discharged. Thus, the voltage remaining on the capacitor following an exposure period is inversely proportional to the amount of light sensed.

[0021] For many digital image sensor arrays 16, there is typically one row of analog-to-digital converters ("ADCs") 18 (one ADC per column). During a given frame interval, all rows of the array 16 are sampled (usually top-to-bottom, one after the other), sometimes referred to herein as "row-major" order. With each sample, the ADC 18 converts the sensed voltage into a digital value for the pixel location per column in the array. The frame ends when all rows of the array 16 have been sampled. The above process is repeated in row-major order on a frame-by-frame basis. The net result is a series of digital values, each representing a pixel location in the frame. The number of bits used to represent each sample can vary widely. For example, each voltage may be converted by the ADC 18 into an 8- or 10-bit value.

[0022] The image sensor array 16 can be either monochrome or color. In the former case, the digital values ​​produced by the ADC 18 represent only one color. For the latter, well-known color techniques such as Bayer filtering are typically applied. For Bayer filtering, individual photodiodes are selectively covered with filters of a given color (e.g., either red (R) or blue (B) or green (G)). In alternative embodiments, CYGM (cyan, yellow, green and magenta) or CMY (cyan, magenta and yellow) filtering may be used. Regardless of the type of filter used, the magnitude of the filtered light is measured at each sample location.

[0023] The ISP 20 is arranged to interpolate the sequence of digital values ​​received from the ADC 18. By interpolation, the ISP 20 takes the information contained in the digital values ​​of each pixel measurement and its geometric neighboring pixel measurements and defines an estimate of the color of the corresponding pixel. To output a full-color image in a particular color space (of which there are many), the ISP 20 interpolates the "missing" color values ​​at each location. That is, given only a single color measurement per pixel, the ISP algorithmically estimates the "missing" color values ​​to generate, for example, an RGB or YCbCr representation of the pixel. The ISP 20 thus generates a set of samples 22 for a given pixel of a given frame, each set of samples 22 representing a color value (either measured or interpolated) for a given pixel location in the frame.

[0024] In another embodiment, the series of voltages need not be converted to digital by an ADC or processed by the ISP. A series of analog voltages may be output from the sensor 16 as analog samples, in which case the transmitter 28 may perform the encoding on the analog samples rather than the digital samples. These analog signals are presented to the transmitter 28, which operates in a sampled analog manner to perform the encoding in a mathematically identical manner to the digital version. In this embodiment ISP (20), the video streamer (21) and retimer (26) would not be used.

[0025] The content of a given set of samples 22 may vary since there are many ways to represent color. RGB provides three color values. With YCbCr, Y is the luminance component, and Cb and Cr are the blue-difference and red-difference chroma values, respectively. The YCbCr color space is defined by a mathematical coordinate transformation from the associated RGB color space. In yet another way to represent color, an alternative approach may be used. For example, every other pixel is represented by its luminance (Y) value, while an alternative pixel is represented by either a Cb (blue) or Cr (red) value. Thus, in various embodiments, each set of samples 22 includes a number "S" of sample values ​​that are transmitted in parallel. With RGB, the number S of samples per set of samples 22 is S=3, while for YCbCr, S=2. The number of samples generated by the ISP per pixel location depends on the ISP implementation (particularly the color space applied) and may be less than 2 or greater than 4.

[0026] In response, the video streamer 21 generates a series of time-sequenced sets of samples 22. Typically, each set of samples 22 output together represents a light measurement of one pixel location on the array 16. The value and number of samples generated by the ISP per pixel location depends on the ISP implementation (particularly the color space applied). The output of the video streamer 21 is a continuous stream of time-sequenced sets of samples 22 as long as the array 16 is sensing, with each time-sequenced set of samples 22 representing a pixel in a row, from left to right, in row-major order, from frame to frame. The stream of sets of samples 22 is then processed by the video sink 14 after transmission to reconstruct the image sensed by the image array sensor 16, frame by frame.

[0027] In another optional embodiment, the stream of several sets of samples 22 may be stored in the storage device 24. In this manner, the stream of several sets of samples 22 may be transmitted any time after the video stream was initially captured by the image sensor 16. For example, the stream of several sets of samples 22 may be captured during a time interval and then either transmitted frame by frame to the video sink 14 for display and stored in the storage unit 24 for transmission to the video sink 14 at some later time. In this manner, the video captured by the video source 12 may be displayed by the video sink 14 in a time-shifted manner.

[0028] The advantage of using SSVT in the context of image capture and display is that "images are measured on inherently error-prone sensors, displayed on inherently noisy LED arrays, and viewed by the extremely complex and robust human visual system." As a result, the communication requirements for video are very different from those for traditional digital artifacts (such as spreadsheets and email), where bit-perfect transmission is required. Traditional video transmission, however, treats video signals like an entirely different kind of (digital) document. However, with SSVT, the video signal is transmitted in an electrically robust manner. Among the advantages of SSVT is that "any uncompensated errors that occur in the EM signal measurements at the receiver will appear in the reconstructed image as broad-spectrum temporal and spatial noise." Such white noise is more acceptable to human perception than the blank screen, repeating image, and blocky compression artifacts that arise from traditional bit-serial transmission.

[0029] send 1 further includes a transmit re-timer 26 and a spread spectrum video transport (SSVT) transmitter (TX) 28 on the transmitting side. As described in more detail below, the re-timer 26 is responsible for decoding or exposing color component information (e.g., RGB values) from each of a number of sets of samples 22 in the stream generated by the video streamer 21. The SSVT 28 is then responsible for (a) distributing the set of samples 22 into one of a number of encoder input vectors by using a predetermined permutation, (b) applying SSDS modulation to each of the number of encoder input vectors, (c) encoding the number of input vectors with SSDS-based encoding to generate a number of sequences of EM level signals, and then (d) transmitting the number of sequences of EM level signals over a number of EM paths on a transmission medium such as a radio towards the video sink 14. The stream of the number of sets of input samples 22 is distributed at a first clock rate (pix-clk) to generate the encoder input vectors according to a predetermined permutation. The encoded EM signal may then be transmitted over the medium at a second clock rate (SSVT_clk).

[0030] On the receiving side, there is provided an SSVT receiver (RX) 30, a re-timer 32, and a video sink 14. The functions of the SSVT receiver (RX) 30 and the re-timer 32 are complementary to the re-timer 26 and the SSVT transmitter 28 on the transmitting side. That is, the SSVT receiver RX 30 (a) receives several sequences of EM level signals from several EM paths of the transmission medium, (b) decodes each sequence by applying SSDS-based demodulation to reconstruct the video samples into several output vectors, and (c) collects the samples from the several output vectors into several sets of samples 22 into a reconstruction of the original stream by using the same permutation used to distribute the input samples into the input vectors on the transmitting side. The re-timer 32 then converts the reconstructed output samples into a format suitable for display by the video sink 14 or into a format suitable for storage on the receiving side for display in time-shift mode. The number S of output sample values ​​in each set of samples 22 is determined by the color space applied by the video source (S=3 for RGB, S=2 for YCbCr). In other situations, the sample values ​​S in each set of samples 22 may be less than two (ie, just one) or more than three.

[0031] As described in more detail below, a stream of several sets of input samples 22 are spread at a first clock rate (pix-clk) to generate encoder input vectors according to a predetermined permutation. Then, SSDS-based modulation is applied to each of the encoder input vectors, resulting in the generation of an encoded EM code for each encoder input vector. The EM signals are then transmitted over the vehicle in parallel at a second clock rate (SSVT_clk). Applying direct sequence spread spectrum (SSDS) to each sample in the encoder input vector provides electrical resilience but at the expense of bandwidth per sample. By modulating a set of mutually orthogonal codes and transmitting all of the resulting EM signals simultaneously, some or all of the lost bandwidth is recovered.

[0032] 2A is a logical block diagram of an SSVT transmitter 28 and an SSVT receiver 30 connected by a transmission medium 34. The SSVT transmitter 28 includes a stripper 40 and a number of encoders 42. The SSVT receiver 30 includes a number of decoders 44 and a collector 46.

[0033] On the transmitting side, the stripper 40 of the SSVT receiver 30 is arranged to receive color information (e.g., R, G and B values) exposed in the input sets of samples 22. In response, the stripper 40 takes the exposed color information of the incoming sets of samples 22 and constructs a number of encoder input vectors according to a predefined permutation. In the embodiment shown in FIG. 2A, there are four encoder input vectors (V0, V1, V2 and V3), one for each of the four EM paths on the transmission medium 34. In various embodiments, the transmission medium 34 can be a cable, such as an HDMI, optical fiber or wireless. The number of paths on the transmission medium 34 ranges from one to any number greater than or equal to two. One of the multiple encoders 42 is assigned to one of the four vectors V0, V1, V2 and V3, respectively. Each encoder 42 is responsible for encoding the sample values ​​contained in the corresponding encoder input vector and for generating an EM signal to be transmitted on one of the parallel paths on the transmission medium 34.

[0034] In this particular embodiment shown, there are four EM paths, and the four encoders 42 each generate an EM signal for each of the four paths, respectively. However, it should be understood that the invention should in no way be limited to four paths. On the contrary, the number of paths on the transmission medium 34 can range widely from one to any number greater than one, including five or more.

[0035] Permutation Example 2B, a diagram of one possible permutation performed by the scatterer 40 to construct four vectors V0, V1, V2, and V3 is shown. Each of the vectors includes N samples of color information. In this example, the exposed color information of the sets of samples 22 is "RGB", respectively. The exposed RGB samples of the sets of samples 22 in this example are assigned from left to right to vectors V0, V1, V2, and V3. In other words, the "R", "G", and "B" values ​​of the leftmost sample and the "R" signal of the next set of samples 22 are assigned to vector V0, while the next (from left to right) "G", "B", "R", and "G" values ​​of the next sample 22 are assigned to vector V1, the next (from left to right) "G", "B", "R", and "G" values ​​are assigned to vector V2, and the next (from left to right) "R", "G", "R", and "R" values ​​are assigned to vector V3. A fourth vector V3 is assigned to the signal and the above process is repeated until each of the four vectors V0, V1, V2 and V3 has N samples.

[0036] In various embodiments, N of samples can vary widely. As an example, consider an embodiment with N=60. In this case, the total number of N samples contained in the four vectors V0, V1, V2 and V3 is 240 (60×4=240). The four encoder input vectors V0, V1, V2 and V3, when fully constructed, contain 80 (240 / 3=80) distinct sets of samples 22 (where S=3). In other words: Vector V0 is the sample P0, N0~P0, N N-1 Includes; Vector V1 is the sample P1, N0~P1, N N-1 Includes; Vector V2 is sample P2, N0~P2, N N-1 including; and Vector V3 is sample P3, N0~P3, N N-1 Includes.

[0037] It should be understood that the above examples are merely illustrative and therefore should not be construed as limiting. The number of samples N may be approximately 60. It should also be understood that (a) the exposed color information of each set of samples may be any color information (e.g., Y, C, Cr, Cb, etc.) and is not limited to RGB. The number of EM paths on the transmission medium 34 may also vary widely. Thus, the number of vectors V and the number of encoders may also vary widely from just 1 or any number greater than 1. It should also be understood that "any permutation scheme used to construct the vectors may be used, limited only by the requirement that any permutation scheme used at the transmitting end is also used at the receiving end."

[0038] 3A is a block diagram of SSVT transmitter 28. As discussed herein, the outputs of encoders 42 (EM signals 0-P-1) are directed onto a transmission medium, such as cable, optical fiber, wireless, etc. Distributor 40 includes assembly bank 50, relay bank 52, presentation bank 54, and controller 56. Encoder block 60 includes a bank of digital-to-analog converters (DACs) 62 and any number P of encoders 42 (one for each EM path for transmitting the EM signals over the transmission medium).

[0039] As a stream of input video samples is received into assembly bank 50, the input video samples are (1) iteratively distributed by assigning the samples to encoder input vectors (one vector per encoder) according to a predefined permutation, (2) encoded by applying modulation to each of the input vectors by using orthogonal codes to generate multiple composite EM signals (one analog signal from each encoder), and then (3) transmitted over a transmission medium.

[0040] The stripper 40 is arranged to receive, one after the other, the exposed color information (e.g., RGB) of the stream of sets of samples 22. In response, the assembly bank 50 constructs four vectors V0, V1, V2 and V3 from the exposed color information (e.g., RGB) of the arriving stream of sets of samples 22. Once received, the sets of samples 22 are stored in the assembly bank 50 according to a predefined permutation.

[0041] The relay bank 52 facilitates the crossing of N samples of each of the four vectors V0, V1, V2 and V3 from a first clock frequency or domain used by the retimer 26 into a second clock frequency or domain used for encoding and transmitting the resultant EM level signal on the transmission medium 34. As already discussed in the above example with N=60 and S=3, samples representing exactly 80 pairs of RGB samples are contained within the four encoder input vectors V0, V1, V2 and V3.

[0042] In various embodiments, the first clock frequency can be faster, slower, or the same as the second clock frequency. The first clock frequency f_pix is ​​determined by the video format selected by the video source. The second clock frequency f_ssvt is a function of f_pix, the number of EM paths in the transmission medium P, the number of samples in each set of input / output samples S, and the SSVT transformation parameters N (the number of input / output vector locations) and L (the length of each SSDS code), where f_ssvt=(f_pix×S×L) / (P×N). With this arrangement, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at another rate. These rates may be the same or different. The encoder performs the encoding while the next input vector is prepared. The presentation bank 54 presents N samples of each of the four encoder input vectors V0, V1, V2, and V3 to the encoder block 60 (e.g., vector V0 is represented by Sample 0,0 ~Sample 0,N-1 (including

[0043] Controller 56 controls the operation and timing of assembly bank 50, relay bank 52 and present bank 54. In particular, the controller is responsible for defining the permutation and number of samples N to be used in constructing the four encoder input vectors V0, V1, V2 and V3. Controller 56 is also responsible for coordinating the clock domain crossing from a first clock frequency to a second clock frequency performed by relay bank 52. Controller 56 is further ... -1 ) to the encoder block 60.

[0044] Within the encoder block 60, there are P×N samples (Sample 0,0 ~Sample P-1,N-1 A plurality of digital-to-analog converters (DACs) 62 are provided, each arranged to receive one of the inputs of the digital inputs. Each DAC 62 converts its received sample from the digital domain into a differential pair of voltage signals having a magnitude proportional to its arriving digital value. The output of the DAC 62 can range from a minimum voltage to a maximum voltage.

[0045] Four encoders 142 are provided for each of the four encoder input vectors V0, V1, V2 and V3. Each encoder 42 receives a differential pair of signals for each of the N samples of its encoder input vector, modulates each of the N differential pairs of voltage signals by using a chip from the code corresponding to each sample, accumulates these modulation values, and then generates L differential output levels that generate one of the EM signals. Since there are four encoders 42 in this example, there are EM Signal0 to EM Signal3 output simultaneously. Preferably, L≧N≧2. As explained, the encoding can be analog (a DAC is placed before the encoder) or digital (the L levels are converted to analog by a DAC before being transmitted). The L analog output levels are then transmitted as part of the SSVT signal on its EM path to the SSVT receiver. Advantageously, the SSVT signal is an analog signal and no DAC is required in the source driver.

[0046] The sequencer circuit 65 coordinates the timing of the operation of the DAC 62 and the encoder 42. The sequencer circuit 65 is responsible for controlling the clocks of the DAC 62 and the encoder 42. As will be explained in more detail below, the sequencer circuit 65 is also responsible for generating two clock phase signals “clk1” and “clk2” that are responsible for controlling the operation of the encoder 42.

[0047] 3B, there is shown a circuit diagram of an encoder 42 for one of the input vectors V. The encoder circuit 42 includes a multiplier stage 71 having a number of multiplier stages 70 and an accumulator stage 72 including a differential amplifier 74.

[0048] Each multiplier stage 70 receives a differential pair of sample signals (+Sample N-1 / -Sample N-1Each multiplier stage 70 also includes a terminal for receiving a chip from the code, an inverter 73, several sets of switches S1-S1, S2-S2 and S3-S3 driven by clk1 and clk2, respectively, and equal value storage devices C1 and C2, each storing voltage samples as they are exposed to various switches and thus storing different voltages across each device at various times according to the switching sequence.

[0049] In operation, each multiplier stage 70 modulates its received differential pair analog signal by conditionally multiplying it by either (+1) or (-1) depending on the value of the received chip. If the chip is (+1), when clk1 is active, switch pairs S1-S1 and S3-S3 are closed while switch pair S2-S2 remains open. This results in the + / - samples of both differential pairs being stored on storage devices C1 and C2, respectively, without inversion (i.e., multiplied by +1). On the other hand, if the chip is (-1), the above-mentioned complementary state occurs. In other words, when clk1 is active, switch pair S1-S1 is open, switch pair S2-S2 is closed, and switch pair S3-S3 is closed. This results in the samples of the differential pairs being switched and stored on C1 and C2, respectively, thus multiplying by -1.

[0050] The accumulator stage 72 operates to accumulate charge on the storage devices C1 and C2 of all multiplier stages 70. When clk1 transitions to an inactive state and clk2 transitions to an active state, all clk1 controlled switches (S3-S3, S4-S4) open and clk2 controlled switches (S5-S5, S6-S6) close. As a result, all charges on the first storage devices C1 of all multiplier stages 70 are amplified by amplifier 78 and accumulated on a first input of differential amplifier 74, while all charges on the second storage devices C2 of all multiplier stages 70 are amplified by amplifier 78 and accumulated on a second input of differential amplifier 74. In response, differential amplifier 74 generates a pair of differential electromagnetic (EM) level signals. Amplifier 74 may use the same Vcm as the amplifier 78 immediately to its left. Depending on the implementation, the resistor R1 shown for each amplifier 78 and 74 may be the same or different, and the resistor R1 for amplifier 74 may be the same or different from that of amplifier 78. Capacitors C1, C2, C3 and C4 should be of the same size.

[0051] The above process is performed for all four vectors V0, V1, V2 and V3. In addition, the above process is continuously repeated as long as several sets of streams of samples 22 are received by the SSVT transmitter 28. In response, four streams of differential EM output level signals are transmitted over the transmission medium 34 to the SSVT receiver 30.

[0052] SSVT signal encoding and decoding FIG. 4A shows a simple example of how signal samples (in this case analog values) are coded in an encoder and then transmitted over an electromagnetic path. Shown is an input vector of N analog values ​​902-908 representing the voltages of individual pixels in a video frame. These voltages may represent the luminance of a black and white image or the luminosity of a particular color value in a pixel (e.g., the R, G, or B color value of the pixel) (i.e., each value represents a sensed or measured amount of light in a specified color space). Although pixel voltages are used in this example, this coding technique could be used with voltages representing any of a wide variety of signals from a sensor (LIDAR values, audio values, tactile values, aerosol values, etc.). Signal samples that are digital values ​​could also be coded, and this digital coding is described below. Furthermore, even though one encoder and one EM path are shown, one embodiment of the present invention works well with multiple encoders, each transmitting over an EM path.

[0053] Preferably, these voltages range from 0 to 1V for efficiency, but different ranges are possible. These voltages are usually taken from the pixels in a row of a frame in a particular order, but other conventions can be used to select and order these pixels. Regardless of which convention is used to select these pixels and order them for encoding, that same convention will be used at the receiving end by the decoder to decode these voltages in the same order and place them in the resulting frame to which they belong. Similarly, if the frame is in color and uses RGB, the convention at the encoder could be that all of the R pixel voltages are encoded first, then the G and B voltages, or the convention could be that voltages 902-906 are the RGB values ​​of the pixels in that row, and the next three voltages 908-912 represent the RGB values ​​of the next pixel. Again, the same convention used by the encoder to order and encode the voltages is used by the decoder at the receiving end. Any particular convention for ordering the analog values ​​902-908 (whether by color value, by row, etc.) can be used as long as the decoder uses the same convention. As shown, any number N of analog values ​​902-908 can be presented for encoding at one time using the codebook 920, limited only by the number N of entries in the codebook.

[0054] As mentioned above, the codebook 920 has an arbitrary number N of codes 932-938; i.e., in this simple example, the codebook has four codes, which means that four analog values ​​902-908 are encoded at a time. Many more codes could be used, such as 127 codes, 255 codes, etc., but due to practical considerations such as circuit complexity, it is preferable to use fewer codes. As is known in the art, the codebook 920 includes N mutually orthogonal codes, each of length L; in this example, L=4. Typically, each code is an SSDS code, but not necessarily a spreading code as discussed herein. As shown, each code is divided into L time intervals (also called "chips"), each time interval containing the binary value of that code. As shown in code representation 942, the code 934 may be represented in traditional binary form "1100", but the same code may also be represented as "11-1-1", as shown in code representation 944, for ease of use in modulating values, as will be described below. Codes 932 and 936-938 may also be represented by codes 942 or by 944. Note that each code of length L is not associated with a different computing device (such as a phone), a different person, or a different transmitter.

[0055] Thus, to transmit the four analog values ​​902-908 (in this simple example) over the transmission medium 34 to a receiver (with a corresponding decoder), the following technique is used: Each analog value will be modulated by each chip in the representation 944 of its corresponding code; for example, value 902 (i.e., .3) is modulated 948 in turn by each chip in the representation 944 of code 932. The modulation 948 may be a multiplication operator. Thus, modulating .3 with code 932 results in the sequence ".3, 3, 3, 3". Modulating .7 with code 934 results in ".7, 7, -.7, -.7"; a value "0" becomes "0, 0, 0, 0"; and a value "1" becomes "1, -1, 1, -1". Typically, the first chip of each code modulates its corresponding analog value, and then the next chip of each code modulates that analog value, but an implementation may also modulate a particular analog value with all the chips of that code before moving on to the next analog value.

[0056] For each time interval, the modulated analog values ​​are summed 951 (perceived vertically in this figure) to obtain analog output levels 952-958; for example, the sum of the modulation values ​​for these time intervals results in output levels of 2, 0, 6, and -1.4. These analog output levels 952-958 may be further normalized or amplified to match the voltage constraints of the transmission line and then transmitted sequentially as they are generated on the electromagnetic path (such as a differential twisted pair) of the transmission medium 34. A receiver then receives these output levels 952-958 in that order and then decodes them using the same codebook 920 using the inverse of the encoding scheme shown here. The resulting pixel voltages 902-908 may then be displayed within the frame of a display at the receiving end according to the convention used. Thus, the analog values ​​902-908 are effectively coded in parallel and transmitted on a single electromagnetic path in a series of L analog output levels 952-958. An infinite number of encoders and electromagnetic paths can also be used as shown and described herein. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0057] Advantageously, even though the use of robust SSDS techniques (such as spreading codes) results in significant bandwidth loss, the use of mutually orthogonal codes, modulating each sample with a chip of its corresponding code, summing, and transmitting N samples in parallel using L power levels results in significant bandwidth gain. In contrast to traditional CDMA techniques, in which binary numbers are coded successively and then added, the present invention first modulates each sample with each chip in the corresponding code, and then sums those modulations at each time interval of the code to obtain the resulting analog voltage level at each particular time interval. It is these analog output levels (not the binary number representation) that are transmitted over the transmission medium. Furthermore, the present invention transmits analog voltages from one video source to another video sink (i.e., from end-point to end-point). Unlike CDMA techniques, which allow multiple accesses by different people, different devices, or different sources, the modulation and summation of samples of the present invention is used to compensate for the bandwidth loss introduced by SSDS techniques, transmitting a frame or frames of video information from a single video source to a single video sink (i.e., from a single sensor (or sensors) at the source to a single location at the sink).

[0058] 4B illustrates the novel encoding technique that is applicable to signal samples that are digital values, where digital values ​​902'-908' are digital representations of voltages (i.e., binary numbers transmitted and stored as bits). Using various examples of voltages, value 902' is "1101", value 904' is "0011", value 906' is "0001" and value 908' is "1000". Each digital value is modulated (digitally multiplied) by a representation 944 of each code (i.e., by "1" or "-1" depending on the chip of the code that corresponds to the digital value being modulated). Considering only the first time interval 940 of each code and adding the most significant bit (MSB), which is the sign bit, a modulation of "1101" results in "01101" (MSB "0" signifies a positive value), a modulation of "0011" results in "00011", a modulation of "0001" results in "00001", and a modulation of "1000" results in "01000". These modulation values ​​are shown and annotated on the first time interval. (Although not shown, modulating with a -1 chip results in a negative value that can be expressed in binary using the preferred binary representation for negative values).

[0059] By digitally summing, these modulation values ​​in the first time interval result in digital value 952' "011001" (again, the MSB is the sign bit); the other digital values ​​954'-958' are not shown in this example but are calculated in the same way. Considering this sum in base 10, we can verify that the modulation values ​​13, 3, 1 and 8 sum to 25. Although not shown in this example, typically an additional MSB is available for the result levels 952'-958' in that the sum may require more than six bits. For example, if the values ​​902'-908' are represented using 4 bits, the levels 952'-958' may be represented using a maximum of 10 bits in the case that there are 64 codes (adding the log2 of 64 bits). Or, if 32 modulation values ​​are summed, five more bits are added. The number of bits required for the output level depends on the number of codes.

[0060] The output levels 950' may first be normalized to accommodate the input requirements of the DAC, and then sequentially fed to the DAC 959 to convert each digital value to its corresponding analog value for transmission on the EM path. The DAC 959 may be a MAX5857 RF DAC (including a clock multiplying PLL / VCO and a 14-bit RF DAC core, where the complex path may be bypassed to directly access the RF DAC core), followed by a bandpass filter, not shown, and then a variable gain amplifier (VGA). In some situations, the number of bits used in the levels 950' is greater than the number allowed by the DAC 959, for example, the levels 952' are represented by 10 bits, but the DAC 959 is an 8-bit DAC. In these situations, the appropriate number of LSBs are discarded and the remaining MSBs are processed by the DAC, with no loss of visual quality of the resulting image on the display.

[0061] Advantageously, all digital values ​​are modulated and then all these modulated digital values ​​are digitally summed to generate a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each binary digit of a digital value and then sums these modulated bits to generate an output. For example, assuming there are B bits in each digital value, with CDMA there would be a total of B x L power levels to transmit, whereas with this new digital encoding technique there would only be a total of L power levels to transmit, thus having an advantage.

[0062] FIG. 4C illustrates the decoding of analog input levels encoded using the encoder of FIG. 4A. As shown, L input levels 950 are received on a single electromagnetic path of the transmission medium 34. As described herein and noted above, the codebook 920 includes N orthogonal codes 932-938 that are used to decode the input levels 950 to generate N analog values ​​902-908, i.e., an output vector of the same analog values ​​902-908 encoded as described above. To perform the decoding, as indicated by the vertical arrows, each input level 952-958 is modulated 961 with each chip of each code that corresponds to a particular index in the output vector 902-908. Considering the modulation of the levels 952-958 by the first code 932, such modulation produces a sequence of modulation values ​​"2, 0, 6, -1.4". Modulation of levels 952-958 with a second code 934 produces a sequence of modulation values ​​"2,0,-.6,1.4". Modulation with a third code 936 produces "2,0,-.6,-1.4" and modulation with a fourth code 938 produces "2,0,6,1.4".

[0063] The modulation values ​​of each sequence are then summed to generate one of the analog values ​​902-908, as indicated by the horizontal arrows. For example, the first sequence is summed to generate the analog value "1.2" (which becomes "3" after normalization using a scale factor of "4"). In a similar manner, the modulation values ​​of the other three sequences are summed to generate the analog values ​​"2.8", "0" and "4", which after normalization results in an output vector of analog values ​​902-908. Each code may modulate an input level and then the sequences may be summed, or all codes may modulate an input level before each sequence is summed. Thus, an output vector of N analog values ​​902-908 is transported in parallel using L output levels.

[0064] Although examples of decoded digital input levels are not shown in these examples, one skilled in the art will recognize that it is simple and clear to perform such decoding by reading the encoding of digital values ​​in the above description.

[0065] Figures 4D1, 4D2 and 4D3 show that the encoders and decoders can operate on either analog or digital samples. Various analog and digital encoders and decoders have already been described above.

[0066] FIG. 4D1 illustrates the use of an analog encoder and corresponding analog decoder. The input to the analog encoder 900 is either analog samples 970 converted to analog by a DAC 972 located in the analog encoder or digital samples 971. In this manner, either analog or digital samples arriving at the analog encoder can be encoded for transmission over an electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog samples to generate analog samples 970 for output. The analog samples 970 may be used as is or may be converted to digital samples using an ADC (not shown).

[0067] FIG. 4D2 illustrates the use of a digital encoder and a corresponding analog decoder. The input to the digital encoder 901 is either analog samples 970 or digital samples 971 converted to digital by an ADC 973 located in the digital encoder. Because the encoder is digital, a DAC 959 located in the encoder converts the encoded samples to analog before transmission over the electromagnetic path. In this manner, either analog or digital samples arriving at the digital encoder can be encoded for transmission over the electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog samples to generate analog samples 970 for output. The analog samples 970 may be used as is or may be converted to digital samples using an ADC.

[0068] FIG. 4D3 illustrates the use of a digital decoder to decode an encoded analog signal arriving over an electromagnetic path on a transmission medium 34. The encoded analog signal can be transmitted by using either the analog encoder of FIG. 4D1 or the digital encoder of FIG. 4D2. An ADC 974 located in a digital decoder 976 receives the encoded analog samples transmitted over the electromagnetic path and converts the samples to digital. These encoded digital samples are then decoded by the digital decoder 976 into digital samples 978 (corresponding to the values ​​of the input vector of samples originally encoded before transmission over the electromagnetic path). The digital samples 978 can be used as is or can be converted to analog samples using a DAC.

[0069] FIG. 4E shows a simulation (resembling an idealized oscilloscope trace) of an SSVT waveform 602 transmitted over an electromagnetic path after being output from an analog encoder (or after being digitally encoded and then converted by a DAC). The vertical axis is voltage, and the horizontal axis is the 100 ps oscilloscope measurement time interval. Note that the SSVT signal 602 is an analog waveform rather than a digital signal (i.e., the signal does not represent a binary number), and in this embodiment, may transport a range of voltages from about -15V to about +15V. The voltage values ​​of an analog waveform are (or at least can be) fully analog. Also, the voltage is not limited to some maximum value, although higher values ​​are impractical.

[0070] As explained before, analog voltage levels are transmitted in series over the electromagnetic path, with each level (either the analog output levels 952-958 after passing through the DAC or the digital output levels 952'-958') being the sum of modulated samples for each time interval. When transmitted, these output levels appear as waveforms, such as waveform 602. In particular, voltage level 980 represents the sum (i.e., output level) of modulated samples in a particular time interval. Using a simple example, the series of voltage levels 980-986 represents the transmission of four output levels. In this example, 32 codes are used, meaning that 32 samples can be transmitted in parallel; thus, voltage levels 980-986 (followed by 28 voltage levels in succession) form a parallel transmission of 32 samples (such as pixel voltages from a video source). After that transmission, the next 32 voltage levels of waveform 602 represent the transmission of the next 32 samples. In general, waveform 602 represents the encoding of analog or digital values ​​into analog output levels and the transmission of those levels within discrete time intervals to form a composite analog waveform.

[0071] Due to such phenomena as attenuation, reflections due to impedance mismatch, and intrusive aggressor signals, every electromagnetic path degrades the electromagnetic signal propagating through it, and therefore a taken measurement of the input level at the receiving terminal is always subject to an error with respect to the corresponding output level made available at the transmitting terminal. Therefore, scaling of the input level at the receiver (or normalization or amplification of the output level at the transmitter) can be performed to correct, as known in the art. Furthermore, due to process gain, the decoded input level at the decoder is normalized by a scale factor using the code length to recover the transmitted output level, as known in the art. Furthermore, as described herein, it is preferable that L≧N≧2, but it is possible that in some situations L is less than N (i.e., N>L≧2).

[0072] Receiver 5A shows a block diagram of the SSVT receiver 30, retimer 32, and video display 85 of the video sink 14. On the receiving side, the SSVT receiver 30 is responsible for decoding the stream of four differential EM level output signals received on the transmission medium 34 back into a suitable format for display. Once back into a suitable format, the video content contained in the samples 22 (e.g., signal S) can be presented on the video display (frame-by-frame). As a result, the video capture by the video source 12 can be reproduced by the video sink 14. Alternatively, the decoded video information can be stored in a time-shift mode for display at a later time.

[0073] The receiver 30 reverses the encoding performed by the transmitting SSVT transmitter 28. The receiver 30 uses four decoders 80 and one collector 46. The decoders 80 reconstruct the four differential EM level output signals into four decoder output vectors. The collector 46 then assigns the samples of the decoder output vectors to the original stream of samples 22 in sets. Each set contains S reconstructed samples that correspond to the original S samples at that location in the stream.

[0074] P decoders 80 (labeled 0 to P-1) generate differential EM level signals Level0 to Level P-1 In response, each of the decoders 80 receives the reconstructed samples (Sample 0 to Sample N-1 ) for the case where there are four decoders 80 (P=4), four vectors V0, V1, V2 and V3 are constructed, respectively.

[0075] The reconstruction bank 82 stores N reconstructed samples (Sample 0 to Sample 1) of each of the four decoder output vectors V0, V1, V2, and V3 at the end of each decoding interval. N-1An analog-to-digital converter (ADC) 84 samples and holds N samples (Sample 0 to Sample 1) of each of the four vectors V0, V1, V2, and V3. N-1 Each ADC converts the received differential pair voltage signal into a corresponding digital value and outputs a digital sample (Sample N-1 ~Sample0). The ADC runs at clock speed = f_ssvt / L.

[0076] The collector 46 includes a relay bank 86 and a decomposition bank 88. The relay bank 86 stores all reconstructed samples (N n-1 The decomposition bank 88 receives (a) a sample of each of the four decoder output vectors V0, V1, V2, and V3. N-1 〜Sample0) back into exposed color information (e.g., S signal) of a stream of several (e.g., "S=3 for RGB pixels" in this example) sets of samples 22 by using the same permutation scheme used at the transmitting side, and (b) traverse the reconstructed samples from the second clock domain to the first clock domain. The stream of several (e.g., "S=3 for RGB pixels" in this example) sets of reconstructed samples 22 is then provided to a re-timer 32 which reformats the video signal. Thus, the output of the re-timer 32 is a sequence of several time-sequenced sets of samples 22 regenerated. The video sink 14 includes a bank of DACs 103 and a video display 85. The bank of DACs 103 is responsible for converting the samples 22 in the digital domain back to the analog domain. In one embodiment, a DAC 103 is provided for each row in the display 85. Once converted to the analog domain, the samples 22 are displayed on the video display 85 in a well-known manner.

[0077] The receiver 30 also includes a channel aligner 87 and a collector controller 89, which receives framing and aperture information from each decoder 80. In response, the collector controller 89 coordinates the timing of the relay bank 86 and / or the decomposition bank 88 to ensure that all samples presented to the decomposition bank come from a common time interval (the level signal transmitted by the SSVT transmitter 28). As a result, (a) the decomposition by the bank 88 can be delayed until all samples have been received, and (b) the individual channels of the transmission medium 34 do not all need to be of the same length, since the decomposition bank 88 compensates for any timing differences. The collector controller 89 is also responsible for keeping up with any permutations and ensuring that the decomposition bank 88 applies the same permutation that was used in constructing the transmit side vectors V0, V1, V2 and V3.

[0078] In the above embodiment, ADC 84 converts the decoded samples to the digital domain, and a DAC in video sink 14 converts the ordered set of samples 22 back to the analog domain just prior to display. Depending on the implementation and the nature of the samples (e.g., color video samples, black and white video samples, audio sample values, etc.), it may not be necessary to use an ADC to convert the samples back to digital, nor to use a stagger or decomposition bank, etc. For example, once the samples have been decoded and output from each decoder (i.e., once each decoder outputs an output vector of 1 to N sample values), these samples may be used according to the implementation.

[0079] Alternative Embodiments In the above embodiment, ADC 84 converts the decoded samples to the digital domain, and ADC 103 in video sink 14 converts ordered set of samples 22 back to the analog domain just prior to display.

[0080] 5B illustrates an alternative embodiment of SSVT receiver 30. In this alternative embodiment, the samples output from reconstruction bank 82 can remain in the analog domain, thus eliminating the need for ADC 103 in video sink 14. With this embodiment, ADC 84 is eliminated and replaced with a buffer stage (not shown) for buffering the samples output from the reconstruction bank.

[0081] The reconstruction bank 82 stores N reconstructed samples (Sample 0 to Sample 1) of each of the four decoder output vectors V0, V1, V2, and V3 at the end of each decoding interval. N-1 ) of each of the differential pairs. When the EOB signal is received by the reconstruction bank 82, its contents are buffered before being cleared. A strobe signal, or equivalent timing signal, is then used to control the output of the buffered samples to the relay bank 86. These received differential pair voltage signals are then used to generate a sample (Sample N-1 1. Each reconstruction bank essentially reconstructs the differential pair of voltages into a single voltage. The relay bank 86 outputs all the reconstructed samples (N 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 N-1 .N0) and acts as an analog output buffer. Once moved into the relay bank, the samples are triggered by a latch signal derived from the decoded SSVT signal. Once released from the relay bank, the samples are sent to a level shifter 503.

[0082] The framed video signal is then provided to a level shifter 503 that can optionally adjust their gain and gamma values ​​according to gain and gamma value inputs. The gain determines how much amplification is applied, and the gamma curve relates luminous flux to perceived luminance, linearizing human light perception of luminous flux. In an analog level shifter 503, gamma can be implemented by a non-linear amplification characteristic in one non-exclusive embodiment. Level shifting and gain are optionally implemented in driver circuitry associated with the level shifter 503 by setting the output stage amplification.

[0083] The receiver 30 also includes a channel aligner 87 and a collector controller 89, which receives framing and aperture information from each decoder 80. In response, the relay controller 89 coordinates the timing of the relay banks 86 to ensure that all samples come from a common time interval (the level signal transmitted by the SSVT transmitter). As a result, the individual channels of the transmission medium do not all have to have the same length, as the channel aligner 87 and relay controller 89 compensate for any timing differences. The gate driver control signals provide timing information to the gate drivers (or to intermediate circuitry) (which in turn provides the correct timing and control signals to the gate drivers) and may originate from the channel aligner 87.

[0084] Once shifted by the level shifter 503, the samples of a given frame are moved into a latch 504 which is triggered by a latch signal 506 which is derived from the collector controller 89 decoded SSVT signal. Once released from the latch 504, the samples are used to drive source electrodes in their corresponding columns of the display panel as known in the art.

[0085] Thus, with this embodiment, the samples generated by the decoder 80 remain in the analog domain within the receiver 30 from receipt by the decoder 80 via the latching provided by the latch 504. As a result, the DAC 103 within the video sink 14 may be eliminated. Note that Figure 5B discloses a decoder that buffers and then level shifts (amplifies) the samples within the relay bank 86. It is also possible to level shift and then buffer the samples at the output.

[0086] Decoder 6 is a logic diagram of one of the four decoders 80. The decoder 80 includes a differential amplifier 92 and a sample and hold circuit 94 arranged to receive and sample and hold one of the four differential EM level signals received on the transmission medium 34. The sampled EM level signals are then fed to N decoder track circuits 96 (N n-1 1 through N0). The sequence controller 98 provides the same SSDS chips that were applied at the transmitter to each of the N decoder track circuits 96. This results in a sample output (N n-1 〜N0) are provided to the reconstruction bank 82. Again, the same SSDS chips used at the transmitter are used by each of the decoder track circuits 96. As a result, the demodulated samples N n-1 ~N0 is the same as before modulation on the transmitting side.

[0087] The decoder sequence controller 98 of each of the decoders 80 also generates a number of control signals, including a strobe signal, an end of bank (EOB) signal, an aperture signal, and a framing signal. The strobe signal is provided to the ADC 84 to indicate when the analog-to-digital conversion process of a given reconstructed bank content may begin. The EOB signal is provided to the reconstruction bank 82 to indicate when the relay bank 86 has completely filled with samples. When this occurs, the EOB signal is asserted to begin the next set of reconstructed samples (N n-1. . N0) and clears both the encoder 96 and the relay bank 86. The aperture control signal is provided to the sample and hold circuit 94 and the framing signal is provided to the channel aligner 87 and the relay controller 89.

[0088] Referring to Figure 7, a diagram of an exemplary encoder track circuit 96 is shown. The decoder track circuit 96 includes a multiplier section 100 and an accumulator section 102. The multiplier section includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1-C1 on the first (positive) and second (negative) power supply rails. The accumulator section 102 includes additional pairs of transistors S4-S4, S5-S5, S6-S6, and S7-S7, an operational amplifier 104, and a pair of capacitors CF-CF on the first (positive) and second (negative) power supply rails, respectively.

[0089] For each demodulation cycle, a differential EM level signal pair is received at a first level input (level+) terminal and a second level input (level-) terminal. The differential EM level signal pair is demodulated in multiplier section 100 by conditional inversion by multiplying by either one (1) or negative (-1) depending on the value of the received SSDS chip.

[0090] If the SSDS chip has a value of (+1), when clk1 is active, the transistor pairs S1-S1 and S3-S3 close while S2-S2 remains open. As a result, the voltage values ​​at the first level input (level+) terminal and the second level input (level-) terminal are passed and stored by the two capacitors C1 and C1 on the positive and negative rails, respectively. In other words, the input values ​​are multiplied by (+1) and no inversion occurs.

[0091] If the SSDS chip has a value of -1, the S1-S1 switches are both off, while the switches S2-S2 and S3-S3 are all turned on when clk1 is active. As a result, the voltage values ​​received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided at the first or positive terminal is routed to and stored on the capacitor C1 on the lower negative rail, while the voltage value provided on the second or (-) terminal is switched to and stored on the capacitor C1 on the upper positive rail. Thus, the received voltage value at the input terminal is inverted, i.e., multiplied by (-1).

[0092] When clk1 transitions to an inactive state, the stored charge on C1 and C1 remains. When clk2 transitions to an active state, transistor pair S4-S4 opens while transistor pairs S5-S5 and S6-S6 close. The stored charge on capacitor C1 on the lower or negative rail and C1 on the upper or positive rail are then provided to the differential inputs of operational amplifier 104. The output of operational amplifier 104 is the original + / - sample pair prior to transmit encoding.

[0093] The charge stored on the two capacitors C1 and C1 is also transferred to the capacitor CF on the upper or positive rail and the capacitor CF on the lower or negative rail when Clk2 is active. With each demodulation cycle, the charge on the capacitor C1 on the upper rail and the capacitor C1 on the lower rail are stored on the two capacitors CF and CF on the upper and lower rails, respectively. When the clk1 and EOB signals are both active, the transistor pair S7-S7 are both closed, shorting the plates of the capacitors CF and CF together. As a result, the stored charge is removed and the two capacitors CF and CF are reset and ready for the next demodulation cycle.

[0094] Since each decoder 80 has N encoders 96, N decoded or original + / - sample pairs are regenerated every demodulation cycle. These N + / - sample pairs are then provided to the reconstruction bank 82, the ADC 84, then to the collector 46 (which includes a relay bank 86 and a decomposition bank 88), and finally to the retimer 32. As a result, the original set of samples 22 is regenerated with its original color content information (e.g., S=3 for RGB) and is ready for display on the display 85 of the video sink 14.

[0095] The decoder track 96 reconstructs the input level samples over a series of L cycles, demodulating each successive input level with the successive SSDS chips of the code of the track. The result of each of the L demodulations is stored on a feedback capacitor CF. When EOB is asserted during clk1 corresponding to the first demodulation cycle of a decoding cycle, CF is cleared after EOB to start accumulating again from zero volts or some other reset voltage. In various non-exclusive embodiments, the value of L is a predetermined parameter. In general, the higher the parameter L, the greater the SSDS process gain and the better the electrical resilience of the transmission of the SSVT signal on the transmission medium 34. On the other hand, the higher the parameter L, the higher the required frequency for application of the SSVT modulation, which may degrade the signal quality due to the insertion loss caused by the transmission medium 34.

[0096] The above demodulation cycle is repeated over and over again by each of the four decoders 80. The end result is the recovery of the original time-sequential string of sets of samples 22 (i.e., a set of S samples), each with their original color content information. The sets of samples 22 are then processed as is well known in the art and displayed on the display 85 of the video sink 14. Alternatively, the recovered sets of samples 22 may be stored at the receiver for display in a time-shifted mode.

[0097] Passive multiply-accumulator decoder In an alternative embodiment, a passive multiplier-accumulator decoder may optionally be used within the decoder block 80 as described with reference to FIG. 5A. As described in more detail below, the passive multiplier-accumulator processes groups of (L) differential pair samples of the video media received on the transmission medium 34, where (L) is the length of the SSDS code used to encode the media prior to transmission. The decoder is passive because the correlation function is implemented by charge sharing across multiple capacitors that are equivalent to a normalized sum of the modulation values. The decoder is a multiplier-accumulator because the product results of the (L) differential pair samples and their corresponding SSDS chip values ​​are stored on multiple storage devices (e.g., capacitors) during the decoding process. The multiple storage devices are then shorted together to perform the normalized summation.

[0098] 8A illustrates a passive multiplier accumulator decoder 120. In one embodiment, the passive multiplier accumulator decoder 120 includes a chip multiplier stage 122, a first storage bank A (including a (+) set of (L) capacitors and a (-) set of (L) capacitors), and a first pair of capacitors 129. Also provided are a pair of reset elements 128 each disposed on a feedback path coupled between the (+ / -) output and the (- / +) input of the differential amplifier 124. The reset elements 128 reset the feedback capacitors 129 to implement a switched capacitor amplifier.

[0099] Chip multiplier stage 122 is configured to sequentially receive on transmission medium 34 L differential pair samples of the video medium that have been encoded by encoder 28 using direct sequence spread spectrum (SSDS) encoding as previously described. Chip multiplier stage 122 is also configured to receive SSDS chip values, each defined by the mutually orthogonal SSDS codes used to encode the differential pair samples by encoder 28. In a non-exclusive embodiment, channel aligner 87 is responsible for sequentially applying the correct SSDS chip value to each of the received differential pair samples.

[0100] In operation, one differential pair sample is received per clock cycle of the sampling clock Fssvt. In response to each received differential pair sample, chip multiplier stage 122 does the following: (1) applying SSDS chip values ​​of mutually orthogonal SSDS codes to the received differential pair samples; (2) Multiplying the differential pair sample by an applied chip value. Depending on the state of the applied chip value for a given differential pair sample, the multiplier is either (+1) or (-1). One non-limiting application is, for example, if the chip value is in a first state (e.g., "1"), the multiplier is (+1). If the chip value is in a second state (e.g., "0"), the multiplier is (-1); (3) The voltage charge corresponding to the product of the multiplication is stored on the (+) and (-) pairs of capacitors in storage block A, respectively. If the chip value is (+1), the charge is stored without any inversion. If the chip value is (-1), the charge is first inverted before storage. This inversion is performed by swapping the + and - input values ​​of the input signal.

[0101] As the (L) differential pair of video media signals are sequentially received, the above process is repeated for each sample, so that the (L) capacitors in the (+) and (-) pairs are sequentially written to and each store a charge commensurate with the multiplication product of the received (L) differential samples.

[0102] When the (L) differential samples are received and all of the (L) capacitors of the (+) and (-) capacitor sets of storage bank A store the multiplication product results, the passive multiplier accumulator decoder 120 outputs the decoded differential video media sample output (i.e., Sample P-1,N-1 + , Sample P-1 . N-1 - ), which is accomplished by the assertion of an "averaging" control signal, (1) interruption of storage of multiplication product charge in capacitor bank A; (2) causing a shorting of the charge on all of the (L) capacitors of the (+) capacitors in storage bank A, causing the accumulated charge to be "dumped" onto the input of amplifier 124. Amplifier 124 responds by slewing its output to control the voltage on the input via a feedback mechanism via a first capacitor 129 coupled to the negative (-) output terminal of differential amplifier 124. By dumping the accumulated charge on all of the (+) capacitors, an "average" voltage is achieved on the output of amplifier 124; (3) Shorting together the charge on all (L) of the (-) capacitors in storage bank A causes the accumulated charge to be "dumped" onto the input of amplifier 124. Amplifier 124 responds by slewing its output to control the voltage on the input via a feedback mechanism via a second capacitor 129 coupled to the positive (+) output terminal of differential amplifier 124. By dumping the accumulated charge on all of the (-) capacitors, an "average" voltage is achieved on the output of amplifier 124.

[0103] By simply shorting together all of the (+) capacitors and all of the (-) capacitors in storage bank A, an average of the accumulated charges of the (L) arriving differential samples is provided respectively on the output pair of amplifier 124. Thus, the averaging is essentially done "for free" (meaning that the correlation process is done passively with minimal active components).

[0104] The decoded differential video media samples are therefore represented by the difference between the average voltage on the positive output terminal and the average voltage on the negative output terminal of differential amplifier 124. Differential amplifier 124 works by relying on the sizing of capacitor 129 relative to the capacitors in storage bank A to provide gain or attenuation so as to protect the averaging process from external influences, while suppressing any common voltage between the two capacitors. With the additional gain and buffering, the decoded differential video media samples are more suitable for driving reconstruction bank 82 as shown in Figures 5A or 5B.

[0105] The frequency of the differential amplifier 124 does not need to operate at the same frequency Fssvt as that used to sample the (L) arriving differential samples. Since the averaging operation is performed on every (L) arriving sample, the frequency of the differential amplifier 124 need only be Fssvt / L. By reducing the speed / settling time requirements of the differential amplifier 124, less power is required to perform the function as well as to perform the averaging more precisely.

[0106] A reset circuit 128 for differential amplifier 124 is provided to initialize or reset the voltage on capacitor 129 to zero volts every Fssvt / L cycles. Without a reset prior to each averaging operation, differential amplifier 124 would average the previous value of L samples with the current average of L values ​​rather than simply amplifying the differential input it received for a single averaging operation.

[0107] Due to the above embodiment, storage bank A cannot be used to store the multiplication product charges of the incoming differential samples during the averaging operation, which may result in processing delays.

[0108] In an alternative embodiment, the passive multiplier-accumulator decoder 120 may also optionally include a second storage bank B that includes (L) sets of (+) and (-) capacitors, a second differential amplifier 126, a second set of capacitors 129, a pair of reset circuits 128, and a multiplexer 130. The second storage bank B, the differential amplifier 126, the second set of capacitors 129, and the reset circuit 128 all operate substantially similarly to their counterparts described above. Accordingly, a detailed description of these components will not be provided herein for the sake of brevity.

[0109] In operation, the two storage banks A and B are used alternatively; one is sampling while the other is averaging (and vice versa). By using one bank to sample while the other is averaging, processing delays are reduced in at least two ways. First, multiple incoming (L) differential pair signals can be received, multiplied, and stored without interruption. Second, any speed / settling time requirements of the differential amplifier following the averaging operation are nearly eliminated since one bank is always sampling while the other is averaging (and vice versa).

[0110] To implement some embodiments of the passive multiply-accumulator decoder 120 with two storage banks A and B, several control signals are required. These control signals include: (1) A sample / average control signal provided to storage bank A while a complementary average / sample signal is provided to storage bank B. Because these two control signals are complementary, one storage bank will always be sampling on the currently arriving (L) differential signal while the differential amplifier associated with the other storage bank is averaging (and vice versa); and (2) A bank select control signal is provided to multiplexer 130. Thus, when one bank is sampling and storing, multiplexer 130 selects the differential amplifier output (either 124 or 126) of the other bank that is averaging. By transitioning the bank select control signal to coincide with the transitions of the sample / average control signal, the output of multiplexer 130 is always selected to select the capacitor bank that is averaging. As a result, composite differential video media samples are continuously generated as long as chip multiplier stage 122 is receiving the incoming differential input signal.

[0111] FIG. 9 is a timing diagram illustrating an alternative nature of the operation of a two-bank embodiment of the passive multiply-accumulator decoder 120.

[0112] As can be seen in this diagram, the two capacitor banks A and B alternate between sampling and averaging. From left to right, capacitor bank A first samples, then averages, outputs the result on the output of differential amplifier 124, then samples again. At the same time, capacitor bank B does the complementary thing, which means: first averages the result and outputs it to differential amplifier 126, then samples, then averages the result and outputs it to differential amplifier 126. This alternating pattern is continuously repeated by transitioning the state of the average / control signal every (L) clock cycles of Fssvt. This results in a plurality of output decoded differential video media samples being generated continuously.

[0113] 10 illustrates an exemplary storage bank 140 (e.g., either A or B) and control logic. Using the above example with L=128, storage bank 140 would include 128 stages (labeled 1 through (L) in the figure). Each stage includes a first pair of switches (S1-S1), a second pair of switches (S2-S2), and complementary capacitors C(+) and C(-).

[0114] Each stage is also configured to receive an output from the control logic unit 148 to control the opening and closing of the first pair of switches S1-S1. In a non-exclusive embodiment, the control logic unit 148 includes a cyclic shift register of length (L) bits that circulates a single "1" bit through the (L) stages. The position of the "1" bit at any time selects which of the (L) stages will be used for sampling the multiplication product of a given differential pair input. By circulating the "1" bit to approximately coincide with the (L) Fssvt clock cycles, (L) samples are collected on the (L) stages respectively. In various alternative embodiments, the pulse width of the single "1" bit may be the same as the pulse width of the Fssvt clock or may be somewhat smaller. By using a smaller pulse width, any overlap between the sampling capacitors of adjacent stages (L) that are partially turned on is avoided or mitigated.

[0115] Each stage also has an input terminal configured to receive either the sample / average control signal of capacitor bank A or the complementary average / sample control signal of capacitor bank B. This control signal is used by both banks to control the opening and closing of a second set of switches S2-S2.

[0116] During sampling, the sample / average of capacitor bank A (or the average / sample of capacitor bank B) signal is held during the sampling state, so that switch S2-S2 remains open.

[0117] During sampling, the control logic unit 148 cycles a single "1" bit sequentially for each of stages (L) through (1). As a result, only one stage is selected per Fssvt clock cycle. For the selected stage, switch S1-S1 is closed, allowing a charge value corresponding to the multiplication product of the currently received differential pair sample to be received and stored on the C(+) and C(-) capacitors of the selected stage.

[0118] By circulating through all (L) stages, a charge commensurate with the multiplication product of the received (L) arriving differential signal vs. samples is generated (L)F ssvt Each of the (L) stages is stored over a clock cycle. Once all of the (L) stages have accumulated their charge, the averaging operation is ready to take place.

[0119] To begin the averaging operation, the sample / average signal of storage bank A (or the average / sample signal of storage bank B) transitions to the AVERAGE state and the control logic unit 148 stops cycling the "1" bit. This causes switches S1-S1 of all (L) stages to be opened and switches S2-S2 of all (L) stages to be closed. This causes the charge on the complementary capacitors C(+) and C(-) of all (L) stages to be "dumped" (i.e., averaged) onto the inputs of amplifier 124 at the (-) and (+) terminals of the corresponding differential amplifier, respectively.

[0120] Note that during the "dump" / averaging process, it is possible to connect another capacitor (previously initialized to have no charge) to some sets of the L capacitors in order to transfer a certain percentage of the result (this percentage depends on the ratio of the size of the additional capacitor to the sum of the L capacitors) to the additional capacitor. This technique provides a means to pass the result to the input of the corresponding differential amplifier (either 124 in bank A or 126 in bank B).

[0121] It should be understood that although the storage banks A and B in FIG. 8A above are symmetrical and both contain (L) stages, this is by no means a requirement. Conversely, the A and B storage banks do not need to be perfect replicas. There is only a need to have enough replicas to meet the requirement that a continuous stream of differential input samples can be handled. For example, one or both storage banks may have fewer than (L) stages. In alternative embodiments, only a small number of stages in the storage banks need to be replicated. The number of potentially duplicated stages need only be sufficient to ensure completion of the averaging operation into the amplifier 124 output, and the time of the potentially duplicated stages needs to be sufficient for the amplifier to go through Mux 130 to deliver the result to the next circuit. The output of the result (by the amplifier) ​​of one bank can occur during the next sampling even if both banks share storage elements, since the output amplifier is "standalone" after the evaluation is completed.

[0122] FIG. 8B shows a passive multiplier-accumulator decoder 120' that implements a partial pipeline approach where no multiplexers are required. Only a small number of stages in storage banks A' and B' need to be duplicated. The number of potentially duplicated stages is sufficient to ensure completion of the averaging operation into amplifier 125 and the time of the potentially duplicated stages is sufficient for the amplifier to settle in order to deliver the result to the next circuit. Thus, banks A and B from FIG. 8A are essentially "cut" or shortened to include only L stages less, resulting in banks A' and B'. A new storage bank C is provided that includes the remaining stages (e.g., if banks A' and B' have (LX) stages, where X is a positive integer greater than 0, then bank C will have X stages). Thus, once the values ​​from chip multiplier stage 122' have filled Bank A' and Bank C, and have been sampled and output by amplifier 125, the result from stage 122' fills Bank B' (allowing time for amplifier 125 to settle and for amplifier 125 to output its voltage received via Bank A'). Thus, Banks A' and B' are sized such that once the amplifier has finished outputting a voltage via Bank A', the result from Bank B' (previously loaded) is loaded into Bank C and Bank B' continues to fill (now Bank A' begins to fill while the Bank B' result is being output). The advantages of this are less duplication of circuitry, less chip area required, only one amplifier is needed, and no multiplexers are needed.

[0123] The various above-described embodiments of the passive multiplier-accumulator decoder 120 are essentially "drop-in" replacements for the N decoders used in the decoder block 80 as shown in Figures 5A and 5B. As explained above, N decoder circuits (N0 to N -1) are provided for each decoder block 80. Each of the N decoder circuits is configured to sequentially receive the differential level samples (+ / - level signals). When the differential level signals are received, each of the N passive multiplier accumulator decoder circuits 120 applies the same unique SSDS code of the mutually orthogonal SSDS codes used to encode for the transmitter's level position (P) and sample position (N). As a result, each passive multiplier accumulator decoder circuit 120 generates a differential pair of samples for its given P and N position. In other words, for all of the N decoder circuits of each decoder of the (P) decoder 80, the (Sample 0+ , sample 0- ~Sample P-1,N-1 + , Sample P-1,N-1 - ) are generated and provided to reconstruction bank 82. In the non-exclusive embodiment described with respect to Figures 5A and 5B, and herein with respect to Figures 8A and 8B, N is 64 channels and the length L of the SSDS code is L=128.

[0124] The above discussion of the various encoders and decoders is described with respect to differential signals. However, it should be noted that this is by no means a requirement. In various alternative embodiments, the encoders and decoders may be configured to similarly operate and process non-differential signals (i.e., single signals).

[0125] Radio transmission of SSVT signals As noted above, one possible choice for transmission medium 34 is wireless. As described in detail below, a wireless embodiment is provided for transmitting and receiving SSVT electromagnetic ("EM") signals.

[0126] 11 is a block diagram 200 of a wireless implementation of the transmission medium 34 (the medium 34 is not shown because it is wireless). According to this embodiment, a wireless transmitter 202 and an antenna 204 are provided on the transmit side, and a receiver 206 and an antenna 208 are provided on the receive side. Shown are simplified versions of the SSVT transmitter 28 and the SSVT receiver 30. The collector 46 of the SSVT receiver 30 can be implemented as shown in FIG. 5A or 5B, and the output 240 from the SSVT receiver 30 can be the RGB signal of FIG. 5A or the analog samples of FIG. 5B.

[0127] A transmitter 202 modulates the SSVT electromagnetic signal generated by the SSVT transmitter 28 into one or more frequency bands. Once modulated, the frequency bands are broadcast by an antenna 204. On the receiving side, an antenna 208 receives the broadcast and provides the modulated carrier signal to a radio receiver 206. In response, the receiver 206 demodulates and generates an SSVT electromagnetic signal that is then provided to the SSVT receiver 30. The SSVT electromagnetic signal may also be provided to any of the SSVT receivers described in patent applications 17 / 686,790 (HYFYP004AX1), 17 / 887,849 (HYFYP006), or 17 / 900,570 (HYFYP009). Once decoded, the video signal or samples are available to drive a video display as previously described.

[0128] 12A is a block diagram of a transmitter 202. The transmitter 202 includes an antenna 204, one or more (P) modulators 210, a carrier frequency generator 212, one or more (P) bandpass filters 214, a summing node 216, and a power amplifier 218. The amount of encoders 42 in the SSVT transmitter 82, and therefore the amount of EM signal output, is represented by (P). In the case where only one encoder 42 is used in the SSVT transmitter (i.e., P=1), the summing node 216 is not required. The modulation scheme may be various and may represent modulation by carrier, vestigial carrier, double sideband, single sideband, and a myriad of other modulations. Those skilled in the art will recognize that other modulation schemes may be used as long as the wireless transmission standards of the particular band are adhered to.

[0129] In operation, one or more electromagnetic (EM) signals (P) generated by the SSVT transmitter 28 are provided to one or more modulators 210. In response, the modulators 210 each modulate one of the electromagnetic signals onto (P) different carrier frequency signals. Preferably, the (P) carrier signals are of different frequencies, but all derived from the same fundamental sinusoidal frequency. By modulating, each of the (P) electromagnetic signals is essentially superimposed onto the (P) carrier frequency signal. Bandpass filters 214 then respectively filter each of the modulated carrier frequency signals. The bandpass filter outputs are then summed at summing node 216, which effectively sums all of the P voltage waveforms to generate a composite signal. Amplifier 218 amplifies the composite signal at antenna 204. In response, antenna 204 wirelessly broadcasts the composite signal (i.e., the amplified, summed, and filtered modulated carrier frequency signals). Preferably, both the amplifier and the antenna are selected to be able to handle the additional bandwidth created by the composite signal.

[0130] One variation in some implementations would be to eliminate the individual bandpass filters 214 paired with each modulator 210 and have only wider bandpass filters to ensure compliance with bandwidth allocations within a given jurisdiction's bandwidth reservation. The strict restriction to a narrower bandwidth before the composite structure after summing node 216 is a limitation and added complexity that may not be needed in some applications.

[0131] The above modulation and broadcasting operations occur continuously as long as the SSVT transmitter 28 is generating the (P) electromagnetic signal from the stream of video samples, resulting in a continuous broadcast of an encoded radio signal representing the stream of video samples.

[0132] 12B is a block diagram of the receiver 206. The receiver 206 includes an antenna 208, a gain controller 220, one or more (P) demodulators 222, one or more (P) low pass filters 224, a discriminator circuit 226, and a Voltage Controlled Frequency Source (VCFS) 228.

[0133] In operation, the composite signal broadcast by transmitter 202 is received by antenna 208. Gain controller 220 adjusts the gain of the received composite signal; the gain controller may be implemented by using either an automated gain controller (AGC) or a programmable gain amplifier (PGA). In either case, the gain adjusted composite signal is provided to each of the demodulators 222.

[0134] In response, each demodulator 222 demodulates and produces one of the (P) electromagnetic signals from the composite signal. In one embodiment, each of the demodulators 222 is a superheterodyne receiver that uses frequency mixing to convert the received signal to an intermediate frequency (IF) that can be more easily processed than the original incoming composite signal. Alternatively, each of the demodulators 222 is a Direct Conversion Receiver (DCR), which is a radio receiver designed to demodulate the incoming composite signal by using synchronous detection driven by a local oscillator whose frequency is the same as or very close to the carrier frequency of the incoming composite signal. Regardless of the type of demodulator used, each of the (P) demodulated signals is provided to one of the low pass filters 224. Each low pass filter filters its received demodulated electromagnetic signal as previously described and provides its output to the SSVT receiver.

[0135] As an example, either the decoder of FIG. 5A or FIG. 5B may be used, as well as any other decoder capable of decoding the demodulated electromagnetic signal into the original video media stream.

[0136] The discriminator circuit 226 provides a feedback loop between the output 230 of each demodulator of the demodulators 222 and the VCFS 228. In the event that one or more of the frequencies used by the demodulators 222 for demodulation drifts, the discriminator circuit 226 serves to adjust the demodulation frequency(ies) to lock on to the same frequency as the received carrier frequency.

[0137] Described above is a wireless embodiment in which any number of electromagnetic signals are modulated, filtered, and then summed to be amplified by an amplifier and output by an antenna, resulting in lower cost since only a single amplifier and a single antenna are required. In an alternative embodiment of the wireless transmitter 202, there is no summing node 216, and each of the (P) electromagnetic signals from the SSVT transmitter 82 is modulated and filtered, as described, and then amplified and output by using a power amplifier and antenna per signal. In other words, instead of a single power amplifier and antenna, there would be a (P) amplifier and an antenna. Similarly, the wireless receiver 206 could be implemented by using a (P) antenna, and a (P) gain controller, a demodulator and a filter per signal, as described.

[0138] The present embodiments should be considered as illustrative and not restrictive, and the invention should not be limited to the details set forth herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. 1. A transmitter apparatus for transmitting an input payload of one or more sampled video signals over a wireless electromagnetic path, comprising: a permutation unit for assigning samples from the input payload to locations in one or more indexed input vectors of N locations each using a pre-defined permutation, each location in the indexed input vector receiving one of the samples; one or more encoders, each encoder encoding the N samples of one of the one or more input vectors into an ordered sequence of L output values ​​with reference to N mutually orthogonal codes of a predetermined code set of length L, each of the N codes being used to encode one of the N samples; a wireless transmitter including one or more modulators, each configured to modulate one of the L output values ​​of the sequence onto one or more carrier frequency signals; and an antenna configured to wirelessly broadcast L output values ​​of said one or more sequential sequences each modulated onto said one or more carrier frequencies. A transmitter device comprising:

2. 2. The transmitter apparatus of claim 1, wherein any two of the one or more carrier frequency signals are at different frequencies.

3. 2. The transmitter apparatus of claim 1, further comprising one or more bandpass filters configured to bandpass filter the L output values ​​of the one or more ordered sequences respectively modulated onto the one or more carrier frequencies.

4. 2. The transmitter apparatus of claim 1, further comprising a summing node configured to sum two or more of the ordered sequences of L output values ​​modulated onto two or more carrier frequencies, respectively.

5. 2. The transmitter apparatus of claim 1, further comprising a power amplifier configured to amplify the L output values ​​of the one or more sequential sequences modulated onto the one or more carrier frequencies prior to being broadcast by the antenna.

6. 2. The transmitter apparatus of claim 1, wherein the N samples encoded by each of the encoders are analog samples and the L output values ​​of the one or more ordered sequences are analog values.

7. 2. The transmitter apparatus of claim 1, wherein the N samples encoded by each of the encoders are digital samples, the apparatus further comprising: at least one D / A converter for converting the L output values ​​of the one or more ordered sequences into analog values.

8. 2. The transmitter apparatus of claim 1, wherein the one or more sampled video signals originate from a single video device source and the electromagnetic path terminates at a single video device sink.

9. 2. The transmitter apparatus of claim 1, wherein each of the one or more encoders synchronously encodes the N samples into L output values ​​of the ordered sequence, respectively, the N samples being represented by the L output values.

10. 2. The transmitter apparatus of claim 1, wherein said output terminal transmits said sequence of L analog output values ​​over said electromagnetic path to a single video equipment sink.

11. The transmitter apparatus of claim 1 , wherein L≧N≧2.

12. The transmitter apparatus of claim 1 , wherein N>L≧2.

13. 1. A receiver apparatus for receiving one or more ordered sequences of L analog input values ​​from an electromagnetic path, said receiver apparatus comprising: an antenna configured to receive radio broadcasts on one or more carrier frequencies, the one or more carrier frequencies having one or more sequential sequences of L analog input values ​​modulated thereon, respectively; a radio receiver including one or more demodulators configured to demodulate each of the L analog input values ​​of the one or more ordered sequences from the one or more carrier frequencies; one or more decoders, each decoder decoding one of the L analog input values ​​of the ordered sequence into an output vector of N samples with reference to N mutually orthogonal codes of a predetermined code set of length L, each of the N codes being used to decode one of the N samples, the predetermined code set being the same as the code set used to encode the L input values ​​of the ordered sequence; and a permutation unit that assembles the N samples from each of the output vectors into one or more reconstructed sampled video signals by using a predetermined permutation that is the inverse of the permutation used in a transmitter device corresponding to the receiver device.

14. 14. The receiver apparatus of claim 13, further comprising a gain controller configured to adjust a gain of the one or more carrier frequencies in accordance with the one or more ordered sequences of L analog input values ​​respectively modulated thereon.

15. 15. The receiver apparatus of claim 14, wherein the gain controller is one of an automatic gain controller (AGC) or a programmable gain amplifier (PGA).

16. 14. The receiver apparatus of claim 13, wherein the one or more demodulators are each one of a direct conversion receiver (DCR) or a superheterodyne receiver.

17. 14. The receiver apparatus of claim 13, further comprising one or more low-pass filters for low-pass filtering each of the L analog input values ​​of the demodulated one or more ordered sequences.

18. 14. The receiver apparatus of claim 13, further comprising a discriminator circuit used to adjust one or more frequencies used to demodulate the one or more ordered sequences of L analog input values ​​from the one or more carrier frequencies.

19. 14. The receiver apparatus of claim 13, wherein the decoded video samples are substantially the same as those encoded into the one or more ordered sequences of L analog input values ​​prior to the radio broadcast.

20. 14. The receiver apparatus of claim 13, wherein the L input values ​​for decoding are analog input values, and the decoder decodes the L analog input values ​​to generate the output vector of N samples, the N samples being analog values.

21. 14. The receiver apparatus of claim 13, further comprising at least one analog-to-digital converter for converting each of the L analog input values ​​into L digital input values, wherein the decoder decodes the L digital input values ​​to generate the output vector of N samples, the N samples being digital values.

22. 14. The receiver apparatus of claim 13, wherein one or more sampled video signals corresponding to the one or more reconstructed sampled video signals originate from a single video device source, and the one or more reconstructed sampled video signals are delivered to a single video device sink.

23. 14. The receiver apparatus of claim 13, wherein the decoder synchronously decodes each of the L input values ​​into the output vector of N samples, the N samples representing the L input values.

24. 14. The receiver device of claim 13, wherein the receiver device is at a single video equipment sink.

25. 14. The transmitter apparatus of claim 13, wherein L > N > 2.

26. The transmitter apparatus of claim 13, wherein N>L≧2.

27. 1. An encoder configured to generate one or more electromagnetic signals each representative of a video medium, the one or more electromagnetic signals comprising: (a) distributing video media samples into one or more vectors; (b) applying a direct sequence spread spectrum (SSDS) code to the video media samples distributed within the one or more vectors, respectively; (c) accumulating results from the application of the SSDS codes to the video media samples distributed within the one or more vectors, respectively; (d) generating the one or more electromagnetic signals from the accumulation results of the one or more vectors, respectively; a wireless transmitter including one or more modulators configured to modulate the one or more electromagnetic signals onto one or more carrier frequency signals, respectively; and an antenna configured to wirelessly broadcast said one or more electromagnetic signals each modulated onto said one or more carrier frequencies. A transmitter including

28. 28. The transmitter of claim 27, wherein the applying of the SSDS code includes conditionally multiplying a value indicative of each of the video samples distributed within the one or more vectors by either (+1) or (-1) depending on a chip value of the SSDS code applied to the one or more vectors, respectively.

29. 28. The transmitter of claim 27, wherein the accumulation further comprises accumulating multiplication results of the video samples distributed within the one or more vectors multiplied by either (+1) or (-1) depending on the chip value of the SSDS code applied to each of the one or more vectors.

30. 28. The transmitter of claim 27, wherein the encoder is further configured to generate the one or more streams of electromagnetic signals by repeating (a)-(d) on the stream of video media samples.

31. 28. The transmitter of claim 27, wherein the one or more carrier frequency signals are derived from a fundamental carrier frequency.

32. 32. The transmitter of claim 31 , wherein any two of the one or more carrier frequency signals are at different frequencies.

33. 30. The transmitter of claim 27, further comprising one or more bandpass filters configured to bandpass filter the one or more electromagnetic signals respectively modulated onto the one or more carrier frequencies.

34. 30. The transmitter of claim 27, further comprising a summing node configured to sum two or more electromagnetic signals respectively modulated onto two or more carrier frequencies.

35. 28. The transmitter of claim 27, further comprising a power amplifier configured to amplify the one or more electromagnetic signals modulated onto the one or more carrier frequencies prior to being broadcast by the antenna.

36. The encoder further comprises: (e) receiving a stream of image samples including color values ​​and pixel related information; (f) distributing the received video samples into the one or more vectors by using a predetermined permutation; (g) applying the SSDS code to the video signals respectively distributed within the one or more vectors; and (h) repeating (e) through (g) as said stream of video samples is received in chronological order.

28. The transmitter of claim 27, configured to generate the one or more electromagnetic signals by:

37. The color value is one of the following: (i) red (R) value; (j) blue color (B) value; (k) green color (G) value; (l) luminance value (Y); (m) chrominance (C) value; (n) blue difference chroma (Cb) value; (o) the red difference chroma (Cr) value; or (p) any combination of (i) to (0) 37. The transmitter of claim 36, comprising:

38. 28. The transmitter of claim 27, wherein the encoder is a spread spectrum video transport (SSVT) encoder.

39. an antenna configured to receive radio broadcasts on one or more carrier frequencies, the one or more carrier frequencies having one or more electromagnetic signals respectively modulated thereon; a radio receiver including one or more demodulators configured to demodulate the one or more electromagnetic signals from the one or more carrier frequencies, respectively; and a decoder configured to decode the demodulated one or more electromagnetic signals to recover video media encoded within the electromagnetic signals by: (a) applying to the one or more electromagnetic signals the same direct sequence spread spectrum (SSDS) code that was used to encode the video media into the electromagnetic signals prior to the wireless broadcast; and (b) generating one or more video samples from the SSDS codes respectively applied to the one or more electromagnetic signals; A receiver including:

40. The decoder comprises: conditionally multiplying the one or more electromagnetic signals by a number of chips associated with the SSDS code used to respectively encode the video media into the one or more electromagnetic signals prior to said wireless broadcast; generating product results of the plurality of conditional multiplications of the one or more electromagnetic signals, respectively; and 40. The receiver of claim 39, wherein the receiver recovers the encoded video media in the one or more electromagnetic signals by generating video media samples from the product results of the one or more electromagnetic signals, respectively.

41. 40. The receiver of claim 39, further comprising a gain controller configured to adjust a gain of the one or more carrier frequencies in accordance with the one or more electromagnetic signals respectively modulated thereon.

42. 42. The receiver of claim 41, wherein the gain controller is one of an automatic gain controller (AGC) or a programmable gain amplifier (PGA).

43. 40. The receiver of claim 39, wherein the one or more demodulators are each one of a direct conversion receiver (DCR) or a superheterodyne receiver.

44. 40. The receiver of claim 39, further comprising one or more low pass filters for low pass filtering the demodulated one or more electromagnetic signals, respectively.

45. 40. The receiver of claim 39, further comprising a discriminator circuit used to adjust one or more frequency signals used to demodulate the one or more electromagnetic signals from the one or more carrier frequencies.

46. 40. The receiver of claim 39, wherein the decoded video samples are substantially the same as those encoded into the one or more electromagnetic signals prior to the wireless broadcast.

47. 40. The receiver of claim 39, wherein the video samples are decoded in time order and used to drive a video display.

48. The video sample is one of the following: (c) red (R) value; (d) blue color (B) value; (e) green color (G) value; (f) luminance value (Y); (g) chrominance (C) value; (h) blue difference chroma (Cb) value; (i) the red difference chroma (Cr) value; or (j) Any combination of (c) to (i) 40. The receiver of claim 39, further comprising color values ​​comprising:

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