Codeword synchronization method, communication device, chip, and chip system - Patents.com

Abstract

The present application provides a codeword synchronization method, a communication device, a chip, and a chip system, and relates to the field of communication technology. The method includes the steps of: entering a synchronization position determination state in response to a start signal; determining a synchronization position in a received data sequence in the synchronization position determination state, where the synchronization position indicates a start position of a codeword in the data sequence; entering a lock loss detection state in response to determining the synchronization position; verifying a number of selected codewords based on the synchronization position in the lock loss detection state, and re-entering the synchronization position determination state in response to a verification failure. According to the solution of the present application, codeword synchronization can be implemented continuously without inserting additional alignment markers, thereby saving transmission resources.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202210113601.8, filed on January 30, 2022, and entitled "STATE MACHINE BASED BLOCK CODE SELF-SYNCHRONIZATION METHOD," and Chinese Patent Application No. 202210520888.6, filed on May 12, 2022, and entitled "CODEWORD SYNCHRONIZATION METHOD, COMMUNICATION DEVICE, CHIP, AND CHIP SYSTEM," both of which are incorporated by reference in their entireties herein.

[0002] The present application relates to the field of communication technologies, and in particular to a codeword synchronization method, a communication device, a chip, and a chip system. [Background technology]

[0003] Currently, with the development of communication technology, channel loss and noise become important factors limiting data transmission speed and distance. Forward error correction (FEC) provides error correction protection to data during transmission, thereby increasing the data transmission speed and transmission distance of the channel. FEC includes block codes, which include linear block codes and non-linear block codes. Since the encoding and decoding of linear block codes is simple, linear block codes are widely applied in the physical layer and media access control (MAC) sublayer of the data link layer in the open system interconnection model (OSI) model of Ethernet.

[0004] The error detection and correction functions of linear block codes need to be implemented based on complete code words. Therefore, code word boundaries need to be determined in the data sequence, i.e. the start and end of a complete code word need to be found. This process is called code word synchronization or frame synchronization.

[0005] Currently, synchronization solutions applicable to linear block codes are available in the industry. The alignment marker (AM) synchronization solution used in 200 / 400 GE of the 802.3 standard is used as an example. In this solution, a fixed AM sequence needs to be inserted at the interval of a codeword having a certain length, and the receiver can perform codeword synchronization by identifying the AM sequence. However, the presence of the AM sequence is equivalent to the insertion of additional data into the data stream transmitted by the transmitter, thus adding redundant information. Summary of the Invention

[0006] The present application provides a codeword synchronization method, a communication device, a chip, and a chip system, so that codeword synchronization can be implemented without inserting AM, thereby saving transmission resources. [Means for solving the problem]

[0007] According to a first aspect, the present application provides a codeword synchronization method, the method including the steps of: entering a synchronization position determination state in response to a start signal, determining a synchronization position in a received data sequence in the synchronization position determination state, the synchronization position indicating a starting position of a codeword in the data sequence, entering a lock loss detection state in response to determining the synchronization position, and verifying in the lock loss detection state a number of selected codewords based on the synchronization positions and re-entering the synchronization position determination state in response to a verification failure.

[0008] In the solution of the present application, a synchronization position determination state is entered in response to a start signal, and a synchronization position is determined in the synchronization position determination state. A lock loss detection state is entered after the synchronization position is determined. In the lock loss detection state, if it is determined that the synchronization position does not satisfy the verification condition, the synchronization position is re-determined. In this way, the synchronization method is a self-synchronization method, and codeword synchronization can be implemented without inserting AM in the transmitter, thereby saving transmission resources. In addition, if the detected synchronization position is inaccurate, the synchronization position may be re-determined, so that successive codeword synchronization can also be performed. In addition, a state machine is further used to implement successive codeword synchronization, so that successive codeword synchronization can be implemented more accurately.

[0009] In a possible implementation, determining a synchronization position in the received data sequence in a synchronization position determination state includes selecting N observed bits from the data sequence and determining a synchronization position in the synchronization position determination state based on positions of the N observed bits, where N is an integer greater than or equal to 1.

[0010] In the solution of the present application, the observation bits belong to a data sequence and the positions of the observation bits are positions within the data sequence that are possible synchronization positions.

[0011] In a possible implementation, determining the synchronization position based on the positions of the N observed bits comprises selecting a synchronization position from the positions of the N observed bits.

[0012] In the present solution, the synchronization position can be determined directly from the positions of the N observed bits.

[0013] In a possible implementation, the synchronization position determination state includes a first counter reset sub-state and a first code word verification sub-state, and the step of selecting N observation bits from the data sequence and selecting a synchronization position from the positions of the N observation bits in the synchronization position determination state includes the steps of setting an initial value of a first code word counter in the first counter reset sub-state and selecting one observation bit from the data sequence, and entering the first code word verification sub-state in response to selecting one first test block from the data sequence based on the current observation bit. the length of the first test block is equal to the codeword length and a start position of the first test block and a position of the current observed bit are separated by an integer amount of the codeword length; verifying the first test block in a first codeword verification sub-state and in response to the first test block satisfying a verification condition, incrementing a count value of a first codeword counter by X, where X is an integer greater than or equal to 1; and in response to the count value of the first codeword counter being equal to a first threshold, determining the position of the current observed bit as a synchronization position.

[0014] In the solution of the present application, in the test block selected using the current observation bit, the first threshold of consecutive test blocks meets the verification condition, and the position of the current observation bit is determined as the synchronization position.In this way, since the amount of states of the state machine is relatively small, the synchronization position can be determined quickly.

[0015] In a possible implementation, the step of selecting N observation bits from the data sequence and selecting a synchronization position from the positions of the N observation bits in the synchronization position determination state further includes the step of re-entering the first code word verification sub-state in response to the count value of the first code word counter being less than a first threshold and verifying a next first test block selected based on the current observation bits.

[0016] In a possible implementation, the synchronization position determination state further includes a first codeword valid portion state, and the step of increasing the count value of the first codeword counter by X in response to the first test block satisfying the verification condition includes the steps of entering the first codeword valid portion state in response to the first test block satisfying the verification condition, and incrementing the count value of the first codeword counter by X in the first codeword valid portion state.

[0017] In a possible implementation, the step of selecting N observation bits from the data sequence and selecting a synchronization position from the positions of the N observation bits in the synchronization position determination state further includes a step of verifying a next observation bit selected from the data sequence in response to the first test block not satisfying the verification condition.

[0018] In the solution of the present application, after the first test block is selected based on the current observation bit, if the first test block does not meet the verification condition, it indicates that the position of the current observation bit is not a synchronization position, and continues to determine whether the next observation bit is a synchronization position. In this way, the synchronization position can be determined quickly.

[0019] In a possible implementation, the synchronization position determination state further includes a first slip portion state, and the step of verifying a next observation bit selected from the data sequence in response to the first test block not satisfying the verification condition includes the steps of entering the first slip portion state in response to the first test block not satisfying the verification condition, slipping to the next observation bit in the first slip portion state, and re-entering the first counter reset portion state in response to slipping to the next observation bit and verifying the next observation bit.

[0020] In the solution of the present application, if the first test block does not satisfy the verification condition, the first slip sub-state is entered, a slip process is performed to slip to the next observation bit, and the first counter reset sub-state is entered again.

[0021] In a possible implementation form, the synchronization position determination state further includes a first synchronization lock initialization sub-state, and prior to the step of setting an initial value of the first codeword counter in the first counter reset sub-state, the method further includes a step of setting a value of a first synchronization lock variable to a first value in the first counter reset sub-state.

[0022] In a possible implementation form, the synchronization position determination state further includes a first synchronization lock success partial state, and the step of determining the position of the current observation bit as a synchronization position in response to the count value of the first codeword counter being equal to the first threshold includes a step of entering the first synchronization lock success partial state in response to the count value of the first codeword counter being equal to the first threshold, and a step of setting a value of a first synchronization lock variable to a second value in the first synchronization lock success partial state, wherein the value of the first synchronization lock variable being the second value indicates that the position of the current observation bit is a synchronization position.

[0023] In a possible implementation, the method further includes setting a value of the first codeword variable to be verified to a third value in the first synchronization lock initialization sub-state, and entering the first codeword verification sub-state in response to selecting one first test block from the data sequence based on the current observation bits includes setting a value of the first codeword variable to a fourth value in response to selecting one first test block from the data sequence based on the current observation bits, and entering the first codeword verification sub-state in response to the value of the first codeword variable to be verified being the fourth value and the value of the first synchronization lock variable being the first value.

[0024] In a possible implementation, the lock loss detection state includes a second code word verification sub-state, and the step of verifying the multiple code words selected based on the synchronization position in the lock loss detection state includes the steps of re-entering the first counter reset sub-state in response to determining the synchronization position, entering a second code word verification sub-state in response to selecting one first code word based on the synchronization position, and verifying the first code word in the second code word verification sub-state.

[0025] In a possible implementation, in the lock loss detection state, the step of verifying the multiple codewords selected based on the synchronization position further includes a step of setting an initial value of a first codeword counter and an initial value of a first invalid codeword counter in a first counter reset substate, and the step of re-entering the synchronization position determination state in response to a verification failure further includes a step of increasing a count value of the first codeword counter by Y and increasing a count value of the first invalid codeword counter by Z in response to the first codeword not satisfying the verification condition, where both Y and Z are integers greater than or equal to 1, and a step of re-entering the synchronization position determination state in response to the count value of the first invalid codeword counter being equal to the third threshold when the count value of the first codeword counter is less than or equal to the second threshold and the third threshold is less than the second threshold.

[0026] In the solution of the present application, the synchronization position determination process and the lock loss detection process can share some states, so that the process of implementing consecutive codeword synchronization can be simplified.

[0027] In a possible implementation, the synchronous position determination state includes a first slip portion state, and the step of re-entering the synchronous position determination state includes the steps of entering the first slip portion state, slipping to the next observation bit in the first slip portion state, and in response to slipping to the next observation bit, re-entering the first counter reset portion state and verifying the next observation bit.

[0028] In a possible implementation, the step of determining a synchronization position based on the positions of the N observed bits includes the steps of selecting a candidate position in the data sequence from the positions of the N observed bits, and determining the synchronization position based on the candidate position.

[0029] In the solution of the present application, the position that is most likely to be the synchronization position, i.e., the candidate position, can be first selected from the positions of the N observed bits, and then the candidate position is used to determine the synchronization position, resulting in a more accurate determined synchronization position.

[0030] In a possible implementation, N is greater than 1, and the synchronization position determination state includes a second counter reset sub-state and a third codeword verification sub-state, and the step of selecting N observation bits from the data sequence and selecting a candidate position in the data sequence from positions of the N observation bits in the synchronization position determination state includes the steps of: setting an initial value of a second codeword counter and an initial value of a first currently valid codeword counter in the second counter reset sub-state and selecting one observation bit from the data sequence; entering a third codeword verification sub-state in response to selecting one second test block from the data sequence based on the current observation bit, wherein a length of the second test block is equal to the codeword length, and a starting position of the second test block and a position of the current observation bit are separated by an integer amount of the codeword length; and entering a third codeword verification sub-state in the third codeword verification sub-state. in response to the second test block satisfying the verification condition, increasing a count value of a first currently valid codeword counter by P, where P is an integer greater than or equal to 1; in response to the second codeword counter count value being equal to a fourth threshold value and the first currently valid codeword counter count value being greater than a current value of a maximum valid codeword number variable, incrementing a value of an observed bit number variable by 1, updating a value of a candidate synchronization position variable to a current observed bit position, and updating a current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter; and in response to the value of the observed bit number variable being equal to N, determining the current value of the candidate synchronization position variable as a candidate position.

[0031] In the solution of the present application, verification is performed successively on N observation bits, and among the N observation bits, the observation bit corresponding to the maximum number of test blocks that meet the verification condition is selected, and the position of the observation bit is determined as a candidate position. In this way, each observation bit is verified to select a candidate position, so that the determined candidate position can be more accurate, in other words, the determined candidate position is more likely to be a synchronization position.

[0032] In a possible implementation, the synchronization position determination state further includes a candidate position selection substate, and in response to the count value of the second codeword counter being equal to the fourth threshold and the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword number variable, the step of increasing the value of the observed bit number variable by one, updating the value of the candidate synchronization position variable to the current observed bit position, and updating the current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter is the step of entering a candidate position selection sub-state in response to the count value of the second codeword counter being equal to the fourth threshold value, and in the candidate position selection sub-state, in response to the count value of the second codeword counter being equal to the fourth threshold value and the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword number variable, increasing the value of the observed bit number variable by one, updating the value of the candidate synchronization position variable to the current observed bit position, and updating the current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter.

[0033] In a possible implementation, the step of selecting N observed bits from the data sequence and selecting a candidate position in the data sequence from positions of the N observed bits in the synchronization position determination state further includes the step of verifying the next observed bit selected from the data sequence in response to the value of the number of observed bits variable being less than N.

[0034] In a possible implementation, the synchronization position determination state further includes a second slip portion state, and the step of verifying the next observed bit selected from the data sequence in response to the value of the number of observed bits variable being less than N includes the steps of entering the second slip portion state in response to the value of the number of observed bits variable being less than N, slipping to the next observed bit in the second slip portion state, and re-entering the second counter reset portion state in response to slipping to the next observed bit and verifying the next observed bit.

[0035] In a possible implementation form, the synchronization position determination state further includes a second synchronization lock initialization sub-state, and prior to the step of setting an initial value of the second codeword counter and an initial value of the first currently valid codeword counter in the second counter reset sub-state, the method further includes the step of setting the value of the observed bit number variable to a fifth value, setting the value of the candidate synchronization position variable to a sixth value, and setting the value of the maximum valid codeword number variable to a seventh value in the second synchronization lock initialization sub-state.

[0036] In a possible implementation, the method further includes setting a value of the second codeword variable to be verified to a third value in the second synchronization lock initialization sub-state, and entering the third codeword verification sub-state in response to selecting one second test block from the data sequence based on the current observation bits includes setting a value of the second codeword variable to a fourth value in response to selecting one second test block from the data sequence based on the current observation bits, and entering the third codeword verification sub-state in response to the value of the second codeword variable to be verified being the fourth value.

[0037] In a possible implementation, the step of selecting N observation bits from the data sequence and selecting a candidate position in the data sequence from the positions of the N observation bits in the synchronization position determination state further includes the step of re-entering a third code word verification sub-state in response to the count value of the second code word counter being less than a fourth threshold and verifying a next second test block selected based on the current observation bits.

[0038] In a possible implementation, the synchronization position determination state includes a third counter reset sub-state and a fourth code word verification sub-state, and the step of selecting N observation bits from the data sequence and selecting a candidate position in the data sequence from the positions of the N observation bits in the synchronization position determination state includes the steps of setting an initial value of a third code word counter and an initial value of a first valid code word counter in the third counter reset sub-state and selecting one observation bit from the data sequence; and entering a fourth code word verification sub-state in response to selecting one third test block from the data sequence based on the current observation bit, wherein a length of the third test block is equal to the code word length and the third test block is equal to the code word length. the start position of the test block and the position of the current observed bit are separated by an integer amount of the codeword length; verifying the third test block in a fourth codeword verification sub-state; in response to the third test block satisfying a verification condition, incrementing a count value of the third codeword counter by M and incrementing a count value of the first valid codeword counter by Q, where both M and Q are integers greater than or equal to 1; and determining the position of the current observed bit as a candidate position in response to the count value of the first codeword counter being equal to the sixth threshold if the count value of the third codeword counter is less than or equal to a fifth threshold and the fifth threshold is greater than or equal to a sixth threshold.

[0039] In the solution of the present application, N observation bits are verified sequentially, and when the number of test blocks that satisfy the verification condition reaches a certain number in the test block selected based on the certain observation bit, the position of the observation bit is determined as a candidate position. In this way, it is possible that verification does not need to be performed for all observation bits, so that the candidate position can be determined quickly.

[0040] In a possible implementation form, the synchronization position determination state further includes a second code word valid portion state, and the step of increasing the count value of the third code word counter by M and increasing the count value of the first valid code word counter by Q in response to the third test block satisfying the verification condition includes the steps of entering the second code word valid portion state in response to the third test block satisfying the verification condition, and in the second code word valid portion state, increasing the count value of the third code word counter by M and increasing the count value of the first valid code word counter by Q.

[0041] In a possible implementation form, the step of selecting N observation bits from the data sequence and selecting a candidate position in the data sequence from the positions of the N observation bits in the synchronization position determination state further includes a step of verifying the next observation bit selected from the data sequence in response to the count value of the third code word counter being equal to a fifth threshold and the count value of the first valid code word counter being less than a sixth threshold in the second code word valid portion state.

[0042] In a possible implementation form, the step of selecting N observation bits from the data sequence and selecting a candidate position in the data sequence from the positions of the N observation bits in the synchronization position determination state further includes the step of re-entering a fourth code word verification sub-state in response to the count value of the third code word counter being less than a fifth threshold and the count value of the first valid code word counter being less than a sixth threshold in the second code word valid sub-state and verifying a next third test block selected based on the current observation bits.

[0043] In a possible implementation, the synchronization position determination state further includes a first code word invalid portion state, and the step of selecting N observation bits from the data sequence and selecting a candidate position in the data sequence from the positions of the N observation bits in the synchronization position determination state further includes the steps of entering the first code word invalid portion state in response to a third test block not satisfying a verification condition, increasing a count value of a third code word counter by M in the first code word invalid portion state, and verifying the next observation bit selected from the data sequence in response to the count value of the third code word counter being equal to a fifth threshold.

[0044] In a possible implementation form, the step of selecting N observation bits from the data sequence and determining a candidate position within the data sequence based on the N observation bits in the synchronization position determination state further includes, in response to the count value of the third code word counter being less than a fifth threshold in the first code word invalid portion state, re-entering a fourth code word verification portion state to verify the next third test block selected based on the current observation bits.

[0045] In a possible implementation, the synchronization position determination state includes a third slip portion state, and the step of verifying the next observation bit selected from the data sequence further includes the steps of entering the third slip portion state, slipping to the next observation bit in the third slip portion state, and in response to slipping to the next observation bit, re-entering the third counter reset portion state and verifying the next observation bit.

[0046] In a possible implementation form, the synchronization position determination state further includes a third synchronization lock initialization sub-state, and prior to the step of setting an initial value of the third codeword counter and an initial value of the first valid codeword counter in the third counter reset sub-state, the method further includes a step of setting the value of the third verification target codeword variable to a third value in the third synchronization lock initialization sub-state.

[0047] In a possible implementation, the step of entering a fourth codeword verification sub-state in response to selecting one third test block from the data sequence based on the current observed bits includes the steps of setting a value of a third codeword variable to be verified to a fourth value in response to selecting one third test block from the data sequence based on the current observed bits, and entering the fourth codeword verification sub-state in response to the value of the third codeword variable to be verified being the fourth value.

[0048] In a possible implementation, determining the synchronization location based on the candidate location includes verifying the candidate location and determining the candidate location as the synchronization location after successful verification.

[0049] In the solution of the present application, after a candidate position is selected, the candidate position is verified, and after the verification is successful, the candidate position is determined as a synchronization position. Because further verification is performed on the candidate position, the determined synchronization position can be more accurate.

[0050] In a possible implementation, the synchronization position determination state further includes a fourth counter reset sub-state and a fifth codeword verification sub-state, and the step of verifying the candidate position and determining the candidate position as a synchronization position after the verification is successful includes the steps of: setting an initial value of a fourth codeword counter in the fourth counter reset sub-state and selecting one fourth test block from the data sequence based on the candidate position; entering a fifth codeword verification sub-state in response to selecting one fourth test block from the data sequence based on the candidate position; verifying the fourth test block in the fifth codeword verification sub-state; in response to the fourth test block satisfying the verification condition, increasing a count value of the fourth codeword counter by R, where R is an integer greater than or equal to 1; and determining the candidate position as a synchronization position in response to the count value of the fourth codeword counter being equal to a seventh threshold value.

[0051] In the solution of the present application, the fourth test block selected based on the candidate position is verified in sequence, and when the number of the fourth test blocks that meet the verification condition reaches a certain number, the candidate position is determined as a synchronization position, so that it can be determined whether the candidate position is a synchronization position.

[0052] In a possible implementation, the synchronization position determination state further includes a third codeword valid portion state, and the step of increasing the count value of the fourth codeword counter by R in response to the fourth test block satisfying the verification condition includes the steps of entering the third codeword valid portion state in response to the fourth test block satisfying the verification condition, and increasing the count value of the fourth codeword counter by R in the third codeword valid portion state.

[0053] In a possible implementation, the step of verifying the candidate position and determining the candidate position as a synchronization position after successful verification further includes the step of re-entering a fifth code word verification sub-state in response to the count value of the fourth code word counter being less than a seventh threshold and verifying a next fourth test block selected based on the candidate position.

[0054] In a possible implementation form, the step of verifying the candidate position and determining the candidate position as a synchronization position after successful verification further includes a step of reselecting the candidate position in response to a fourth test block not satisfying the verification condition.

[0055] In the solution of the present application, if one fourth test block does not satisfy the verification condition, the candidate position is reselected, so that the selected candidate position may be more likely to be a synchronization position.

[0056] In a possible implementation form, the synchronization position determination state further includes a first resynchronization sub-state, and the step of reselecting a candidate position in response to a fourth test block not satisfying the verification condition includes a step of entering the first resynchronization sub-state in response to the fourth test block not satisfying the verification condition, and a step of setting a value of a first resynchronization lock variable to a second value in the first resynchronization sub-state, wherein the value of the first resynchronization lock variable being the second value indicates reselection of a candidate position in the data sequence.

[0057] In a possible implementation form, the synchronization position determination state further includes a second synchronization lock success partial state, and the step of determining the candidate position as a synchronization position in response to the count value of the fourth codeword counter being equal to the seventh threshold includes a step of entering the second synchronization lock success partial state in response to the count value of the fourth codeword counter being equal to the seventh threshold, and a step of setting a value of a second synchronization lock variable to a second value in the second synchronization lock success partial state, wherein the value of the second synchronization lock variable being the second value indicates that the candidate position is a synchronization position.

[0058] In a possible implementation, determining the synchronization position based on the candidate position includes determining the candidate position as the synchronization position.

[0059] In the solution of the present application, the candidate positions are directly determined as synchronous positions, so that the synchronous positions can be determined quickly.

[0060] In a possible implementation, the step of verifying a plurality of codewords selected based on a synchronization position in the lock loss detection state and re-entering the synchronization position determination state in response to a verification failure includes the step of verifying codewords in a codeword set selected based on the synchronization position in the lock loss detection state, the codeword set including a target number of codewords, and the step of re-entering the synchronization position determination state in response to the number of codewords in the codeword set that do not satisfy the verification condition reaching an eighth threshold.

[0061] In the solution of the present application, after the synchronization position is selected, it is continuously judged whether the synchronization position is correct, so that continuous codeword synchronization can be performed.In addition, it is judged whether the number of codewords that do not meet the verification condition reaches a certain value, and the number of codewords that do not meet the verification condition is relatively small.Therefore, it is judged whether the synchronization position is correct based on the number of codewords that do not meet the verification condition, so that it can be more quickly judged whether the synchronization position is correct.

[0062] In a possible implementation, the lock loss detection state includes a fifth counter reset sub-state and a sixth code word verification sub-state, and in the lock loss detection state, the step of verifying a code word in a code word set selected based on the synchronization position, the code word set including a target number of code words, and in response to a number of code words in the code word set not satisfying the verification condition reaching an eighth threshold, the step of re-entering the synchronization position determination state includes the steps of setting an initial value of a fifth code word counter and an initial value of a second invalid code word counter in the fifth counter reset sub-state, and entering a sixth codeword verification sub-state in response to selecting one second codeword from the data sequence based on the eighth threshold; verifying the second codeword in the sixth codeword verification sub-state; incrementing a count value of a fifth codeword counter by one and incrementing a count value of a second invalid codeword counter by one in response to the second codeword not satisfying the verification condition; and re-entering a synchronization position determination state in response to the count value of the second invalid codeword counter being equal to an eighth threshold if the count value of the fifth codeword counter is less than the target value.

[0063] In the solution of the present application, after a synchronization position is selected, it is continuously determined whether the synchronization position is correct, so that successive codeword synchronization can be performed.

[0064] In a possible implementation, the lock loss detection state further includes a second codeword invalid portion state, and the step of increasing the count value of the fifth codeword counter by one in response to the second codeword not satisfying the verification condition includes the steps of entering the second codeword invalid portion state in response to the second codeword not satisfying the verification condition, and in the second codeword invalid portion state, increasing the count value of the fifth codeword counter by one and increasing the count value of the second invalid codeword counter by one.

[0065] In a possible implementation form, in the lock loss detection state, the step of verifying a codeword in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords, and the step of re-entering the synchronization position determination state in response to the number of codewords in the codeword set that do not satisfy the verification condition reaching an eighth threshold further include the steps of increasing the count value of a fifth codeword counter by 1 in response to a second codeword that satisfies the verification condition, and re-entering the fifth counter reset sub-state in response to the count value of the fifth codeword counter being equal to the target value and performing a next verification on the synchronization position.

[0066] In a possible implementation, the lock loss detection state further includes a fourth codeword valid portion state, and the step of increasing the count value of the fifth codeword counter by one in response to the second codeword satisfying the verification condition includes the steps of entering the fourth codeword valid portion state in response to the second codeword satisfying the verification condition, and increasing the count value of the fifth codeword counter by one in the fourth codeword valid portion state.

[0067] In a possible implementation form, in the lock loss detection state, the step of verifying a code word in a code word set selected based on the synchronization position, the code word set including a target number of code words, and the step of re-entering the synchronization position determination state in response to the number of code words in the code word set that do not satisfy the verification condition reaching an eighth threshold further includes the step of re-entering the sixth code word verification sub-state in response to the count value of the fifth code word counter being less than the target value in the third code word valid sub-state to verify the next second code word selected based on the synchronization position.

[0068] In a possible implementation form, in the lock loss detection state, the step of verifying a code word in a code word set selected based on a synchronization position, the code word set including a target number of code words, and the step of re-entering the synchronization position determination state in response to the number of code words in the code word set that do not satisfy the verification condition reaching an eighth threshold further includes the step of re-entering the sixth code word verification sub-state in response to the count value of the fifth code word counter being less than the target value and the count value of the second invalid code word counter being less than the eighth threshold in the second code word invalid sub-state to verify the next second code word selected based on the synchronization position.

[0069] In a possible implementation form, in the lock loss detection state, the step of verifying a code word in a code word set selected based on the synchronization position, the code word set including a target number of code words, and the step of re-entering the synchronization position determination state in response to the number of code words in the code word set that do not satisfy the verification condition reaching an eighth threshold further includes the step of re-entering the fifth counter reset sub-state in response to the count value of the fifth code word counter being equal to the target value and the count value of the second invalid code word counter being less than the eighth threshold in the second code word invalid sub-state and performing a next verification on the synchronization position.

[0070] In possible implementations, the verification condition is that the number of zero elements in the syndrome of the test block or codeword is greater than a synchronous threshold, or the verification condition is that the number of non-zero elements in the syndrome of the test block or codeword is less than an asynchronous threshold, or the verification condition is that the test block or codeword is an error correcting test block, or the verification condition is that the re-parity bits of the test block or codeword are the same as the original parity bits.

[0071] In the solution of the present application, verification can be performed in multiple ways on a test block or code word, so that the test blocks and code words are verified more flexibly.

[0072] In possible implementations, the start signal includes a system reset or start signal, a data receive fail signal, or a resynchronization signal.

[0073] In a possible implementation, the data sequence is a bit stream that is encoded via FEC. In this manner, the codeword synchronization method can be applied to a bit stream that is encoded via FEC.

[0074] According to a second aspect, the present application provides a codeword synchronization device, comprising: a synchronization position determination module configured to enter a synchronization position determination state in response to a start signal, and to determine a synchronization position within the received data sequence in the synchronization position determination state, the synchronization position indicating a starting position of a codeword within the data sequence; a lock loss detection module configured to, in response to determining the synchronization position, enter a lock loss detection state, verify the selected codewords based on the synchronization position in the lock loss detection state, and, in response to a verification failure, re-enter a synchronization position determination state; Includes.

[0075] According to a third aspect, the present application provides a communication device. The communication device includes a processor and a memory. The memory stores at least one computer instruction. The computer instruction is loaded and executed by the processor to implement a codeword synchronization method according to the first aspect or a possible implementation of the first aspect.

[0076] According to a fourth aspect, the present application provides a chip, the chip being configured to implement a codeword synchronization method according to the first aspect or a possible implementation of the first aspect.

[0077] According to a fifth aspect, the present application provides a chip system. The chip system includes a first chip and a second chip that are cascaded. The first chip is configured to implement a codeword synchronization method according to the first aspect or a possible implementation of the first aspect. The second chip is configured to perform codeword synchronization based on an AM mode. [Brief description of the drawings]

[0078] [Figure 1] FIG. 2 is a diagram of the principle of a state machine according to an exemplary embodiment of the present application; [Diagram 2] 4 is a diagram of codewords and synchronization positions according to an exemplary embodiment of the present application; [Diagram 3] FIG. 2 is a diagram of an application scenario according to an exemplary embodiment of the present application. [Figure 4] FIG. 2 is a diagram of an application scenario according to an exemplary embodiment of the present application. [Diagram 5] FIG. 2 is a diagram of an application scenario according to an exemplary embodiment of the present application. [Figure 6] FIG. 2 is a diagram of an application scenario according to an exemplary embodiment of the present application. [Figure 7] FIG. 2 is a schematic logic diagram of codeword synchronization according to an exemplary embodiment of the present application. [Figure 8] 4 is a flowchart of a method for implementing codeword synchronization based on a state machine, according to an exemplary embodiment of the present application. [Figure 9] FIG. 4 is a state diagram for determining a synchronization position according to an exemplary embodiment of the present application. [Figure 10] FIG. 4 is a state diagram for synchronization position determination and loss of lock detection according to an exemplary embodiment of the present application. [Figure 11] FIG. 4 is a state diagram for determining candidate locations according to an exemplary embodiment of the present application. [Figure 12] FIG. 4 is a state diagram for determining candidate locations according to an exemplary embodiment of the present application. [Figure 13] FIG. 4 is a state diagram for determining candidate locations according to an exemplary embodiment of the present application. [Figure 14] FIG. 13 is a state diagram for determining to validate a candidate location according to an exemplary embodiment of the present application. [Figure 15] FIG. 13 is a state diagram for determining to validate a candidate location according to an exemplary embodiment of the present application. [Figure 16] FIG. 4 is a state diagram of a loss of lock detection process, according to an exemplary embodiment of the present application. [Figure 17] FIG. 4 is a state diagram of a loss of lock detection process, according to an exemplary embodiment of the present application. [Figure 18] FIG. 4 is a state diagram for determining candidate locations according to an exemplary embodiment of the present application. [Figure 19] 2 is a schematic diagram of a codeword synchronizer structure according to an exemplary embodiment of the present application; [Figure 20] 1 is a diagram of a structure of a communication device according to an exemplary embodiment of the present application. [Figure 21] 1 is a diagram of a structure of a communication device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] To clarify the objectives, technical solutions and advantages of the present application, the implementation of the present application will be further described in detail hereinafter with reference to the accompanying drawings.

[0080] In the following, some terms and concepts in the embodiments of the present application are explained and explained.

[0081] 1. Codeword synchronization: Codeword synchronization refers to the process of determining the start and end positions of a complete codeword within a data sequence. A data sequence is sometimes called a data stream or a bit stream, and codeword synchronization is sometimes called frame synchronization.

[0082] 2. State machine: Full name finite state machine (FSM). A state machine is a mathematical model obtained by extracting and abstracting the operations necessary to implement a certain function. A state machine divides all the operations necessary for the function implementation into a finite number of related states. Each state contains one or more sub-operations. Transitions between states are triggered by the change of an input signal or certain parameters. The certain parameters are stored in registers and are considered as register variables. A state machine can be in only one state at any moment.

[0083] When the state machine is implemented in hardware, it comprises combinational logic and registers, the combinational logic configured to perform operations and the registers configured to store register variables.

[0084] State machines are represented in multiple ways, with state diagrams (or state transition diagrams) being the most common due to their intuitiveness. In a state diagram, each state is represented using a rectangle, divided into two parts by a horizontal line within the rectangle, with the state name at the top and the operations to be performed in that state at the bottom. Transitions between states are represented using one-way arrows, with text descriptions on the arrows indicating the condition that must be met for the transition, which is called the transition condition. Figure 1 provides an example of a single state and the conditions for entering and leaving that state. When a state machine enters a state, it first executes the operations in that state, then detects whether the transition condition is met, and enters the next corresponding state if the transition condition is met.

[0085] In FIG. 1, states are represented using rectangles. This is merely an example herein. States may alternatively be represented using other shapes, such as circles, and state transitions may alternatively be represented using other arrows or forms. This is not a limitation in the embodiments of the present application.

[0086] The following provides background to the present application.

[0087] Due to the effects of signal loss and noise, errors occur when a signal is transmitted through a channel, which affects the reliability of the communication system. When a signal is represented in the form of a data sequence containing multiple bits, the transmission error is specifically embodied as a change in the value of some bits in the data sequence, i.e., bit errors occur. FEC is a technique for controlling transmission errors in communication systems. In FEC techniques, redundant information is transmitted along with the original data sequence to recover errors and reduce the bit error rate during transmission. FEC can be classified into block codes and convolutional codes based on different data sequence processing modes. Block codes may be further subdivided into linear block codes and nonlinear block codes. A systematic code of linear block codes is used as an example. The transmitter groups the original data sequence. Each group has a length of k bits. In each group, nk bits of redundant information are added according to a specific encoding rule, and the redundant information is called parity bits. Finally, a codeword of length n bits is obtained. Both n and k are integers. Thus, in a codeword of length n bits, the first k bits are the original data, also called information bits, and the last nk bits are parity bits. A complete codeword includes information bits and parity bits. After a codeword is transmitted from a transmitter to a receiver through a channel, if the number of error bits in the codeword is within the error correction range, the receiver can check and correct the error bits by decoding, and restore the received codeword to the original data transmitted by the transmitter, thereby reducing the interference caused by the channel and improving the reliability of the communication system. The error detection and error correction functions of a linear block codeword need to be implemented based on the complete codeword. Therefore, before the data sequence received by the receiver is decoded, the boundaries of the codeword need to be determined in the data sequence, i.e., the start and end positions of the complete codeword need to be found. This process is called codeword synchronization or frame synchronization.If the codeword synchronization is incorrect, i.e., if the correct starting position is not determined, the error detection or error correction effect cannot be achieved in the subsequent decoding process, and the bit error rate may even be increased, causing the performance degradation of the communication system. It can be seen that the codeword synchronization is important.

[0088] A systematic code is used as an example. Figure 2 provides the synchronization position of a codeword. As shown in Figure 2, the length of the whole codeword is n bits, the first k bits are original data, and the last nk bits are parity bits, and the synchronization position in the data sequence is the start position of the codeword, i.e., the position of the first bit in the codeword. In the data sequence, there are multiple synchronization positions, and the multiple synchronization positions are associated with each other. In other words, the interval between adjacent synchronization positions is fixed, and the interval is equal to the length of the codeword, which is called the codeword length for short.

[0089] In the embodiment of the present application, a systematic code is used as an example for explanation below, but the present application is not limited to systematic codes and can also be applied to non-systematic codes. The present application is applicable to all communication systems using linear block codes. Linear block codes include, but are not limited to, Reed-Solomon code (RS code), Bose-Chaudhuri-Hocquenghem code (BCH code), Low-Density Parity-Check code (LDPC code), Hamming code, Golay code, and Reed-Muller code.

[0090] The following describes the hardware device and application scenario in the embodiment of the present application.

[0091] The embodiments of the present application are applicable to communication devices that perform FEC, such as routers, switches, or servers.

[0092] The following provides three application scenarios that are implemented with reference to the physical layer of the Ethernet standard. For example, in a two-level cascaded FEC scenario, the Reed-Solomon code (RS) of the Ethernet standard is used as the cascaded outer FEC (FEC1). Since the AM solution is already used in the Ethernet standard to perform receiver RS-FEC codeword synchronization, the codeword synchronization solution in the embodiment of this application can be applied to the inner FEC (FEC2) of the two-level cascaded FEC. The inner FEC may also be called the first FEC, and the outer FEC may also be called the second FEC.

[0093] In application scenario 1, the two-level cascaded FEC is located in different chips. The chip where FEC1 is located can use the transmitting end structure and the receiving end structure defined in the existing standard, and the codeword synchronization is performed using the AM solution during decoding. Referring to FIG. 3, in the transmitter and the receiver, FEC1 is usually integrated in an application specific integrated circuit (ASIC), and the codeword synchronization is performed during decoding using the AM solution, and FEC2 is usually integrated in a clock and data recovery (CDR), a retimer, an optical digital signal processor (oDSP), etc., and the codeword synchronization is performed during decoding using the solution in the embodiment of this application. Application scenario 1 is usually a long-distance or high-rate transmission scenario, and FEC2 needs to be used at the relay node to enhance the error correction capability. In this specification, when the relay node is an oDSP, the link can transmit an optical signal.

[0094] In application scenario 2, two-level cascade FEC is located in the same chip in both transmitter and receiver. Referring to Fig. 4, in transmitter and receiver, FEC1 is integrated in ASIC, and codeword synchronization is performed during decoding using AM solution, and FEC2 is integrated in ASIC, and codeword synchronization is performed during decoding using codeword synchronization solution in the embodiment of this application. In application scenario 2, physical units of FEC2 are further added in transmitting end chip and receiving end chip.

[0095] In application scenario 3, the two-level cascaded FEC is located on the same chip at one end of the transmitter and receiver, and on a different chip at the other end. In FEC1, codeword synchronization is performed during decoding using the AM solution, and in FEC2, codeword synchronization is performed during decoding using the codeword synchronization solution in the embodiment of this application. In application scenario 3, a physical unit of FEC2 is added at one end where the two-level cascaded FEC is located on the same chip, and FEC1 at the other end still uses the transmitting end structure or the receiving end structure defined in the Ethernet standard, and FEC2 is integrated into CDR, retimer, oDSP, etc. Referring to FIG. 5, in the transmitter, FEC1 and FEC2 are integrated into ASIC, and in the receiver, FEC1 is integrated into ASIC, and FEC2 is integrated into CDR, retimer, or oDSP. Referring to FIG. 6, in the transmitter, FEC1 is integrated into the ASIC, and FEC2 is integrated into the CDR, retimer, or oDSP, and in the receiver, FEC1 and FEC2 are integrated into the ASIC.

[0096] It should be noted that the three application scenarios are described using two-level cascaded FEC as an example. The codeword synchronization solution in the embodiment of the present application may alternatively be applied to a multi-level cascaded FEC scenario, and may be applied not only to the inner FEC technique, but also to the technique of each layer FEC. This is not limited in the embodiment of the present application.

[0097] In addition, this embodiment of the present application may alternatively be applied to a non-cascaded FEC scenario, in other words, both the transmitter and the receiver perform FEC once, and the codeword synchronization solution in the embodiment of the present application may also be applied once to FEC.

[0098] The following describes the steps of a method for implementing codeword synchronization based on a state machine in one embodiment of the present application.

[0099] In this embodiment of the present application, the complete synchronization procedure includes two phases, a synchronization lock phase and a lock loss detection phase, to form a closed loop so that the receiving side of the communication system is in a synchronization lock state as long as possible, as shown in Figure 7. For example, in the synchronization lock phase, the synchronization position is determined, and in the lock loss detection phase, it is continuously determined whether the synchronization position is correct, and if the synchronization position is incorrect, the synchronization position is re-determined.

[0100] In this embodiment of the application, each state is represented using a rectangle, divided into two parts by a horizontal line in the rectangle, the upper part is the state name, and the lower part is the operation to be performed in that state. The representation of the state is just an example. This is not limited in the embodiment of the application. In the text description, {} indicates the name of a single state, and [] indicates the name of a register variable. In the state diagram, "+" indicates logical OR, "*" indicates logical AND, "!" indicates logical negation, "<=" indicates that the left variable is assigned the value of the right variable, and "+++" indicates that the value of the register variable stored in the register is increased by 1. UCT means unconditional transition.

[0101] 8 is a flowchart of a method according to an embodiment of the present application. The method is applied to a communication device in a communication network, specifically a receiver device configured to receive data. The communication device may be various devices that perform FEC, including but not limited to routers, switches, servers, etc. The method includes steps 801 to 804.

[0102] STEP 801: A sync position determination state is entered in response to detecting a start signal.

[0103] In this embodiment, during synchronous position determination, after a [START SIGNAL] is detected, an unconditional transition is triggered to enter the {synchronous position determination state}.

[0104] For example, the "start signal" includes a system reset signal, a system start signal, a data reception failure signal, or a resynchronization signal. The system reset signal indicates that a portion of the receiver used for decoding is being reconfigured. The system start signal indicates that a portion of the receiver used for decoding is activated. For example, the system start signal is detected, for example, when a data sequence is received. The data reception failure signal indicates a decoding failure at the receiver. The resynchronization signal indicates that the synchronization position is re-determined.

[0105] In this specification, the system reset signal, the system start signal, the system receive signal, and the resynchronization signal are all register variables and are represented as [system reset signal], [system start signal], [system receive signal], and [resynchronization signal], respectively.

[0106] Step 802: The state machine determines a synchronization position in a data sequence in a synchronization position determination state, where the synchronization position indicates a starting position of a codeword in the data sequence.

[0107] A data sequence is received from a transmitter. The data sequence includes a number of bits, each bit being binary data. The data sequence may also be referred to as a bit sequence. The data sequence uses a linear block code. When the data sequence is transmitted over a channel, bit errors may exist and error detection, error correction, and other operations need to be performed.

[0108] In this embodiment, the state machine determines a synchronization position in the data sequence in the {synchronization position determination state}, where the synchronization position is the starting position of a codeword in the data sequence.

[0109] Step 803: The state machine enters a loss of lock detection state in response to determining the synchronization position.

[0110] The loss of lock detection state is a state of the state machine and is denoted as {loss of lock detection state}.

[0111] Step 804: In a loss of lock detection state, the state machine verifies the selected codewords based on the synchronization position and updates the synchronization position in response to a verification failure.

[0112] According to the solution of the present application, the codeword synchronization of the data sequence sent by the transmitter can be implemented in the receiver without inserting additional overhead bits into the data sequence, and the synchronization reliability is high. In addition, after the synchronization position is determined, a lock loss detection mechanism is further used to determine whether the synchronization position is accurate, thereby further improving the synchronization reliability.

[0113] In the case of step 802, the synchronization position determination process is specifically as follows.

[0114] N observation bits are selected from the data sequence, and the synchronization position is determined based on the position of the observation bit in {synchronization position determination state}, where N is an integer equal to or greater than 1. The position of a specific observation bit may be the synchronization position. There are multiple observation bit selection methods. The following provides three possible implementations.

[0115] In one implementation, N observed bits are selected from a data sequence. If N is greater than 1, the spacing between adjacent observed bits in the multiple observed bits is the same.

[0116] In another implementation, the concept of a test block is introduced in the codeword synchronization process. A test block belongs to a data sequence, and the test block includes multiple bits. The length of the test block is the same as the codeword length. Each test block can be considered to simulate one codeword. If N is greater than 1, N observation bits may be placed in one test block, and the positions of the N observation bits in one test block move backwards sequentially. For example, the number of N observation bits is equal to the test block length, in other words, the positions of all bits in a single test block are traversed by traversing the positions of N observation bits. Since traversing the positions of all bits in a single test block can be considered as traversing the positions of all bits in a single codeword, the determined synchronization position can be more accurate. However, as the number of observation bits increases, the resources consumed in the codeword synchronization process also increase. As another example, the number of N observation bits is less than the test block length, and one observation bit may be selected for every M bits in the test block, where M is an integer equal to or greater than 1, and M is less than n, and n is the number of bits included in the codeword.

[0117] In yet another implementation, the positions of the N observation bits in each test block are moved backward in sequence. For example, one bit is selected as an observation bit every L*n+M bits, where L is the number of test blocks in the interval, L is an integer equal to or greater than 1, and the test block length is n, i.e., the test block includes n bits. By selecting the observation bits in this manner, the interval between adjacent observation bits is relatively large, and the correlation between the observation bits is low, so that the effect of burst bit errors can be reduced, and thus the codeword synchronization accuracy can be further improved. In this specification, the number of observation bits is equal to or less than n. When the number of observation bits is equal to n, the position of the first bit in each of the multiple test blocks is regarded as an equivalent position, and the position of the i-th bit is regarded as an equivalent position, so that when the number of observation bits is equal to n, all equivalent positions can be traversed by traversing the positions of the N observation bits, and as a result, all positions in the multiple test blocks can be traversed by traversing the N observation bits, where i is greater than 1 and less than or equal to n.

[0118] For example, below we provide two possible implementations that determine the synchronization position based on the position of the observed bit.

[0119] In one implementation, the synchronization position is selected from the positions of the N observed bits.

[0120] In this implementation, the principle of selecting the synchronization position is: sequentially selecting an observation bit; sequentially selecting multiple test blocks based on one observation bit selected each time; and if the multiple test blocks all meet the verification condition of a specific observation bit, determining the position of the observation bit as the synchronization position, where the positions of the multiple test blocks in the data sequence may be consecutive or non-consecutive. For ease of explanation, in this implementation, the test block is called the first test block. The number of the multiple test blocks may be set based on empirical values ​​or based on simulation analysis results. In this embodiment of the present application, the test block meeting the verification condition means that the test block is an acceptable block codeword, and the test block not meeting the verification condition means that the test block is not an acceptable block codeword. In this specification, the test block is an acceptable block codeword and is considered as an acceptable block codeword based on the current verification scheme.

[0121] Specifically, Figure 9 is a diagram for implementing codeword synchronization. As shown in Figure 9, {synchronization position determination state} includes {first counter reset partial state} and {first codeword verification partial state}, where {first counter reset partial state} is a state in which the counter required in the codeword synchronization process is reset, and {first codeword verification partial state} is a state in which the test block is verified. The processing method for selecting a synchronization position based on the positions of N observation bits is as follows.

[0122] The initial value of [First Codeword Counter] is set to {First Counter Reset Partial State}, and the initial value can be 0 or another value. One observation bit is selected from the received data sequence, and one first test block is selected from the data sequence based on the observation bit. The start position of the first test block and the position of the current observation bit are separated by an integer amount of the codeword length. For the observation bit selection method, please refer to the above description. The details will not be described again in this specification.

[0123] In response to selecting one first test block, a {first codeword verification sub-state} is entered, the first test block is verified in the {first codeword verification sub-state}, and a count value of the [first codeword counter] is incremented by X in response to the first test block satisfying a verification condition, where X is a value greater than or equal to 1.

[0124] A value relationship between the count value of the [first codeword counter] and a first threshold is determined, and in response to the count value of the [first codeword counter] being equal to the first threshold, the position of the currently observed bit is determined as a synchronization position.

[0125] When X is equal to 1, the first threshold is the number of first test blocks selected based on the observed bits. When X is greater than 1, the first threshold is X times the number of first test blocks selected based on the observed bits.

[0126] Optionally, in response to the count value of the [first codeword counter] being less than the first threshold, a next first test block is selected based on the current observed bits, a next first test block is selected from the data sequence based on the current observed bits, and the next first test block is verified. In this specification, selecting a next first test block based on the current observed bits means sequentially selecting first test blocks from the data sequence back and forth. The intervals between adjacent first test blocks may be equal or unequal, and the positions of adjacent first test blocks in the data sequence may be adjacent or non-adjacent.

[0127] Optionally, the {synchronization position determination state} further includes a {first code word valid portion state}. In response to the first test block satisfying a verification condition, the {first code word valid portion state} is entered. In the {first code word valid portion state}, the count value of the [first code word counter] is increased by X.

[0128] Optionally, the value of the [first code word valid variable] is set to a second value in response to the first test block satisfying a verification condition, and the {first code word valid portion state} is entered in response to the value of the [first code word valid variable] being the second value.

[0129] Optionally, in response to the first test block not satisfying the verification condition, a next observation bit is selected from the data sequence, and the next observation bit is verified. The verification manner of all the observation bits is the same. In this specification, the observation bits are selected sequentially, that is, the observation bits selected twice consecutively move sequentially backward in the data sequence.

[0130] Optionally, the {synchronization position determination state} further includes a {first slip portion state}, where the {first slip portion state} is a state in which an observation bit is slipped. In response to the first test block not satisfying a verification condition, the {first slip portion state} is entered. The next observation bit in the data sequence is slipped to the {first slip portion state}. The slip operation may be implemented using a slip (SLIP) function. In response to slipping to the next observation bit, the {first counter reset portion state} is entered and the next observation bit is verified.

[0131] Optionally, the value of the [first slip complete variable] is set to true or another value after the next observation bit slips, and the {first counter reset substate} is entered in response to the value of the [first slip complete variable] being true or another value indicating slip completion.

[0132] The value of the [first slip complete variable] is set to false or another value every time in the {first counter reset substate}.

[0133] Optionally, the value of the [first code word valid variable] is set to a first value in response to a first test block not satisfying a verification condition, and a {first slip portion state} is entered in response to the value of the [first code word valid variable] being the first value.

[0134] Optionally, the {synchronization position determination state} further includes {first synchronization lock initialization sub-state}, and the {first synchronization lock initialization sub-state} is a synchronization start state.

[0135] In response to detecting the [start signal], a {first sync lock initialization sub-state} is entered and the value of the [first sync lock variable] is set to a first value in the {first sync lock initialization sub-state}, where the first value may be false, 0, etc.

[0136] Optionally, after the value of [first synchronization lock variable] is set to a first value in {first synchronization lock initialization sub-state}, a {first counter reset sub-state} is entered with an unconditional transition.

[0137] Optionally, the value of the [first codeword variable to be verified] is set to a third value in the {first synchronization lock initialization sub-state}, where the third value may be false, 0, etc., and the value of the [first codeword variable to be verified] is set to a fourth value after one first test block is selected, where the fourth value may be true, 1, etc., and in response to the value of the [first codeword variable to be verified] being the fourth value and the value of the [first synchronization lock variable] being the first value, the {first codeword verification sub-state} is entered and the value of the [first codeword variable to be verified] is set to the third value upon entering the {first codeword verification sub-state}.

[0138] Optionally, when the {synchronization position determination state} further includes a {first synchronization lock initialization substate}, the value of the [first synchronization lock variable] is set to a second value in response to the count value of the [first codeword counter] being equal to the first threshold, where the second value may be true, 1, etc. When the value of the [first synchronization lock variable] is the second value, it indicates that the position of the current observed bit is a synchronization position.

[0139] Optionally, when the {synchronization position determination state} further includes a {first synchronization lock initialization substate}, the {synchronization position determination state} further includes a {first synchronization lock success substate}, where the {first synchronization lock success substate} is a state in which synchronization is completed.

[0140] In response to the count value of the [first codeword counter] being equal to the first threshold, the {first sync lock successful partial state} is entered. The value of the [first sync lock variable] is set to a second value of the {first sync lock successful partial state}, which may be true, 1, etc. When the value of the [first sync lock variable] is the second value, it indicates that the current observed bit position is a sync position.

[0141] Optionally, whether the first test block satisfies the verification condition may be determined based on an eigenvalue of the first test block. The eigenvalue of the first test block includes a syndrome, a re-parity bit, or an error correction. If the corresponding eigenvalue is a syndrome, the verification function may be a computer syndrome (CAL_SYNDROME) function. If the corresponding eigenvalue is a re-parity bit, the verification function may be a re-parity bit comparison (COMPARE_PARITY) function. If the corresponding eigenvalue is an error correction, the verification function may be an error correction (ERROR_CORRECTION) function. The verification function shown in FIG. 9 is a CAL_SYNDROME function.

[0142] For example, if the eigenvalue of the first test block is a syndrome, it is determined whether the number of zero elements in the syndrome is greater than a synchronization threshold, and if the number of zero elements is greater than the synchronization threshold, the first test block satisfies the verification condition, i.e., the first test block is determined to be an acceptable block codeword, and if not, the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword. Alternatively, it is determined whether the number of non-zero elements in the syndrome is less than an asynchronous threshold, and if the number of non-zero elements is less than the asynchronous threshold, the first test block satisfies the verification condition, i.e., the first test block is determined to be an acceptable block codeword, and if not, the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword.

[0143] If the eigenvalue of the first test block is a re-parity bit, it is determined whether the re-parity bit is the same as the original parity bit, and if the re-parity bit is the same as the original parity bit, it may be determined that the first test block satisfies the verification condition, i.e., the first test block is an acceptable block codeword; otherwise, it is determined that the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword.

[0144] If the eigenvalue of the first test block is error correcting, it is determined whether the first test block can be corrected by the decoding algorithm, and if the first test block can be corrected by the decoding algorithm, it may be determined that the first test block satisfies the verification condition, i.e., the first test block is an acceptable block codeword; otherwise, it is determined that the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword.

[0145] It should be noted that each of the above three possible verification methods can be used for the test block verification, or two or all of the above three possible verification methods can be used for the test block verification. In addition, the verification may be alternatively performed in another manner. This is not limited in the embodiment of the present application.

[0146] The principle of verifying that a test block satisfies a verification condition in order to determine the position of an observation bit as a synchronization position is as follows.

[0147] For each linear block codeword, a check matrix can be generated. The check matrix describes the linear relationship between data in the linear block codeword, and the check matrix can be applied to the decoding process. When the data sequence is a linear block codeword, the data sequence also has a check matrix, which can be called the check matrix of the data sequence. Specifically, for the relationship between the data sequence and the check matrix of the data sequence, please refer to Equation (1).

number

[0148] In formula (1), C is the codeword in the data sequence, S is the syndrome of the codeword, and H is the check matrix of the data sequence. From formula (1), it can be seen that the syndrome of the codeword in the data sequence is obtained by multiplying the transpose of the check matrix of the data sequence, and the syndrome is a zero vector.

[0149] When the data sequence is the data sequence received by the receiver, the starting position of the codeword in the data sequence is determined. If the codeword is selected from the data sequence without using the correct starting position, the obtained codeword does not satisfy equation (1). In this case, the syndrome of the codeword in the data sequence may be expressed as equation (2). S R = R H T (2)

[0150] In equation (2), R is the codeword in the data sequence received by the receiver, and S R is the syndrome of the codeword, and H is the check matrix of the original data sequence sent by the transmitter. The syndrome of a codeword in the data sequence received by the receiver is the product of the codeword and the transpose of the check matrix of the original data sequence sent by the transmitter. From equations (1) and (2), if a codeword contains an error bit, S R It can be seen that x is not an all-zero matrix. Thus, the syndrome of the first test block in the data sequence received by the receiver can be used to determine whether the first test block satisfies the verification condition.

[0151] In the state diagram shown in FIG. 9, {first sync lock initialization sub-state} is represented as FEC_LOCK_INIT_1, {first counter reset sub-state} is represented as RESET_CNT_1, {first codeword verification sub-state} is represented as CW_CHECK_1, {first slip sub-state} is represented as SLIP_1, and {first sync lock success sub-state} is represented as FEC_LOCK_GOOD_1. The [first synchronization lock variable] is represented as fec_cw_sync_1, the [first code word variable to be verified] is represented as test_cw_1, the count value of the [first code word counter] is represented as cw_cnt_1, the value of the [first code word valid variable] when set to the second value is represented as valid_cw_1, the value of the [first code word valid variable] when set to the first value is represented as !valid_cw_1, and the [first slip completed variable] is represented as slip_done_1.

[0152] Another principle of selecting the synchronization position is to traverse N observation bits and determine the synchronization position at the position of the N observation bits. For example, N observation bits are traversed, and a fourth threshold test block is successively selected based on each observation bit, and the number of test blocks that satisfy the verification condition in the fourth threshold test block is determined, and the positions of the fourth threshold test block in the data sequence may be consecutive or discontinuous. The position of the observation bit corresponding to the maximum number of test blocks that satisfy the verification condition is determined as the synchronization position, or the position of the observation bit corresponding to the minimum number of test blocks that do not satisfy the verification condition is determined as the synchronization position. In this specification, the fourth threshold is a value obtained when W is equal to or less than 1. The fourth threshold may be set based on an empirical value or based on a simulation analysis result.

[0153] Specifically, for the state diagram for determining the synchronization position, please refer to the description of FIG. 11 below. This is equivalent to the signal output in FIG. 11 being the second transition signal. The second transition signal is used to trigger entering the {lock loss detection state}.

[0154] Another principle of selecting the synchronization location is: starting from the first observation bit, sequentially verifying whether all observation bits satisfy the synchronization condition, where the synchronization condition may be that at least a sixth threshold test block in the fifth threshold test blocks selected successively based on the observation bits satisfies the verification condition, where the positions of the fifth threshold test blocks in the data sequence may be consecutive or discontinuous, and the positions of the sixth threshold test blocks in the data sequence may be consecutive or discontinuous; and if a certain observation bit satisfies the synchronization condition, determining the position of the observation bit as the synchronization location. In this way, the observation bit verification can be completed in advance, which can save resources for determining the synchronization location.

[0155] In this specification, the fifth threshold is a value obtained when M is equal to or less than 1, and the sixth threshold is a value obtained when Q is equal to or less than 1. The fifth threshold and the sixth threshold may be set based on empirical values ​​or based on simulation analysis results.

[0156] Specifically, for the state diagram for determining the synchronization position, please refer to the description of FIG. 12 below. This is equivalent to the signal output in FIG. 12 being the second transition signal. The second transition signal is used to trigger entering the {lock loss detection state}.

[0157] For example, after the synchronization position is determined, the {lock loss detection state} is entered. Figure 10 is a state diagram in which a state machine implements the codeword synchronization process. In the state diagram shown in Figure 10, the synchronization position determination process and the lock loss detection process share the {first counter reset substate} and the {first slip substate}.

[0158] Specifically, referring to FIG. 10, the {lock loss detection state} includes the {second code word verification substate}, and the {second code word verification substate} is a state in which the code word is verified. In response to determining the synchronization position, the {first counter reset substate} is entered, or the {first counter reset substate} is entered with an unconditional transition if the value of the [first synchronization lock variable] is the second value. In the {first counter reset substate}, the initial value of the [first code word counter] and the initial value of the [first invalid code word counter] are set. Both initial values ​​may be 0. A code word is selected from the data sequence based on the synchronization position. In this specification, for ease of explanation, the code word selected based on the synchronization position is referred to as the first code word.

[0159] In response to selecting one first codeword, a {second codeword verification sub-state} is entered and the first codeword is verified in the {second codeword verification sub-state}.

[0160] In response to the first codeword not satisfying the verification condition, the count value of the [first codeword counter] is incremented by Y, and the count value of the [first invalid codeword counter] is incremented by Z, where both Y and Z are integers equal to or greater than 1. In response to the count value of the [first invalid codeword counter] being equal to a third threshold when the count value of the [first codeword counter] is equal to or less than the second threshold, indicating that the number of invalid codewords has reached the number of updated synchronization positions, re-enter the {synchronization position determination state}, and perform a synchronization position update operation. When Y is equal to 1, the second threshold is the number of first codewords selected based on the synchronization positions. When Y is greater than 1, the second threshold is Y times the number of first codewords selected based on the synchronization positions. When Z is equal to 1, the third threshold is the number of first codewords not satisfying the verification condition. When Z is greater than 1, the third threshold is Z times the number of first codewords not satisfying the verification condition. The second threshold and the third threshold may be set based on empirical values, or may be set based on the results of a simulation analysis.

[0161] Optionally, whether the first code word satisfies the verification condition may be determined based on the eigenvalue of the first code word. See Equation (1) and Equation (2) for the principle.

[0162] Optionally, the {lock loss detection state} further includes a {codeword invalid portion state}, which is a state entered when the first codeword does not satisfy a verification condition. In response to the first codeword not satisfying the verification condition, the {codeword invalid portion state} is entered. In the {codeword invalid portion state}, the count value of the [first codeword counter] is increased by Y, and the count value of the [first invalid codeword counter] is increased by Z.

[0163] Optionally, in response to the count value of the [first codeword counter] being less than the second threshold and the count value of the [first invalid codeword counter] being less than the third threshold, the {second codeword verification sub-state} is re-entered, a next first codeword is selected based on the synchronization position, and the next first codeword is verified. In this specification, the count value of the [first invalid codeword counter] being less than the third threshold indicates a relatively small number of invalid codewords, and verification may be performed on the next first codeword.

[0164] Optionally, in response to the count value of the [first codeword counter] being equal to the second threshold and the count value of the [first invalid codeword counter] being less than the third threshold, the {first counter reset sub-state} is re-entered and the next verification continues to be performed on the synchronization position. In this specification, the number of invalid codewords in the first codeword of the second threshold is relatively small, which indicates that the synchronization position is now accurate, and the verification may continue to be performed.

[0165] Optionally, the value of the [codeword valid variable] is set to a first value in response to a first code word that does not satisfy the verification condition, and the {codeword invalid portion state} is entered in response to the value of the [codeword valid variable] being the first value.

[0166] Optionally, the count value of the [first codeword counter] is incremented by Y in response to the first codeword satisfying the verification condition, and the {first counter reset substate} is re-entered in response to the count value of the [first codeword counter] being equal to the second threshold, indicating that the synchronization position is accurate, and the next verification continues to be performed on the synchronization position.

[0167] In response to the count value of the [first codeword counter] being less than the second threshold, the {second codeword verification substate} is re-entered and a next first codeword is selected based on the synchronization position and the next first codeword is verified.

[0168] Optionally, the {lock loss detection state} further comprises a {codeword valid portion state}, the {codeword valid portion state} being a state entered when the first codeword satisfies a verification condition. In response to the first codeword satisfying the verification condition, the {codeword valid portion state} is entered.

[0169] Optionally, the value of the [codeword valid variable] is set to a second value in response to the first codeword satisfying the verification condition, and the {codeword valid part state} is entered in response to the value of the [codeword valid variable] being the second value.

[0170] Optionally, if the {synchronization position determination state} further includes a {first slip portion state}, the process of re-entering the {synchronization position determination state} includes the steps of: entering the {first slip portion state} in response to the count value of the [first invalid code word counter] being equal to a third threshold; slipping to the next observed bit in the data sequence in the {first slip portion state}; and, in response to slipping to the next observed bit, entering the {first counter reset portion state} and verifying the next observed bit.

[0171] Optionally, the value of the [first slip completed variable] is set to a second value after the next observation bit slips, and in response to the value of the [first slip completed variable] being the second value, the {first counter reset sub-state} is re-entered, and in the {first counter reset sub-state} the value of the [first slip completed variable] is set to the first value and the next observation bit is verified.

[0172] Optionally, the value of the [first codeword variable to be verified] is set to a fourth value after one first codeword is selected, and in response to the value of the [first codeword variable to be verified] being the fourth value and the value of the [first synchronization lock variable] being the second value, {second codeword verification sub-state} is entered, and the value of the [first codeword variable to be verified] is set to a third value after entering the {second codeword verification sub-state}.

[0173] In the state diagram shown in FIG. 10, {first sync lock initialization sub-state} is represented as FEC_LOCK_INIT_1, {first counter reset sub-state} is represented as RESET_CNT_1, {second codeword verification sub-state} is represented as CW_CHECK_2, {codeword valid sub-state} is represented as VALID_CW_0, {first slip sub-state} is represented as SLIP_1, {first sync lock success sub-state} is represented as FEC_LOCK_GOOD_1, and {codeword invalid sub-state} is represented as INVALID_CW_0. The [first synchronization lock variable] is represented as fec_cw_sync_1, the [first code word variable to be verified] is represented as test_cw_1, the count value of the [first code word counter] is represented as cw_cnt_1, the value of the [code word valid variable] when set to the second value is represented as valid_cw_0, the value of the [code word valid variable] when set to the first value is represented as !valid_cw_0, the count value of the [first invalid code word counter] is represented as invalid_cw_cnt_1, and the [first slip completed variable] is represented as slip_done_1.

[0174] In the state diagram shown in FIG. 10, the first test block selected based on the observation bit belongs to the first subsequence, the first code word selected based on the synchronization position belongs to the second subsequence, both the first subsequence and the second subsequence belong to the data sequence, and the second subsequence is placed after the first subsequence.

[0175] In another implementation, N observation bits are selected from the data sequence in a {synchronization position determination state}, where N is 1 or more, and candidate positions are selected from the positions of the N observation bits, and a synchronization position is determined based on the candidate positions.

[0176] The candidate location is a location that is most likely to be a synchronization location. The candidate location may be determined as a synchronization location. Alternatively, a number of test blocks selected based on the candidate location are verified, and the candidate location is determined as a synchronization location after the verification is successful.

[0177] For example, there are multiple ways to determine candidate locations. The following provides three possible implementations. Please refer to Scheme 1 to Scheme 3.

[0178] Method 1: Traverse N observation bits and determine candidate positions at the positions of the N observation bits. For example, N observation bits are traversed, and a fourth threshold test block is successively selected based on each observation bit, and the number of test blocks that satisfy the verification condition in the fourth threshold test block is determined, and the positions of the fourth threshold test block in the data sequence may be consecutive or non-consecutive. The position of the observation bit corresponding to the maximum number of test blocks that satisfy the verification condition is determined as the candidate position, or the position of the observation bit corresponding to the minimum number of test blocks that do not satisfy the verification condition is determined as the candidate position. In this way, since N observation bits are traversed, the determined candidate position is most likely to be a synchronization position. In this implementation, the value of N may be the number of bits included in a single codeword.

[0179] Specifically, referring to the state diagram shown in FIG. 11, the {synchronization position determination state} includes {second counter reset partial state}, {third code word verification partial state}, and {candidate position selection partial state}, where the {second counter reset partial state} is a state in which the counter is reset, the {third code word verification partial state} is a state in which the test block is verified, and the {candidate position selection partial state} is a state in which a candidate position is selected.

[0180] In the {second counter reset substate}, the initial value of the [second codeword counter] and the initial value of the [first currently valid codeword counter] are set, one observation bit is selected from the received data sequence, and one test block is selected from the data sequence based on the current observation bit. For ease of explanation, the selected test block is called the second test block, the length of the second test block is equal to the codeword length, and one second test block simulates one codeword.

[0181] In response to selecting the second test block, a {third codeword verification substate} is entered.

[0182] The second test block is verified in {third codeword verification sub-state}. For the verification scheme, please refer to the above verification scheme of the first test block. The details will not be described again in this specification. In {third codeword verification sub-state}, the count value of [second codeword counter] is increased by W. In response to the second test block satisfying the verification condition, the count value of [first currently valid codeword counter] is increased by P, where both W and P are integers equal to or greater than 1.

[0183] In response to the count value of the [second codeword counter] being equal to the fourth threshold, the {candidate position selection substate} is entered. In this specification, the count value of the [second codeword counter] is equal to the fourth threshold. When W is equal to 1, it indicates that a verification has been performed on the second test block of the fourth threshold corresponding to the current observation bit, and it can be determined whether the position of the current observation bit is a candidate position. When W is greater than 1, it indicates that a verification has been performed on a plurality of second test blocks corresponding to the current observation bit, and it can be determined whether the position of the current observation bit is a candidate position.

[0184] In the {candidate position selection substate}, the value of the [observation bit count variable] is increased by one.

[0185] In the {candidate position selection substate}, in response to the count value of the [first currently valid codeword counter] being greater than the current value of the [maximum valid codeword number variable], the value of the [candidate synchronization position variable] is updated to the position of the currently observed bit, and the value of the [maximum valid codeword number variable] is updated to the count value of the [first currently valid codeword counter]. If the count value of the [first currently valid codeword counter] is less than the current value of the [maximum valid codeword number variable], the [candidate synchronization position variable] is not updated. If the count value of the [first currently valid codeword counter] is equal to the current value of the [maximum valid codeword number variable], the [candidate synchronization position variable] may or may not be updated.

[0186] In response to the value of the [number of observation bits variable] being less than N, the next observation bit after the current observation bit in the data sequence is verified. In this specification, the value of the [number of observation bits variable] being less than N indicates that the N observation bits have not been completely verified, the next observation bit should be selected, and the next observation bit is verified.

[0187] In response to the value of the number of observation bits variable being equal to N, the value of the candidate synchronization position variable is determined as a candidate position. Optionally, after the candidate position is determined, a first transition signal may be output. The first transition signal may be the candidate position or a signal that triggers entering the next state.

[0188] In response to the second test block not satisfying the verification condition, a value relationship between the count value of the [second codeword counter] and a fourth threshold is determined. In response to the count value of the [second codeword counter] being less than the fourth threshold, a next second test block is selected based on the current observed bit, and the next second test block is verified. In response to the count value of the [second codeword counter] being equal to the fourth threshold, a {candidate position selection substate} is entered.

[0189] Optionally, the {synchronization position determination state} further includes a {second synchronization lock initialization substate}.

[0190] Prior to entering the {second counter reset sub-state}, in response to detecting a [start signal], a {second synchronization lock initialization sub-state} is entered. In the {second synchronization lock initialization sub-state}, the value of the [observed bit count variable] is set to a fifth value, the fifth value may be 0, the value of the [candidate synchronization position variable] is set to a sixth value, the sixth value may be 0, and the value of the [maximum valid codeword number variable] is set to a seventh value, the seventh value may be 0.

[0191] Optionally, after these variables are set, the {second counter reset substate} is entered with an unconditional transition.

[0192] Optionally, the value of [second synchronization lock variable] is set to the first value in {second synchronization lock initialization sub-state}.

[0193] Optionally, in the {second synchronization lock initialization substate}, the value of the [current position number variable] is set to 0, etc., and in the {candidate position selection substate}, the value of the [current position number variable] is incremented by 1. In this way, the current position variable is recorded, so that the position of the current observation bit that has been traversed can be obtained.

[0194] Optionally, the value of [second codeword variable to be verified] is set to a third value in {second synchronization lock initialization sub-state}.

[0195] Optionally, the value of the [second codeword variable to be verified] is set to a fourth value in response to selecting one second test block from the data sequence based on the current observed bits, where the fourth value may be true or another value, and in response to the value of the [second codeword variable to be verified] being the fourth value, a {third codeword verification sub-state} is entered, and in the {third codeword verification sub-state} the value of the [second codeword variable to be verified] is set to the third value to verify the second test block.

[0196] Optionally, in response to the count value of the [second code word counter] being less than a fourth threshold and the value of the [second code word variable to be verified] being a fourth value, the {third code word verification substate} is re-entered, a next second test block is selected based on the current observed bits, and the next second test block is verified.

[0197] Optionally, the {synchronization position determination state} further includes a {second slip portion state}, which is a state in which an observation bit is slipped. In response to the value of the [observation bit number variable] being less than N, indicating that N observation bits have not been completely traversed, the {second slip portion state} is entered. The position of the next observation bit in the data sequence is slipped to the {second slip portion state}. In response to slipping to the next observation bit, the {second counter reset portion state} is entered, and the next observation bit is verified. Thus, in this manner, all observation bits may be traversed and the most likely candidate position may be selected, so that the selected candidate position can be more accurate.

[0198] After slipping to the next observation bit, the value of the [second slip done variable] is set to a second value, where the second value is true or another value. In response to the value of the [second slip done variable] being the second value, the {second counter reset partial state} is entered and the next observation bit is verified. The value of the [second slip done variable] is set to a first value in the {second counter reset partial state}, where the first value is false or another value.

[0199] In this specification, all observed bits are verified in the same process. For the observed bit selection method, please refer to the above description. The details will not be described again in this specification.

[0200] In the state diagram shown in FIG. 11, the {second sync lock initialization sub-state} is represented as FEC_LOCK_INIT_2, the {second counter reset sub-state} is represented as RESET_CNT_2, the {third code word verification sub-state} is represented as CW_CHECK_3, the {candidate position selection sub-state} is represented as SELECT_SYNC_LOCK, and the {second slip sub-state} is represented as SLIP_2. [The second synchronization lock variable] is represented as fec_cw_sync_2, the [second codeword variable to be verified] is represented as test_cw_2, the count value of the [second codeword counter] is represented as cw_cnt_2, the [second slip completion variable] is represented as slip_done_2, the [number of observed bits variable] is represented as location_num, the [candidate synchronization position variable] is represented as sync_location, the [maximum valid codeword number variable] is represented as max_valid_cw_cnt, the [current position number variable] is represented as current_location, the count value of the [first currently valid codeword counter] is represented as current_valid_cw_cnt, ``codeword valid'' is represented as valid_cw, and ``if'' indicates the case.

[0201] Method 2: Starting from the first observation bit, sequentially verify whether all observation bits meet the synchronization condition, the synchronization condition may be that at least a certain number of test blocks in a plurality of test blocks selected successively based on the observation bits meet the verification condition, the positions of the plurality of test blocks in the data sequence may be consecutive or discontinuous, the positions of the certain number of test blocks in the data sequence may be consecutive or discontinuous, and if a certain observation bit meets the synchronization condition, determine the position of the observation bit as a candidate location. In this way, the observation bit verification can be completed in advance, which can save resources for determining the candidate location.

[0202] Specifically, referring to the state diagram shown in FIG. 12, the {synchronization position determination state} includes {third counter reset partial state}, {fourth code word verification partial state}, and {second code word valid partial state}, where the {third counter reset partial state} is a state in which the counter is reset, the {fourth code word verification partial state} is a state in which the test block is verified, and the {second code word valid partial state} is a state entered when the test block satisfies the verification condition.

[0203] The {third counter reset substate} is set with the initial value of [third codeword counter] and the initial value of [first valid codeword counter]. One observed bit is selected from the data sequence, and one test block is selected from the data sequence based on the current observed bit. For ease of explanation, the selected test block is called the third test block. The length of the third test block is equal to the codeword length, and the start position of the third test block and the position of the observed bit are separated by an integer amount of the codeword length.

[0204] In response to selecting one third test block, the {fourth codeword verification sub-state} is entered. The third test block is verified in the {fourth codeword verification sub-state}. For the verification scheme, please refer to the verification scheme of the first test block.

[0205] In response to the third test block satisfying the verification condition, a {second codeword valid portion state} is entered. In the {second codeword valid portion state}, the count value of the [third codeword counter] is incremented by M and the count value of the [first valid codeword counter] is incremented by Q, where both M and Q are integers greater than or equal to 1.

[0206] If the count value of the [third codeword counter] is equal to or less than the fifth threshold, the position of the current observation bit is determined as a candidate position in response to the count value of the [first valid codeword counter] being equal to the sixth threshold. Optionally, after the candidate position is determined, a first transition signal may be output. The first transition signal may be the candidate position or may be a signal that triggers entering the next state. If M is equal to 1, the fifth threshold is the number of third test blocks selected based on the observation bit. If M is greater than 1, the fifth threshold is M times the number of third test blocks selected based on the observation bit. If Q is equal to 1, the sixth threshold is the number of third test blocks that satisfy the verification condition. If Q is greater than 1, the sixth threshold is Q times the number of third test blocks that satisfy the verification condition. The fifth threshold and the sixth threshold may be set based on empirical values ​​or may be set based on simulation analysis results.

[0207] Optionally, in the {second code word valid portion state}, in response to the count value of the [third code word counter] being equal to the fifth threshold and the count value of the [first valid code word counter] being less than the sixth threshold, indicating that the third test block of the fifth threshold does not include a third test block of the sixth threshold that satisfies the verification condition, and a next observed bit selected from the data sequence is verified.

[0208] In response to the count value of the [third codeword counter] being less than the fifth threshold and the count value of the [first valid codeword counter] being less than the sixth threshold in the {second codeword valid portion state}, indicating that the fifth threshold third test block is not completely verified, the {fourth codeword verification portion state} is re-entered and a next third test block selected based on the current observed bits is verified.

[0209] Optionally, the value of the [second code word valid variable] is set to a second value in response to a third test block satisfying a verification condition, and the {second code word valid portion state} is entered in response to the value of the [second code word valid variable] being the second value.

[0210] Optionally, the {synchronization position determination state} further includes a {first code word invalid portion state}, which is a state entered when the test block does not satisfy the verification condition. In response to the third test block not satisfying the verification condition, the {first code word invalid portion state} is entered, and in the {first code word invalid portion state}, the count value of the [third code word counter] is increased by M.

[0211] A next observed bit selected from the data sequence is verified in response to the count value of the third codeword counter being equal to the fifth threshold. In response to the count value of the third codeword counter being less than the fifth threshold, indicating that the fifth threshold third test block is not fully verified, the fourth codeword verification substate is re-entered and a next third test block selected based on the current observed bit is verified.

[0212] Optionally, the value of the [second code word valid variable] is set to a first value in response to the third test block not satisfying the verification condition, and a {first code word invalid portion state} is entered in response to the value of the [second code word valid variable] being the first value.

[0213] Optionally, the {synchronization position determination state} further includes a {third slip portion state}, which is a state in which the next observation bit is slipped. In response to the count value of the [third codeword counter] being equal to the fifth threshold, the {third slip portion state} enters the {first codeword invalid portion state}. Alternatively, in response to the count value of the [third codeword counter] being equal to the fifth threshold and the count value of the [first valid codeword counter] being less than the sixth threshold, the {third slip portion state} enters the {second codeword valid portion state}. The next observation bit is slipped to the {third slip portion state}. In response to slipping the next observation bit, the {third counter reset portion state} is re-entered and the next observation bit is verified.

[0214] After slipping to the next observation bit, the value of the [third slip done variable] is set to a second value, the second value being true or another value. In response to the value of the [third slip done variable] being the second value, the {third counter reset partial state} is entered and the next observation bit is verified. The value of the [third slip done variable] is set to a first value in the {third counter reset partial state}, the first value being false or another value.

[0215] Optionally, the {sync position determination state} further includes a {third sync lock initialization sub-state}, the {third sync lock initialization sub-state} being an initialization state. The {third sync lock initialization sub-state} is entered in response to detecting a start signal prior to entering the {third counter reset sub-state}.

[0216] In the {third synchronization lock initialization sub-state}, the value of the [third synchronization lock variable] is set to a first value, and the value of the [third codeword variable to be verified] is set to a third value, where the third value is false or another value. After the processing is completed, the {third counter reset sub-state} is entered with an unconditional transition. The value of the [third codeword variable to be verified] is set to a fourth value after one third test block is selected based on the current observation bit, where the fourth value is true or another value.

[0217] In the {third counter reset sub-state}, in response to the value of [third code word variable to be verified] being a fourth value, a {fourth code word verification sub-state} is entered.

[0218] In the {second code word valid partial state}, in response to the value of the [third code word variable to be verified] being a fourth value, and in response to the count value of the [third code word counter] being less than a fifth threshold and the count value of the [first valid code word counter] being less than a sixth threshold, the {fourth code word verification partial state} is re-entered and the next third test block selected based on the current observation bits is verified.

[0219] In the {first code word invalid partial state}, in response to the value of the [third code word variable to be verified] being a fourth value and in response to the count value of the [third code word counter] being less than a fifth threshold, the {fourth code word verification partial state} is re-entered and the next third test block selected based on the current observed bits is verified.

[0220] In the procedure shown in Figure 12, all observed bits are verified in the same process. For the observed bit selection method, please refer to the above description. The details will not be described again in this specification.

[0221] Method 3: Starting from the first observation bit, sequentially verify whether all observation bits satisfy a synchronization condition, where the synchronization condition may be that a plurality of test blocks selected successively based on the observation bits satisfy the verification condition, and the positions of the plurality of test blocks in the data sequence may be successive or discontinuous, and if a particular observation bit satisfies the synchronization condition, determine the position of the observation bit as a candidate location. In this way, the observation bit verification can be completed in advance, which can save resources for determining the candidate location. This implementation form is a special example of method 2.

[0222] Specifically, referring to the state diagram shown in FIG. 13, the {synchronization position determination state} includes {third counter reset partial state}, {fourth code word verification partial state}, and {second code word valid partial state}.

[0223] The initial value of the third codeword counter is set to {third counter reset partial state}. One observation bit is selected from the data sequence, and one test block is selected from the data sequence based on the current observation bit. For ease of explanation, the selected test block is called the third test block.

[0224] In response to selecting one third test block, a {fourth codeword verification sub-state} is entered. The third test block is verified in the {fourth codeword verification sub-state}. For example, the third test block is verified based on an eigenvalue of the third test block.

[0225] In response to the third test block satisfying the verification condition, the {second codeword valid portion state} is entered. In the {second codeword valid portion state}, the count value of the [third codeword counter] is incremented by M.

[0226] The position of the current observation bit is determined as a candidate position in response to the count value of the third codeword counter being equal to the fifth threshold. Optionally, after the candidate position is determined, a first transition signal may be output. The first transition signal may be a candidate position or a signal that triggers entering a next state.

[0227] A next third test block selected based on the currently observed bits is verified in response to the count value of the third codeword counter being less than a fifth threshold.

[0228] In response to the third test block not satisfying the verification condition, a {third slip sub-state} is entered. The next observation bit is slipped into the {third slip sub-state}. In response to slipping the next observation bit, a {third counter reset sub-state} is entered and the next observation bit is verified.

[0229] Optionally, the value of the [second code word valid variable] is set to a second value in response to the third test block satisfying the verification condition, and the {second code word valid part state} is entered in response to the value of the [second code word valid variable] being the second value. For a specific slip description, please refer to the description of FIG. 12.

[0230] Optionally, the {synchronization position determination state} further includes {third synchronization lock initialization substate}. For explanation, please refer to the above description. Details will not be described again in this specification.

[0231] In the state diagrams shown in Figures 12 and 13, the {third counter reset sub-state} is represented as RESET_CNT_3, the {fourth codeword verification sub-state} is represented as CW_CHECK_4, the {third slip sub-state} is represented as SLIP_3, the {third sync lock initialization sub-state} is represented as FEC_LOCK_INIT_3, the {first codeword invalid sub-state} is represented as INVALID_CW_1, and the {second codeword valid sub-state} is represented as VALID_CW_2. The [third synchronization lock variable] is represented as fec_cw_sync_3, the [third code word variable to be verified] is represented as test_cw_3, the count value of the [third code word counter] is represented as cw_cnt_3, the [third slip completed variable] is represented as slip_done_3, the count value of the [first valid code word counter] is represented as valid_cw_cnt_1, the value of the [second code word valid variable] when set to the second value is represented as valid_cw_2, and the value of the [second code word valid variable] when set to the first value is represented as !valid_cw_2.

[0232] For example, after the candidate locations are selected, a synchronization location is determined based on the candidate locations.

[0233] In a first implementation form of determining a synchronization position based on a candidate position, the candidate position is determined as a synchronization position. Specifically, the {synchronization position determination state} further includes {third synchronization lock success partial state}. When a candidate position is determined by method 1, the {third synchronization lock success partial state} is entered in response to the value of the [observation bit number variable] being equal to N. When a candidate position is determined by method 2, the {third synchronization lock success partial state} is entered in response to the count value of the [second valid code word counter] being equal to a sixth threshold. When a candidate position is determined by method 3, the {third synchronization lock success partial state} is entered in response to the count value of the [third code word counter] being equal to a fifth threshold. In the {third synchronization lock success partial state}, the value of the [synchronization lock variable] is set to the second value. In the first implementation form of determining a synchronization position based on a candidate position, the candidate position is directly determined as a synchronization position, so that resources for determining a synchronization position can be saved.

[0234] In a second implementation of determining a synchronization position based on a candidate position, the candidate position is verified, and the candidate position is determined as a synchronization position after successful verification.

[0235] Specifically, in one implementation, referring to the state diagram shown in Figure 14, multiple test blocks are consecutively selected based on the candidate position. For ease of explanation, the test block selected in this implementation is called the fourth test block. If the multiple test blocks all meet the verification condition, the candidate position is determined as a synchronization position, and the positions of the multiple test blocks in the data sequence may be consecutive or non-consecutive.

[0236] The {synchronization position determination state} further includes {fourth counter reset partial state} and {fifth code word verification partial state}, where {fourth counter reset partial state} is a state in which the counter is reset and {fifth code word verification partial state} is a state in which the test block is verified.

[0237] The initial value of the [fourth codeword counter] is set to {fourth counter reset sub-state}. For a candidate position, the [fourth codeword counter] is used to record the number of test blocks selected based on the candidate position. A fourth test block is selected from the data sequence based on the candidate position. In response to selecting one fourth test block, {fifth codeword verification sub-state} is entered.

[0238] The fourth test block is verified in {the fifth codeword verification substate}. For the verification scheme, please refer to the above verification scheme of the first test block. The details will not be described again in this specification.

[0239] In response to the fourth test block satisfying the verification condition, the count value of the [fourth codeword counter] is incremented by R, where R is an integer greater than or equal to 1. The candidate position is determined as a synchronization position in response to the count value of the [fourth codeword counter] being equal to a seventh threshold value.

[0240] When R is equal to 1, the seventh threshold is the number of fourth test blocks selected based on the candidate positions. When R is greater than 1, the seventh threshold is R times the number of fourth test blocks selected based on the candidate positions. The seventh threshold may be set based on experience or based on a simulation analysis result.

[0241] Optionally, the synchronization position determination state further includes a {third codeword valid portion state}, which is a state entered when the test block satisfies a verification condition. In response to the fourth test block satisfying the verification condition, the {third codeword valid portion state} is entered. In the {third codeword valid portion state}, the count value of the [fourth codeword counter] is increased by R. The candidate position is determined as a synchronization position in response to the count value of the [fourth codeword counter] being equal to a seventh threshold. In response to the count value of the [fourth codeword counter] being less than the seventh threshold, the {fifth codeword verification portion state} is re-entered and a next fourth test block selected based on the candidate position is verified.

[0242] Optionally, the candidate location is reselected in response to the fourth test block failing the verification condition.

[0243] Optionally, the value of the [third code word valid variable] is set to a second value, the second value being true or another value, in response to the fourth test block satisfying a verification condition. In response to the value of the [third code word valid variable] being the second value, a {third code word valid portion state} is entered.

[0244] The value of the [third code word valid variable] is set to a first value, the first value being false or another value, in response to the fourth test block not satisfying the verification condition. The candidate location is reselected in response to the value of the [third code word valid variable] being the first value.

[0245] Optionally, the {synchronization position determination state} further includes a {first resume portion state}. In response to the value of the [third code word valid variable] being a first value, the {first resume portion state} is entered. In the {first resume portion state}, the value of the [resynchronization lock variable] is set to a second value. In response to the value of the [resynchronization lock variable] being the second value, it is determined that a start signal has been detected and a candidate position is reselected.

[0246] Optionally, the {synchronization position determination state} further includes a {third synchronization lock success partial state}, and the {third synchronization lock success partial state} is a state in which a synchronization position is determined. In response to the count value of the [fourth codeword counter] being equal to the seventh threshold, the {third synchronization lock success partial state} is entered. In the {third synchronization lock success partial state}, the value of the [third synchronization lock variable] is set to a second value. In response to the value of the [third synchronization lock variable] being the second value, the value of the [third synchronization lock variable] being the second value may indicate that the candidate position is a synchronization position, and an unconditional transition may be made to output a second transition signal. The second transition signal is used to trigger entering the {lock loss detection state}, and the second transition signal may be a synchronization position or another trigger signal.

[0247] Optionally, the value of the [fourth codeword variable to be verified] is set to a second value in response to selecting one fourth test block based on the synchronization position, and the {fifth codeword verification sub-state} is entered in response to the value of the [fourth codeword variable to be verified] being the second value. Alternatively, the {fifth codeword verification sub-state} is entered in response to the value of the [fourth codeword variable to be verified] being the second value and the count value of the [fourth codeword counter] being less than a seventh threshold. In the {fifth codeword verification sub-state}, the value of the [fourth codeword variable to be verified] is set to the first value.

[0248] In this manner, after a candidate position is determined, it continues to be further determined whether the candidate position is a synchronous position, thereby further improving the accuracy of the synchronous position.

[0249] In the state diagram shown in FIG. 14, the {third sync lock success sub-state} is represented as FEC_LOCK_GOOD_3, the {fourth counter reset sub-state} is represented as RESET_CNT_4, the {fifth codeword verification sub-state} is represented as CW_CHECK_5, the {third codeword valid sub-state} is represented as VALID_CW_3, and the {first restart sub-state} is represented as RESTART_1. [The third synchronization lock variable] is represented as fec_cw_sync_3, the [fourth code word variable to be verified] is represented as test_cw_4, the count value of the [fourth code word counter] is represented as cw_cnt_4, the [resynchronization lock variable] is represented as restart_fec_lock, when the value of the [third code word valid variable] is the first value, it is represented as !valid_cw_3, and when the value of the [third code word valid variable] is the second value, it is represented as valid_cw_3.

[0250] In another implementation, the multiple test blocks are selected consecutively based on the candidate position. For ease of explanation, the selected test block in this implementation is called the fifth test block. If a certain number of test blocks in the multiple test blocks meet the verification condition, the candidate position is determined as a synchronization position, and the positions of the multiple test blocks in the data sequence may be consecutive or discontinuous, and the positions of the certain number of test blocks in the data sequence may be consecutive or discontinuous.

[0251] Specifically, referring to the state diagram shown in FIG. 15, the {synchronization position determination state} further includes {sixth counter reset partial state}, {seventh code word verification partial state}, and {fifth code word valid partial state}, where the {sixth counter reset partial state} is a state in which the counter is reset, the {seventh code word verification partial state} is a state in which the test block is verified, and the {fifth code word valid partial state} is a state entered when the test block satisfies the verification condition.

[0252] In the {6th counter reset sub-state}, an initial value of the [6th codeword counter] and an initial value of the [4th valid codeword counter] are set. For a candidate position, the [6th codeword counter] is used to record the number of test blocks selected based on the candidate position, and the [4th valid codeword counter] is used to record the number of test blocks that satisfy the verification condition. One fifth test block is selected from the data sequence based on the candidate position. In response to selecting one fifth test block, the {7th codeword verification sub-state} is entered.

[0253] Optionally, in the {sixth counter reset sub-state}, the value of the [fourth slip completed variable] may be further set to the first value to indicate that a slip does not currently need to be performed.

[0254] The fifth test block is verified in the {seventh codeword verification substate}. For the verification scheme, please refer to the above verification scheme of the first test block. The details will not be described again in this specification.

[0255] In response to the fifth test block satisfying the verification condition, a {fifth codeword valid portion state} is entered. In the {fifth codeword valid portion state}, the count value of the [sixth codeword counter] is incremented by E, where E is an integer equal to or greater than 1, and the count value of the [fourth valid codeword counter] is incremented by F, where F is an integer equal to or greater than 1. If the count value of the [sixth codeword counter] is less than or equal to a ninth threshold, the candidate position is determined as a synchronization position in response to the count value of the [fourth valid codeword counter] being equal to a tenth threshold. The candidate position is reselected in response to the count value of the [sixth codeword counter] being equal to the ninth threshold and the count value of the [fourth valid codeword counter] being less than the tenth threshold. In response to the count value of the [sixth codeword counter] being less than the ninth threshold and the count value of the [fourth valid codeword counter] being less than the tenth threshold, the {seventh codeword verification substate} is re-entered, and the next fifth test block selected based on the candidate position continues to be verified. If E is equal to 1, the ninth threshold is the number of fifth test blocks selected based on the candidate position. If E is greater than 1, the ninth threshold is E times the number of fifth test blocks selected based on the candidate position. If F is equal to 1, the tenth threshold is the number of fifth test blocks that satisfy the verification condition. If F is greater than 1, the tenth threshold is F times the number of fifth test blocks that satisfy the verification condition. The ninth and tenth thresholds may be set based on empirical values ​​or may be set based on simulation analysis results.

[0256] Optionally, the {synchronization position determination state} further includes a {third codeword invalid portion state}, which is a state entered when the test block does not satisfy the verification condition. In response to the fifth test block not satisfying the verification condition, the {third codeword invalid portion state} is entered. In the {third codeword invalid portion state}, the count value of the [sixth codeword counter] is increased by E. The candidate position is re-determined in response to the count value of the [sixth codeword counter] being equal to the ninth threshold. In response to the count value of the [sixth codeword counter] being less than the ninth threshold, the {seventh codeword verification portion state} is re-entered, and the next fifth test block selected based on the candidate position continues to be verified.

[0257] Optionally, the value of the [fourth code word valid variable] is set to a second value in response to the fifth test block satisfying a verification condition, and the {fifth code word valid portion state} is entered in response to the value of the [fourth code word valid variable] being the second value.

[0258] The value of the [fourth code word valid variable] is set to a first value in response to the fifth test block not satisfying a verification condition, and a {third code word invalid portion state} is entered in response to the value of the [fourth code word valid variable] being the first value.

[0259] Optionally, the {synchronization position determination state} further includes a {second restart part state}, and the {second restart part state} is a state in which a signal for re-determining the candidate position is output. The {second restart part state} enters the {third code word invalid part state} in response to the count value of the [sixth code word counter] being equal to a ninth threshold. Alternatively, the {second restart part state} enters the {fifth code word valid part state} in response to the count value of the [sixth code word counter] being equal to a ninth threshold and the count value of the [fourth valid code word counter] being less than a tenth threshold. In the {second restart part state}, the value of the [resynchronization lock variable] is set to a second value. In response to the value of the [resynchronization lock variable] being set to the second value, it is determined that a start signal has been detected and the candidate position is reselected.

[0260] Optionally, the {synchronization position determination state} further includes a {fourth synchronization lock success partial state}, which is a state in which synchronization is completed. In response to the count value of the [fourth valid codeword counter] being equal to the tenth threshold, the {fourth synchronization lock success partial state} is entered. In the {fourth synchronization lock success partial state}, the value of the [fourth synchronization lock variable] is set to a second value. The value of the [fourth synchronization lock variable] being the second value indicates that the candidate position is a synchronization position, and an unconditional transition may be made to output a second transition signal. The second transition signal is used to trigger entering the {lock loss detection state}.

[0261] Optionally, the value of the [fifth codeword variable to be verified] is set to a second value in response to selecting one fifth test block based on the candidate location, and the {seventh codeword verification sub-state} is entered in response to the value of the [fifth codeword variable to be verified] being the second value. Alternatively, the {seventh codeword verification sub-state} is re-entered in response to the value of the [fifth codeword variable to be verified] being the second value and the count value of the [sixth codeword counter] being less than the ninth threshold. Alternatively, the {seventh codeword verification sub-state} is re-entered in response to the value of the [fifth codeword variable to be verified] being the second value, the count value of the [sixth codeword counter] being less than the ninth threshold, and the count value of the [fourth valid codeword counter] being less than the tenth threshold. In the {seventh codeword verification sub-state}, the value of the [fifth codeword variable to be verified] is set to the first value.

[0262] In the state diagram shown in FIG. 15, the {sixth counter reset sub-state} is represented as RESET_CNT_6, the {seventh codeword verification sub-state} is represented as CW_CHECK_7, the {fourth sync lock successful sub-state} is represented as FEC_LOCK_GOOD_4, the {fifth codeword valid sub-state} is represented as VALID_CW_5, the {third codeword invalid sub-state} is represented as INVALID_CW_3, and the {second restart sub-state} is represented as RESTART_2. The [fourth synchronization lock variable] is represented as fec_cw_sync_4, the [fifth code word variable to be verified] is represented as test_cw_5, the count value of the [sixth code word counter] is represented as cw_cnt_6, the count value of the [fourth valid code word counter] is represented as valid_cw_cnt_4, the [resynchronization lock variable] is represented as restart_fec_lock, and when the value of the [fourth code word valid variable] is the first value, it corresponds to !valid_cw_4, and when the value of the [fourth code word valid variable] is the second value, it corresponds to valid_cw_4.

[0263] In the state diagrams shown in Figures 9 and 11 to 13, the test block selected based on the observed bits belongs to the first subsequence. In the state diagrams shown in Figures 14 and 15, the test block selected based on the candidate position belongs to the third subsequence, and both the first subsequence and the third subsequence belong to the received sequence, and the third subsequence is located after the first subsequence. In addition, the first subsequence and the third subsequence may alternatively partially overlap.

[0264] In another implementation, a ninth threshold fifth test block may be successively selected based on the candidate position, the ninth threshold fifth test block is traversed, and a tenth threshold fifth test block within the ninth threshold fifth test block satisfies the verification condition, and the candidate position is determined as a synchronization position.

[0265] For example, in step 804, enter {lock loss detection state} and perform lock loss detection. There are several ways to perform lock loss detection. The following provides three possible ways:

[0266] Scheme 1: In the {lock loss detection state}, verify the multiple code words selected based on the synchronization position, and re-enter the synchronization position determination state in response to the number of code words among the multiple code words that do not meet the verification condition reaching a certain value. For example, the target number of code words is continuously selected based on the synchronization position, and if the eighth threshold code words in the target number of code words do not meet the verification condition, the synchronization position is determined to be incorrect, and the synchronization position is updated, otherwise, the synchronization position is determined to be correct. If the synchronization position is correct, the number of code words that do not meet the verification condition is relatively small. Therefore, it is determined whether the number of code words that do not meet the verification condition reaches the eighth threshold, and it can be more quickly determined whether the synchronization position is incorrect. In this specification, the target number of code words may be continuous or discontinuous in the data sequence.

[0267] Specifically, referring to the state diagram shown in FIG. 16, the {lock loss detection state} includes {fifth counter reset sub-state} and {sixth code word verification sub-state}, where the {fifth counter reset sub-state} is the state in which the counter is reset and the {sixth code word verification sub-state} is the state in which the code word is verified.

[0268] After the synchronization position is determined, the fifth counter reset substate is entered. In the fifth counter reset substate, the initial values ​​of the fifth codeword counter and the second invalid codeword counter are set. In this specification, both initial values ​​may be 0.

[0269] A codeword is selected from the data sequence based on the synchronization position. For ease of explanation, the codeword selected based on the synchronization position is referred to as a second codeword. Optionally, a codeword is selected from a fourth subsequence of the data sequence based on the synchronization position. The fourth subsequence is different from both the first subsequence and the third subsequence described above, and the fourth subsequence is located after the third subsequence.

[0270] In response to selecting one second code word, enter {sixth code word verification sub-state}. The second code word is verified in {sixth code word verification sub-state}. The verification method of the second code word is the same as that of the first code word. Details are not described again in this specification.

[0271] In response to the second codeword not satisfying the verification condition, the count value of the [fifth codeword counter] is incremented by one and the count value of the [second invalid codeword counter] is incremented by one. A next verification is performed on the synchronization position in response to the count value of the [fifth codeword counter] equaling the target value and the count value of the [second invalid codeword counter] being less than the eighth threshold. In this specification, the count value of the [fifth codeword counter] equaling the target value and the count value of the [second invalid codeword counter] being less than the eighth threshold indicate that the number of codewords that do not satisfy the verification condition among the target number of codewords is relatively small and the synchronization position is correct.

[0272] The synchronization position of the data sequence is re-determined in response to the count value of the second invalid codeword counter being equal to an eighth threshold value, where, as used herein, the count value of the second invalid codeword counter being equal to the eighth threshold value indicates that a relatively large number of codewords do not satisfy the verification condition, and thus the synchronization position is inaccurate.

[0273] Optionally, the {lock loss detection state} further includes a {second code word invalid portion state}, which is a state entered when the code word does not satisfy the verification condition. In response to the second code word not satisfying the verification condition, the {second code word invalid portion state} is entered. In the {second code word invalid portion state}, the count value of the [fifth code word counter] is increased by 1, and the count value of the [second invalid code word counter] is increased by 1.

[0274] Optionally, in the {second code word invalid partial state}, in response to the count value of the [fifth code word counter] being less than the target value and the count value of the [first invalid code word counter] being less than the eighth threshold, the {sixth code word verification partial state} is re-entered and the next second code word selected based on the synchronization position is verified.

[0275] Optionally, the {lock loss detection state} further includes a {fourth code word valid part state}, which is a state entered when the code word satisfies a verification condition. In response to the second code word satisfying the verification condition, the {fourth code word valid part state} is entered. In the {fourth code word valid part state}, the count value of the [fifth code word counter] is increased by one. A next verification is performed on the synchronization position in response to the count value of the [fifth code word counter] being equal to the target value. A next second code word selected based on the synchronization position is verified in response to the count value of the [fifth code word counter] being less than the target value.

[0276] Optionally, the value of the [fifth code word valid variable] is set to a second value in response to the second code word satisfying the verification condition, and the {fourth code word valid portion state} is entered in response to the value of the [fifth code word valid variable] being the second value.

[0277] The value of the [fifth code word valid variable] is set to a first value in response to the second code word satisfying a verification condition, and a {second code word invalid portion state} is entered in response to the value of the [fifth code word valid variable] being the first value.

[0278] Optionally, the value of the [sixth codeword variable to be verified] is set to a second value in response to selecting one second codeword based on the synchronization position, and the {sixth codeword verification sub-state} is entered in response to the value of the [sixth codeword variable to be verified] being the second value. Alternatively, the {sixth codeword verification sub-state} re-enters the {fourth codeword valid sub-state} in response to the value of the [sixth codeword variable to be verified] being the second value and the count value of the [fifth codeword counter] being less than the target value. Alternatively, in the {second codeword invalid sub-state}, the {sixth codeword verification sub-state} is re-entered in response to the value of the [sixth codeword variable to be verified] being the second value, the count value of the [fifth codeword counter] being less than the target value, and the count value of the [second invalid codeword counter] being less than the eighth threshold. In the {sixth codeword verification sub-state}, the value of the [sixth codeword variable to be verified] is set to the first value.

[0279] Optionally, in response to the value of the [second synchronization lock parameter] being the second value, the {fifth counter reset sub-state} is entered. Alternatively, in response to the value of the [third synchronization lock parameter] being the second value, the {fifth counter reset sub-state} is entered. In response to the value of the [fourth synchronization lock parameter] being the second value, the {fifth counter reset sub-state} is entered. Alternatively, in response to a second transition signal, the second transition signal being a signal output when position determination is completed.

[0280] Optionally, in response to the count value of the [second invalid code word counter] being equal to an eighth threshold, a third transition signal is output, the third transition signal indicating re-determining the synchronization position of the data sequence.

[0281] Optionally, the lock loss detection state further includes a {third restart partial state}, which is a state in which a signal for re-determining the synchronization position is output. The {third restart partial state} is entered in response to the count value of the [first invalid codeword counter] being equal to an eighth threshold value. In the {third restart partial state}, the value of the [resynchronization lock variable] is set to a second value. The value of the [resynchronization lock variable] being the second value indicates that the synchronization position is re-determined.

[0282] In the state diagram shown in Figure 16, the {fifth counter reset substate} is represented as RESET_CNT_5, the {sixth codeword verification substate} is represented as CW_CHECK_6, the {fourth codeword valid substate} is represented as VALID_CW_4, and the {second codeword invalid substate} is represented as INVALID_CW_2. The [sixth codeword variable to be verified] is represented as test_cw_6, the count value of the [fifth codeword counter] is represented as cw_cnt_5, the count value of the [second invalid codeword counter] is represented as invalid_cw_cnt_2, the [resynchronization lock variable] is represented as restart_fec_lock, and when the value of the [fifth codeword valid variable] is a first value, it corresponds to !valid_cw_5, and when the value of the [fifth codeword valid variable] is a second value, it corresponds to valid_cw_5.

[0283] Method 2: Continuously select the codeword of the target number based on the synchronization position, traverse the codeword of the target number, and if the codeword of the 11th threshold in the codeword of the target number satisfies the verification condition, determine that the synchronization position is correct; otherwise, determine that the synchronization position is incorrect, and the 11th threshold is greater than the 8th threshold.

[0284] Specifically, referring to the state diagram shown in FIG. 17, the {lock loss detection state} includes {seventh counter reset sub-state} and {eighth code word verification sub-state}, where the {seventh counter reset sub-state} is the state in which the counter is reset and the {eighth code word verification sub-state} is the state in which the code word is verified.

[0285] After the synchronization position is determined, the seventh counter reset substate is entered. In the seventh counter reset substate, the initial values ​​of the seventh codeword counter and the fifth valid codeword counter are set. In this specification, both initial values ​​may be 0.

[0286] A codeword is selected from the data sequence based on the synchronization position. For ease of explanation, the codeword selected based on the synchronization position is referred to as a second codeword. Optionally, a codeword is selected from a fourth subsequence of the data sequence based on the synchronization position. The fourth subsequence is different from both the first subsequence and the third subsequence described above, and the fourth subsequence is located after the third subsequence.

[0287] In response to selecting one second code word, enter the {8th code word verification sub-state}. In the {8th code word verification sub-state}, the second code word is verified and the count value of the [7th code word counter] is increased by 1. The verification method of the second code word is the same as that of the first test block. Details will not be described again in this specification.

[0288] In the {eighth codeword verification sub-state}, the count value of the [fifth valid codeword counter] is incremented by one in response to the second codeword satisfying the verification condition.

[0289] The next second code word selected based on the synchronization position is verified in response to the count value of the [seventh code word counter] being less than the target value.

[0290] The next test continues to be performed for the synchronization position in response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth valid codeword counter] being greater than or equal to the eleventh threshold value.

[0291] The third transition signal is output in response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth valid codeword counter] being less than the eleventh threshold, and the third transition signal indicates re-determining the synchronization position within the data sequence. Alternatively, the lock loss detection state further includes a {fourth restart sub-state}. In response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth valid codeword counter] being less than the eleventh threshold, the {fourth restart sub-state} is re-entered. In the {fourth restart sub-state}, the value of the [resynchronization lock variable] is set to a second value. The value of the [resynchronization lock variable] being the second value indicates that the synchronization position is re-determined.

[0292] Optionally, the value of the [7th codeword variable to be verified] is set to a second value (e.g., true) in response to selecting one second codeword based on the synchronization position, and the {8th codeword verification sub-state} is entered in response to the value of the [7th codeword variable to be verified] being the second value. Alternatively, the {8th codeword verification sub-state} is re-entered in response to the value of the [7th codeword variable to be verified] being the second value and the count value of the [7th codeword counter] being less than the target value. In the {8th codeword verification sub-state}, the value of the [7th codeword variable to be verified] is set to a first value (e.g., false).

[0293] In the state diagram shown in Fig. 17, {the seventh counter reset substate} is represented as RESET_CNT_7, {the eighth codeword verification substate} is represented as CW_CHECK_8, [the seventh codeword variable to be verified] is represented as test_cw_7, the count value of [the seventh codeword counter] is represented as cw_cnt_7, the count value of [the fifth valid codeword counter] is represented as valid_cw_cnt_5, the second codeword satisfies the verification condition is represented as valid_cw, and "if" indicates the case.

[0294] Method 3: Successively verify the codewords selected based on the synchronization position, and determine the number of codewords that meet the verification condition until the maximum number of codewords reaches a target value. In this process, when the number of codewords that meet the verification condition reaches an eleventh threshold, the synchronization position is determined to be correct.

[0295] It should be noted that the above-mentioned synchronization position determination process and lock loss detection process may be combined in any manner. In addition, the above-mentioned synchronization position determination and lock loss detection may be implemented using the same state machine. Alternatively, two partial state machines, namely partial state machine 1 and partial state machine 2, are used for the implementation. Partial state machine 1 is used to implement the synchronization position determination process, and partial state machine 2 is used to implement the lock loss detection process. Alternatively, three partial state machines, namely partial state machine 3, partial state machine 4, and partial state machine 5, are used for the implementation. Partial state machine 3 is used to implement the candidate position determination process, partial state machine 4 is used to implement the synchronization position determination process, and partial state machine 5 is used to implement the lock loss detection process.

[0296] For example, Figure 18 is a state diagram in which one state machine realizes the synchronization position determination process. For the explanation of the state diagram shown in Figure 18, please refer to the explanation of the state diagram shown in Figure 13 and Figure 14. Compared with Figure 13 and Figure 14, {third synchronization lock success partial state} is added, which is represented as (FEC_LOCK_GOOD_3), and {first resume partial state} is replaced with {third slip partial state}.

[0297] Please note that the state diagram in this embodiment of the application uses an example where the increment value of the register variable is 1.

[0298] The configuration of the codeword synchronization device will be described below.

[0299] Figure 19 is a schematic diagram of the structure of a codeword synchronization device according to an exemplary embodiment of the present application. The device may be implemented as a part or whole of the device through a combination of hardware. The device provided in this embodiment of the present application can implement the procedure of Figure 8 of the embodiment of the present application. The device includes a synchronization position determination module 1910 and a lock loss detection module 1920.

[0300] The synchronous position determination module 1910 includes: in response to a start signal, entering a synchronous position determination state; In the synchronization position determination state, a synchronization position in the received data sequence is determined, the synchronization position indicating the starting position of a codeword in the data sequence, which can be specifically used to implement the synchronization position determination function in steps 801 and 802 and to perform the implicit steps included in steps 801 and 802. It is configured as follows.

[0301] The loss of lock detection module 1920, in response to determining the synchronization position, enters a loss of lock detection state; In the lock loss detection state, verify the selected codewords based on the synchronization position, and in response to a verification failure, re-enter the synchronization position determination state, which may be specifically used to implement the lock loss detection function in steps 803 and 804 and to perform the implicit steps included in steps 803 and 804. It is configured as follows.

[0302] In a possible implementation, the synchronization position determination module 1910 includes: Select N observed bits from the data sequence, and determine a synchronization position based on the positions of the N observed bits in a synchronization position determination state, where N is an integer equal to or greater than 1. It is configured as follows.

[0303] In a possible implementation, the synchronization position determination module 1910 is configured to select a synchronization position from the positions of the N observed bits.

[0304] In a possible implementation, the synchronization position determination state includes a first counter reset substate and a first codeword verification substate.

[0305] The synchronous position determination module 1910 includes: setting an initial value of a first codeword counter in a first counter reset substate and selecting one observation bit from the data sequence; entering a first codeword verification substate in response to selecting a first test block from the data sequence based on the currently observed bit, the first test block having a length equal to the codeword length and a start position of the first test block and a position of the currently observed bit separated by an integer amount of the codeword length; verifying a first test block in a first codeword verification sub-state; incrementing a count value of a first codeword counter by X in response to the first test block satisfying a verification condition, where X is an integer greater than or equal to 1; determining a position of a currently observed bit as a synchronization position in response to the count value of the first codeword counter being equal to a first threshold value; It is configured as follows.

[0306] In a possible implementation, the synchronization position determination module 1910 includes: In response to the count value of the first codeword counter being less than the first threshold, re-entering the first codeword verification substate to verify a next first test block selected based on the current observed bits. The method is further configured as follows.

[0307] In a possible implementation, the synchronization position determination state further includes a first codeword valid portion state.

[0308] The synchronization position determination module 1910 enters a first codeword valid portion state in response to a first test block satisfying a verification condition; In the first code word valid portion state, the count value of the first code word counter is increased by X. The method is further configured as follows.

[0309] In a possible implementation, the synchronization position determination module 1910 includes: In response to the first test block not satisfying the verification condition, verifying a selected next observed bit from the data sequence. The method is further configured as follows.

[0310] In a possible implementation, the synchronization position determination state further includes a first slip portion state.

[0311] The synchronization position determination module 1910 enters a first slip portion state in response to a first test block not satisfying a verification condition; slipping to the next observed bit in a first slip portion state; In response to slipping to the next observation bit, re-entering the first counter reset substate to examine the next observation bit. The method is further configured as follows.

[0312] In a possible implementation, the synchronous position determination state further includes a first synchronous lock initialization substate.

[0313] The synchronization position determination module 1910 is further configured to set a value of a first synchronization lock variable to a first value in a first synchronization lock initialization sub-state before setting an initial value of the first codeword counter in the first counter reset sub-state.

[0314] In a possible implementation, the sync position determination state further includes a first sync lock success substate.

[0315] The synchronous position determination module 1910 includes: enter a first sync lock success substate in response to the count value of the first codeword counter being equal to a first threshold; In the first synchronization lock success partial state, a value of the first synchronization lock variable is set to a second value, and the value of the first synchronization lock variable being the second value indicates that the position of the current observation bit is a synchronization position. The method is further configured as follows.

[0316] In a possible implementation, the synchronization position determination module 1910 includes: setting a value of the first codeword variable to a third value in a first synchronization lock initialization substate; in response to selecting a first test block from the data sequence based on the current observed bits, setting a value of the first codeword to be verified variable to a fourth value; entering a first codeword verification substate in response to the value of the first codeword variable being the fourth value and the value of the first synchronization lock variable being the first value; The method is further configured as follows.

[0317] In a possible implementation, the loss of lock detection state includes a second codeword verification substate.

[0318] The lock loss detection module 1920 includes: re-entering a first counter reset substate in response to determining the synchronization position; in response to selecting the one first codeword based on the synchronization position, entering a second codeword verification substate; Verify the first codeword in a second codeword verification substate. It is configured as follows.

[0319] In a possible implementation, the lock loss detection module 1920 includes: Setting an initial value of a first codeword counter and an initial value of a first invalid codeword counter in a first counter reset substate The method is further configured as follows.

[0320] The lock loss detection module 1920 includes: in response to the first codeword not satisfying a verification condition, incrementing a count value of the first codeword counter by Y and incrementing a count value of the first invalid codeword counter by Z, both Y and Z being integers equal to or greater than 1; re-entering a synchronization position determination state in response to the count value of the first invalid codeword counter being equal to the third threshold value when the count value of the first codeword counter is less than or equal to the second threshold value and the third threshold value is less than the second threshold value. It is configured as follows.

[0321] In a possible implementation, the synchronous position determination state includes a first slip portion state.

[0322] The lock loss detection module 1920 includes: Entering the first slip portion state, slipping to the next observed bit in a first slip portion state; In response to slipping to the next observation bit, re-entering the first counter reset substate to examine the next observation bit. It is configured as follows.

[0323] In a possible implementation, the synchronization position determination module 1910 includes: selecting a candidate position in the data sequence from the positions of the N observed bits; Determining a sync position based on candidate positions It is configured as follows.

[0324] In a possible implementation, N is greater than 1 and the synchronization position determination state includes a second counter reset substate and a third codeword verification substate.

[0325] The synchronous position determination module 1910 includes: setting an initial value of a second codeword counter and an initial value of a first currently valid codeword counter in a second counter reset substate and selecting one observed bit from the data sequence; in response to selecting one second test block from the data sequence based on the current observed bit, entering a third codeword verification substate, the length of the second test block being equal to the codeword length, and a starting location of the second test block and a location of the current observed bit being separated by an integer amount of the codeword length; verifying the second test block in a third codeword verification sub-state and incrementing a count value of the second codeword counter by W, where W is an integer greater than or equal to 1; and in response to the second test block satisfying the verification condition, incrementing a count value of the first currently valid codeword counter by P, where P is an integer greater than or equal to 1; in response to the count value of the second codeword counter being equal to the fourth threshold value and in response to the count value of the first currently valid codeword counter being greater than a current value of the maximum valid codeword number variable, incrementing a value of the observed bit number variable by one, updating a value of the candidate synchronization position variable to the current observed bit position, and updating a current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter; In response to the value of the number of observed bits variable being equal to N, the value of the current candidate synchronization position variable is determined to be the candidate position. It is configured as follows.

[0326] In a possible implementation, the synchronized location determination state further includes a candidate location selection substate.

[0327] The synchronous position determination module 1910 includes: entering a candidate location selection substate in response to the count value of the second codeword counter being equal to a fourth threshold; in the candidate position selection substate, in response to the count value of the second codeword counter being equal to the fourth threshold value and in response to the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword number variable, increase the value of the observed bit number variable by 1, update the value of the candidate synchronization position variable to the current observed bit position, and update the current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter. It is configured as follows.

[0328] In a possible implementation, the synchronization position determination module 1910 is further configured to, in response to the value of the number of observed bits variable being less than N, verify a next observed bit selected from the data sequence.

[0329] In a possible implementation, the synchronization position determination state further includes a second slip portion state.

[0330] The synchronous position determination module 1910 includes: in response to the value of the number of observed bits variable being less than N, entering a second slip substate; slipping to the next observed bit in a second slip portion state; In response to slipping to the next observation bit, re-entering the second counter reset substate to examine the next observation bit. It is configured as follows.

[0331] In a possible implementation, the synchronous position determination state further includes a second synchronous lock initialization substate.

[0332] The synchronous position determination module 1910 includes: In the second sync lock initialization substate, set the value of the observed bit count variable to a fifth value, set the value of the candidate sync position variable to a sixth value, and set the value of the maximum valid codeword count variable to a seventh value. The method is further configured as follows.

[0333] In a possible implementation, the synchronization position determination module 1910 includes: Setting the value of the second codeword variable to be verified to a third value in the second synchronization lock initialization substate. The method is further configured as follows.

[0334] The synchronous position determination module 1910 includes: in response to selecting a second test block from the data sequence based on the current observed bits, setting a value of a second codeword to be verified variable to a fourth value; entering a third codeword verification substate in response to the value of the second codeword variable being a fourth value; It is configured as follows.

[0335] In a possible implementation, the synchronization position determination module 1910 includes: In response to the count value of the second codeword counter being less than a fourth threshold, re-entering a third codeword verification substate to verify a next second test block selected based on the current observed bits. The method is further configured as follows.

[0336] In a possible implementation, the synchronization position determination state includes a third counter reset substate and a fourth codeword verification substate.

[0337] The synchronous position determination module 1910 includes: setting an initial value of a third codeword counter and an initial value of a first valid codeword counter in a third counter reset substate, and selecting one observed bit from the data sequence; in response to selecting a third test block from the data sequence based on the current observed bit, entering a fourth codeword verification substate, the third test block having a length equal to the codeword length, and a start location of the third test block and a location of the current observed bit separated by an integer amount of the codeword length; verifying the third test block in a fourth codeword verification sub-state; in response to the third test block satisfying a verification condition, incrementing a count value of the third codeword counter by M and incrementing a count value of the first valid codeword counter by Q, both M and Q being integers greater than or equal to 1; determining a position of a currently observed bit as a candidate position in response to the count value of the first codeword counter being equal to the sixth threshold when the count value of the third codeword counter is equal to or less than a fifth threshold and the fifth threshold is equal to or less than a sixth threshold; It is configured as follows.

[0338] In a possible implementation, the synchronization position determination state further includes a second codeword valid portion state.

[0339] The synchronous position determination module 1910 includes: in response to the third test block satisfying a verification condition, entering a second codeword valid portion state; In the second codeword valid portion state, the third codeword counter is incremented by M, and the first valid codeword counter is incremented by Q. It is configured as follows.

[0340] In a possible implementation, the synchronization position determination module 1910 includes: verifying a next observed bit selected from the data sequence in response to the third codeword counter having a count value equal to the fifth threshold and the first valid codeword counter having a count value less than a sixth threshold in the second codeword valid portion state; The method is further configured as follows.

[0341] In a possible implementation, the synchronization position determination module 1910 includes: in response to the third codeword counter being less than the fifth threshold and the first valid codeword counter being less than the sixth threshold in the second codeword valid substate, re-entering a fourth codeword verification substate to verify a next third test block selected based on the current observed bits. The method is further configured as follows.

[0342] In a possible implementation, the synchronization position determination state further includes a first code word invalid portion state.

[0343] The synchronous position determination module 1910 includes: enter a first codeword invalid portion state in response to the third test block not satisfying a verification condition; incrementing a count value of a third code word counter by M in the first code word invalid portion state; verifying a next observed bit selected from the data sequence in response to the third codeword counter's count value being equal to the fifth threshold value; The method is further configured as follows.

[0344] In a possible implementation, the synchronization position determination module 1910 is further configured to, in the first code word invalid portion state, re-enter a fourth code word verification portion state in response to the count value of the third code word counter being less than a fifth threshold, and verify a next third test block selected based on the current observation bits.

[0345] In a possible implementation, the synchronous position determination state further includes a third slip portion state.

[0346] The synchronous position determination module 1910 includes: Entering the third slip portion state, slip to the next observed bit in a third slip substate; In response to slipping to the next observation bit, re-entering a third counter reset substate to examine the next observation bit. It is configured as follows.

[0347] In a possible implementation, the synchronous position determination state further includes a third synchronous lock initialization sub-state.

[0348] The synchronous position determination module 1910 includes: Set the value of a third codeword variable to be verified to a third value in a third synchronization lock initialization substate. The method is further configured as follows.

[0349] In a possible implementation, the synchronization position determination module 1910 includes: in response to selecting a third test block from the data sequence based on the current observed bits, setting a value of a third codeword to be verified variable to a fourth value; entering a fourth codeword verification substate in response to the value of the third codeword variable being a fourth value; It is configured as follows.

[0350] In a possible implementation, the synchronization position determination module 1910 includes: The candidate position is verified, and the candidate position is determined as a synchronization position after the verification is successful. It is configured as follows.

[0351] In a possible implementation, the synchronization position determination state further includes a fourth counter reset substate and a fifth codeword verification substate.

[0352] The synchronous position determination module 1910 includes: setting an initial value of a fourth codeword counter in a fourth counter reset sub-state and selecting a fourth test block from the data sequence based on the candidate position; entering a fifth codeword verification substate in response to selecting a fourth test block from the data sequence based on the candidate location; verifying a fourth test block in a fifth codeword verification sub-state; in response to the fourth test block satisfying the verification condition, incrementing a count value of a fourth codeword counter by R, where R is an integer greater than or equal to 1; determining the candidate position as a synchronization position in response to the count value of the fourth codeword counter being equal to a seventh threshold value; It is configured as follows.

[0353] In a possible implementation, the synchronization position determination state further includes a third codeword validity portion state.

[0354] The synchronous position determination module 1910 includes: in response to the fourth test block satisfying a verification condition, entering a third codeword valid portion state; In the third code word valid portion state, the count value of the fourth code word counter is increased by R. It is configured as follows.

[0355] In a possible implementation, the synchronization position determination module 1910 includes: and in response to the count value of the fourth codeword counter being less than the seventh threshold, re-entering a fifth codeword verification substate to verify a next fourth test block selected based on the candidate position. The method is further configured as follows.

[0356] In a possible implementation, the synchronization position determination module 1910 includes: reselecting the candidate location in response to the fourth test block not satisfying the verification condition. The method is further configured as follows.

[0357] In a possible implementation, the synchronization position determination state further includes a first resynchronization sub-state.

[0358] The synchronous position determination module 1910 includes: entering a first resynchronization substate in response to a fourth test block not satisfying a verification condition; Setting a value of the first resynchronization lock variable to a second value in the first resynchronization sub-state, the value of the first resynchronization lock variable being the second value indicating reselection of the candidate position in the data sequence. The method is further configured as follows.

[0359] In a possible implementation, the sync position determination state further includes a second sync lock success substate.

[0360] The synchronous position determination module 1910 includes: enter a second sync lock success substate in response to the count value of the fourth codeword counter being equal to a seventh threshold; Setting a value of a second synchronization lock variable to a second value in a second synchronization lock successful partial state, the value of the second synchronization lock variable being the second value indicating that the candidate position is a synchronization position. It is configured as follows.

[0361] In a possible implementation, the synchronization position determination module 1910 includes: Determine the candidate position as a sync position It is configured as follows.

[0362] In a possible implementation, the lock loss detection module 1920 includes: In the lock loss detection state, verifying codewords in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords, and re-entering the synchronization position determination state in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold. It is configured as follows.

[0363] In a possible implementation, the loss of lock detection state includes a fifth counter reset substate and a sixth codeword verification substate.

[0364] The lock loss detection module 1920 includes: setting an initial value of a fifth codeword counter and an initial value of a second invalid codeword counter in a fifth counter reset substate; entering a sixth codeword verification substate in response to selecting a second codeword from the data sequence based on the synchronization position; verifying the second code word in a sixth code word verification sub-state; in response to the second codeword not satisfying the verification condition, incrementing a count value of the fifth codeword counter by one and incrementing a count value of the second invalid codeword counter by one; re-entering a synchronization position determination state in response to the count value of the second invalid codeword counter being equal to an eighth threshold value when the count value of the fifth codeword counter is less than the target value. It is configured as follows.

[0365] In a possible implementation, the loss of lock detection state further includes a second codeword invalid portion state.

[0366] The lock loss detection module 1920 includes: enter a second code word invalid portion state in response to the second code word not satisfying a verification condition; In the second code word invalid portion state, the count value of the fifth code word counter is increased by 1, and the count value of the second invalid code word counter is increased by 1. It is configured as follows.

[0367] In a possible implementation, the lock loss detection module 1920 includes: incrementing a count value of a fifth codeword counter by one in response to the second codeword satisfying a verification condition; In response to the count value of the fifth codeword counter being equal to the target value, re-entering a fifth counter reset substate to perform a next test on the synchronization position. The method is further configured as follows.

[0368] In a possible implementation, the loss of lock detection state further includes a fourth codeword valid portion state.

[0369] The lock loss detection module 1920 includes: in response to the second code word satisfying a verification condition, entering a fourth code word valid portion state; In the fourth code word valid portion state, the count value of the fifth code word counter is increased by 1. The method is further configured as follows.

[0370] In a possible implementation, the lock loss detection module 1920 includes: in response to the count value of the fifth codeword counter being less than the target value in the fourth codeword validity substate, re-entering a sixth codeword verification substate to verify a next second codeword selected based on the synchronization position. The method is further configured as follows.

[0371] In a possible implementation, the lock loss detection module 1920 includes: in response to the fifth codeword counter being less than the target value and the second invalid codeword counter being less than the eighth threshold in the second codeword invalid portion state, re-entering a sixth codeword verification portion state to verify a next second codeword selected based on the synchronization position. The method is further configured as follows.

[0372] In a possible implementation, the lock loss detection module 1920 includes: in response to the fifth codeword counter count value being equal to the target value and the second invalid codeword counter count value being less than an eighth threshold value in the second codeword invalid portion state, re-entering a fifth counter reset portion state and performing a next test on the synchronization position; The method is further configured as follows.

[0373] In a possible implementation, the verification condition is that the number of zero elements in the syndrome of the test block or codeword is greater than a synchronization threshold, or The verification condition is that the number of non-zero elements in the syndrome of the test block or codeword is less than an asynchronous threshold, or The verification condition is that the test block or codeword is an error-correcting test block, or The verification condition is that the re-parity bits of the test block or codeword are the same as the original parity bits.

[0374] In possible implementations, the start signal includes a system reset signal, a system start signal, a data receive fail signal, or a resynchronization signal.

[0375] In a possible implementation, the data sequence is a bit stream that is encoded via FEC.

[0376] The configuration of the communication device will be described below.

[0377] Figure 20 is a diagram of the structure of a communication device according to one embodiment of the present application. Referring to Figure 20, the communication device 2000 is optionally implemented using a general bus architecture. The communication device 2000 includes at least one processor 2001, a communication bus 2002, a memory 2003, and at least one network interface 2004. The communication device of the structure shown in Figure 20 may be a router, a switch, etc., as described above.

[0378] The processor 2001 may be, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits configured to implement the solutions of the present application. For example, the processor 2001 may include an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD may be, for example, a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0379] The communication bus 2002 is configured to transfer information between the aforementioned components. The communication bus 2002 can be classified as an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line represents a bus in FIG. 20, but this does not mean that there is only one bus or only one type of bus.

[0380] The memory 2003 may be, for example, a read-only memory (ROM) or another type of static storage device capable of storing static information and instructions, for example, a random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions, for example, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other compact disc storage, an optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray optical discs, etc.), a magnetic disc storage medium or another magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. However, this is not limited thereto. The memory 2003 may, for example, exist independently and be connected to the processor 2001 via a communication bus 2002. Alternatively, the memory 2003 and the processor 2001 may be integrated together.

[0381] The network interface 2004 is any transceiver type device configured to communicate with another device or a communication network. The network interface 2004 may include a wired network interface or may include a wireless network interface. The wired network interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless network interface may be a wireless local area network (WLAN) interface, a network interface for a cellular network, or a combination thereof, etc.

[0382] In a specific implementation, in one example, the processor 2001 may include one or more CPUs.

[0383] In a specific implementation, in one example, the communications device 2000 may include multiple processors. Each of the processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0384] FIG. 21 is another structure diagram of a communication device according to an embodiment of the present application. When the communication device is a forwarding device on a network, such as a router or a switch, please refer to the device structure diagram shown in FIG. 21 for the communication device. The device 2100 includes a main control board and one or more interface boards. The main control board is communicatively connected to the interface boards. The main control board is also called a main processing unit (MPU) or a route processor card. The main control board controls and manages each component in the device 2100, including route calculation, device management, and function maintenance. The interface board is also called a line processing unit (LPU) or a line card, and is configured to forward data.

[0385] In some embodiments, the device 2100 may also include a switching board. The switching board is communicatively connected to the main control board and the interface board. The switching board is configured to forward data between the interface boards. The switching board may also be referred to as a switch fabric unit (SFU). The interface board includes a central processing unit, a memory, a forwarding chip, and a physical interface card (PIC). The central processing unit is communicatively connected to the memory, the network processor, and the physical interface card. The memory is configured to store a forwarding table. The forwarding chip is configured to forward the received data frame based on the forwarding table stored in the memory. If the destination address of the data frame is the address of the device 2100, the data frame is sent to the CPU for processing. If the destination address of the data frame is not the address of the device 2100, a next hop and an outbound interface corresponding to the destination address are found in the forwarding table based on the destination address, and the data frame is forwarded to the outbound interface corresponding to the destination address. The forwarding chip may be a network processor (NP). The PIC, also called a sub-card, may be mounted on an interface board and is responsible for converting optical or electrical signals into data frames, checking the validity of the data frames, and then forwarding the data frames to a forwarding chip for processing.

[0386] In some embodiments, the central processing unit may also perform the functions of the forwarding chip, for example, implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board. The communication connection between the main control board, the interface board, and the switching board may be implemented via a bus. In some embodiments, the forwarding chip may be implemented via an ASIC or FPGA.

[0387] Logically, the device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board and a central processing unit. The forwarding plane includes components for performing forwarding, such as memory, PICs, and NPs. The control plane performs functions such as the function of a router to generate forwarding tables, process signaling packets and protocol packets, and configure and maintain the status of PE1. The control plane communicates the generated forwarding tables to the forwarding plane. On the forwarding plane, the NPs look up tables to forward packets received by the PICs of the device 2100 based on the forwarding tables delivered by the control plane. The forwarding tables delivered by the control plane may be stored in memory. In some embodiments, the control plane and the forwarding plane may be completely separate and are not on the same device.

[0388] In a particular embodiment, the interface board is configured to receive a data sequence, the data sequence comprising a plurality of bits.

[0389] The main control board is configured to determine a synchronization position in the data sequence, which indicates the starting position of the code word in the data sequence, and perform lock loss detection. For detailed processing process, please refer to the description of Figure 8. Details will not be described again in this specification.

[0390] In a possible implementation, an interprocess communication (IPC) channel is established between the main control board and the interface boards, and the main control board and the interface boards communicate with each other via the IPC channel.

[0391] An embodiment of the present application further provides a chip, which is configured to implement the aforementioned codeword synchronization method.

[0392] An embodiment of the present application further provides a chip system. The chip system includes a first chip and a second chip that are cascaded. The first chip is configured to implement the above-mentioned codeword synchronization method. The second chip is configured to perform codeword synchronization based on AM mode. In other words, the codeword synchronization method in the present application is used for inner FEC, and the codeword synchronization method based on AM mode is used for outer FEC.

[0393] In some embodiments provided in the present application, it should be understood that the disclosed system architecture, devices, and methods may be implemented in other ways. For example, the described device embodiment is merely an example. For example, the division into modules is merely a logical division of functions, and may be other divisions in actual implementation. For example, multiple modules or components may be combined or integrated as another system, or some features may be ignored or not implemented. In addition, the mutual couplings or direct couplings or communication connections shown or discussed may be implemented through some interfaces. Indirect couplings or communication connections between devices or modules may be implemented in electronic, mechanical, or other forms.

[0394] In this application, terms such as "first" and "second" are used to distinguish between the same or similar items having essentially the same purpose or function. It should be understood that there is no logical or chronological order dependency between "first" and "second", and that the quantity and execution order are not limited. In the following description, terms such as "first" and "second" are used to describe various elements, but it should be further understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another element. For example, a first test block can be referred to as a second test block, and similarly, a second test block can be referred to as a first test block, without departing from the scope of various examples. Both the first test block and the second test block may be test blocks, or may be separate and different test blocks in some cases.

[0395] In this application, the term "at least one" means one or more, and in this application, the term "plurality" means two or more.

[0396] The above description is merely an exemplary implementation of the present application, and is not intended to limit the scope of protection of the present application. Any equivalent modifications or replacements that are easily conceived by those skilled in the art within the technical scope disclosed in this application shall be included in the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims. [Explanation of symbols]

[0397] 1910 Synchronous Positioning Module 1920 Lock Loss Detection Module 2000 Communication Devices 2001 Processor 2002 Communication Bus 2003 Memory 2004 Network Interface 2100 Devices

Claims

1. 1. A method for codeword synchronization, the method comprising: in response to a start signal, entering a synchronous position determination state; determining a synchronization position within a received data sequence in the synchronization position determination state, the synchronization position indicating a start position of a codeword within the data sequence; entering a loss of lock detection state in response to determining said synchronization position; verifying, in the loss of lock detection state, a plurality of selected code words based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state. The codeword synchronization method includes:

2. The step of determining a synchronization position within a received data sequence in the synchronization position determination state comprises: selecting N observed bits from the data sequence and determining the synchronization position based on positions of the N observed bits in the synchronization position determination state, where N is an integer greater than or equal to 1; 2. The method of claim 1, comprising:

3. The step of determining the synchronization position based on the positions of the N observed bits comprises: selecting said synchronization position from said positions of said N observed bits.

3. The method of claim 2, comprising:

4. the synchronization position determination state includes a first counter reset substate and a first codeword verification substate; the step of selecting N observed bits from the data sequence and selecting the synchronization position from the positions of the N observed bits in the synchronization position determination state comprises: setting an initial value of a first codeword counter in the first counter reset sub-state and selecting one observed bit from the data sequence; entering the first codeword verification substate in response to selecting a first test block from the data sequence based on the currently observed bit, the first test block having a length equal to a codeword length, and a start position of the first test block and a position of the currently observed bit being separated by an integer amount of the codeword length; verifying the first test block in the first codeword verification sub-state; in response to the first test block satisfying a verification condition, incrementing a count value of the first codeword counter by X, where X is an integer greater than or equal to 1; determining the position of the currently observed bit as the synchronization position in response to the count value of the first codeword counter being equal to a first threshold; 4. The method of claim 3, comprising:

5. the step of selecting N observed bits from the data sequence and selecting the synchronization position from the positions of the N observed bits in the synchronization position determination state comprises: in response to the count value of the first codeword counter being less than the first threshold, re-entering the first codeword verification substate to verify a next first test block selected based on the current observed bits.

5. The method of claim 4, further comprising:

6. The synchronization position determination state further includes a first code word valid portion state; In response to the first test block satisfying a verification condition, the step of incrementing the count value of the first codeword counter by X comprises: entering the first codeword valid portion state in response to the first test block satisfying the verification condition; incrementing the count value of the first codeword counter by X in the first codeword valid portion state; 6. The method of claim 4 or 5, comprising:

7. the step of selecting N observed bits from the data sequence and selecting the synchronization position from the positions of the N observed bits in the synchronization position determination state comprises: verifying a next observed bit selected from the data sequence in response to the first test block not satisfying the verification condition.

7. The method of claim 4, further comprising:

8. the synchronous position determination state further includes a first slip portion state; the step of verifying a next observed bit selected from the data sequence in response to the first test block not satisfying the verification condition comprises: entering the first slip portion state in response to the first test block not satisfying the verification condition; slipping to the next observed bit in the first slip portion state; in response to slipping to the next observation bit, re-entering the first counter reset sub-state and validating the next observation bit; 8. The method of claim 7, comprising:

9. the synchronous position determination state further includes a first synchronous lock initialization substate; Prior to the step of setting an initial value of a first codeword counter in the first counter reset sub-state, the method further comprises: setting a value of a first synchronization lock variable to a first value in the first synchronization lock initialization sub-state; 9. The method of claim 4, further comprising:

10. The synchronous position determination state further includes a first synchronous lock success partial state; determining the position of the currently observed bit as the synchronization position in response to the count value of the first codeword counter being equal to a first threshold value, entering the first sync lock success sub-state in response to the count value of the first codeword counter being equal to the first threshold; setting the value of the first sync lock variable to a second value in the first sync lock successful partial state, the value of the first sync lock variable being the second value indicating that the position of the currently observed bit is the sync position; 10. The method of claim 9, comprising:

11. The method comprises: setting a value of a first codeword variable to a third value in the first synchronization lock initialization sub-state; Further comprising: said step of entering said first codeword verification substate in response to selecting a first test block from said data sequence based on said currently observed bits comprises: in response to selecting the one first test block from the data sequence based on the currently observed bits, setting the value of the first codeword to be verified variable to a fourth value; entering the first codeword verification substate in response to the value of the first codeword variable being the fourth value and the value of the first synchronization lock variable being the first value; 11. The method of claim 9 or 10, comprising:

12. the loss of lock detection state includes a second codeword verification substate; The step of verifying a plurality of code words selected based on the synchronization position in the loss of lock detection state comprises: re-entering the first counter reset sub-state in response to determining the synchronization position; in response to selecting a first codeword based on the synchronization position, entering the second codeword verification substate; verifying the first codeword in the second codeword verification substate; 12. The method according to any one of claims 4 to 11, comprising:

13. The step of verifying a plurality of code words selected based on the synchronization position in the loss of lock detection state comprises: setting the initial value of the first codeword counter and an initial value of a first invalid codeword counter in the first counter reset partial state. Further comprising: The step of re-entering the synchronous position determination state in response to a verification failure comprises: in response to the first codeword not satisfying the verification condition, incrementing the count value of the first codeword counter by Y and incrementing the count value of the first invalid codeword counter by Z, both Y and Z being integers equal to or greater than 1; re-entering the synchronization position determination state in response to the count value of the first invalid codeword counter being equal to a third threshold when the count value of the first codeword counter is less than or equal to a second threshold and the third threshold is less than the second threshold; 13. The method of claim 12, further comprising:

14. the synchronous position determination state includes the first slip portion state; The step of re-entering the synchronous position determination state comprises: entering the first slip portion state; slipping to the next observed bit in the first slip portion state; in response to slipping to the next observation bit, re-entering the first counter reset sub-state and validating the next observation bit; 14. The method of claim 13, comprising:

15. The step of determining the synchronization position based on the positions of the N observed bits comprises: selecting candidate positions within the data sequence from the positions of the N observed bits; determining the synchronization position based on the candidate positions; 3. The method of claim 2, comprising:

16. N is greater than 1, and the synchronization position determination state includes a second counter reset substate and a third codeword verification substate; The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: setting an initial value of a second codeword counter and an initial value of a first currently valid codeword counter in the second counter reset sub-state and selecting one observed bit from the data sequence; entering the third codeword verification substate in response to selecting a second test block from the data sequence based on the currently observed bit, the second test block having a length equal to a codeword length, and a start position of the second test block and a position of the currently observed bit being separated by an integer amount of the codeword length; verifying the second test block in the third codeword verification sub-state and incrementing a count value of the second codeword counter by W, where W is an integer greater than or equal to 1; and in response to the second test block satisfying a verification condition, incrementing a count value of the first currently valid codeword counter by P, where P is an integer greater than or equal to 1; in response to the count value of the second codeword counter being equal to a fourth threshold value and in response to the count value of the first currently valid codeword counter being greater than a current value of a maximum valid codeword number variable, incrementing a value of an observed bit number variable by one, updating a value of a candidate synchronization position variable to the position of the currently observed bit, and updating the current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter; determining the value of the current candidate synchronization position variable as the candidate position in response to the value of the number of observed bits variable being equal to N; 16. The method of claim 15, comprising:

17. The synchronous location determination state further includes a candidate location selection substate; in response to the count value of the second codeword counter being equal to a fourth threshold value and in response to the count value of the first currently valid codeword counter being greater than a current value of a maximum valid codeword number variable, increasing a value of an observed bit number variable by one, updating a value of a candidate synchronization position variable to the position of the currently observed bit, and updating the current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter entering the candidate location selection substate in response to the count value of the second codeword counter being equal to the fourth threshold; in response to the count value of the second codeword counter being equal to the fourth threshold value and the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword number variable, in the candidate position selection substate, increasing the value of the observed bit number variable by one, updating the value of the candidate synchronization position variable to the position of the current observed bit, and updating the current value of the maximum valid codeword number variable to the count value of the first currently valid codeword counter; 17. The method of claim 16, comprising:

18. The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: examining a next observed bit selected from the data sequence in response to the value of the number of observed bits variable being less than N.

18. The method of claim 16 or 17, further comprising:

19. the synchronous position determination state further includes a second slip portion state; said step of examining a next observed bit selected from said data sequence in response to said value of said number of observed bits variable being less than N comprises: entering the second slip portion state in response to the value of the number of observed bits variable being less than N; slipping to the next observed bit in the second slip portion state; in response to slipping to the next observation bit, re-entering the second counter reset sub-state and validating the next observation bit; 20. The method of claim 18, comprising:

20. the synchronous position determination state further includes a second synchronous lock initialization substate; Prior to the step of setting an initial value of a second codeword counter and an initial value of a first currently valid codeword counter in the second counter reset sub-state, the method further comprises: setting the value of the number of observed bits variable to a fifth value, setting the value of the candidate synchronization position variable to a sixth value, and setting the value of the maximum number of valid codewords variable to a seventh value in the second synchronization lock initialization substate.

20. The method of any one of claims 16 to 19, further comprising:

21. The method comprises: setting a value of a second codeword to be verified variable in the second synchronization lock initialization sub-state to a third value. Further comprising: said step of entering said third codeword verification substate in response to selecting a second test block from said data sequence based on said currently observed bits comprises: in response to selecting the one second test block from the data sequence based on the currently observed bits, setting the value of the second codeword to be verified variable to a fourth value; entering the third codeword verification substate in response to the value of the second codeword variable being the fourth value; 21. The method of claim 20, comprising:

22. The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: in response to the count value of the second codeword counter being less than the fourth threshold, re-entering the third codeword verification substate to verify a next second test block selected based on the current observed bits.

22. The method of any one of claims 16 to 21, further comprising:

23. the synchronization position determination state includes a third counter reset substate and a fourth codeword verification substate; The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: setting an initial value of a third codeword counter and an initial value of a first valid codeword counter in the third counter reset sub-state and selecting one observed bit from the data sequence; entering the fourth codeword verification substate in response to selecting a third test block from the data sequence based on the currently observed bit, wherein a length of the third test block is equal to a codeword length, and a start position of the third test block and a position of the currently observed bit are separated by an integer amount of the codeword length; verifying the third test block in the fourth codeword verification sub-state; in response to the third test block satisfying a verification condition, incrementing a count value of the third codeword counter by M and incrementing a count value of the first valid codeword counter by Q, where both M and Q are integers equal to or greater than 1; determining the position of the currently observed bit as the candidate position in response to the count value of the first codeword counter being equal to a sixth threshold when the count value of the third codeword counter is less than or equal to a fifth threshold and the fifth threshold is less than or equal to the sixth threshold; 16. The method of claim 15, comprising:

24. The synchronization position determination state further includes a second code word valid portion state; the step of incrementing the count value of the third codeword counter by M and incrementing the count value of the first valid codeword counter by Q in response to the third test block satisfying a verification condition comprises: entering the second codeword valid portion state in response to the third test block satisfying the verification condition; incrementing the count value of the third codeword counter by M and incrementing the count value of the first valid codeword counter by Q in the second codeword valid portion state; 24. The method of claim 23, comprising:

25. The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: verifying a next observed bit selected from the data sequence in response to the count value of the third code word counter being equal to the fifth threshold and the count value of the first valid code word counter being less than the sixth threshold in the second code word valid portion state.

25. The method of claim 24, further comprising:

26. The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: in response to the count value of the third codeword counter being less than the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold in the second codeword valid partial state, re-entering the fourth codeword verification partial state to verify a next third test block selected based on the current observed bits.

26. The method of claim 24 or 25, further comprising:

27. The synchronization position determination state further includes a first code word invalid portion state; The steps of selecting N observed bits from the data sequence and selecting candidate positions within the data sequence from the positions of the N observed bits in the sync position determination state include: entering the first codeword invalid portion state in response to the third test block not satisfying the verification condition; incrementing the count value of the third codeword counter by M in the first codeword invalid portion state; in response to the count value of the third codeword counter being equal to the fifth threshold, verifying the next observed bit selected from the data sequence; 27. The method of any one of claims 23 to 26, further comprising:

28. The step of selecting N observed bits from the data sequence and determining a candidate position within the data sequence based on the N observed bits in the synchronous position determination state comprises: in response to the count value of the third codeword counter being less than the fifth threshold in the first codeword invalid substate, re-entering the fourth codeword verification substate to verify the next third test block selected based on the current observed bits.

28. The method of claim 27, further comprising:

29. the synchronous position determination state includes the third slip portion state; said step of examining a selected next observed bit from said data sequence comprising: entering the third slip portion state; slipping to the next observed bit in the third slip portion state; in response to slipping to the next observation bit, re-entering the third counter reset sub-state and validating the next observation bit; 28. The method of any one of claims 25 to 27, further comprising:

30. the synchronous position determination state further includes a third synchronous lock initialization substate; Prior to the step of setting an initial value of a third codeword counter and an initial value of a first valid codeword counter in the third counter reset sub-state, the method further comprises: setting a value of a third codeword variable to a third value in the third synchronization lock initialization sub-state.

30. The method of any one of claims 23 to 29, further comprising:

31. said step of entering said fourth codeword verification substate in response to selecting a third test block from said data sequence based on said currently observed bits comprises: in response to selecting the one third test block from the data sequence based on the currently observed bits, setting the value of the third codeword to be verified variable to a fourth value; in response to the value of the third codeword variable being the fourth value, entering the fourth codeword verification substate; 31. The method of claim 30, comprising:

32. The step of determining the synchronization position based on the candidate positions comprises: verifying the candidate location and determining the candidate location as the synchronization location after the verification is successful.

32. The method of any one of claims 15 to 31, comprising:

33. the synchronization position determination state further includes a fourth counter reset substate and a fifth code word verification substate; The step of verifying the candidate position and determining the candidate position as the synchronization position after the verification is successful, setting an initial value of a fourth codeword counter in the fourth counter reset sub-state and selecting a fourth test block from the data sequence based on the candidate positions; in response to selecting the one fourth test block from the data sequence based on the candidate position, entering the fifth codeword verification substate; verifying the fourth test block in the fifth codeword verification substate; in response to the fourth test block satisfying the verification condition, incrementing a count value of the fourth codeword counter by R, where R is an integer greater than or equal to 1; determining the candidate position as the synchronization position in response to the count value of the fourth codeword counter being equal to a seventh threshold; 33. The method of claim 32, comprising:

34. the synchronization position determination state further includes a third code word valid portion state; the step of incrementing a count value of the fourth codeword counter by R in response to the fourth test block satisfying the verification condition comprises: entering the third codeword valid portion state in response to the fourth test block satisfying the verification condition; incrementing the count value of the fourth codeword counter by R in the third codeword valid portion state; 34. The method of claim 33, comprising:

35. The step of verifying the candidate position and determining the candidate position as the synchronization position after the verification is successful, re-entering the fifth codeword verification substate in response to the count value of the fourth codeword counter being less than the seventh threshold to verify a next fourth test block selected based on the candidate location.

35. The method of claim 33 or 34, further comprising:

36. The step of verifying the candidate position and determining the candidate position as the synchronization position after the verification is successful, reselecting a candidate location in response to the fourth test block not satisfying the verification condition.

36. The method of any one of claims 33 to 35, further comprising:

37. the synchronization position determination state further includes a first resynchronization substate; The step of reselecting candidate locations in response to the fourth test block not satisfying the verification condition comprises: entering the first resynchronization sub-state in response to the fourth test block not satisfying the verification condition; setting a value of a first resynchronization lock variable to a second value in the first resynchronization partial state, the value of the first resynchronization lock variable being the second value indicating reselection of the candidate position within the data sequence; 37. The method of claim 36, comprising:

38. The synchronous position determination state further includes a second synchronous lock success partial state; the step of determining the candidate position as the synchronization position in response to the count value of the fourth codeword counter being equal to a seventh threshold value, entering the second sync lock success substate in response to the count value of the fourth codeword counter being equal to the seventh threshold; setting a value of the second synchronization lock variable to the second value in the second synchronization lock successful partial state, the value of the second synchronization lock variable being the second value indicating that the candidate position is the synchronization position; 38. The method of any one of claims 33 to 37, comprising:

39. The step of determining the synchronization position based on the candidate positions comprises: determining the candidate position as the synchronous position; 32. The method of any one of claims 15 to 31, comprising:

40. the step of verifying, in the loss of lock detection state, a plurality of selected code words based on the synchronization position and, in response to a verification failure, re-entering the synchronization position determination state, in the lock loss detection state, verifying codewords in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords; and in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold, re-entering the synchronization position determination state.

40. The method of any one of claims 1 to 39, comprising:

41. the loss of lock detection state includes a fifth counter reset substate and a sixth codeword verification substate; the step of verifying, in the lock loss detection state, a codeword in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords; and re-entering the synchronization position determination state in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold; setting an initial value of a fifth codeword counter and an initial value of a second invalid codeword counter in the fifth counter reset partial state; in response to selecting a second code word from the data sequence based on the synchronization position, entering the sixth code word verification substate; verifying the second codeword in the sixth codeword verification substate; in response to the second codeword not satisfying the verification condition, incrementing a count value of the fifth codeword counter by one and incrementing a count value of the second invalid codeword counter by one; re-entering the synchronization position determination state in response to the count value of the second invalid codeword counter being equal to the eighth threshold value if the count value of the fifth codeword counter is less than a target value; 41. The method of claim 40, comprising:

42. the loss of lock detection state further includes a second codeword invalid portion state; the step of incrementing a count value of the fifth codeword counter by one and incrementing a count value of the second invalid codeword counter by one in response to the second codeword not satisfying the verification condition comprises: entering the second code word invalid portion state in response to the second code word not satisfying the verification condition; incrementing the count value of the fifth codeword counter by one and incrementing the count value of the second invalid codeword counter by one in the second codeword invalid portion state; 42. The method of claim 41 , comprising:

43. the step of verifying, in the lock loss detection state, a codeword in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords; and re-entering the synchronization position determination state in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold; in response to the second codeword satisfying the verification condition, incrementing the count value of the fifth codeword counter by one; in response to the count value of the fifth codeword counter being equal to the target value, re-entering the fifth counter reset sub-state to perform a next test on the synchronization position; 43. The method of claim 41 or 42, further comprising:

44. the loss of lock detection state further includes a fourth codeword valid portion state; the step of incrementing the count value of the fifth codeword counter by one in response to the second codeword satisfying a verification condition comprises: in response to the second codeword satisfying the verification condition, entering the fourth codeword valid portion state; incrementing the count value of the fifth codeword counter by one in the fourth codeword valid portion state; 44. The method of claim 43, comprising:

45. the step of verifying, in the lock loss detection state, a codeword in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords; and re-entering the synchronization position determination state in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold; in response to the count value of the fifth codeword counter being less than the target value in the fourth codeword validity substate, re-entering the sixth codeword verification substate to verify a next second codeword selected based on the synchronization position.

45. The method of claim 43 or 44, further comprising:

46. the step of verifying, in the lock loss detection state, a codeword in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords; and re-entering the synchronization position determination state in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold; in response to the count value of the fifth codeword counter being less than the target value and the count value of the second invalid codeword counter being less than the eighth threshold in the second codeword invalid portion state, re-entering the sixth codeword verification portion state to verify the next second codeword selected based on the synchronization position.

46. ​​The method of any one of claims 41 to 45, further comprising:

47. the step of verifying, in the lock loss detection state, a codeword in a codeword set selected based on the synchronization position, the codeword set including a target number of codewords; and re-entering the synchronization position determination state in response to a number of codewords in the codeword set not satisfying the verification condition reaching an eighth threshold; re-entering the fifth counter reset sub-state in response to the count value of the fifth codeword counter being equal to the target value and the count value of the second invalid codeword counter being less than the eighth threshold value in the second codeword invalid sub-state to perform a next test on the synchronization position.

47. The method of any one of claims 41 to 46, further comprising:

48. The verification condition is that the number of zero elements in the syndrome of the test block or codeword is greater than a synchronization threshold, or The verification condition is that the number of non-zero elements in the syndrome of the test block or codeword is less than an asynchronous threshold; or the verification condition is that the test block or codeword is an error-correcting test block; or the verification condition is that the re-parity bits of the test block or codeword are the same as the original parity bits; 48. The method of any one of claims 4 to 14, 16 to 31, 33 to 38, and 40 to 47.

49. 49. The method of claim 1, wherein the initiation signal comprises a system reset signal, a system start signal, a data receive fail signal, or a resynchronization signal.

50. 50. The method according to claim 1, wherein the data sequence is a bit stream encoded by forward error correction (FEC).

51. A communications device, the communications device comprising a processor and a memory; The memory stores at least one computer instruction; The computer instructions are loaded and executed by the processor to implement a method according to any one of claims 1 to 50. Communication devices.

52. A chip, the chip being configured to implement a method according to any one of claims 1 to 50.

53. A chip system, the chip system comprising a first chip and a second chip connected in cascade, The first chip is configured to implement the method according to any one of claims 1 to 50, The second chip is configured to perform codeword synchronization using an alignment marker AM method. Chip system.

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