Data processing method, processing device and storage system

Abstract

The present disclosure provides a data processing method, a processing device, and a storage system. The data processing method includes the steps of: reading two burst data from a first storage channel and a second storage channel to obtain four burst data, the four burst data corresponding to the encoded data stored in the first storage channel and the second storage channel, the encoded data being obtained by encoding k data code elements written in the first storage channel and the second storage channel, the encoded data including k data code elements and m check code elements, and the total bit width of the m check code elements is eight times the bit width of one error correction code element; organizing the four burst data into a set of error correction code words including k readback data code elements and m readback check code elements; and performing a decoding operation based on the set of error correction code words to obtain an error-corrected code element. According to this data processing method, simultaneous error correction of two code elements can be realized.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202310037736.5, filed on January 9, 2023, and the entire contents disclosed in the above-mentioned Chinese patent application are incorporated herein by reference as part of this application.

[0002] SUMMARY OF THE DISCLOSURE The embodiments of the present disclosure relate to a data processing method, a processing device, and a storage system. [Background technology]

[0003] Data is easily affected by environmental factors during transmission, communication, and storage, which can lead to data errors. For example, Double Data Rate (DDR) memory (such as DDR SDRAM and DDR internal memory) is affected by environmental factors such as electromagnetic interference during operation, which can lead to errors in the internal memory. For users who require high stability, errors in the internal memory can cause fatal problems. For example, in the case of servers, the requirements for reliability of DDR data are relatively high, and the error correction technology of DDR memory can improve the stability and error correction capabilities of the server's internal memory. For example, an internal memory module that supports error detection and correction (Error Correcting Code, ECC) can improve the stability and error correction capabilities of the server's internal memory.

[0004] For some DDR internal memory, when a correctable error (CE) occurs, it is not necessary to replace the internal memory DIMM immediately. However, when an uncorrectable error (UE) occurs, in the past, if two internal memory chips have errors at the same time, an uncorrectable error is reported, which usually results in data loss and makes it impossible to recover the data. When data is lost, it affects the processor and other computing units to perform the corresponding operations, preventing related functions and applications from working properly, which eventually causes downtime. Summary of the Invention [Means for solving the problem]

[0005] According to a first aspect of the present disclosure, there are provided a data processing method, a processing device, a storage system, an electronic device and a storage medium for realizing simultaneous error correction of two code elements.

[0006] According to at least one embodiment of the present disclosure, a method for processing data is provided, the method including: reading two burst data from a first storage channel and a second storage channel, respectively, to obtain four burst data, the four burst data corresponding to encoded data stored in the first storage channel and the second storage channel, the encoded data being obtained by encoding k data code elements written in the first storage channel and the second storage channel, the encoded data including k data code elements and m check code elements, a total bit width of the m check code elements being eight times a bit width of one error correction code element; organizing the four burst data into a set of error correction code words including k readback data code elements and m readback check code elements; and performing a decoding operation based on the set of error correction code words to obtain an error-corrected code element.

[0007] For example, according to a processing method according to at least one embodiment of the present disclosure, the step of organizing four burst data into one set of error correction code words includes the steps of: combining, among two burst data read from a first memory channel, burst data corresponding to the same memory chip as one error correction code word code element to obtain a first portion of error correction code words; combining, among two burst data read from a second memory channel, burst data corresponding to the same memory chip as one error correction code word code element to obtain a second portion of error correction code words; and combining the first portion of error correction code words and the second portion of error correction code words.

[0008] For example, according to at least one embodiment of the processing method of the present disclosure, the step of encoding the k data code elements written in the first storage channel and the second storage channel includes a step of encoding the k data code elements based on an encoding matrix, and the step of performing a decoding operation based on the set of error-correcting code words to obtain error-corrected code elements includes a step of decoding the set of error-correcting code words based on a decoding matrix to obtain syndrome data, and a step of obtaining the error-corrected code elements using the syndrome data, wherein the encoding matrix is ​​a matrix with at least k+m rows and k columns and includes a Vandermonde type matrix, the decoding matrix is ​​a matrix with at least m rows and k+m columns and includes a Vandermonde type matrix, the Vandermonde type matrix is ​​a matrix related to the Vandermonde matrix, and k≦p n -1, m ≤ p n where n is the number of bits in each code element and p is the storage capacity of a single bit.

[0009] For example, according to at least one embodiment of the processing method of the present disclosure, the encoding matrix includes a first section including an identity matrix with k rows and k columns and a second section including a Vandermonde type matrix with m rows and k columns, and the step of encoding k data code elements based on the encoding matrix to obtain encoded data includes a step of multiplying the k data code elements with the identity matrix with k rows and k columns to obtain k data code elements, and a step of multiplying the k data code elements with the Vandermonde type matrix with m rows and k columns to obtain m check code elements.

[0010] For example, according to at least one embodiment of the processing method of the present disclosure, the decoding matrix includes a third section including a Vandermonde type matrix with m rows and k columns and a fourth section including an identity matrix with m rows and m columns, and the step of decoding the set of error correction code words based on the decoding matrix to obtain syndrome data includes the step of multiplying the k readback data code elements and the m readback check code elements using the decoding matrix to obtain syndrome data.

[0011] For example, according to at least one embodiment of the processing method of the present disclosure, the step of obtaining error-corrected code elements using syndrome data includes the steps of: reading syndrome data; and outputting k readback data code elements as error-corrected code elements in response to the syndrome data being all 0, where the syndrome data being all 0 indicates that the k readback data code elements and the m readback check code elements have no errors; and outputting k readback data code elements as error-corrected code elements in response to the syndrome data having one 1, where the syndrome data having one 1 indicates that the k readback data code elements have no errors and the m readback check code elements have no errors. the step of indicating that there is an error in a readback check code element corresponding to syndrome data that is 1; and, in response to the presence of v 1s in the syndrome data, performing error correction on the erroneous code elements among the k readback data code elements and the m readback check code elements to obtain error-corrected code elements, wherein the presence of v 1s in the syndrome data indicates that there are errors in v1 readback data code elements among the k readback data code elements that correspond to the syndrome data that is 1, and that there are errors in v2 readback check code elements among the m readback check code elements that correspond to the syndrome data that is 1, where v≧2, v1≦m, v2≦m, and v1+v2=v.

[0012] For example, according to at least one embodiment of the processing method of the present disclosure, the step of performing error correction on erroneous code elements among the k readback data code elements and the m readback check code elements using the syndrome data to obtain error-corrected code elements includes the steps of identifying error positions and error values ​​of the erroneous code elements among the k readback data code elements and the m readback check code elements using the syndrome data, and performing error correction on the erroneous code elements using the error positions to obtain error-corrected code elements.

[0013] For example, according to at least one embodiment of the processing method of the present disclosure, the step of identifying error locations and error values ​​of erroneous code elements of the k readback data code elements and the m readback check code elements using the syndrome data may include: 1) A dual data code element error correction operation including the steps of constructing a quadratic or higher order equation using syndrome data, and determining an error location and an error value based on the quadratic or higher order equation; 2) assuming that the value of the single check code element is an error, and determining an error location and an error value based on the equality of the ratio relationship between the syndrome data and the ratio relationship between the elements of the Vandermonde type matrix corresponding to the syndrome data; and 3) determining an error location and an error value based on the fact that a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data are equal, the single data code element error correction operation including the steps of:

[0014] For example, according to at least one embodiment of the processing method of the present disclosure, the quadratic or higher degree equation is a quadratic equation, p=2, m=4, the syndrome data is (s0, s1, s2, s3), Here, the step of constructing a quadratic or higher order equation using syndrome data is quadratic equation constructing JPEG2025504734000002.jpg624, where JPEG2025504734000003.jpg1935, Here, the step of determining the error location and the error value based on a quadratic or higher degree equation includes: Depending on whether a is non-zero, JPEG2025504734000004.jpg830, and the quadratic equation is converting the image to JPEG2025504734000005.jpg725; obtaining two roots y and y' of JPEG2025504734000006.jpg725; obtaining error positions x and x' as JPEG2025504734000007.jpg1068; Using error location and syndrome data, error value JPEG2025504734000008.jpg66 and and calculating JPEG2025504734000009.jpg87, where JPEG2025504734000010.jpg1129, JPEG2025504734000011.jpg732, Here, the step of determining an error location and an error value on the assumption that the value of a single check code element is an error and based on the equality of a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data, includes: Assume that the value of the test internal memory chip ecc0 corresponding to s0 is false; Based on JPEG2025504734000012.jpg926, the error location is x and the internal memory chip ecc0 is inspected, and the error value is JPEG2025504734000013.jpg95 and JPEG2025504734000014.jpg920; Assume that the value of the test internal memory chip ecc1 corresponding to s1 is false; Based on JPEG2025504734000015.jpg942, the error location is x and the internal memory chip ecc1 is inspected, and the error value is s0 and JPEG2025504734000016.jpg634; Assume that the value of the test internal memory chip ecc2 corresponding to s2 is false; Based on JPEG2025504734000017.jpg943, the error location is x and the internal memory chip ecc2 is inspected, and the error value is s0 and JPEG2025504734000018.jpg735; Assume that the value of the test internal memory chip ecc3 corresponding to s3 is false; Based on JPEG2025504734000019.jpg1126, the error location is x and the internal memory chip ecc3 is inspected, and the error value is s0 and and calculating that the image is JPEG2025504734000020.jpg635; Here, the step of determining the error location and the error value based on the fact that the ratio relationship between the syndrome data and the ratio relationship between the elements of the Vandermonde type matrix corresponding to the syndrome data are equal includes the steps of: The method includes a step of calculating, based on JPEG2025504734000021.jpg1138, that the error location is x and the error value is s0.

[0015] For example, according to at least one embodiment of the present disclosure, The step of obtaining the two roots y and y' of JPEG2025504734000022.jpg723 is done by mathematical operations: Find the solution for JPEG2025504734000023.jpg723, Obtaining the two roots y and y' of JPEG2025504734000024.jpg723, or by looking up a table, This involves obtaining the two roots y and y' of JPEG2025504734000025.jpg723.

[0016] For example, according to at least one embodiment of the present disclosure, a processing method is performed by a mathematical operation Find the solution for JPEG2025504734000026.jpg723, The step of obtaining the two roots y and y' of JPEG2025504734000027.jpg723 is to perform an exclusive OR operation on u. Find the solution for JPEG2025504734000028.jpg723, This involves obtaining the two roots y and y' of JPEG2025504734000029.jpg723.

[0017] For example, according to at least one embodiment of the present disclosure, y and u are both 8-bit finite field numbers, and an exclusive OR operation on u yields The steps to solve JPEG2025504734000030.jpg723 are: Y0=not Y0', or Y0' xor 1, Y1=Y1', Y2=Y2', Y3=Y3', Y4=Y4', Y5=Y5', Y6=Y6', Y7=Y7', and Y7=U0 xor U1 xor U2 xor U4, Y6= U0 xor U1 xor U2 xor U4 xor U7, Y5= U1 xor U2 xor U3 xor U4 xor U6, Y4 = U0 xor U7, Y3 = U1 xor U2 xor U3 xor U4, Y2 = U0 xor U3 xor U4 xor U6, Y1 = U0 xor U2 xor U4, Y0 = U3 xor U6, U5=Tr(u) where U0 through U7 represent the 0th through 7th bits of u, respectively. Y0 through Y7 represent the 0th through 7th bits of y, respectively. Y0' through Y7' represent the 0th bit through the 7th bit of y', respectively. Tr(u) is This indicates whether there is a solution for JPEG2025504734000031.jpg723, where Tr(u) = 1 indicates that there is no solution and Tr(u) = 0 indicates that there is a solution.

[0018] For example, in accordance with at least one embodiment of the processing method of the present disclosure, the Vandermonde type matrix may include a Vandermonde matrix, a Vandermonde matrix left-right inverse, a Vandermonde matrix up-down inverse, or a Vandermonde matrix transpose.

[0019] According to at least one embodiment of the present disclosure, a data processing apparatus is provided, the apparatus including: a reading unit configured to read two burst data from a first storage channel and a second storage channel respectively to obtain four burst data, the four burst data corresponding to encoded data stored in the first storage channel and the second storage channel, the encoded data being obtained by encoding k data code elements written to the first storage channel and the second storage channel, the encoded data including k data code elements and m check code elements, a total bit width of the m check code elements being eight times a bit width of one error correction code element, the four burst data being organized into a set of error correction code words including the k readback data code elements and the m readback check code elements; and a decoding module configured to perform a decoding operation based on the set of error correction code words to obtain an error-corrected code element.

[0020] According to at least one embodiment of the present disclosure, there is provided a storage system including a data processing device as described above, and a storage unit including the first storage channel and the second storage channel as described above.

[0021] According to at least one embodiment of the present disclosure, an electronic device is provided that includes a processor and a memory storing instructions that, when executed by the processor, cause the processor to perform the data processing method described above.

[0022] In accordance with at least one embodiment of the present disclosure, a computer-readable storage medium is provided having stored thereon instructions that, when executed by a processor, cause the processor to perform the method for processing data described above.

[0023] According to at least one embodiment of the present disclosure, simultaneous error correction of two code elements can be achieved. [Brief description of the drawings]

[0024] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the following briefly describes the accompanying drawings of the embodiments of the present disclosure. It is clear that the accompanying drawings in the following description are only related to some embodiments of the present disclosure and are not limitations on the present disclosure. [Figure 1] 1 is a flowchart of a method for processing data in accordance with at least one embodiment of the present disclosure, in accordance with an embodiment of the present disclosure. [Diagram 2] 1 is a schematic diagram of a data processing device in accordance with at least one embodiment of the present disclosure. [Diagram 3] FIG. 2 is a schematic diagram of an encoding module in accordance with at least one embodiment of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram of an encoding operation in accordance with at least one embodiment of the present disclosure. [Diagram 5] FIG. 2 is a schematic diagram of a decoding module and an error correction module in accordance with at least one embodiment of the present disclosure. [Figure 6]FIG. 2 is a schematic diagram of a decoding operation in accordance with at least one embodiment of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram of a double data error correction operation in accordance with at least one embodiment of the present disclosure. [Figure 8] FIG. 1 is a schematic diagram of solving a finite field quadratic equation, in accordance with at least one embodiment of the present disclosure. [Figure 9A] FIG. 13 is a schematic diagram of an internal memory configuration in the case of one fixed error+one random error, in accordance with at least one embodiment of the present disclosure. [Figure 9B] FIG. 13 is a schematic diagram of an internal memory configuration in the case of two fixed errors, in accordance with at least one embodiment of the present disclosure. [Figure 9C] FIG. 13 is a schematic diagram of an internal memory configuration in the case of two random errors, in accordance with at least one embodiment of the present disclosure. [Figure 10] FIG. 1 is a schematic diagram of a storage system in accordance with at least one embodiment of the present disclosure. [Figure 11] FIG. 1 is a schematic diagram of an electronic device in accordance with at least one embodiment of the present disclosure. [Figure 12] FIG. 1 is a schematic diagram of a non-transitory readable storage medium in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in connection with specific embodiments, it should be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover all changes, modifications, and equivalents included within the spirit and scope of the present disclosure, as defined by the appended claims. It should be noted that all method operations described herein can be realized by any functional block or functional arrangement, and that any functional block or functional arrangement can be realized as physical or logical entities, or a combination of both.

[0026] In order to make the present disclosure easier to understand for those skilled in the art, the present disclosure will be described in more detail below in combination with the accompanying drawings and specific examples.

[0027] It should be noted that the examples described below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific external shapes, hardware, connection relationships, operations, numerical values, conditions, data, orders, etc. shown and described. By reading this specification, a person skilled in the art can utilize the concept of this disclosure to construct many more embodiments not mentioned in this specification.

[0028] The terms used in this disclosure are general terms currently widely used in the field of the present disclosure with respect to the function of the present disclosure, but these terms may change according to the intention of a person skilled in the art, precedent, or new technology in the field. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in this specification should not be understood as simple names, but are based on the meaning of the terms and the overall description of the present disclosure.

[0029] In this disclosure, flowcharts are used to describe the operations performed by the system according to the embodiments of the present application. It should be understood that the above or following operations are not necessarily performed in precise order. Conversely, various steps may be processed in reverse order or simultaneously, as desired. At the same time, other operations may be added to these procedures, or operations of one or more steps may be removed from these procedures.

[0030] First, the abbreviations and related terms used in this application will be defined and explained.

[0031] Double-Symbol Correction (DSC): A technology that can simultaneously correct two symbols at once.

[0032] DDR (Double Data Rate): Double Data Rate.

[0033] DDR SDRAM: Double-rate synchronous dynamic random access memory, called DDR.

[0034] ECC (Error Check Correction): A technology that realizes "error detection and correction" using error correction code or error correction coding, which can improve the stability and reliability of computer operation.

[0035] RS (Reed-Solomon) coding: Also called Reed-Solomon code, it is a forward error correcting channel coding that is effective for polynomials generated by calibration of oversampled data. RS code is a special non-binary BCH code with high error correction capabilities.

[0036] SDDC (Single Device Data Correction): Correction of data on a single chip.

[0037] DDDC (Double Device Data Correction): Correction of data on two chips.

[0038] Internal Memory Channel: Each internal memory controller may have multiple internal memory channels, for example, general internal memory channel 0, internal memory channel 1.

[0039] UE (Uncorrectable Error): An error that cannot be corrected.

[0040] CE (Correctable Error): Correctable error.

[0041] Data Device: An internal memory chip that stores data.

[0042] ECC Device: An internal memory chip that stores check bits.

[0043] Symbol: Also called a code element, it is the smallest unit used in ECC error correction. There are usually x4 chips and x8 chips, and the corresponding symbols are 4-bit and 8-bit data.

[0044] Finite Field: Also called a Galois field, a field that contains only a finite number of elements, and may be written, for example, as GF(2n), where n represents the number of bits of an element in the field.

[0045] Vandermonde matrix: A matrix whose columns are geometric series. An example Vandermonde matrix is: It could also be JPEG2025504734000032.jpg3848.

[0046] It should be understood that the above defined terms are merely exemplary definitions in a particular application scenario to facilitate a better understanding of this specification, for example, the exemplary definition of a particular internal memory described above may be extended to other types of internal memory or other memories.

[0047] In the case of memory (e.g., DDR internal memory), if errors occur simultaneously in two memory chips, the conventional system reports an uncorrectable error, which cannot be corrected, and even if read again, the error will be uncorrectable, resulting in data loss and, in serious cases, system downtime. If the hardware records information such as the previous correctable error location and uses algorithmic post-processing to achieve the goal of correcting the two internal memory chips one by one, it can also solve part of the problem of two simultaneous errors. However, there are a number of prerequisites, the coverage rate is low, and one of the two internal memory chips in which errors occur simultaneously must be the internal memory chip in which the previous correctable error was reported.

[0048] The mainstream method for correcting the two example errors is DDDC, which includes the following key points: Lockstep must be activated, In terms of algorithm, ECC uses Parity+CRC. Only one memory chip can be modified per algorithmic operation. If the second internal memory chip needs to be corrected, the previously faulty internal memory chip must be replaced with a redundant internal memory chip (spare device), written, and then an algorithm must be used to find the second faulty internal memory chip. It is only possible to correct errors that occur in two internal memory chips in a time-division multiplexing manner. If errors occur in two memory chips at the same time, there is nothing DDDC technology can do and the system will report an uncorrectable error.

[0049] According to at least one embodiment of the present disclosure, a data processing method, a data processing device, a storage system, an electronic device, and a storage medium are proposed, and for example, when an error occurs in two code elements (e.g., two storage chips of DDR4 and DDR5) at any time, the errors occurring in the two code elements (e.g., two storage chips of DDR4 and DDR5) can be corrected simultaneously without the involvement of software and without relying on past recorded information. In this way, the reliability of the memory is significantly improved, and the risk of data loss and system down is reduced. In the following, the data processing method, processing device, storage system, electronic device, and storage medium according to the embodiment of the present disclosure will be described in detail with reference to the drawings.

[0050] First, a data processing method according to an embodiment of the present disclosure is described below, which can be applied to data processing devices, storage systems, electronic devices, and other suitable software or hardware, or a combination of hardware and software, as further described below.

[0051] FIG. 1 shows a flowchart of a data processing method 100 according to at least one embodiment of the present disclosure, which may include steps S102 to S106.

[0052] In step S102, two burst data are read from each of the first and second memory channels to obtain four burst data, the four burst data corresponding to the encoded data stored in the first and second memory channels, the encoded data being obtained by encoding k data code elements written in the first and second memory channels, the encoded data including k data code elements and m check code elements, and a total bit width of the m check code elements is eight times the bit width of one error correcting code element.

[0053] In some embodiments, k and m correspond to the total number of data storage chips in the first storage channel and the second storage channel and the total number of check storage chips in the first storage channel and the second storage channel, respectively, the bit width of each data code element among the k data code elements is twice the bit width of the corresponding data storage chip, the bit width of each check code element among the m check code elements is twice the bit width of the corresponding check storage chip, and k and m are positive integers. For example, in an exemplary DDR4 or DDR5, the first storage channel and the second storage channel both include eight x4 data internal memory chips and two x4 check internal memory chips (ecc internal memory chips), so the bit width of one error correction code element is 4 bits corresponding to the minimum unit of error correction, k=16, m=4, the bit width of each data storage chip and check storage chip is x4 (4 bits), and the bit width of each data code element and check code element is x8. Thus, the total bit width of the m check code elements of the encoded data is 4*8=32 bits, and the bit width of the error correction code element is 4 bits. Of course, the embodiment is not limited thereto, and the bit width of the data storage chip and the check storage chip may be changed, for example, two x4 data storage chips (or check storage chips) may be embodied as one x8 data storage chip (or check storage chip), in which case k, m can still correspond to the bit width of x4, i.e., the bit width of one error correction code element.

[0054] In some embodiments, the data code elements may be decoded and error corrected (if necessary) in a check operation to obtain data or instructions for performing a calculation to achieve a given function, and the check code elements may provide information in the decoding and error correction (if necessary) to ensure that correct data is obtained.

[0055] Exemplary first and second storage channels may be, for example, two internal memory channels, channel 0 and channel 1, in DDR4 or DDR5.

[0056] In step S104, the four burst data are organized into a set of error correction code words, which includes k readback data code elements and m readback check code elements.

[0057] In some embodiments, the four burst data (also referred to herein as readback encoded data, which is essentially the encoded data read from the first storage channel and the second storage channel) correspond to the encoded data, but the encoded data may be interfered with by environmental factors, such as electromagnetic, during transmission or in the storage unit (including the first storage channel and the second storage channel), resulting in data errors. Therefore, the k readback data code elements (i.e., the data code elements read from the first storage channel and the second storage channel) and the m readback check code elements (i.e., the check code elements read from the first storage channel and the second storage channel) may be different from the k data code elements and the m check code elements included in the encoded data.

[0058] In some embodiments, the storage unit may be the memory itself, such as a DDR memory or a DDR internal memory, while in other embodiments, the storage unit may be a storage array within the memory.

[0059] In step S106, a decoding operation is performed based on the set of error-correcting code words to obtain error-corrected code elements. In this way, according to the data processing method 100 according to at least one embodiment of the present disclosure, simultaneous error correction of two code elements or symbols (i.e., error-correcting code elements) is realized by reading two burst data from two storage channels respectively. For example, when the two erroneous code elements are in two different storage chips, error correction of two storage chips can be realized, and when the two erroneous code elements are in the same storage chip, error correction of a single storage chip can be realized.

[0060] For example, in DDR internal memory, the data bit width of DDR is usually fixed. For example, in the case of DDR4, it is 72+8 (data bit width+check bit width), and in the case of DDR5, it is 32+8 (data bit width+check bit width), and thus error correction of a code element with a x8 bit width can be realized. For example, if one x4 of this x8 code element exists in one chip (for example, a x4 or x8 chip), and the other x4 exists in another chip (for example, a x4 or x8 chip), error correction of these two chips can be realized. Also, for example, if the code element of x8 exists in one chip (for example, a x8 chip), error correction of one chip can be realized.

[0061] Other aspects of the data processing method according to at least one embodiment of the present disclosure are described in detail below.

[0062] In some embodiments, as an alternative or complement to the processing method described above with reference to Fig. 1, at least one embodiment of the present disclosure further provides an encoding method, the encoding method including: encoding the k data code elements written in the first storage channel and the second storage channel to obtain encoded data including k data code elements and m check code elements, and a total bit width of the m check code elements is eight times the bit width of one error-correcting code element. In this way, the encoded data corresponds to the four burst data, so that one set of error-correcting code words includes k readback data code elements and m readback check code elements, and the decoding is facilitated to realize the error correction of two code elements.

[0063] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the step of organizing the four burst data into one set of error correction code words includes the steps of: combining the two burst data read from the first storage channel, which correspond to the same storage chip, as one error correction code word code element to obtain a first part of error correction code words; combining the two burst data read from the second storage channel, which correspond to the same storage chip, as one error correction code word code element to obtain a second part of error correction code words; and combining the first part of error correction code words and the second part of error correction code words. In this way, according to the processing method of at least one embodiment of the present disclosure, the two burst data read from each storage channel can be combined to realize the organization of one set of error correction code words. However, the embodiment is not limited thereto, and the burst data corresponding to the same data storage chip in each storage channel may be combined into one data code element, and the burst data corresponding to the same check storage chip may be combined into one check code element to obtain the data code elements and check code elements of each storage channel, and these data code elements and check code elements may be combined to realize the formation of a set of error correction code words.

[0064] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the step of encoding the k data code elements written in the first storage channel and the second storage channel includes a step of encoding the k data code elements based on an encoding matrix, and the step of performing a decoding operation based on a set of error-correcting code words to obtain error-corrected code elements includes a step of decoding the set of error-correcting code words based on a decoding matrix to obtain syndrome data, and a step of obtaining the error-corrected code elements using the syndrome data, wherein the encoding matrix is ​​a matrix with at least k+m rows and k columns and includes a Vandermonde type matrix, the decoding matrix is ​​a matrix with at least m rows and k+m columns and includes the Vandermonde type matrix, the Vandermonde type matrix is ​​a matrix related to the Vandermonde matrix, and k≦p n -1, m ≤ p n where n is the number of bits in each code element and p is the storage capacity of a single bit.

[0065] In some embodiments, for example, the positions (also referred to as error symbol positions or error code element positions) and error values ​​of erroneous data code elements and check code elements can be determined based on the syndrome data, and error correction can be performed on the error code based on the syndrome data to obtain error-corrected code elements, for example error-corrected data code elements or error-corrected check code elements.

[0066] At least one embodiment of the present disclosure can be implemented in a finite field, where k≦p n -1, m ≤ p n where n is the number of bits in each code element and p is the storage capacity of a single bit, so that p and n define a finite field GF(p n ) can be constructed.

[0067] Note that the storage capacity of a single bit means the amount of data that can be represented by a single bit, i.e., p-ary. In some embodiments, p may be 2 (e.g., a single bit can represent two-ary data (0, 1)), so that GF(2 n ), k≦2 n -1, m≦2 n In some other embodiments, p may be 3 or other numbers (e.g., in quantum computing, a single bit can represent 3 (or more) elemental data), where k, m, and n may be positive integers and p may be a prime number.

[0068] In some embodiments, the Vandermonde type matrix includes the Vandermonde matrix and variants thereof. For example, the Vandermonde type matrix includes the Vandermonde matrix, the left-right flip of the Vandermonde matrix, the top-down flip of the Vandermonde matrix, the transpose of the Vandermonde matrix, or other variants that swap elements in the Vandermonde matrix. An exemplary Vandermonde matrix is: It could also be JPEG2025504734000033.jpg3849.

[0069] Table 1 shows a comparison table between the data processing method according to at least one embodiment of the present disclosure and the number of code elements of the RS code.

[0070] JPEG2025504734000034.jpg27125

[0071] Refer to Table 1. GF(2 n ) for the number of data code elements and the number of check code elements in the RS code, k+m≦2 n -1. In contrast, GF(2 n), the data processing method of the present disclosure is based on a Vandermonde type matrix, and the number of data code elements can be k≦2n-1 and the number of check code elements can be m≦2n. For example, assuming n=4, k=11 and m=4 can be used for the RS code, but k=15 and m=4 can be used for the data processing method of the present disclosure. In this case, the data processing method of the present disclosure can support more check code elements and data code elements (e.g., k=15 in the data processing method of the present disclosure vs. k=11 in the RS code), and is easily extensible (e.g., the possible values ​​of k and m in the data processing method of the present disclosure are more flexible (e.g., k may be 15, 14, 13, 12, 11, etc.).

[0072] Therefore, the data processing method according to at least one embodiment of the present disclosure is based on a Vandermonde type matrix, which can support more check code elements and data code elements than the RS code, and has a higher code rate, which improves error correction capability and makes it easier to scale. However, the embodiments are not limited thereto, and the above-mentioned encoding and decoding may be realized by other methods.

[0073] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the encoding matrix may include a first section that may include an identity matrix with k rows and k columns, and a second section that may include a Vandermonde type matrix with m rows and k columns, and the step of encoding k data code elements based on the encoding matrix to obtain encoded data may include a step of multiplying the k data code elements with an identity matrix with k rows and k columns to obtain k data code elements, and a step of multiplying the k data code elements with a Vandermonde type matrix with m rows and k columns to obtain m check code elements. In this way, according to the processing method of at least one embodiment of the present disclosure, multiple types of encoding matrices can be formed, so that the flexibility of the formed encoding matrix can be improved. It should be understood that the encoding matrix may additionally include other sections, and the other sections can be set to 0 or 1 or other suitable values ​​without affecting the realization of the above-mentioned encoding.

[0074] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the identity matrix with k rows and k columns of the first partition may be distributed to any k+m rows of the encoding matrix, and the Vandermonde type matrix with m rows and k columns of the second partition may be distributed to any k+m rows of the encoding matrix, and the positions of the first partition and the second partition are not crossed. In this way, according to the processing method of at least one embodiment of the present disclosure, each row of the identity matrix and the Vandermonde type matrix can be flexibly distributed in the encoding matrix.

[0075] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the k-row, k-column identity matrix of the first partition may be distributed in the first k rows of the encoding matrix, and the m-row, k-column Vandermonde type matrix of the second partition may be distributed in the k+1-th to k+m-th rows of the encoding matrix. In this way, the structure of the encoding matrix formed by the processing method according to at least one embodiment of the present disclosure is simple. Of course, the embodiment is not limited thereto, and the positions of the identity matrix and the Vandermonde type matrix in the embodiment may be interchanged, so that the structure of the encoding matrix formed is similarly simple.

[0076] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the decoding matrix may include a third section that may include a Vandermonde type matrix with m rows and k columns, and a fourth section that may include an identity matrix with m rows and m columns, and the step of decoding the readback encoded data based on the decoding matrix to obtain the syndrome data may include a step of multiplying the k readback data code elements and the m readback check code elements using the decoding matrix to obtain the syndrome data. In this way, according to the processing method of at least one embodiment of the present disclosure, multiple types of decoding matrices can be formed, and the flexibility of the formed decoding matrix is ​​improved. It should be understood that the decoding matrix may additionally include other sections, and the other sections can be set to 0 or 1 or other suitable values ​​without affecting the realization of the above-mentioned decoding.

[0077] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the Vandermonde type matrix with m rows and k columns of the third partition may be distributed to any k+m columns of the decoding matrix, and the identity matrix with m rows and m columns of the fourth partition may be distributed to any k+m columns of the decoding matrix, and the positions of the third partition and the fourth partition are not crossed. In this way, according to the processing method of at least one embodiment of the present disclosure, each row of the identity matrix and the Vandermonde type matrix can be flexibly distributed in the decoding matrix.

[0078] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the Vandermonde type matrix with m rows and k columns of the third partition may be distributed in the first k columns of the encoding matrix, and the identity matrix with m rows and m columns of the fourth partition may be distributed in the k+1th to k+mth columns of the encoding matrix. In this way, the structure of the decoding matrix formed by the processing method according to at least one embodiment of the present disclosure is simple. Of course, the embodiment is not limited thereto, and the positions of the identity matrix and the Vandermonde type matrix in the embodiment may be interchanged, so that the structure of the decoding matrix formed is similarly simple.

[0079] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the step of obtaining the error-corrected code elements using the syndrome data includes the steps of: reading the syndrome data; and outputting k readback data code elements as the error-corrected code elements in response to the syndrome data being all 0, where the syndrome data being all 0 may indicate that the k readback data code elements and the m readback check code elements are error-free; and outputting the k readback data code elements as the error-corrected code elements in response to the syndrome data having one 1, where the syndrome data having one 1 indicates that the k readback data code elements are error-free and the m readback check code elements are error-free. and performing error correction on erroneous code elements among the k readback data code elements and the m readback check code elements using the syndrome data in response to v 1s in the syndrome data to obtain error-corrected code elements, where v 1s in the syndrome data may indicate that v1 readback data code elements corresponding to the syndrome data that is 1 out of the k readback data code elements have errors, and v2 readback check code elements corresponding to the syndrome data that is 1 out of the m readback check code elements have errors, where v≧2, v1≦m, v2≦m, v1+v2=v. In this way, according to the processing method according to at least one embodiment of the present disclosure, it is possible to determine whether an error has occurred in the readback data code elements and the readback check code elements and to determine the location of the error based on the obtained syndrome data.

[0080] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the step of performing error correction on the erroneous code elements among the k readback data code elements and the m readback check code elements to obtain error-corrected code elements using the syndrome data may include the steps of identifying error positions and error values ​​of the erroneous code elements among the k readback data code elements and the m readback check code elements using the syndrome data, and performing error correction on the erroneous code elements using the error positions to obtain error-corrected code elements. In this way, according to the processing method according to at least one embodiment of the present disclosure, error correction can be performed on the erroneous code elements in the readback data code elements and the readback check code elements based on the obtained syndrome data.

[0081] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the step of identifying error locations and error values ​​of erroneous code elements of the k readback data code elements and the m readback check code elements using the syndrome data includes: 1) a dual data code element error correction operation that may include the steps of constructing a quadratic or higher order equation using syndrome data, and determining an error location and an error value based on the quadratic or higher order equation; 2) assuming that the value of the single check code element is an error, and determining an error location and an error value based on the equality of a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data; and 3) determining an error location and an error value based on the ratio relationship between the syndrome data and the ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data being equal.

[0082] The syndrome data may include information indicating that the error is a double data code element error, a single data code element and single check code element error, or a single data code element error, and an error location and an error value can be obtained by an operation corresponding to each of these errors (for example, the above operations 1) to 3). For example, if the error is a double data code element error, the error location and error value can be obtained by the above operation 1), but in this case, the above operations 2) and 3) may be unsolved. For example, if the error is a single data code element and single check code element error, the error location and error value can be obtained by the above operation 2), but in this case, the above operations 1) and 3) may be unsolved. For example, if the error is a single data code element error, the error location and error value can be obtained by the above operation 3), but in this case, the above operations 1) and 2) may be unsolved.

[0083] In the above embodiment, in order to determine the error location and error value of the erroneous code elements in the k readback data code elements and the m readback check code elements using the syndrome data, the above operations 1) to 3) can be performed simultaneously to cover, for example, possible correctable errors and uncorrectable errors (e.g., two erroneous code elements), providing the applicability of the processing method of at least one embodiment of the present disclosure to various error scenes, for example, correctable errors and uncorrectable errors. However, it should be understood that the embodiment is not limited thereto, and only a part of the above operations 1) to 3) may be performed, for example, only the above operation 3) may be performed in a specific error scene, for example, in an error scene where correctable errors occur frequently.

[0084] In this way, the processing method according to at least one embodiment of the present disclosure can realize the construction of quadratic or higher order equations based on Vandermonde type matrices, and can realize the rapid determination of error locations and error values ​​of erroneous code elements. In some embodiments, the quadratic or higher order equations may be quadratic equations. However, the embodiments are not limited thereto, and the syndrome data may be used to construct other equations (e.g., cubic equations, etc.) or combinations of different types of equations (e.g., combinations of quadratic and cubic equations, etc.). The syndrome data may also be used to determine error locations and error values ​​in ways other than equations (e.g., look-up tables, etc.).

[0085] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the quadratic or higher degree equation may be a quadratic equation, p=2, m=4, and the syndrome data may be (s0, s1, s2, s3); Here, the step of constructing a quadratic or higher order equation using syndrome data is quadratic equation JPEG2025504734000035.jpg624, where: JPEG2025504734000036.jpg2635, Here, the step of determining the error location and the error value based on a quadratic or higher degree equation includes: Depending on whether a is non-zero, JPEG2025504734000037.jpg929, and the quadratic equation is converting the image to JPEG2025504734000038.jpg626; obtaining two roots y and y' of JPEG2025504734000039.jpg626; obtaining error positions x and x' as JPEG2025504734000040.jpg967; Using error location and syndrome data, error value JPEG2025504734000041.jpg65 and and calculating JPEG2025504734000042.jpg67, where JPEG2025504734000043.jpg1831, Here, the step of determining an error location and an error value on the assumption that the value of a single check code element is an error and based on the equality of a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data, includes: Assume that the value of the test internal memory chip ecc0 corresponding to s0 is false; Based on JPEG2025504734000044.jpg925, the error location is x and the internal memory chip ecc0 is inspected, and the error value is JPEG2025504734000045.jpg96 and JPEG2025504734000046.jpg920; Assume that the value of the test internal memory chip ecc1 corresponding to s1 is false; Based on JPEG2025504734000047.jpg943, the error location is x and the internal memory chip ecc1 is inspected, and the error value is s0 and JPEG2025504734000048.jpg634; Assume that the value of the test internal memory chip ecc2 corresponding to s2 is false; Based on JPEG2025504734000049.jpg1143, the error location is x and the internal memory chip ecc2 is inspected, and the error value is s0 and JPEG2025504734000050.jpg735; Assume that the value of the test internal memory chip ecc3 corresponding to s3 is false; Based on JPEG2025504734000051.jpg1026, the error location is x and the internal memory chip ecc3 is inspected, and the error value is s0 and and calculating that the image is JPEG2025504734000052.jpg635; Here, the step of determining the error location and the error value based on the fact that the ratio relationship between the syndrome data and the ratio relationship between the elements of the Vandermonde type matrix corresponding to the syndrome data are equal to each other includes the steps of: The method may include calculating, based on JPEG2025504734000053.jpg1037, that the error location is x and the error value is s0. In this way, according to at least one embodiment of the processing method of the present disclosure, a quadratic equation is constructed under the finite field GF(2n), and four check code elements can be used to realize simultaneous error correction of two symbol positions. In contrast, an error correction method based on RS code cannot obtain a solution for two error positions, and therefore cannot realize the construction of the quadratic equation, for example, and cannot realize simultaneous error correction of two symbol positions.

[0086] It should be understood that the above embodiment is not limited thereto, and the error correction of two symbol positions or the error correction of other number of symbol positions can be realized by other finite fields and other number of check code elements. For example, when m=3, the error correction of two adjacent symbol positions (for example, if the first symbol position is j, the second symbol position is j+1) can be realized, since only three equations are needed to obtain two adjacent symbol positions and two corresponding error values. Furthermore, the error correction of two symbol positions can be realized by other types of equations (for example, cubic equations, combination of quadratic and cubic equations, etc.) or other solving methods (for example, look-up tables, etc.).

[0087] In some embodiments, a processing method according to at least one embodiment of the present disclosure includes: The step of obtaining the two roots y and y' of JPEG2025504734000054.jpg722 is done by mathematical operations: Find the solution for JPEG2025504734000055.jpg722, Obtaining the two roots y and y' of JPEG2025504734000056.jpg722, or by looking up a table, The method may include a step of obtaining two roots y and y′ of JPEG2025504734000057.jpg722. In this manner, according to at least one embodiment of the present disclosure, By providing a flexible method for finding the two roots y and y' of JPEG2025504734000058.jpg722, it is possible to easily realize the determination of the error location and the error value.

[0088] For example, a lookup table is expected to store u, y and y', and corresponding y and y' can be obtained based on u. The method based on the lookup table can realize the quick determination of y and y', which contributes to the speedup of determining the error location and the error value.

[0089] In some embodiments, the processing method according to at least one embodiment of the present disclosure performs a mathematical operation to Find the solution for JPEG2025504734000059.jpg722, The step of obtaining the two roots y and y' of JPEG2025504734000060.jpg722 is to perform an exclusive OR operation on u. Find the solution for JPEG2025504734000061.jpg722, The method may include a step of obtaining two roots y and y' of JPEG2025504734000062.jpg722. In this manner, according to at least one embodiment of the processing method of the present disclosure, y and y' can be obtained by an exclusive OR operation. However, the embodiment is not limited thereto, and y and y' may be obtained by other logical operations.

[0090] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, y and u may both be 8-bit finite field numbers, where by performing an exclusive-or operation on u: The steps to solve JPEG2025504734000063.jpg722 are: Y0=not Y0', or Y0' xor 1, Y1=Y1', Y2=Y2', Y3=Y3', Y4=Y4', Y5=Y5', Y6=Y6', Y7=Y7', and Y7=U0 xor U1 xor U2 xor U4, Y6= U0 xor U1 xor U2 xor U4 xor U7, Y5= U1 xor U2 xor U3 xor U4 xor U6, Y4 = U0 xor U7, Y3 = U1 xor U2 xor U3 xor U4, Y2 = U0 xor U3 xor U4 xor U6, Y1 = U0 xor U2 xor U4, Y0 = U3 xor U6, U5=Tr(u), where U0 through U7 represent the 0th through 7th bits of u, respectively. Y0 through Y7 represent the 0th through 7th bits of y, respectively. Y0' through Y7' represent the 0th bit through the 7th bit of y', respectively. Tr(u) is This indicates whether there is a solution for JPEG2025504734000064.jpg722, where Tr(u) = 1 indicates that there is no solution and Tr(u) = 0 indicates that there is a solution.

[0091] In this way, according to at least one embodiment of the present disclosure, for an 8-bit finite field number, two roots y and y' can be obtained based on the above specific logical operations. However, the embodiment is not limited thereto, and two roots y and y' may be obtained for other bit numbers and based on other logical operations.

[0092] In some embodiments, the processing method according to at least one embodiment of the present disclosure further includes performing error correction on the m readback check code elements using the syndrome data in response to the syndrome data having one 1. In this manner, the processing method according to at least one embodiment of the present disclosure may perform error correction on the erroneous check code element among the readback check code elements.

[0093] In some embodiments, according to the processing method according to at least one embodiment of the present disclosure, the step of obtaining an error-corrected code element using syndrome data is similar to obtaining an error-corrected code element using syndrome data in a related art error correction method based on RS code.

[0094] Corresponding to the data processing method according to at least one embodiment of the present disclosure, the present disclosure further provides a data processing device.

[0095] 2 is a schematic diagram of a data processing device 200 in accordance with at least one embodiment of the present disclosure. As shown in FIG. 2, the processing device 200 includes a reading module 210 and a decoding module 220.

[0096] The reading module 210 is configured to read two burst data from the first storage channel and the second storage channel respectively to obtain four burst data, the four burst data corresponding to the encoded data stored in the first storage channel and the second storage channel, the encoded data being obtained by encoding k data code elements written in the first storage channel and the second storage channel, the encoded data including the k data code elements and m check code elements, a total bit width of the m check code elements being eight times the bit width of one error correction code element, and to organize the four burst data into a set of error correction code words including k readback data code elements and m readback check code elements.

[0097] The decoding module 200 is configured to perform a decoding operation based on the set of error-correcting code words to obtain error-corrected code elements.

[0098] In this manner, according to at least one embodiment of the data processing apparatus 200 of the present disclosure, simultaneous error correction of two code elements or symbols is realized by reading two burst data from two storage channels respectively.

[0099] The above describes only a portion of the data processing device 200 according to at least one embodiment of the present disclosure in relation to FIG. 2. The remaining portion of the data processing device 200 may refer to each aspect of the data processing method 100 described in relation to FIG. 1 of the present disclosure, and the effects of each aspect of the data processing method 100 described in relation to FIG. 1 of the present disclosure may similarly be mapped to the data processing device 200 described in relation to FIG. 2 of the present disclosure, and description thereof will be omitted here.

[0100] For example, the data processing device 200 according to at least one embodiment of the present disclosure may alternatively or additionally include an encoding module to perform the above-mentioned encoding. Also, for example, the data processing device 200 according to at least one embodiment of the present disclosure may further include an error correction module to perform the above-mentioned error correction operation.

[0101] Hereinafter, exemplary application scenarios of encoding / decoding that can utilize a data processing method or processing device according to at least one embodiment of the present disclosure will be described with reference to Figures 3 to 8. It should be understood that the application scenarios shown in Figures 3 to 8 do not exhaustively list each aspect of the data processing method or processing device described above, but are merely illustrative, and that each aspect described in relation to Figures 3 to 8 and the aspects described in relation to Figures 1 and 2 can be mutually referenced without going beyond the scope of the present disclosure.

[0102] In an exemplary application scenario of this encoding / decoding, a method is possible to simultaneously correct two symbol positions based on the Vandermonde matrix. For example, in the case of a DDR internal memory, the structure of this method can be used to simultaneously correct uncorrectable errors that occur in the DDR internal memory.

[0103] An exemplary application scenario of this encoding / decoding may include an encoding module, a decoding module, and an error correction module.

[0104] FIG. 3 is a schematic diagram of an encoding module 300 in accordance with at least one embodiment of the present disclosure.

[0105] 3, the input of the encoding module 300 is a data code element 302, and the output is a data code element and a check code element 304. The output data code element and check code element 304 are stored in the internal memory chip through a DDR internal memory channel after a certain mapping is performed.

[0106] In the encoding module, an encoding operation can be performed. In the encoding operation, a Vandermonde matrix is ​​multiplied by data code elements to obtain m check code elements, where both multiplication and addition are finite field operations. If there are k data code elements, the encoding matrix has (k+m) rows and k columns. The first k rows of the encoding matrix are an identity matrix, and the last m rows of the encoding matrix are a Vandermonde matrix, which is multiplied by the data code elements to obtain m check code elements.

[0107] FIG. 4 is a schematic diagram of an encoding operation 400 according to at least one embodiment of the present disclosure, where k=8, m=4, a is a polynomial representation of a finite field element, and a=2. Referring to FIG. 4, the encoding matrix (the matrix on the left side of FIG. 4) has 12 rows and 8 columns. The first 8 rows of the encoding matrix are an identity matrix, i.e., all data code elements are directly transmitted without processing. The last 4 rows of the encoding matrix are a Vandermonde matrix. The encoding matrix is ​​multiplied with the data code element (the matrix in the middle of FIG. 4) to obtain the encoding matrix (the matrix on the right side of FIG. 4). The encoded data includes the data code element and the four data code elements (c0 to c3) obtained by encoding.

[0108] It should be understood that k=8, m=4 and other parameters in FIG. 4 and described below in relation to FIG. 5 to FIG. 8 are exemplary only, and the values ​​of k, m and other parameters may be adjusted according to actual needs (e.g., k=16 in the example described below with reference to FIG. 9A to 9C), and the encoding matrix, decoding matrix, etc. may be modulated and extended accordingly.

[0109] FIG. 5 is a schematic diagram of a decoding module 500 and an error correction module 550 in accordance with at least one embodiment of the present disclosure.

[0110] Referring to FIG. 5, the input of the decoding module 500 is a data code element and a check code element 510 obtained by converting stored data read from a DDR internal memory channel (e.g., corresponding to the readback encoded data described above) via the same mapping as the encoding module.

[0111] A decoding operation can be performed in the decoding module 500. In the decoding operation, a decoding matrix is ​​used to multiply the read k data code elements (e.g., corresponding to the above k readback data code elements) by the read m check code elements (e.g., corresponding to the above m readback check code elements) to obtain m syndromes s0, s1, s2,..., s3 (e.g., corresponding to the above syndrome data).

[0112] FIG. 6 is a schematic diagram of a decoding operation 600 according to at least one embodiment of the present disclosure, where k=8, m=4, a is a polynomial expression of a finite field element, and a=2. Referring to FIG. 6, the decoding matrix is ​​a 4-row, 12-column matrix, the left 8 columns are the same Vandermonde matrix used in the encoding module, and the right 4 columns are an identity matrix. FIG. 6 shows the process of the decoding operation of 8 data d0 to d7 and 4 check code elements c0 to c3, and the finally obtained 4 syndromes s0, s1, s2 and s3 are all 0, which indicates that there is no error in the read stored data.

[0113] Continuing to refer to FIG. 5, the input of the error correction module 550 is the output of the decoding module (ie, the m syndromes) and the output is the corrected data code elements (which may include corrected check code elements) 520.

[0114] Error correction calculation can be performed in the error correction module 550. In the following, the error correction calculation will be described using an example where k=8, m=4, a is a polynomial expression of a finite field element, and a=2.

[0115] In the error correction calculation, the error symbol position and value are calculated using the features of the syndrome (s0, s1, s2, s3), and the specific steps are as follows: Step 1. Read syndromes (s0,s1,s2,s3). Step 2. If (s0, s1, s2, s3) are all 0, it indicates that there are no errors in any of the read data code elements and check code elements, and proceed to step 6; otherwise, proceed to step 3. Step 3. If three of (s0, s1, s2, s3) are 0, i.e., if one of (s0, s1, s2, s3) is 1, it indicates that an error has occurred in one check code element, i.e., it indicates that an error has occurred in the corresponding check chip (ecci, i is 0 to 3), and proceed to step 6; otherwise, proceed to step 4. Step 4. Perform the following six operations a) to f) on (s0, s1, s2, s3) and then proceed to step 5. Operation a) Double data error correction operation (2 data error correction), Operation b) Data and ECC0 error correction operation (data & ECC0 error correction), Operation c) Data and ECC1 error correction operation (data & ECC1 error correction), Operation d) Data and ECC2 error correction operation (data & ECC2 error correction), E) Data and ECC3 error correction calculations (data & ECC3 error correction), Operation f) Single data error correction operation. All of the above operations a) to f) output whether or not there is a solution, the error location, and the error value. Step 5: After performing error correction using the error location solved by the calculation, the data code element is output and the process ends. Step 6. Output the data code element directly and finish.

[0116] The calculations a) to f) will be explained in detail below.

[0117] In the following, operation a) double data error correction operation will be described.

[0118] 7 is a schematic diagram of a double data error correction operation 700 in accordance with at least one embodiment of the present disclosure. The double data error correction operation is described below with reference to FIG.

[0119] First, calculate a, b, and c using syndrome (s0, s1, s2, s3), and the calculation formula is: JPEG2025504734000065.jpg2335, Quadratic equations in finite fields using a, b, and c We can construct JPEG2025504734000066.jpg724. If a is 0, this module has no solution. If a is not 0, JPEG2025504734000067.jpg929, the equation is: It can be converted to JPEG2025504734000068.jpg726, Then, we can directly check whether the quadratic equation can be solved, and obtain the values ​​of y and y' (intermediate variables) by exclusive OR operation. In the following, we will describe the specific process of obtaining the values ​​of y and y' (intermediate variables) by exclusive OR operation in relation to Figure 8.

[0120] and, For JPEG2025504734000069.jpg965, obtain the error positions x and x', and use the error positions and syndromes to calculate the error value JPEG2025504734000070.jpg66 and JPEG2025504734000071.jpg67 is calculated, where The image is JPEG2025504734000072.jpg1831.

[0121] FIG. 8 illustrates a quadratic equation in a finite field according to at least one embodiment of the present disclosure. 8 is a schematic diagram 800 for solving JPEG2025504734000073.jpg750. In FIG. 8, y and u are both 8-bit finite field numbers.

[0122] Referring to Figure 8, U0 to U7 on the left side are inputs, where U0 to U7 represent the 0th bit to the 7th bit of u, respectively. Y0 to Y7 and Y0' to Y7' on the bottom side are outputs. The two roots of JPEG2025504734000074.jpg622 are y and y', where Y0 to Y7 represent the 0th to 7th bits of y, respectively, and Y0' to Y7' represent the 0th to 7th bits of y', respectively; Y0 to Y7 and Y0' to Y7' satisfy the following relationship. Y0 = not Y0' (or Y0'xor 1, note that inversion is equivalent to exclusive-oring with 1) Y1=Y1', Y2=Y2', Y3=Y3', Y4=Y4', Y5=Y5', Y6=Y6', Y7=Y7', Tr(u) is This indicates whether or not there is a solution to JPEG2025504734000075.jpg622. If Tr(u) = 1, there is no solution to the equation, if Tr(u) = 0, there is a solution to the equation, and if 8 bits are the code element, then Tr(u) = U5. With u=24, Calculating the two roots of JPEG2025504734000076.jpg624, U3=1, U4=1, U0, U1, U2, U5, U6, U7=0, U5=Tr(u)=0, there is a solution to the equation, and Y7=U0 xor U1 xor U2 xor U4, Y6=U0 xor U1 xor U2 xor U4 xor U7, Y5=U1 xor U2 xor U3 xor U4 xor U6, Y4=U0 xor U7, Y3=U1 xor U2 xor U3 xor U4, Y2=U0 xor U3 xor U4 xor U6, Y1=U0 xor U2 xor U4, Y0=U3 xor U6, Therefore, we can calculate y[7:0]=8'b11000011=195, and by flipping the last bit (the flip between Y0 and Y0' in Figure 8), we get y'[7:0]=8'b11000010=194, where 195 and 194 are These are the two roots of JPEG2025504734000077.jpg624.

[0123] In the above, in relation to FIG. 8, the mathematical operation method is used to solve the quadratic equation in a finite field. JPEG2025504734000078.jpg622 has been described. However, the embodiment is not limited to this, and the method of solving a quadratic equation in a finite field using a lookup table may be used. We may solve JPEG2025504734000079.jpg622. For example, if u is equal to 24, we look up the 24th entry in the lookup table, which contains the values ​​of y and y' (because the last bits of y and y' are reversed, we only need to store 7 bits of y[7:1], not 16 bits, since we read it from the table and fill it with 0s or 1s to get y and y').

[0124] The following describes operation b) data and ecc0 error correction operations.

[0125] This operation assumes that the value of ecc0 is incorrect, For JPEG2025504734000080.jpg925, the error positions are x and ecc0, and the error values ​​are JPEG2025504734000081.jpg95 and The result is JPEG2025504734000082.jpg920.

[0126] The following describes operation c) data and ecc1 error correction operations.

[0127] This operation assumes that the value of ecc1 is incorrect, If it is JPEG2025504734000083.jpg1042, the error positions are x and ecc1, and the error values ​​are s0 and The result is JPEG2025504734000084.jpg635.

[0128] The following describes operation d) data and ECC2 error correction operations.

[0129] This operation assumes that the ecc2 value is incorrect, If the image is JPEG2025504734000085.jpg943, the error positions are x and ecc2, and the error values ​​are s0 and The result is JPEG2025504734000086.jpg634.

[0130] In the following, operation e) data and ecc3 error correction operations are described.

[0131] This operation assumes that the ecc3 value is incorrect, If it is JPEG2025504734000087.jpg925, the error location is x and ecc3, and the error value is s0 and The result is JPEG2025504734000088.jpg633.

[0132] In the following, operation f) single data error correction operation will be described.

[0133] For JPEG2025504734000089.jpg937, the error position is x and the error value is s0.

[0134] The above operations a) to f) only perform error correction of a single data code element, while error correction of a single check code element may be performed by step 3.

[0135] In this exemplary application scenario of the encoding / decoding, the Vandermonde matrix can be used to simultaneously correct errors in two symbol positions. In an additional embodiment, if an error occurs in only one symbol, the same matrix can be used to correct it, so there is no need to change the algorithm. In the exemplary application scenario of the encoding / decoding, for example, the error correction capability of the DDR internal memory can be effectively improved, and the reliability of the internal memory can be improved.

[0136] For example, in this exemplary application scenario of encoding / decoding, four check code elements can be used to correct simultaneous errors in any one or two code elements. For example, in this exemplary application scenario of encoding / decoding, if an error occurs in only one position, the accuracy rate of correction can reach 100%. For example, in this exemplary application scenario of encoding / decoding, the problem of UE being reported due to simultaneous errors in two positions can be solved, and data loss can be avoided. For example, in this exemplary application scenario of encoding / decoding, if the accuracy of the ECC chip is guaranteed, the accuracy rate of correcting errors in two random data code elements can also reach 100%, that is, there is a solution for many of the above six situations.

[0137] For example, in this exemplary application scenario of the encoding / decoding, the solution of the quadratic equation constructed based on the Vandermonde matrix can be quickly obtained, providing the speed of finding two (symbol positions where errors occur) solutions simultaneously and arbitrarily (for code element positions). For example, in this exemplary application scenario of the encoding / decoding, by utilizing the characteristics of quadratic equations in finite fields, the number of errors can be quickly determined, and whether the error positions contain check chips can be determined, thereby improving the probability of correcting errors. For example, in this exemplary application scenario of the encoding / decoding, operations a) to f) can be performed in parallel during error correction to obtain all possible error positions and error values.

[0138] In an additional aspect of this encoding / decoding example application scenario, the encoding matrix may be permuted, for example, the Vandermonde matrix therein may be replaced with a series of transformations of the Vandermonde matrix, such as left-right flip, up-down flip, transpose, etc. operations.

[0139] In an additional aspect of this exemplary encoding / decoding application scenario, it can be realized using code elements of any bit. For example, in GF(2 n ), Table 2 shows the upper limit of the bit width and number of code elements according to at least one embodiment of the present disclosure.

[0140] TIFF2025504734000090.tif21130

[0141] As can be seen from Table 2, the bit width of the data code element and the check code element do not have to be the same. For example, the data code element is not limited to the bit width of the data internal memory chip, and may be larger than the bit width of the data internal memory chip. For example, if two errors need to be corrected in six 4-bit data code elements, the error correction code can be written in GF(2 4) and can generate four 4-bit check code elements, forming a total bit width of 24+16. 5 ) may be defined above, and four 5-bit check code elements may be generated by padding each 4-bit data code element with a zero to obtain a 5-bit data code element (which provides even greater error correction capability), resulting in a total bit width of 24+20.

[0142] The above-mentioned exemplary application scenarios of the encoding / decoding only realize some or additional aspects of the data processing method and processing device according to at least one embodiment of the present disclosure, and other aspects of the above-mentioned exemplary application scenarios of the encoding / decoding can refer to the data processing method and processing device according to at least one embodiment of the present disclosure and its additional aspects.

[0143] In an exemplary application scenario of this encoding / decoding, a method is possible to simultaneously correct two symbol positions based on the Vandermonde matrix. For example, in the case of a DDR internal memory, the structure of this method can be used to simultaneously correct uncorrectable errors that occur in the DDR internal memory.

[0144] In the following, an exemplary application scenario example of the check code word (ECC word) organization using the data processing method or processing device according to at least one embodiment of the present disclosure will be described in combination with Figures 9A to 8. It should be understood that the application scenarios shown in Figures 9A to 9C are not exhaustive but merely exemplary of each aspect of the data processing method or processing device described above, and each aspect described in relation to Figures 9A to 9C and each aspect described in relation to Figures 1 and 2, and Figures 3 to 8 can be mutually referred to without going beyond the scope of the present disclosure.

[0145] In an exemplary application scenario for organizing the ECC words, a set of ECC words can be obtained, which includes data code elements and check code elements, and these data code elements and check code elements correspond to the data code elements and check code elements in the exemplary application scenarios of encoding / decoding described above, for example, in relation to Figures 3 to 8, thereby realizing corresponding encoding / decoding functions, and finally realizing simultaneous error correction of two code elements.

[0146] In the exemplary application scenario of organizing the ECC word, the memory is embodied as a DDR internal memory including two internal memory channels Ch0 and Ch1, and the bit width of the internal memory chip (data internal memory chip and test internal memory chip ecc) included in each internal memory channel is 4 bits. It should be understood that the embodiment is not limited thereto, and other variations may exist.

[0147] Fig. 9A is a schematic diagram of an internal memory in the case of one fixed error + one random error, according to at least one embodiment of the present disclosure; Fig. 9B is a schematic diagram of an internal memory in the case of two fixed errors, according to at least one embodiment of the present disclosure; Fig. 9C is a schematic diagram of an internal memory in the case of two random errors, according to at least one embodiment of the present disclosure;

[0148] An exemplary manner in which ECC words may be organized is described below with respect to Figure 9A. Referring to Figure 9A, the internal memory may include a lockstep, an internal memory channel Ch0 and an internal memory channel Ch1.

[0149] First, in order to realize synchronous operations, such as writing and reading, between the internal memory channel Ch0 and the internal memory channel Ch1, a memory lock synchronization function is activated.

[0150] In an exemplary data write process, one piece of data is written to the internal memory channel Ch0 and the memory channel Ch1, for example, through the encoding process described above, that is, the write operation of the data to be written to the internal memory channel Ch0 and the internal memory channel Ch1 is realized synchronously. For example, one piece of data is, for example, 256 bits, and the first 128 bits are written to the internal memory channel Ch0, for example, in four burst data, and the last 128 bits are written to the memory channel Ch1, for example, in four burst data. It should be understood that this is only an example, and the above-mentioned one piece of data may include other numbers of bits or may be written to other numbers of burst data. In addition, the writing of data may continue to be written, for example, in the case of FIG. 9A, half of the write data may be written to the internal memory channel Ch0, and the other half may be written to the internal memory channel Ch1.

[0151] In an exemplary data read process, two burst data are read from the internal memory channel Ch0 and the internal memory channel Ch1, respectively, i.e., two burst data Burst0 and Burst1 are read from the internal memory channel Ch0, and two burst data Burst0 and Burst1 are read from the internal memory channel Ch1. Here, the four burst data correspond to the data code elements and check code elements generated by encoding the above-mentioned written data based on, for example, the Vandermonde type matrix as described above.

[0152] An exemplary configuration structure of an ECC word may be as follows:

[0153] Symbol 0 is D0 of Burst 0 of the first x4 data internal memory chip of ch0 and D16 of Burst 1 of the first x4 data internal memory chip of ch0. The two data together are 8 bits and constitute one symbol, i.e., symbol 0. Symbol 1 is D1 of Burst 0 of the second x4 data internal memory chip of ch0 and D17 of Burst 1 of the second x4 data internal memory chip of ch0. The two data together are 8 bits, which constitute one symbol, i.e., symbol 1. Symbol 2 is D2 of Burst0 of the third x4 data internal memory chip of ch0 and D18 of Burst1 of the third x4 data internal memory chip of ch0. The two data together are 8 bits, which constitute one symbol, i.e., symbol 2. Symbol 3 is D3 of Burst 0 of the 4th x4 data internal memory chip of ch0 and D19 of Burst 1 of the 4th x4 data internal memory chip of ch0. The two data together are 8 bits, which constitute one symbol, i.e., symbol 3. … Symbol 7 is D7 of Burst0 of the 8th x4 data internal memory chip of ch0 and D23 of Burst1 of the 8th x4 data internal memory chip of ch0. The two data together are 8 bits, which constitute one symbol, i.e., symbol 7. Symbol 8 is D8 of Burst0 of the first x4 data internal memory chip of ch1 and D24 of Burst1 of the first x4 data internal memory chip of ch1. The two data together are 8 bits, which constitute one symbol, i.e., symbol 8. Symbol 9 is D9 of Burst0 of the second x4 data internal memory chip of ch1 and D25 of Burst1 of the second x4 data internal memory chip of ch1. The two data are 8 bits in total, constituting 9 symbols, i.e., symbol 1. Symbol 10 is D10 of Burst0 of the 3rd x4 data internal memory chip of ch1 and D26 of Burst1 of the 3rd x4 data internal memory chip of ch1. The two data together are 8 bits and constitute one symbol, i.e., symbol 10. Symbol 11 is D11 of Burst0 of the 4th x4 data internal memory chip of ch1 and D27 of Burst1 of the 4th x4 data internal memory chip of ch1. The two data together are 8 bits, which constitute one symbol, i.e., symbol 11. … Symbol 15 is D15 of Burst 0 of the 8th x4 data internal memory chip of ch1 and D31 of Burst 1 of the 8th x4 data internal memory chip of ch1, and these two pieces of data together are 8 bits and constitute one symbol, i.e., symbol 15.

[0154] Similar to the data internal memory chip, the two burst data of two x4 checks on Ch0 and Ch1 each constitute four check code symbols (ecc symbols) as follows: Symbol 16 is C0 of Burst 0 of the first x4 inspection internal memory chip of ch0 and C4 of Burst 1 of the first x4 inspection internal memory chip of ch0. The two inspection codes together are 8 bits, which constitute one symbol, i.e., symbol 16. Symbol 17 is C1 of Burst 0 of the second x4 inspection internal memory chip of ch0 and C5 of Burst 1 of the second x4 inspection internal memory chip of ch0. The two inspection codes together are 8 bits, which constitute one symbol, i.e., symbol 17. Symbol 18 is C2 of Burst0 of the first x4 inspection internal memory chip of ch1 and C6 of Burst1 of the first x4 inspection internal memory chip of ch1. The two inspection codes together are 8 bits, which constitute one symbol, i.e., symbol 18. Symbol 19 is C3 of Burst 0 of the second x4 inspection internal memory chip of ch1 and C7 of Burst 1 of the second x4 inspection internal memory chip of ch0. The two inspection codes together are 8 bits, which constitute one symbol, i.e., symbol 19. A set of ECC words thus formed is 16 data symbols+4 check symbols, for a total of 128 bits of data information and a total of 32 bits of check information.

[0155] The ECC words organized in the above-mentioned manner can achieve a decoding operation using, for example, the Vandermonde matrix algorithm described in relation to Figures 3 to 8 to achieve a single ECC calculation, and can simultaneously correct a situation in which errors occur in two internal memory chips at the same time, without the need to use a method of replacing an internal memory chip as in DDDC.

[0156] For an example scene in which errors occur simultaneously in two internal memory chips, please refer to FIG. 9A to FIG. 9C.

[0157] 9A, there is one fixed error + one random error, and a fixed error occurs in the 4th data internal memory chip in Ch0 (represented as the 4th data internal memory chip is broken and causes errors D3 and D19), and a random error occurs in the 7th data internal memory chip in Ch0 (represented as causing an error D6). The fixed error and the random error may be in the same internal memory channel, or may be in two internal memory channels, respectively.

[0158] 9B, there is shown a case where there are two fixed errors, a fixed error occurs in the fourth data internal memory chip in Ch0 (represented as the fourth data internal memory chip is broken and causes errors D3 and D19), and a random error occurs in the seventh data internal memory chip in Ch1 (represented as the seventh data internal memory chip is broken and causes errors D14 and D30). When errors occur in two internal memory chips at the same time, they may occur in the same internal memory channel, or may occur in two internal memory channels.

[0159] 9C, a case where there are two random errors is shown, where a fixed error occurs in the fourth data internal memory chip in Ch0 (causing an error of D3), and a random error occurs in the sixth data internal memory chip in Ch1 (causing an error of D29). When errors occur simultaneously in two internal memory chips, they may occur in the same internal memory channel, or may occur in two internal memory channels, and the random error may be in any one of the two burst data.

[0160] In the above exemplary application scenario, without the need for software involvement, no record of past error correction, or replacement of internal memory chips, only the hardware structure can be used to correct errors when errors occur simultaneously in two data internal memory chips, effectively solving the problem of errors occurring in two internal memory chips and reporting uncorrectable errors, thereby improving the reliability of memory and reducing the risks of data loss and downtime.

[0161] The above-described exemplary application scenarios only realize some or additional aspects of the data processing method and processing device according to at least one embodiment of the present disclosure, and other aspects of the above-described application scenarios may refer to the data processing method and processing device according to at least one embodiment of the present disclosure and its additional aspects.

[0162] 10 is a schematic diagram of a storage system 1000 in accordance with at least one embodiment of the present disclosure. As shown in FIG. 10, the storage system 1000 includes a processing unit 1010 and a storage unit 1020.

[0163] The processing device 1010 may be the processing device 200 described above in connection with FIG. 2, and the storage unit 1020 may be any memory including a first storage channel and a second storage channel associated with the processing device 200 described above in connection with FIG. 2.

[0164] Therefore, for the processing device 200 of each embodiment of the present disclosure, each aspect thereof may be similarly mapped to the storage system 1000 described in relation to FIG. 10, and description thereof will be omitted in this specification.

[0165] FIG. 11 is a schematic diagram of an electronic device 1100 in accordance with at least one embodiment of the present disclosure.

[0166] As shown in FIG. 11, the electronic device 1100 includes a processor 1110 and a memory 1120. The memory 1120 includes one or more computer program modules 1121. The one or more computer program modules 1121 are stored in the memory 1120 and configured to be executed by the processor 1110, and the one or more computer program modules 1121 include instructions for performing the data processing method according to at least one embodiment of the present disclosure, which, when executed by the processor 1110, can perform one or more steps of the data processing method according to at least one embodiment of the present disclosure and additional aspects thereof. The memory 1120 and the processor 1110 may be interconnected via a bus system and / or other types of connection mechanisms (not shown). For example, the bus may be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be classified into an address bus, a data bus, a control bus, etc.

[0167] Illustratively, the processor 1110 may be a central processing unit (CPU), a digital signal processor (DSP), or other type of processing unit having data processing and / or program execution capabilities, such as a field programmable gate array (FPGA), etc. For example, the central processing unit (CPU) may be an X86 or ARM architecture, a RISC-V architecture, etc. The processor 1110 may be a general-purpose processor or a special-purpose processor and may control other components in the electronic device 1100 to perform desired functions.

[0168] Exemplarily, the memory 1120 may include any combination of one or more computer program products, which may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. The computer-readable storage medium may store one or more computer program modules 1121, and the processor 1110 may operate the one or more computer program modules 1121 to realize various functions of the electronic device 1100. The computer-readable storage medium may also store various application programs, various data, and various data used and / or generated by the application programs, etc.

[0169] For example, the electronic device 1100 may further include input devices such as a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyro, etc., may further include output devices such as a liquid crystal display, a speaker, a vibrator, etc., may further include a storage device such as a magnetic tape, a hard disk (HDD or SDD), etc., and may further include a communication device such as a network interface card such as a LAN card, a modem, etc. The communication device may enable the electronic device 1100 to perform wireless or wired communication with other devices to exchange data and perform communication processing via a network such as the Internet, for example. If necessary, a drive is connected to the I / O interface. Removable storage media such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. are mounted in the drive as necessary to facilitate the computer program read from them being installed in the storage device as necessary.

[0170] For example, the electronic device 1100 may further include a peripheral interface (not shown), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices via wireless communication, the network being, for example, a wireless network, such as the Internet, an intranet, and / or a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan network (MAN). The wireless communication may use any one of a number of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or short message service (SMS), or any other suitable communication protocol. The electronic device 1100 may be, for example, a system on chip (SOC) or a device including the SOC, such as a mobile phone, tablet, notebook computer, e-book, game console, television, digital photo frame, navigation device, home appliance, communication base station, industrial controller, server, or any other device, or may be a combination of any data processing device and hardware, and the embodiments of the present disclosure are not limited thereto. The specific functions and technical effects of the electronic device 1100 may refer to the above description of the data processing method and its additional aspects according to at least one embodiment of the present disclosure, and will not be described here.

[0171] FIG. 12 is a schematic diagram of a non-transitory readable storage medium 1200 in accordance with at least one embodiment of the present disclosure.

[0172] As shown in FIG. 12, a non-transitory readable storage medium 1200 stores computer instructions 1210 which, when executed by a processor, perform one or more steps in the data processing method described above and additional aspects thereof.

[0173] As an example, the non-transitory readable storage medium 1200 may be any combination of one or more computer-readable storage media, for example, one computer-readable storage medium including program code for reading two burst data from a first storage channel and a second storage channel respectively to obtain four burst data, program code for organizing the four burst data into a set of error correction code words, and program code for performing a decoding operation based on the set of error correction code words to obtain error-corrected code elements.

[0174] Illustratively, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform, for example, one or more steps of the data processing method according to at least one embodiment of the present disclosure and additional aspects thereof.

[0175] Illustratively, the non-transitory readable storage medium may include, for example, a memory card in a smartphone, a storage component in a tablet, a hard disk in a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), flash memory, and other non-transitory readable storage media, or any combination thereof.

[0176] In the above detailed description, specific details are set forth for purposes of explanation and not limitation to provide a thorough understanding of the various aspects and embodiments described in the present disclosure. In some cases, detailed descriptions of well-known devices, components, circuits, and methods are omitted to avoid obscuring the description of the embodiments disclosed herein with unnecessary detail. The present specification intends to cover both structural and functional equivalents by reciting all statements of the principles, aspects, and embodiments disclosed herein, as well as specific examples thereof. Moreover, such equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure. Thus, for example, it should be understood that block diagrams in the present specification may represent conceptual diagrams of exemplary circuit systems or other functional units that embody the principles of the described embodiments. Such functions and illustrated functional blocks will be understood as being implemented in hardware and / or implemented in a computer.

[0177] The embodiments in this disclosure will be described in an incremental manner, with the focus being on the differences between each embodiment and other embodiments, and reference will be made to similar or similar portions between the embodiments.

[0178] It should be noted that in this text, relational terms such as "first," "second," etc. are used only to distinguish one entity or operation from another and do not necessarily require or imply that such an actual relationship or sequence exists between those entities or operations. Terms such as "comprise," "comprises," or any other variation thereof, imply a non-exclusive inclusion such that a process, method, article, or device of a set of elements includes not only those elements but also other elements not expressly listed or elements inherent to such process, method, article, or device. In the absence of further limitations, an element qualified by the phrase "comprises" does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0179] What has been described above is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, the scope of which is determined by the claims.

Claims

1. a step of reading two burst data from each of a first storage channel and a second storage channel to obtain four burst data, the four burst data corresponding to encoded data stored in the first storage channel and the second storage channel, the encoded data being obtained by encoding k data code elements written in the first storage channel and the second storage channel, the encoded data including the k data code elements and m check code elements, and a total bit width of the m check code elements being eight times the bit width of one error correction code element; organizing the four bursts of data into a set of error correction code words including k readback data code elements and m readback check code elements; performing a decoding operation based on said set of error-correcting code words to obtain error-corrected code elements.

2. Organizing the four bursts of data into the set of error correction code words comprises: Combining the two burst data read from the first memory channel, which correspond to the same memory chip, into one error-correcting code word code element to obtain a first portion of the error-correcting code word; Combining the two burst data read from the second memory channel, which correspond to the same memory chip, into one error-correcting code word code element to obtain a second portion of the error-correcting code word; and combining said first portion of error correcting codewords with said second portion of error correcting codewords.

3. The step of encoding the k data code elements written to the first storage channel and the second storage channel comprises: encoding the k data code elements based on an encoding matrix; performing a decoding operation based on the set of error-correcting code words to obtain error-corrected code elements, decoding the set of error-correcting codewords based on a decoding matrix to obtain syndrome data; obtaining an error-corrected code element using the syndrome data, The encoding matrix is ​​a matrix with at least k+m rows and k columns and comprises a Vandermonde type matrix, and the decoding matrix is ​​a matrix with at least m rows and k+m columns and comprises a Vandermonde type matrix, the Vandermonde type matrix being a matrix related to the Vandermonde matrix, with k≦p ｎ −1, m≦p ｎ 3. A method according to claim 1, further comprising the steps of: n =p p =n p p , n =p p p , where n is the number of bits in each code element and p is the storage capacity of a single bit.

4. the encoding matrix includes a first partition including an identity matrix with k rows and k columns, and a second partition including a Vandermonde type matrix with m rows and k columns; The step of encoding k data code elements based on the encoding matrix to obtain the encoded data includes: multiplying the k data code elements with the k row and k column identity matrix to obtain the k data code elements; and multiplying said k data code elements with said m rows and k columns Vandermonde type matrix to obtain said m check code elements.

5. the decoding matrix includes a third partition including a Vandermonde type matrix with m rows and k columns, and a fourth partition including an identity matrix with m rows and m columns; Decoding the set of error-correcting code words based on the decoding matrix to obtain syndrome data includes:

5. A method according to claim 3 or 4, further comprising the step of multiplying said k readback data code elements and said m readback check code elements with said decoding matrix to obtain said syndrome data.

6. The step of obtaining the error-corrected code element using the syndrome data includes: reading the syndrome data; outputting the k readback data code elements as the error-corrected code elements in response to the syndrome data being all zero, the syndrome data being all zero indicating that the k readback data code elements and the m readback check code elements are error-free; outputting the k readback data code elements as the error-corrected code elements in response to the syndrome data having one 1, the syndrome data having one 1 indicating that the k readback data code elements are error-free and that the readback check code element corresponding to the syndrome data having one among the m readback check code elements has an error; The processing method according to any one of claims 3 to 5, further comprising: a step of performing error correction on erroneous code elements among the k readback data code elements and the m readback check code elements using the syndrome data in response to v 1's in the syndrome data to obtain the error-corrected code elements, wherein v 1's in the syndrome data indicate that v1 readback data code elements corresponding to the syndrome data that is 1 among the k readback data code elements have errors, and v2 readback check code elements corresponding to the syndrome data that is 1 among the m readback check code elements have errors, where v≧2, v1≦m, v2≦m, and v1+v2=v.

7. The step of performing error correction on erroneous code elements among the k readback data code elements and the m readback check code elements using the syndrome data to obtain the error-corrected code elements includes: using the syndrome data to identify error locations and error values ​​of erroneous code elements of the k readback data code elements and the m readback check code elements; and performing error correction on the erroneous code element using the error location to obtain the error-corrected code element.

8. The step of identifying error locations and error values ​​of erroneous code elements of the k readback data code elements and the m readback check code elements using the syndrome data comprises: 1) constructing a quadratic or higher order equation using the syndrome data; determining the error location and the error value based on the quadratic or higher degree equation; A dual data code element error correction operation including: 2) assuming that the value of the single check code element is an error, and determining the error location and the error value based on the ratio relationship between the syndrome data and the ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data being equal. Single data code element and single check code element error correction operations; and 3) determining the error location and the error value based on the fact that a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data are equal.

8. The method of claim 7, further comprising: a single data code element error correction operation.

9. The quadratic or higher degree equation is a quadratic equation, p=2, m=4, and the syndrome data is (s0, s1, s2, s3), Here, the step of constructing the quadratic or higher degree equation using the syndrome data includes: quadratic equation wherein: and Here, the step of determining the error location and the error value based on a quadratic or higher degree equation includes: Depending on whether a is not 0, Then, the quadratic equation is and converting the obtaining two roots y and y′ of obtaining the error locations x and x' as The error value is calculated using the error location and the syndrome data. and and calculating: and Here, the step of determining the error location and the error value on the assumption that the value of the single check code element is an error and based on the equality of a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data, comprises: Assume that the value of the test internal memory chip ecc0 corresponding to s0 is false, Based on the above, the error location is x and the test internal memory chip ecc0, and the error value is and and calculating that Assume that the value of the test internal memory chip ecc1 corresponding to s1 is false, Based on the above, the error location is x and the test internal memory chip ecc1, and the error value is s0 and and calculating that Assume that the value of the test internal memory chip ecc2 corresponding to s2 is false, Based on the above, the error location is x and the test internal memory chip ecc2, and the error value is s0 and and calculating that Assume that the value of the test internal memory chip ecc3 corresponding to s3 is false, Based on the above, the error location is x and the test internal memory chip ecc3, and the error value is s0 and and calculating that Here, the step of determining the error location and the error value based on the fact that a ratio relationship between the syndrome data and a ratio relationship between elements of a Vandermonde type matrix corresponding to the syndrome data are equal includes the steps of:

9. The method of claim 8, further comprising the step of: calculating the error location to be x and the error value to be s0 based on:

10. The step of obtaining two roots y and y' of By mathematical operations To find the solution of or obtaining the two roots y and y′ of By examining the table, 10. The method of claim 9, further comprising the step of obtaining the two roots y and y' of

11. By mathematical operations To find the solution of The step of obtaining the two roots y and y' of By performing an exclusive OR operation on u To find the solution of 11. The method of claim 10, further comprising the step of obtaining the two roots y and y' of:

12. Both y and u are 8-bit finite field numbers, where u is given by the exclusive OR operation: The steps to solve the problem are: Y0=not Y0′, or Y0′ xor 1, Y1=Y1′, Y2=Y2′, Y=Y′, Y4=Y4′, Y5=Y5′, Y6=Y6′, Y7=Y7′, and Y7=U0 xor U1 xor U2 xor U4, Y6=U0 xor U1 xor U2 xor U4 xor U7, Y5=U1 xor U2 xor U3 xor U4 xor U6, Y4=U0 xor U7; Y3=U1 xor U2 xor U3 xor U4, Y2=U0 xor U3 xor U4 xor U6, Y1=U0 xor U2 xor U4, Y0=U3 xor U6, U5=Tr(u), where U0 to U7 represent the 0th to 7th bits of u, respectively. Y0 to Y7 represent the 0th bit to the 7th bit of y, respectively; Y0' to Y7' represent the 0th bit to the 7th bit of y', respectively; Tr(u) is 12. The method of claim 11, wherein Tr(u)=1 indicates that there is no solution and Tr(u)=0 indicates that there is a solution.

13. 13. The method according to claim 1, wherein the Vandermonde type matrix comprises a Vandermonde matrix, a left-right inverse of a Vandermonde matrix, a top-down inverse of a Vandermonde matrix, or a transpose of a Vandermonde matrix.

14. reading two burst data from each of the first and second storage channels to obtain four burst data, the four burst data corresponding to encoded data stored in the first and second storage channels, the encoded data being obtained by encoding k data code elements written in the first and second storage channels, the encoded data including the k data code elements and m check code elements, a total bit width of the m check code elements being eight times the bit width of one error correction code element; a read unit configured to organize the four bursts of data into a set of error correction code words including k readback data code elements and m readback check code elements; a decoding module configured to perform a decoding operation based on the set of error-correcting code words to obtain error-corrected code elements.

15. A processing device according to claim 14; a storage unit including the first storage channel and the second storage channel.

16. A processor; A memory storing instructions, An electronic device, characterized in that the instructions, when executed by the processor, cause the processor to carry out a processing method according to any one of claims 1 to 13.

17. A computer-readable storage medium having instructions stored thereon, comprising: A computer readable storage medium, characterized in that the instructions, when executed by the processor, cause the processor to perform the processing method according to any one of claims 1 to 13.

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