PROGRAM LOADING METHOD, APPARATUS, COMPUTER-READABLE MEDIUM AND ELECTRONIC DEVICE

Abstract

The present disclosure relates to a program loading method, an apparatus, a computer-readable medium, and an electronic device. The method includes: loading a bin file in a flash memory at a first program loading speed; adjusting the program loading speed to a second speed higher than the first speed based on a configuration parameter in the bin file; and loading an FSBL at the second program loading speed. Implementing the configuration parameter in the bin file adjusts the speed at which Bootrom loads the FSBL from the flash memory, shortening the time it takes Bootrom to load the FSBL, which is applicable when an embedded system supports various flash memories and is concerned about boot time.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application bearing application number 202210055209.2, filed on January 18, 2022, and entitled "Program Loading Method, Apparatus, Computer-Readable Medium, and Electronic Device," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to hardware program loading, and in particular to a program loading method, an apparatus, a computer-readable medium and an electronic device. [Background technology]

[0003] Bootrom or Boot ROM (Read-Only Memory) is a small piece of mask ROM or write-protected flash memory embedded in the CPU chip, which cannot be modified flexibly. If the First Stage BootLoader (FSBL) of an embedded system (such as various accelerator cards in a server) is in the Serial Peripheral Interface Flash (SPI) memory, Bootrom must load the FSBL into the SRAM (Static Random-Access Memory) after the CPU is powered on, verify and execute the FSBL. For security reasons, even in the case of eXecute In Place (XIP), the entire FSBL must be loaded and verified before jumping to execute it.

[0004] Because embedded systems support a variety of SPI Nor flash (non-volatile flash memory), the clock rate of Bootrom's SPI controller is relatively low (usually around 10MHz), which means it takes a long time to load the FSBL, making it unsuitable for systems where boot time is a priority. Summary of the Invention

[0005] This Summary is intended to introduce concepts in a simplified form, which are described in detail in the Specific Embodiments section below. This Summary is not intended to identify key features or essential elements of the claimed technical solution, and is not intended to limit the scope of the claimed technical solution.

[0006] According to a first aspect, the present disclosure provides a program loading method for an electronic device, the method including the steps of: loading the bin file at a program loading speed of a first speed, the bin file including a setting parameter for adjusting the program loading speed, adjusting the program loading speed to a second speed higher than the first speed based on the setting parameter in the bin file, and loading an FSBL of a first stage loaded program at the program loading speed adjusted to the second speed.

[0007] According to a second aspect, the present disclosure provides a program loading device applicable to an electronic device, the device comprising: a load module for loading the bin file at a program load speed of a first speed, the bin file including a setting parameter for adjusting the program load speed, and a processing module for adjusting the program load speed to a second speed higher than the first speed based on the setting parameter in the bin file, the load module being further used for loading an FSBL of a first stage load program at the program load speed adjusted to the second speed.

[0008] According to a third aspect, the present disclosure provides a computer readable medium having stored thereon a computer program which, when executed by a processing device, realises the aforementioned program loading method.

[0009] According to a fourth aspect, the present disclosure provides a computer device including a storage device in which a computer program is stored, and a processing device for executing the computer program in the storage device, thereby realizing the above-mentioned program loading method.

[0010] According to the above technical solution, the bin file in the flash memory is loaded at a first program loading speed, and the program loading speed is adjusted to a second speed higher than the first speed according to the setting parameters in the bin file, and the FSBL is loaded at the second program loading speed. By implementing the setting parameters in the bin file, the speed at which the Bootrom loads the FSBL from the flash memory is adjusted, and the time taken for the Bootrom to load the FSBL is shortened, so that the embedded system can support various flash memories and can be applied when the boot time is important.

[0011] Other features and advantages of the present disclosure will be described in detail in the specific embodiments section below. [Brief description of the drawings]

[0012] The above and other features, advantages, and aspects of each embodiment of the present specification will become more apparent with reference to the accompanying drawings and the following specific embodiments. It should be understood that the same or identical reference numerals refer to the same or identical elements throughout the accompanying drawings. The drawings are schematic, and the proportions of each dimension do not necessarily correspond to real objects and elements. [Figure 1] FIG. 1 is a schematic diagram illustrating a configuration of an electronic device according to an exemplary embodiment of the present disclosure. [Diagram 2] FIG. 2 is a flow diagram of a program loading method according to an exemplary embodiment of the present disclosure. [Diagram 3] FIG. 3 is a parameter allocation diagram of a status register according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of a program loading device according to an exemplary embodiment of the present disclosure. [Diagram 5] FIG. 5 is a schematic diagram illustrating a configuration of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] [Explanation of symbols] 100-electronic equipment; 10-boot ROM; 20-SPI flash memory; 20-program load device; 201-load module; 203-processing module; 600-computer equipment; 601-processing device; 602-ROM; 603-RAM; 604-bus; 605-I / O interface; 606-input device; 607-output device; 608-storage device; 609-communication device.

[0014] Hereinafter, the embodiments of the present disclosure will be described in more detail with reference to the attached drawings. Although the attached drawings show specific embodiments of the present disclosure, it should be understood that the present disclosure can be realized in various forms and should not be interpreted as being limited to the embodiments described herein, but rather, these embodiments are provided to provide a thorough and complete understanding of the present disclosure. It should be understood that the attached drawings and embodiments of the present disclosure are used for illustrative purposes only and are not intended to limit the protection scope of the present disclosure.

[0015] It should be understood that the steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. Additionally, method embodiments may include additional steps and / or omit the performance of illustrated steps. The scope of the present disclosure is not limited in this respect.

[0016] The term "comprises" and variations thereof herein are open ended, i.e., "including but not limited to." The term "based on" means "based at least in part on." Definitions of other terms are provided below.

[0017] It should be noted that concepts such as "first" and "second" referred to in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order or mutual dependencies of functions performed by these devices, modules or units.

[0018] It should be noted that the modifications "one" and "multiple" referred to in the present disclosure are intended to be illustrative rather than limiting, and should be understood by one of ordinary skill in the art as "one or more" unless the context indicates otherwise.

[0019] The names of messages or information exchanged between multiple devices in the embodiments of the present disclosure are not intended to limit the scope of these messages or information, but are used for explanatory purposes only.

[0020] Bootrom is a code hardened in the internal ROM of a CPU, which contains the initial code executed when a process is powered on or reset. The arrangement of certain ribbon pins or internal fuses can determine where to load the next part of the code to be executed from and verify the correctness or validity of the code to be executed. Bootrom may also contain other functions used by user code during or after booting. For example, an iPhone boots a ROM, the code embedded in the mask ROM cannot be corrected, the ROM loads the next level boot loader program from a flash memory (flash) or USB, verifies the signature of the boot loader program using a built-in RSA algorithm, and the ROM provides the function of accelerated decryption for the next level boot loader program.

[0021] SPI flash is a flash storage device that operates through the serial peripheral interface SPI. Flash is usually divided into two types, Nor flash and Nand flash, according to the internal storage configuration, and SPI flash belongs to Nor flash. SPI flash is usually used for storage that is changed infrequently because it is slow to read and write and the number of reads and writes is limited. Previously, the interface of Nor flash was parallel, that is, the data lines and address lines are connected side by side to the pins of an integrated circuit (IC). However, later, those skilled in the art found that Nor flash of different capacities was not compatible in hardware. Since the number of data lines and address lines is not the same, the package is large, and it takes up a lot of space on the printed circuit board (PCB), it was gradually replaced by SPI Nor flash. At the same time, SPI Nor flash pins of different capacities are also compatible and the package is smaller, so now many people skilled in the art directly replace Nor flash with SPI flash.

[0022] XIP means that applications can be executed directly in flash without loading the code into system RAM (Random Access Memory). Flash execution means that code can be executed directly in flash without initializing nor flash. However, often only part of the code is executed, e.g. RAM is initialized.

[0023] If the FSBL of an embedded system is in SPI flash, Bootrom must load the FSBL into SRAM after CPU power-on, and verify the signature of the FSBL before executing it for security reasons. Even in the XIP method, the entire FSBL must be loaded and the signature must be verified before executing the FSBL.

[0024] SPI controllers that support high-speed clock (CLK) (high-speed here usually means clock frequency above 25MHz, i.e. CLK>25MHz) usually come with a Port Physical Layer (PHY). The PHY registers need to be adapted according to board wiring, flash parameters, etc. Bootrom is hardened in the CPU chip and cannot flexibly customize the values ​​of these PHY registers. That is, even if a high-speed SPI controller can adjust the value of the PHY register by jumpers, it does not necessarily cover all the relevant PHY registers by the jumpers. Therefore, Bootrom cannot set the clock rate of the SPI controller high at the stage of loading FSBL, for example, it usually cannot exceed 25MHz.

[0025] SPI is divided into three modes: Single SPI (standard SPI, transmits 1 bit per clock), Dual SPI (double SPI, transmits 2 bits per clock) and Quad SPI (quadruple SPI, transmits 4 bits per clock), which correspond to 3-wire, 4-wire and 6-wire respectively. The more the number of lines in the same clock, the higher the data transmission rate. Most SPI flashes support QSPI (Quad SPI), but the CPU needs to read the Serial Flash Discoverable Parameter (flash SFDP) before deciding which method to enable QSPI. These logics are cumbersome and not suitable to be put into Bootrom.

[0026] Therefore, in order to allow embedded systems to support various SPI Nor flash, the clock rate of Bootrom's SPI controller is relatively conservative (around 10MHz), and the SPI QSPI mode is rarely turned on, so the time to load the FSBL is too long.

[0027] For the above reasons, the application of SPI flash in cases where boot time is sensitive is greatly limited. For example, for a Peripheral component interconnect express (PCIe) board, the PCIe specification requires that the time from system power-on to PCIe initialization completion must be within 120ms. Assuming that the size of FSBL is 50KB and a 10MHz SPI clock is adopted, the speed to load FSBL is 50K×8 / 10MHz=40ms. If it takes 40ms only to load FSBL, the speed of hardware and software initialization before PCIe power-on is too high.

[0028] For the above reasons, the traditional method of loading FSBL is not suitable for the case where boot time is sensitive, so to solve the problem, the present disclosure presents a program loading method for Bootrom applicable to embedded systems, which shortens the time for Bootrom to load FSBL from SPI flash. The method will be described in detail below.

[0029] FIG. 1 is a schematic diagram illustrating the configuration of an electronic device according to an exemplary embodiment of the present disclosure.

[0030] The electronic device 100 includes a boot ROM 10 and an SPI flash memory 20. Here, the SPI flash memory 20 may be an SPI Nor flash.

[0031] The SPI flash memory 20 may store a bin file.

[0032] After the CPU of the electronic device is powered on, Bootrom establishes a communication connection with the SPI flash memory 20. Bootrom first verifies the security of the SPI flash memory 20. After the SPI flash memory 20 passes the security verification, Bootrom reads and executes relevant code in the SPI flash memory 20 to obtain relevant parameters and adapt the PHY registers, or adjust the clock rate of the SPI controller, and then reads the FSBL from the SPI flash memory 20 to perform security verification. After the FSBL passes the security verification, Bootrom executes the FSBL.

[0033] Referring to Figure 2, Figure 2 is a flow diagram of a program loading method according to an exemplary embodiment of the present disclosure. The method includes the following steps:

[0034] In step S101, a bin file is loaded at a first program loading speed.

[0035] In order to accommodate various SPI Nor flash in embedded systems, the clock rate of Bootrom's SPI controller is relatively low, about 10MHz. Therefore, the first speed of this step is a reasonable value in the art, and the value may be obtained based on artificial experience, or may be obtained in other possible ways. For example, the first speed may be, but is not limited to, that the clock rate of the SPI controller is 10MHz.

[0036] The bin file is stored in the SPI flash, and the bin file includes a setting parameter for adjusting the program load speed. The setting parameter includes at least one of a PHY register setting parameter, a flash memory adaptation parameter, and an SPI clock rate parameter. Here, the PHY register setting parameter is used to adjust the PHY register setting of the board level wiring of the embedded system so that the SPI can operate normally, specifically, to adjust the phase relationship between each SPI signal. The SPI clock rate parameter is used to adjust the clock rate of the SPI controller, and the flash memory adaptation parameter is used to enable the QSPI mode of the SPI.

[0037] In step S102, the program loading speed is adjusted to a second speed based on the setting parameters in the bin file.

[0038] For example, in order to enable the SPI to operate normally, the PHY register settings of the board-level wiring of the embedded system are adjusted based on the PHY register setting parameters in the bin file, specifically, the phase relationship between each signal of the SPI is adjusted.

[0039] In addition, the value of the second speed is greater than the first speed, and the second speed is a reasonable value in the art, and the value may be obtained through artificial experience or in other possible manners, for example, the second speed may be such that the clock rate value of the SPI controller is 50 MHz, but is not limited thereto.

[0040] The method of adjusting the program load speed to the second speed based on the setting parameters in the bin file may be to enable the QSPI mode of the SPI based on the flash memory adaptation parameters in the bin file so as to set the program load speed to the second speed. As described above, the SPI is divided into three modes, the Single SPI, Dual SPI, and Quad SPI, which correspond to 3-wire, 4-wire, and 6-wire, respectively. In the same clock, the more the number of lines, the higher the data transmission rate. Flash shipped by different companies corresponds to different adjustment methods, and specifically, the specific adjustment method can be obtained according to the flash manual provided by the company, but is not limited in this disclosure. For example, a flash from a certain company will be taken as an example for explanation. As shown in FIG. 3, a parameter arrangement diagram of the status register is shown. Bits 0 to 7 are all registers, and here, QE (Quad Enable) is usually controlled by the bit 6 register, that is, the QSPI mode is controlled by the bit 6 register. The value of this bit is 0 or 1 and is used to indicate whether or not QSPI is enabled (i.e., 1=Quad Enable, 0=not Quad Enable). Therefore, by adjusting the bit 6 register parameter of the Status Register, the QSPI mode of SPI can be enabled.

[0041] Alternatively, the manner of adjusting the program loading speed to the second speed according to the setting parameters in the bin file may further include adjusting the clock rate of the SPI controller according to the SPI clock rate parameters in the bin file to make the program loading speed to the second speed. In a preferred embodiment, the clock rate of the SPI controller can be adjusted to 50 MHz.

[0042] Alternatively, the manner of adjusting the program load speed to the second speed based on the configuration parameters in the bin file may further include enabling the QSPI mode of the SPI based on the flash memory adaptation parameters in the bin file, and adjusting the clock rate of the SPI controller based on the SPI clock rate parameters in the bin file to make the program load speed the second speed. In a preferred embodiment, the clock rate of the SPI controller can be adjusted to 50 MHz.

[0043] In step S103, the FSBL of the load program of the first stage is loaded at the program load speed adjusted to the second speed.

[0044] Bootrom will read FSBL from SPI flash at the second speed program loading speed, and usually adjust the second speed to 4-5 times faster than the first speed to achieve the purpose of loading FSBL at high speed.

[0045] For example, in the case of the aforementioned PCIe board, the PCIe specification requires that the time from system power-on to completion of PCIe initialization must be within 120 ms. Assuming that the FSBL is 50 KB, when the first speed SPI clock rate (e.g., 10 MHz) is adopted, it takes 50K×8 / 10 MHz=40 ms to load the FSBL. When the program loading method proposed in the present disclosure is adopted, the bin file is loaded at the first speed first. Assuming that the size of the bin file is 500 bytes, when the QSPI mode of the SPI is enabled and the program loading speed is set to the second speed (e.g., 50 MHz), it takes 500×8 / 10 MHz+50K×8 / (4×50 MHz)=0.4 ms+2 ms=2.4 ms to load the FSBL. This saves about 90% of the time to load the FSBL.

[0046] The above method adjusts the speed at which Bootrom loads FSBL from flash memory by executing the setting parameters in the bin file, shortening the time it takes for Bootrom to load FSBL, and is applicable when embedded systems support various flash memories and boot time is important. Products that are forced to use SD / MMC related registers due to the limitations of Bootrom's boot speed can switch to SPI flash, reducing hardware costs.

[0047] Furthermore, the above method further includes the following steps.

[0048] In step S104, the security of the FSBL is verified.

[0049] It should be noted that various possible encryption algorithms can be employed to verify the security of the FSBL, and this disclosure is not limited thereto.

[0050] For example, the security of the FSBL is verified by using the MD5 algorithm. Usually, the FSBL and the first encrypted signature of the FSBL are packaged together and stored in the SPI flash. The first encrypted signature is the signature of the FSBL encrypted with a private key. In step S103, the FSBL and the first encrypted signature of the FSBL are obtained from the FSBL loaded, and the first encrypted signature is decrypted with a public key corresponding to the private key stored in the Bootrom to obtain the decrypted first signature, and the signature of the FSBL is calculated to obtain the second signature of the FSBL. Then, the first signature is compared with the second signature, and if the first signature and the second signature are the same, it is determined that the FSBL has passed the security verification.

[0051] In step S105, if the FSBL passes the security verification, the FSBL is executed.

[0052] In addition, a specific embodiment of the program loading method according to the present disclosure may be to add one plugin to the bootrom. The plugin is not limited to fast loading of FSBL, and other purposes may be achieved by adjusting the code in the plugin. For example, there is a flash that can only access the previous 16M address space without special configuration. After configuring the plugin boot in the corresponding access address space, it can be expanded to 4G address space.

[0053] In summary, the program loading method according to the present disclosure includes loading a bin file in an SPI flash at a first program loading speed, adjusting the program loading speed to a second speed higher than the first speed based on a setting parameter in the bin file, and loading an FSBL at the second program loading speed. By implementing the setting parameter in the bin file, the speed at which Bootrom loads the FSBL from the SPI flash can be adjusted, shortening the time it takes Bootrom to load the FSBL, allowing an embedded system to support various SPI flashes, and being applicable when boot time is important.

[0054] 4 is a block diagram of a program loading device according to an exemplary embodiment of the present disclosure. Referring to FIG. 4, the device 20 includes a load module 201 and a processing module 203.

[0055] The load module 201 is used to load the bin file at a first program load speed, and the bin file includes a configuration parameter for adjusting the program load speed.

[0056] The processing module 203 is used to adjust the program loading speed to a second speed, which is greater than the first speed, based on the setting parameters in the bin file.

[0057] The load module 201 is further used to load the FSBL of the first stage load program at the program load speed adjusted to the second speed.

[0058] Preferably, the configuration parameters include at least one of a port physical layer PHY register configuration parameter, a flash memory adaptation parameter, and a serial peripheral interface SPI clock rate parameter.

[0059] Preferably, the processing module 203 comprises: Obtain the PHY register setting parameters, the flash memory adaptation parameters, and the SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; or enabling a QSPI mode of the SPI according to the flash memory adaptation parameters so that the program load speed is the second speed; or adjusting a clock rate of an SPI in the flash memory according to the SPI clock rate parameter so as to make the program load speed the second speed; Or, enable a QSPI mode of the SPI based on the flash memory adaptation parameter, and adjust a clock rate of the SPI in the flash memory based on the SPI clock rate parameter, so that the program load speed is the second speed.

[0060] Preferably, the processing module 203 further comprises: used to verify the security of the FSBL; If the FSBL passes security verification, it executes the FSBL.

[0061] Preferably, the processing module 203 comprises: obtaining from the loaded FSBL a first encrypted signature of the FSBL; decrypting the first encrypted signature with a pre-stored public key to obtain a decrypted first signature; Computing a signature of the FSBL to obtain a second signature of the FSBL; Comparing the first signature and the second signature; If the first signature and the second signature are the same, then it is used to determine that the FSBL passes the security validation.

[0062] FIG. 5 is a schematic diagram of an electronic device 600 for implementing an embodiment of the present disclosure. Examples of terminal devices in the embodiment of the present disclosure include mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (portable Android (registered trademark) devices), PMPs (portable media players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers, but are not limited thereto. The electronic devices illustrated in FIG. 5 are merely examples and do not limit the functions or scope of use of the embodiment of the present disclosure in any way.

[0063] 5, the electronic device 600 may include a processing unit (e.g., a central processor, a graphic processor, etc.) 601 capable of performing various suitable operations and processes based on a program stored in a read only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. The RAM 603 further stores various types of programs and data required for the operation of the electronic device 600. The processor 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0064] Typically, the I / O interface 605 may be connected to input devices 606, such as a touch screen, touch panel, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc., output devices 607, such as a liquid crystal display (LCD), speaker, vibrator, etc., storage devices 608, such as a magnetic tape, hard disk, etc., and communication devices 606. The communication devices 606 may allow the electronic device 600 to communicate and exchange data with other devices wirelessly or via wires. Although FIG. 5 shows the electronic device 600 with various devices, it should be understood that it is not necessary to implement or include all of the devices shown. More or fewer devices may alternatively be implemented or included.

[0065] In particular, according to an embodiment of the present disclosure, the process described with reference to the flow diagrams may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including a program code for performing the method shown in the flow diagram. In such an embodiment, the computer program may be downloaded or installed from a network by the communication device 606, may be installed from the storage device 608, or may be installed from the ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of the embodiment of the present disclosure are performed.

[0066] It should be noted that the above computer readable medium of the present disclosure may be a computer readable signal medium, or a computer readable storage medium, or any combination thereof. The computer readable storage medium may be, for example, but is not limited to, an electric, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer readable storage medium include, but are not limited to, an electrical connector having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM, flash memory), an optical fiber, a portable compact disk read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, the computer readable storage medium may be any tangible medium that includes or stores a program that can be used by or in combination with an instruction execution system, device, or machine. In the present disclosure, the computer readable signal medium may comprise a data signal carrying computer readable program code, either in baseband or propagated as part of a carrier. Such a propagated data signal may take various forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, so long as it can transmit, propagate, or transmit a program usable by or in combination with an instruction execution system, apparatus, or device. The program code contained in the computer-readable medium may be transmitted by any suitable medium, including, but not limited to, an electrical wire, an optical fiber cable, RF (radio), or the like, or any suitable combination of the above.

[0067] The computer-readable medium may be included in the electronic device, or may be separate from the electronic device.

[0068] Computer program code for carrying out the operations of the present disclosure can be written in one or more program programming languages ​​or combinations thereof, including, but not limited to, object-oriented program programming languages ​​such as Java, Smalltalk, C++, and the like, as well as conventional procedural program programming languages ​​such as "C" or similar program programming languages. The program code may be executed entirely on the user computer, partially on the user computer, as a standalone software package, partially on the user computer and partially on a remote computer, or entirely on a remote computer or server. When a remote computer is used, the remote computer may be connected to the user computer via any type of network, such as a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., connected via the Internet by an Internet Service Provider).

[0069] The flow diagrams and block diagrams in the accompanying drawings illustrate possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams may represent a module, program segment, or part of code, including one or more executable instructions for implementing a certain logical function. It should also be noted that in some alternative forms, the functions shown in the blocks may occur in a different order from the order shown in the accompanying drawings. For example, two blocks shown in succession may actually be executed substantially in parallel, but may be executed in the reverse order depending on the related functions. It should be noted that each block in the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams may be realized by a system using dedicated hardware that executes a certain function or operation, or by a combination of dedicated hardware and computer instructions.

[0070] The modules described in the embodiments of the present disclosure may be realized in software or hardware, and the names of the modules may not be limiting.

[0071] The functionality described herein may be performed, at least in part, by one or more hardware logic components, such as, but not limited to, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0072] In the context of this disclosure, a machine-readable medium may be a tangible medium that can include or store a program used by or in combination with an instruction execution system, device, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electric, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the contents thereof. More specific examples of machine-readable storage media include an electrical connection by one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0073] According to one or more embodiments of the present disclosure, Example 1 comprises: A method applied to an electronic device having a preset bin file stored in a flash memory of the electronic device, comprising: loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; adjusting the program load speed to a second speed greater than the first speed based on the setting parameters in the bin file; loading a first stage load program FSBL at the program load speed adjusted to the second speed.

[0074] According to one or more embodiments of the present disclosure, Example 2 comprises: Provided herein is a method according to embodiment 1, wherein the configuration parameters include at least one of a port physical layer PHY register configuration parameter, a flash memory adaptation parameter, and a serial peripheral interface SPI clock rate parameter.

[0075] According to one or more embodiments of the present disclosure, Example 3 comprises: adjusting the program load speed to a second speed based on the setting parameters in the bin file; obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters such that the program load speed is a second speed; or adjusting a clock rate of the SPI in the flash memory according to the SPI clock rate parameter, such that the program load speed is a second speed; Alternatively, a method as described in Example 1 is provided, which includes a step of enabling a QSPI mode of the SPI based on the flash memory adaptation parameters, and adjusting a clock rate of the SPI in the flash memory based on the SPI clock rate parameters, so that the program load speed becomes the second speed.

[0076] According to one or more embodiments of the present disclosure, Example 4 comprises: after loading the FSBL at the program load speed adjusted to the second speed, performing security verification of the FSBL; The method according to Example 1 is provided, further comprising: executing the FSBL if the FSBL passes security verification.

[0077] According to one or more embodiments of the present disclosure, Example 5 comprises: The step of performing security verification of the FSBL includes: obtaining from the loaded FSBL a first encrypted signature of the FSBL; decrypting the first encrypted signature with a pre-stored public key to obtain a decrypted first signature; computing a signature of the FSBL to obtain a second signature of the FSBL; comparing the first signature with the second signature; If the first signature is identical to the second signature, determining that the FSBL passes the security validation is provided.

[0078] According to one or more embodiments of the present disclosure, Example 6 comprises: Provided is the method according to Example 1, wherein the flash memory of the electronic device is a SPI flash memory.

[0079] According to one or more embodiments of the present disclosure, Example 7 comprises: A program loading device applied to an electronic device in which a bin file preset in a flash memory of the electronic device is stored, a load module for loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; a processing module for adjusting the program load speed to a second speed greater than the first speed based on the setting parameters in the bin file; The load module further provides a program load device used for loading a first stage load program FSBL at the program load speed adjusted to the second speed.

[0080] According to one or more embodiments of the present disclosure, Example 8 comprises: The processing module is used for: obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters such that the program load speed is the second speed; or adjusting a clock rate of an SPI in the flash memory according to the SPI clock rate parameter, such that the program load speed is the second speed; Alternatively, the present invention provides an apparatus as described in Example 7, which includes a step of enabling a QSPI mode of the SPI based on the flash memory adaptation parameters, and adjusting the SPI clock rate in the flash memory based on the SPI clock rate parameters, so that the program load speed becomes the second speed.

[0081] According to one or more embodiments of the present disclosure, Example 9 comprises: A computer-readable medium having a computer program stored thereon, A computer readable medium is provided which, when executed by a processor, implements the program loading method.

[0082] According to one or more embodiments of the present disclosure, Example 10 comprises: A storage device in which a computer program is stored; a processing device for executing the computer program in the storage device, An electronic device that realizes the program loading method is provided.

[0083] The above description is merely illustrative of the preferred embodiments and applied technical principles of the present disclosure. Those skilled in the art should understand that the disclosure scope of the present disclosure is not limited to the technical solutions that combine the specific technical features described above, but also includes other technical solutions that combine the above technical features or the same features in any way without departing from the concept of the above description, for example, the above features are replaced with technical features having similar functions disclosed in this specification (but are not limited thereto).

[0084] Additionally, although operations have been described in a particular order, these operations should not be construed as requiring execution in the particular order or sequence described. Multitasking and parallel processing may be advantageous in certain environments. Similarly, although the above description includes certain specific implementation details, these should not be construed as limiting the scope of the disclosure. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, each feature described in the context of a single embodiment may be implemented in multiple embodiments individually or in any suitable subcombination.

[0085] Although the present subject matter has been described in language specific to structural features and / or method logic operations, it should be understood that the subject matter defined by the appended claims is not necessarily limited to the specific features or operations described above. On the contrary, the specific features and operations described above are merely example forms of implementing the claims.

[0086] In the apparatus according to the above-mentioned embodiment, the specific implementation of each module performing the operations has been described in detail in the embodiment according to the method, but will not be described in detail here.

Claims

1. A method applied to an electronic device having a preset bin file stored in a flash memory of the electronic device, comprising: loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; adjusting the program load speed to a second speed greater than the first speed based on the setting parameters in the bin file; loading a first stage load program FSBL at the program load speed adjusted to the second speed.

2. 2. The method of claim 1, wherein the configuration parameters include at least one of a port physical layer PHY register configuration parameter, a flash memory adaptation parameter, and a serial peripheral interface SPI clock rate parameter.

3. adjusting the program load speed to a second speed based on the setting parameters in the bin file, obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters such that the program load speed is the second speed; or adjusting a clock rate of an SPI in the flash memory based on the SPI clock rate parameter such that the program load speed is the second speed; or enabling a QSPI mode of the SPI based on the flash memory adaptation parameters and adjusting a clock rate of the SPI in the flash memory based on the SPI clock rate parameters so that the program load speed is the second speed.

4. after the step of loading the FSBL at the program load speed adjusted to the second speed, performing security verification of the FSBL; The method of claim 1 , further comprising: if the FSBL passes security validation, executing the FSBL.

5. The step of performing security verification of the FSBL includes: obtaining from the loaded FSBL a first encrypted signature of the FSBL; decrypting the first encrypted signature with a pre-stored public key to obtain a decrypted first signature; computing a signature of the FSBL to obtain a second signature of the FSBL; comparing the first signature with the second signature; 5. The method of claim 4, further comprising: determining that the FSBL passes the security verification if the first signature is identical to the second signature.

6. The method of claim 1 , wherein the electronic device's flash memory is an SPI flash memory.

7. A program loading device applied to an electronic device in which a preset bin file is stored in a flash memory of the electronic device, comprising: a load module for loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; a processing module for adjusting the program load speed to a second speed greater than the first speed based on the setting parameters in the bin file; The load module is further used to load a load program FSBL of a first stage at the program load speed adjusted to the second speed.

8. The processing module is used for: obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters such that the program load speed is the second speed; or adjusting a clock rate of an SPI in the flash memory based on the SPI clock rate parameter such that the program load speed is the second speed; or enabling a QSPI mode of the SPI based on the flash memory adaptation parameters and adjusting a clock rate of the SPI in the flash memory based on the SPI clock rate parameters so that the program load speed is the second speed.

9. A computer-readable medium having a computer program stored thereon, A computer readable medium, the computer program being adapted to implement the method of any one of claims 1 to 6 when executed by a processing device.

10. A storage device in which a computer program is stored; a processing device for executing the computer program in the storage device, An electronic device implementing the method according to any one of claims 1 to 6.

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