Active switch-on time control for bias supply.

Abstract

A bias supply and a plasma processing system are disclosed. A bias supply includes an output node, a feedback node, and a switch network and at least one power supply coupled to the output node and the feedback node. The switch network and the at least one power supply are configured in combination to apply an asymmetric periodic voltage waveform at the output node to the feedback node and provide a corresponding current waveform. A timing parameter estimator receives a digital representation of a complete cycle of the voltage and current waveforms and generates a pulse width control signal to control the switch network based on a crossing time at which the current waveform crosses a threshold current value after dropping from a positive peak current value.

Description

[Technical field]

[0001] The present invention relates generally to power supplies, and more particularly to power supplies for applying voltages for plasma processing. [Background technology]

[0002] Many types of semiconductor devices are fabricated using plasma-based etching techniques. If it is a conductor to be etched, a negative voltage with respect to ground can be applied to the conductive substrate such that across the surface of the substrate conductor, a substantially uniform negative voltage is created that attracts positively charged ions toward the conductor, so that the positive ions that impact the conductor have substantially the same energy.

[0003] However, if the substrate is a dielectric, a constant voltage is not effective to apply a voltage across the surface of the substrate. However, an alternating current (AC) voltage (e.g., high frequency AC or radio frequency (RF)) can be applied to a conductive plate (or chuck) such that the AC field induces a voltage on the surface of the substrate. During the negative portion of the applied waveform, the surface of the substrate becomes negatively charged, which causes ions to be attracted toward the negatively charged surface during the negative portion of the AC cycle. Also, when the ions collide with the surface of the substrate, the impact removes material from the surface of the substrate, resulting in etching.

[0004] In many cases, it is desirable to have a narrow (or specifically adjustable) ion energy distribution, but applying a sinusoidal waveform to a substrate induces a wide distribution of ion energy, which limits the ability of the plasma process to perform a desired etching profile. Known techniques for achieving a narrow (or specifically adjustable) ion energy distribution can be expensive, inefficient, difficult to control, and / or adversely affect plasma density. As a result, many of these known techniques have not been commercially adopted. Thus, systems and methods are needed to address the shortcomings of current technology and provide other new and innovative features. Summary of the Invention [Means for solving the problem]

[0005] An aspect may be characterized as a bias supply for applying a periodic voltage. The bias supply comprises a switch network and at least one power supply coupled to an output node and a feedback node. The switch network and at least one power supply are configured in combination to apply an asymmetric periodic voltage waveform and a corresponding current waveform at the output node to the feedback node. A timing parameter estimator is configured to receive a digital representation of a complete cycle of the asymmetric periodic voltage waveform and the current waveform and generate a pulse width control signal based on a first crossing time at which the current waveform crosses a threshold current value after dropping from a positive peak current value. A gate drive signal generator is configured to provide a gate drive signal to at least one switch of the switch network in response to the pulse width control signal received from the timing parameter estimator to control application of the asymmetric periodic voltage waveform and the current waveform to the output node relative to the feedback node.

[0006] Yet another aspect may be characterized as a method for applying a periodic voltage. The method includes applying an asymmetric periodic voltage waveform and providing a corresponding current waveform at an output node to a feedback node of a bias supply. Digital representations of the asymmetric periodic voltage waveform and the current waveform are received, and a pulse width control signal is generated based on a first crossing time at which the current waveform crosses a threshold current value after dropping from a positive peak current value. A gate drive signal is provided to at least one switch of a switch network in response to the pulse width control signal to control application of the asymmetric periodic voltage waveform.

[0007] Another aspect disclosed herein is a bias supply for applying a periodic voltage comprising an output node, a feedback node, and means for applying an asymmetric periodic voltage waveform and a corresponding current waveform at the output node to the feedback node. The bias supply also comprises a processor and a non-volatile memory, the non-volatile memory comprising non-transient processor-executable instructions for receiving a digital representation of a complete cycle of the asymmetric periodic voltage waveform and the current waveform, and generating a pulse width control signal based on a first crossing time at which the current waveform crosses a threshold current value after dropping from a positive peak current value. In addition, the bias supply comprises a gate drive signal generator configured to provide a gate drive signal to at least one switch of the switch network in response to the pulse width control signal received from the timing parameter estimator to control application of the asymmetric periodic voltage waveform and the current waveform to the output node relative to the feedback node. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram depicting an exemplary plasma processing environment in which the bias sources disclosed herein may be utilized.

[0009] [Diagram 2] FIG. 2 is a schematic diagram depicting an exemplary bias supply.

[0010] [Diagram 3] FIG. 3 is a schematic diagram of a side electrical representation of a plasma processing chamber.

[0011] [Figure 4] FIG. 4 is a block diagram depicting the sampling, readback, and control aspects of the bias supply.

[0012] [Diagram 5] FIG. 5 is a block diagram depicting a control system for a bias supply with two power supplies.

[0013] [Figure 6] FIG. 6 is a block diagram depicting a control system for a bias supply with one power supply.

[0014] [Figure 7A] FIG. 7A is a schematic diagram illustrating an example of a one-switch network that may be implemented in a bias supply having a one-power supply configuration.

[0015] [Figure 7B] FIG. 7B is a schematic diagram illustrating another example of a one-switch network that can be implemented in a bias supply having a one-power supply configuration.

[0016] [Figure 8] FIG. 8 is a schematic diagram illustrating an example of a one-switch network that may be implemented in a bias supply having a two power supply configuration.

[0017] [Figure 9] FIG. 9 depicts graphs and timing diagrams illustrating aspects of a bias supply with a single switch.

[0018] [Figure 10]FIG. 10 depicts a complete digital representation of one cycle of the asymmetric periodic output voltage and current waveforms associated with a bias supply implementation having one switch.

[0019] [Figure 11] FIG. 11 is a flow chart depicting a method for setting gate drive pulse width and reset time that can be implemented in conjunction with a bias supply having a one-switch network and either one or two power supplies.

[0020] [Figure 12] FIG. 12 is a flow chart depicting another method for setting gate drive pulse width and reset time that can be implemented in conjunction with a bias supply having a one-switch network and either one or two power supplies.

[0021] [Figure 13] FIG. 13 is a flow chart depicting a method for setting gate drive pulse width and reset time that may be implemented in conjunction with a bias supply having one switch network and one power supply.

[0022] [Figure 14] FIG. 14 is a flow chart depicting a method for calculating a threshold current value in conjunction with a bias supply having a one-switch network.

[0023] [Figure 15] FIG. 15 is a flow chart depicting a method for calculating a threshold voltage value in conjunction with a bias supply having a one-switch, one-power supply configuration.

[0024] [Figure 16] FIG. 16 is a flow chart depicting a method for calculating threshold voltage values ​​in conjunction with bias supplies having a one-switch, two-power supply configuration.

[0025] [Figure 17] FIG. 17 is a schematic diagram illustrating an example of a two-switch network that may be implemented in a bias supply having a one power supply configuration.

[0026] [Figure 18] FIG. 18 is a schematic diagram illustrating an example of a two-switch network that may be implemented in a bias supply having a two power supply configuration.

[0027] [Figure 19] FIG. 19 depicts graphs and timing diagrams illustrating aspects of a bias supply with two switches.

[0028] [Figure 20] FIG. 20 depicts a complete digital representation of one cycle of the asymmetric periodic output voltage and current waveforms associated with a bias supply implementation having two switches.

[0029] [Figure 21] FIG. 21 is a flow chart depicting a method for setting gate drive pulse width and reset time that can be implemented in conjunction with a bias supply having a two-switch network.

[0030] [Figure 22] FIG. 22 is a flow chart depicting a method for calculating a threshold current value in conjunction with a bias supply having a two-switch network.

[0031] [Figure 23] FIG. 23 is a block diagram depicting components that may be utilized to implement the control aspects disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Detailed Description The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0033] Preliminary Note: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, some blocks in these flowcharts or block diagrams may represent modules, partitions, or portions of code, which comprise one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially in parallel, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system, or a combination of special-purpose hardware and computer instructions, that performs the specified functions or actions.

[0034] For purposes of this disclosure, a source generator is one whose energy is primarily directed to generating and sustaining a plasma, while a "bias source" is one whose energy is primarily directed to generating a surface potential to attract ions and electrons from the plasma.

[0035] Described herein are control aspects of a bias source that may be used to apply a periodic voltage function to a substrate support in a plasma processing chamber. Referring initially to FIG. 1, shown is an exemplary plasma processing environment (e.g., a deposition or etching system) in which a bias source may be utilized. The plasma processing environment may include many pieces of equipment coupled directly and indirectly to a plasma processing chamber 101, a volume containing a plasma 102 and a workpiece 103 (e.g., a wafer) and an electrode 104 (which may be embedded in a substrate support). The equipment may include vacuum handling and gas delivery equipment (not shown), one or more bias sources 108, one or more source generators 112, and one or more source matching networks 113. In many applications, power from a single source generator 112 is connected to one or more source electrodes 105. The source generator 112 may be a higher frequency RF generator (e.g., 13.56 MHz to 120 MHz). Electrode 105 generally represents what may be implemented using an inductively coupled plasma (ICP) source, a dual frequency capacitively coupled plasma source (CCP) with a secondary upper electrode biased at another RF frequency, a helicon plasma source, a microwave plasma source, a magnetron, or other independently operated source of plasma energy.

[0036] In variations of the system depicted in FIG. 1, the source generator 112 and source matching network 113 may be replaced by or augmented with a remote plasma source. Other variations of the system may include only a single bias source 108. It should be appreciated that many other variations of the plasma processing environment depicted in FIG. 1 may be utilized. By way of example, and not limitation, U.S. Pat. No. 10,707,055, issued July 7, 2020, and U.S. Pat. No. 10,811,227, issued October 20, 2020 (both of which are incorporated by reference in their entirety) disclose various types of system designs.

[0037] Also, while the following disclosure generally refers to plasma-based wafer processing, it should be appreciated that implementations can include any substrate processing in a plasma chamber. In some cases, objects other than substrates can also be processed using the systems, methods, and apparatus disclosed herein. In other words, the present disclosure also applies to plasma processing of any object in a sub-atmospheric pressure plasma processing chamber to affect surface changes, sub-surface changes, deposition, or removal by physical or chemical means.

[0038] 2, shown is an example bias supply 208 that may be utilized to implement the bias supply 108 described with reference to FIG. 1. The bias supply 208 generally represents many variations of bias supplies further described herein for applying a periodic voltage function. Thus, reference to the bias supply 208 generally refers to any of the bias supplies further described herein. As shown, the bias supply 208 includes an output 210 (also referred to as an output node 210), a feedback node 212, a switch network 220, an inductance 214 and a first power supply 216 (also referred to herein as a V supply Also shown is an optional second power supply 218 (referred to herein as V rail In general, the bias source 208 has an asymmetric periodic voltage function V out between an output node 210 and a feedback node 212. The current delivered to the load through the output node 210 is fed back to the bias source 208 through a feedback node 212, which may be common to the load.

[0039] 2, the bias supply 208 may include a controller that is coupled to the controller and / or that is coupled to the switch network 220. Variations of the switch network 220 (as well as variations with or without the second power supply 218) are also disclosed further herein, but first it is useful to understand the plasma load aspect.

[0040] 3, shown is a schematic diagram electrically depicting a side view of an exemplary plasma load within a plasma processing chamber 101. As shown, the plasma processing chamber 101 has an input 310 (also referred to as an input node 310) to the plasma processing chamber 101 and a sheath voltage V at the surface of a workpiece 103 (also referred to as a wafer substrate 103). s A node representing the chuck capacitance CC h (including the capacitance of the chuck and the workpiece 103). Therefore, the sheath voltage V s The reference to is also referred to herein as the voltage at the surface of the wafer or substrate. In addition, a feedback node 312 (which may be a connection to ground) is depicted. The plasma 102 in the processing chamber is coupled to the sheath capacitance C s , a diode, and a current source. The diode represents the nonlinear diode-like nature of the plasma sheath, which results in rectification of the applied AC field such that a direct current (DC) voltage drop appears between the workpiece 103 and the plasma 102.

[0041] 4, shown is a block diagram depicting general aspects of measurement, readback, and control. Shown are bias supply 208, a measurement section 620, and a digital control section 622. In general, measurement section 620 receives a signal indicative of a power-related parameter value and provides a digital representation of the power-related parameter value to digital control section 622. For example, the power-related parameter may be the output current i provided to output node 210. out and the voltage V between the output node 210 and the feedback node 212out Although not required, the feedback node may be a ground connection.

[0042] The measurement section 620 may receive a signal from one or more bias supply signal lines 624. The bias supply signal lines 624 may receive a signal from the compensation current I comp The current signal line 626 may provide an analog signal indicative of the current provided to the output node 210 from the current converter, and the voltage line 628 may carry a signal indicative of the voltage V at the output of the bias supply. out In response to receiving the power-related signal, the measurement section 620 samples and digitizes the power-related signal. For example, the measurement section 620 may provide an analog signal indicative of an asymmetric periodic voltage waveform V out , output current waveform i out , and / or the compensation current I comp A complete digital representation of the

[0043] An aspect of many variations of the measurement section 620 is that the complete voltage and current waveforms are captured, which provides improved visibility of the output of the bias supply and enables improved control aspects as further disclosed herein.

[0044] Although not required, the metrology section 620 may be implemented in part by a field programmable gate array, and the digital control section 622 may be implemented by one or more processors executing code stored in a non-transitory medium (to provide the functionality of the digital control section 622). Other combinations of hardware, software, and firmware may be used to implement the metrology section 620 and the digital control section 622.

[0045] As shown, the asymmetric periodic voltage waveform V out , output current waveform i out、 and / or i compThe digital representation of V may be provided to a data reporting component 631, which may be a user interface (e.g., a touch screen display). In addition, the asymmetric periodic voltage waveform V out , output current i out , and / or the compensation current i comp The digital representation of V is provided to a data processing module 630, which further derives the asymmetric periodic voltage waveform V out , output current waveform i out , and / or the compensation current i comp and process the digital representation of the sheath voltage v s , and E ion , V step , ΔE ion , the output voltage slope (e.g., the slope of the third portion of the asymmetric periodic voltage waveform), and / or the slope deviation factor K s etc. may provide a readback of one or more other parameter values.

[0046] Slope deviation coefficient K s can be calculated as follows: [ka] In the formula, the slope w is the slope of the wafer / sheath voltage from t3 to t4.

[0047] Or alternatively, the slope deviation coefficient may be calculated to satisfy the following equation: [ka]

[0048] Slope deviation coefficient K s is the ion current I ion Compensation current I comp For example, K s When is equal to zero, the compensation current provides perfect compensation, and K s >0, then I comp overcompensates the ion current, and K s<0, the compensation current I comp is the ion current I ion Undercompensate.

[0049] As shown, the readback values ​​(e.g., depicted as Readback1 and Readback2) may also be used as part of the feedback control. A first comparator 638 may calculate the difference between a first setpoint, Setpoint1, and a first readback value, Readback1, to produce a first error signal, Error1. A second comparator 640 may calculate the difference between a second setpoint, Setpoint2, and a second readback value, Readback2, to produce a second error signal, Error2. The error signals (Error1 and Error2) may be fed to one or more compensators 632, which may provide control signals (Ctrl_knob1 and Ctrl_knob2) to the bias supply 208 as further described herein.

[0050] Also shown within the digital control section 622 is a timing parameter estimator 634, which determines the output voltage waveform V out and the output current waveform i out , and may generate a pulse width control signal. According to one aspect, the timing parameter estimator 634 detects when there is zero current through the switch of the bias supply and sets the pulse width and causes the switch to open (off) at or after that time to reduce switching related losses, so that the on time for the switch is also controlled. The timing parameter estimator 634 also calculates t reset (shown in FIGS. 4 and 5) may be determined, and t reset Values ​​for may be reported and provided to the data processing module 630 via a data reporting component 631. The timing parameter estimator 634 may be implemented by one or more processors executing code stored in a non-transitory medium and / or other combinations of hardware, software, and firmware.

[0051] The digital control section 622 also comprises a gate drive signal generator 636 configured to provide gate drive signals to the switches S1 and S2 of the bias supply 208 (to control the times that the switches S1 and S2 are on and off) in response to a pulse width control signal 637 from the timing parameter estimator 634 (in a one source configuration) and / or in response to a control signal 639 output by the one or more compensators 632. While many types of switches are controlled by electrical gate drive signals, it is also contemplated that optical control signals may also be used. For example, the gate drive signal generator 636 may provide an optical signal.

[0052] Referring now to FIG. 5, shown is a block diagram illustrating a control system for the bias supply 208 of FIG. 2, which is powered by a first power supply (V supply ) 216 and a second power supply (V rail ) 218. The switch network 220 may comprise a variety of different topologies, including one or two switches, as will be described below.

[0053] As shown in Figures 4 and 5, the control system includes two control "knobs": supply and V rail This approach may be used to control the DC voltage of the compensation current I comp (to control the width of the distribution of ion energies), and V rail In contrast to previous approaches, where the first power supply 216 (V supply ) and the voltage of the second power supply (V rail ) may be controlled based on a general relationship: [ka]

[0054] In this control approach, the first set point is the ion energy set point, E ion_set and the second set point is the spread (also called distribution) of ion energies, Δ Eion_set (E ion_set and Δ Eion_set 5). The data processing module 630 receives the output current waveform i from the measurement section 620. out and the voltage waveform V out Based on the digital representation of E ion and Δ Eion As shown, a first comparator 638 may calculate a first set point, E ion_set and E ion A second comparator 640 may generate a first error signal, Error1, based on the difference between the calculated value of Eion_set and Δ Eion A second error signal, Error 2, may be generated based on the difference between the calculated values ​​of

[0055] Alternatively, the first set point (to set the ion energy) is V step The first set point may be a slope set point (to set the slope of the fourth portion (time between t3 and t4) of the asymmetric periodic voltage waveform), or the second set point may be a slope deviation factor set point (to set the slope deviation factor K s The data processing module 630 may be configured to set the i out and V out Based on the digital representation of V step and the slope or slope deviance coefficient K s In this alternative, the first comparator 638 may calculate a first set point (e.g., V step Set point) and V stepA second comparator 640 may generate a first error signal, Error1, based on the difference between a second set point (either a slope set point or a slope deviation factor set point) and the calculated value of the slope or the slope deviation factor K s A second error signal, Error 2, may be generated based on the difference between the calculated values ​​of

[0056] The control system may include two compensators: a first compensator 1132A and a second compensator 1132B. The first compensator 1132A receives a first error signal, Error 1, and outputs a signal V supply_set and may control the first power supply 216. The second compensator 1132B receives a second error signal, Error 2, and generates a signal V rail_set , which may control the second power supply 218. In some variations, the gate drive signal generator 636 may be set with a fixed switching time for the first switch of the bias supply 208 (and the second switch in the two-switch bias supply). In other variations, the timing parameter estimator 634 may provide a pulse width signal such that the gate drive signal generator 636 may open (off) the switch of the bias supply 208 (thus controlling the on-time of the switch of the bias supply 208) and provide zero current switching. Each of the compensators 1132A, 1132B may be realized by a proportional-integral-derivative (PID) controller, and in some variations, the bandwidth of the first compensator 1132A is set to be different from the bandwidth of the second compensator 1132B, which allows the control loops associated with each of the compensators 1132A, 1132B to be decoupled. For example, the sampling rate of each control loop may be set to a different rate to result in different bandwidths.

[0057] 6, shown is a block diagram depicting a control system for the bias supply 208 of FIG. 2, which is powered by a first power supply 216 (V supply) for controlling the second power supply 218 as in FIG. 5 . The switch network 220 may have a variety of different topologies, including one or two switches, as will be described below. The control system of FIG. 6 for the one-source configuration (since the control system of FIG. 6 is a one-source configuration), includes only the signal V rail_set ) the second compensator 1132B provides a frequency setpoint signal f sw_set 6. As another option, one MIMO compensator 632 can be used with multiple inputs (generally shown as Error1 and Error2 in FIG. 6) and multiple outputs, where Ctrl_knob1 and Ctrl_knob2 in FIG. 6 are respectively provided as V supply_set and V rail_set may be also possible.

[0058] 7A, 7B, and 8, shown are examples of switch networks having one-switch configurations that may be implemented in switch network 220 of bias supply 208 (FIG. 2). FIGURES 7A and 7B depict one-switch configurations that may be implemented in a one-source configuration, i.e., bias supply 208 includes only first power supply 216 and is controlled by an associated one-source control system, such as that of FIGURE 6. FIGURE 8 depicts one-switch configurations that may be implemented in a two-source configuration, i.e., bias supply 208 includes first power supply 216 and second power supply 218 and is controlled by an associated two-source control system, such as that of FIGURE 5.

[0059] In many implementations, the switches disclosed herein are realized by field effect switches such as metal oxide semiconductor field effect transistors (MOSFETs), and in some implementations, the switches are realized by silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) or gallium nitride metal oxide semiconductor field effect transistors (GaN MOSFETs). As another example, the switches may be realized by insulated gate bipolar transistors (IGBTs). In these implementations, the gate drive signal generator 636 may comprise an electrical driver known in the art configured to apply an electrical drive signal to the switch in response to a signal from the timing parameter estimator 634 and / or one or more compensators 632. It is also contemplated that the drive signal may be transmitted via an optical line to carry an optical switching signal. The switch may also switch in response to an optical signal and / or an optical signal that is converted to an electrical drive signal.

[0060] It should be appreciated that each of the switches depicted herein generally represents one or more switches that can be closed and opened, respectively, to connect and disconnect a current path. For example, each of the switches may be realized by multiple switches arranged in series (for improved voltage capability), multiple switches arranged in parallel (for improved current capability), or each of the switches may consist of multiple switches arranged in a series-parallel combination (for improved voltage and / or current capability). In these variations, one skilled in the art will appreciate that each switch may be driven by a corresponding drive signal in a synchronized manner.

[0061] It should also be appreciated that any of the diodes depicted herein may be implemented with multiple diodes. For example, any diode may be implemented with multiple series connected diodes (to improve voltage capability), with multiple diodes arranged in parallel (to improve current capability), or may consist of multiple diodes arranged in a series-parallel combination (for improved voltage and / or current capability).

[0062] 7A, shown is a schematic diagram depicting a switch network 1820B that may be deployed in conjunction with a one-source configuration in which the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-source control system, such as that of FIG. 6, of an embodiment of a switching section 220 having a single switch S1. As shown in FIG. 7A, a first inductor L1 is coupled between a node 1870 and the output node 210. The switch S1 is coupled between the node 1870 and the feedback node 212. A diode D1 is coupled in parallel with the switch S1 between the node 1870 and the feedback node 212.

[0063] 7B, shown is a schematic diagram depicting a switch network 1820C, which may be deployed in conjunction with another embodiment of the switching section 220 having a single switch S1, in which the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-source control system, such as that of FIG. 6. As shown in FIG. 7B, the switch network 1820C comprises a first current path (for current iS1) between the feedback node 212 and a node 1872. The first current path comprises a series combination of a switch S1, a diode D1, and an inductor L1. In addition, the switch network 1820C comprises a second current path (for current iD2) (between the node 1872 and the feedback node 212), which comprises a second diode D2 and an inductive element L2. As shown, the cathode of diode D2 is coupled to the feedback node 212, and a third inductor L3 is positioned between node 1872 and the output node 210.

[0064] Referring now to FIG. 8, shown is a schematic diagram depicting a switch network 1420B, which may be deployed in conjunction with a two-source configuration in which the bias source 208 includes a first power source 216 and a second power source 218 and is controlled by an associated two-source control system such as that of FIG. 5, with a single switch S1. As shown in FIG. 8, the switch network 1420B comprises a first current path (for current iS1) between the node 1050 and the output node 210. The first current path comprises a series combination of the switch S1, a diode D1, and an inductor L1. The switch network 1420B also comprises a second current path (for current iD2) between the output node 210 and the feedback node 212, which comprises a second diode D2 and an inductor L2.

[0065] Also, because switch S1, diode D1, and inductor L1 are arranged in series, it should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned may be changed. In addition, the order in which L2 and D2 are arranged in Figures 7B and 8 may be swapped.

[0066] 9, shown are graphs and timing diagrams illustrating aspects of a bias supply comprising a switching network having a single switch, such as the switching networks of FIGS. 7A, 7B, and 8. As shown in FIG. 9, switch S1 switches the output current waveform i out , asymmetric periodic output voltage waveform V out , and the sheath voltage waveform V s , is closed (on) and then opened (off) for the duration of the gate drive pulse width signal.

[0067] A complete cycle of the asymmetric periodic current and voltage waveforms of FIG. 9 extends from time t0 to t4. out The first portion of the output voltage waveform V rises from a first negative voltage at time t0 when switch S1 is closed (on) to a peak positive voltage level at time t1 (t1=t2). out The second part of the step The asymmetric periodic voltage V drops to a third (negative) voltage level at time t3 by 100 V. As will be explained below, switch S1 is opened (off) at or before time t3. Between times t3 and t4, the asymmetric periodic voltage V out The third (negative slope) portion of decreases steadily and negatively until switch S1 is again closed (on) at time t4.

[0068] Output current waveform i out The first portion of the output current waveform i rises from a threshold current value to a positive peak current value at time t0 when switch S1 is closed (on). outThe second portion of the output current waveform i drops from the positive peak current value, makes a first crossing of the threshold current value at time t1 (t1=t2), and reaches a negative peak current value in the opposite direction. It should be appreciated that the absolute values ​​of the positive peak current value and the negative peak current value may be different. As will be explained below, switch S1 is opened (off) at or after the time of the first crossing of the threshold current value. out The third portion of the output current waveform i then rises from the negative peak current value and again reaches the threshold current value at time t3. out The fourth part of the -I o to reach.

[0069] Voltage waveform V out is a sheath voltage waveform V that is generally negative to attract ions to impinge on the surface of the workpiece and enable etching of the workpiece 103. s During the time t0 to t1 (t1 = t2), an asymmetric periodic voltage waveform V out The first part of is the sheath voltage V s The asymmetric periodic voltage waveform V approaches a positive voltage and repels the positive charge that accumulates on the surface of the workpiece, while the surface of the workpiece is held at a negative voltage. out The second part of the step Only the sheath voltage V drops s to the desired negative voltage (or range of voltages) to achieve the desired ion energy and ion flux. step is the ion at any energy level -E ion During the third portion of the asymmetric periodic voltage waveform, the sheath voltage corresponds to −(E ion +Δ Eion ) can become more negative, resulting in ions at the energy level

[0070] Also, what is shown in FIG. reset (time between t0 and t3) and t ramp(the time between t3 and t4). As shown, t reset is the asymmetric periodic voltage waveform V out t ramp is the voltage waveform V out The third inclined portion includes a third inclined portion.

[0071] Also, what is shown in FIG. 9 is the compensation current I comp This is an example of the compensation current I comp is the asymmetric periodic voltage function V out may be provided throughout the application of I out is the asymmetric periodic voltage waveform V out During the third part of (t ramp Between comp The compensation current I comp may compensate for the ion current in the plasma chamber 101. The compensation current I comp If not accompanied by sheath voltage V s may gradually change and become more positive during the third portion of the asymmetric periodic voltage, which would produce a wider distribution of ion energies, which may not be desirable. However, in some variations, the compensation current I comp may be set to intentionally overcompensate or undercompensate the ion current in the plasma chamber 101 to produce a wider distribution of ion energies. In the mode of operation depicted in FIG. comp is the voltage waveform V out The sheath voltage V s to provide.

[0072] Asymmetric periodic voltage waveform V out The fundamental period (t0 to t4) of may be adjusted to adjust the spread of ion energy. As shown in FIG. 9, a complete current cycle is generated by the asymmetric periodic voltage waveform V out The first and second portions of the current cycle occur between times t0 and t3. The time between complete current cycles occurs between times t3 and t4. ramp An aspect of the present disclosure is toout Adjust the ion current I ion Another aspect of the present disclosure addresses the issue of methods for adjusting the level and distribution of ion energy in a plasma chamber.

[0073] To control the bias supply, a timing parameter estimator 634 estimates the output current i out The gate drive signal generator 636 may detect when the current reverses (crosses a threshold current value) and generate a pulse width signal to the gate drive signal generator 636 to close (on) switch S1 at time t0 and then open (off) at or after the time the current crosses the threshold current value. In particular, switch S1 remains closed (on) for the duration of the gate drive pulse width and opens (off) when the pulse width signal ends. Once the current reverses direction, current no longer flows through switch S1 and switch S1 may then be opened (off) to reduce losses. Switch S1 need not be opened (off) immediately in response to crossing the threshold, but may be opened (off) in response to the voltage output waveform V out But at time t ramp The reset time t reset Before the gate pulse width can be reset, the gate must be opened (off). Thus, between the minimum and maximum pulse widths there is a range within which the pulse width can fall. Figures 10-16, described below, show the relationship between the gate pulse width and the reset time t reset This addresses the calculation of.

[0074] Referring now to FIG. 10, shown is the asymmetric periodic output voltage and output current waveforms V associated with an implementation of bias supply 208 having one switch. out and i out 10 is a graph depicting a complete digital representation of one cycle of the gate drive pulse width provided by the timing parameter estimator 634 to the gate drive signal generator 636 and the reset time treset 10 illustrates various timing parameters used to calculate t0 to t4 In the illustration of FIG. 10, times t0 to t4 correspond to times t0 to t4 in the timing diagram of FIG.

[0075] The timing parameter estimator 634 estimates the asymmetric periodic voltage waveform V out , output current waveform i out , and / or the compensation current I comp From the measurement section 620, the timing parameter estimator 634 receives a fully digital representation of the waveforms. From these waveforms, the timing parameter estimator 634 can accurately calculate the gate drive pulse width, which is provided to the gate drive signal generator 636, so that the switch S1 is opened (off) at the appropriate time with minimal losses. The timing parameter estimator 634 also calculates the reset time t reset Calculate the reset time t reset is the time by which switch S1 must be opened (off), out is used to find the starting point of the slope (third) portion of

[0076] As shown in Figure 10, the output voltage waveform V out rises from a starting negative voltage at time t0 when switch S1 is closed (on) during the first portion, to a peak positive voltage value at time t1, then drops to an intermediate (third) negative voltage at time t3 during the second portion, and then steadily and gradually ramps to an ending negative voltage at time t4 during the third portion. Since time t4 is the end of a cycle and the start of a new cycle, the ending negative voltage should be approximately equal to the starting negative voltage. During the drop between times t1 and t2, the voltage rises from a voltage threshold crossing time t v-cross In this case, the threshold voltage V threshold The threshold voltage V threshold is typically at or near zero volts.

[0077] Output current waveform i outDuring the first portion, starting from time t0 when the switch S1 is closed (on), the threshold current value i threshold The output current waveform i rises from out The second portion of the output current waveform i drops from a positive peak current value to a negative peak current value. During the second portion, out First, the first threshold current crossing time t i-cross1 In this case, the threshold current value i threshold At this time, the window for opening (turning off) switch S1 begins. The output current waveform i out The third part of the current rises from the negative peak value for the second time at the threshold current crossing time t i-cross2 In this case, the threshold current value i threshold At this time, the window for opening (turning off) switch S1 ends. The output current waveform i out The fourth part is then a slightly negative compensation current value -I comp gradually flattens out until

[0078] Referring now to FIG. 11, shown is the gate drive pulse width and reset time t reset 11 is a flow chart depicting a method 1100 implemented by a timing parameter estimator 634 associated with an implementation of the bias source 208 having one switch to set the output current waveform i. The method 1100 may be implemented in conjunction with either the one switch, one source configuration of FIG. 7B or the one switch, two source configuration of FIG. 8. The method 1100 of FIG. 11 out Use the voltage waveform V to set the maximum gate drive pulse width. out An alternative method 1200 for setting the maximum gate drive pulse width using is discussed with reference to FIG.

[0079] In step 1102, the timing parameter estimator 634 calculates a default threshold current value i threshold , the default gate drive pulse width, and the default reset time t resetIn step 1104, the timing parameter estimator 634 loads the output current waveform i out In one embodiment, for example, the estimator 634 captures the asymmetric periodic current waveform i provided by the measurement section 620, as depicted in FIG. out In step 1106, the timing parameter estimator 634 captures one cycle of a complete digital representation of the first threshold current crossing time t i-cross1 and the second threshold current crossing time t i-cross2 Regarding the output current waveform i out Search for.

[0080] In step 1108, the threshold current crossing time t i-cross1 and t i-cross2 If, in step 1106, is not found, the method proceeds to step 1110, where the gate drive pulse width is set as a default pulse width value or a previously calculated pulse width, and a reset time t reset as the default reset time or a previously calculated reset time. In step 1112, the threshold current value i threshold is calculated as described with reference to FIG. 14, and the threshold current value i threshold is updated with the calculated value in step 1114. The method 1100 then loops back to step 1104 and updates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0081] In step 1108, the threshold current crossing time t i-cross1 and t i-cross2 If is found in step 1106, the method proceeds to step 1116. In step 1116, the reset time is determined to be equal to the second threshold current crossing time (t reset =t i-cross2 In other words, the reset time t reset is the output current waveform i outrises to its positive peak current value and falls to its negative peak current value (first, the threshold current value i threshold ), then rises again, the second time to the threshold current value i threshold The time taken to reach the target position is set to be the total time it takes.

[0082] As described above, the pulse width may be set within a range between a maximum pulse width and a minimum pulse width. Also, in step 1116, the minimum pulse width is set to be equal to or smaller than the first threshold current crossing time (t pulse_min =t i-cross1 In other words, the minimum pulse width t pulse_min From time t0, the output current waveform i out rises to its positive peak current value and then falls, first to a threshold current value i threshold In step 1118, the maximum pulse width t pulse_max is the output current waveform i out is the threshold current value i threshold The first time, the output current waveform i out is the threshold current value i threshold The second time, i.e., t pulse_max =0.5(t i-cross1 +t i-cross2 ).

[0083] Step 1120 determines whether the current pulse width is equal to or smaller than the minimum pulse width t with a predefined tolerance, which is a design choice value. pulse-min and maximum pulse width t pulse_max If the current pulse width is within this range, the current pulse width is kept as the pulse width (step 1122) and the method 1100 then loops back to step 1104 and determines whether the asymmetric periodic current waveform i provided by the measurement section 620 is within the range between out The next cycle of is captured and the method repeats from there.

[0084] In step 1120, the current pulse width is compared to the minimum pulse width t pulse-min and maximum pulse width t pulse_max If not, the pulse width is recalculated in step 1124. The pulse width is calculated based on the minimum pulse width t pulse_min and maximum pulse width t pulse_max In one embodiment, the pulse width is set to be anywhere between pulse_width=t pulse_min +w0(t pulse_max -t pulse_min ) where w0 is a design option value between 0 and 1. After the pulse width is recalculated in step 1124, the method 1100 loops back to step 1104 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0085] Referring now to FIG. 12, shown is the gate drive pulse width and reset time t reset 12 is a flowchart depicting an alternative method 1200 that may be implemented by a timing parameter estimator 634 associated with an implementation of the bias supply 208 having one switch to set the output current waveform i out In contrast to the method 1100 of FIG. 11, which uses the voltage waveform V out 8. As with method 1100, method 1200 may be implemented in conjunction with either the one switch, one source configuration of FIG.

[0086] 12, in step 1202, the timing parameter estimator 634 determines the default gate drive pulse width and the default reset time t reset In step 1204, the timing parameter estimator 634 loads the output current waveform i out and the voltage waveform V outIn one embodiment, for example, the estimator 634 captures the asymmetric periodic current waveform i provided by the measurement section 620, as depicted in FIG. out and the asymmetric periodic voltage waveform V out In step 1206, the timing parameter estimator 634 captures one cycle of a complete digital representation of the first threshold current crossing time t i-cross1 and the second threshold current crossing time t i-cross2 Regarding the output current waveform i out Search for.

[0087] In step 1208, the threshold current crossing time t i-cross1 and t i-cross2 If not found in step 1206, the method proceeds to step 1210, where the gate drive pulse width is set as the default pulse width or a previously calculated pulse width, and the reset time t reset as the default reset time or a previously calculated reset time. In step 1212, the threshold current value i threshold is calculated as described with reference to FIG. 14, and the threshold current value i threshold is updated with the calculated value in step 1214. The method 1200 then loops back to step 1204 and calculates the asymmetric periodic current and voltage waveforms i out and V out The next cycle of is captured and the method repeats from there.

[0088] In step 1208, the threshold current crossing time t i-cross1 and t i-cross2 If is found in step 1206, the method proceeds to step 1216. In step 1216, the reset time is determined to be equal to the second threshold current crossing time (t reset =t i-cross2 In other words, the reset time t reset is the output current waveform i out rises to its positive peak current value and falls to its negative peak current value (first, the threshold current i threshold), then rises again, the second time to the threshold current value i threshold Also, in step 1216, the minimum pulse width is set to be the total time it takes to reach the first threshold current crossing time (t pulse_min =t i-cross1 In other words, the minimum pulse width t pulse_min is the output current waveform i out rises to its positive peak current value and then falls, first to a threshold current value i threshold The time taken to reach the target position is set to be the total time it takes.

[0089] In step 1218, the threshold voltage value V threshold (See FIG. 10) is calculated. When using the one switch one source configuration of FIG. 7B, the threshold voltage value V threshold is calculated as shown in FIG. 15. When using the one switch two source configuration of FIG. threshold is calculated as shown in FIG.

[0090] In step 1220, the threshold voltage value V threshold After is calculated, the timing parameter estimator 634 estimates the voltage threshold crossing time t v-cross Regarding the voltage waveform V out In step 1222, the maximum pulse width is calculated based on the voltage threshold crossing time t v-cross (t pulse_max =t v-cross In other words, the maximum pulse width is set to be out rises to its positive peak voltage value and then drops to the threshold voltage value V threshold The time taken to reach the target position is set to be the total time it takes.

[0091] Step 1224 determines whether the current pulse width is equal to or smaller than the minimum pulse width t with a predefined tolerance, which is a design choice value. pulse-min and maximum pulse width t pulse_maxIf the current pulse width is within this range, the current pulse width is kept as the pulse width (step 1226) and the method 1200 loops back to step 1204 and calculates the asymmetric periodic current and voltage waveforms i provided by the measurement section 620. out and V out The next cycle of is captured and the method repeats from there.

[0092] In step 1224, the current pulse width is compared to the minimum pulse width t pulse-min and maximum pulse width t pulse_max If not, the pulse width is recalculated in step 1228. The pulse width is then adjusted to the minimum pulse width t pulse_min and maximum pulse width t pulse_max In one embodiment, the pulse width is set to be anywhere between pulse_width=t pulse_min +w0(t pulse_max -t pulse_min ) where w0 is a design option value between 0 and 1. After the pulse width is recalculated in step 1228, the method 1200 loops back to step 1204 and calculates the asymmetric periodic current and voltage waveforms i out and V out The next cycle of is captured and the method repeats from there.

[0093] FIG. 13 shows the gate drive pulse width and reset time t reset 7 is a flowchart depicting a method 1300 performed by a timing parameter estimator 634 associated with an implementation of the bias source 208 having one switch and one source to set V. The method 1300 may be performed, for example, in conjunction with the one switch one source configuration of FIG.

[0094] 13, in step 1302, the timing parameter estimator 634 determines a default threshold current value i threshold, the default gate drive pulse width, and the default reset time t reset In step 1304, the timing parameter estimator 634 loads the output current waveform i out In one embodiment, for example, the estimator 634 captures the asymmetric periodic current waveform i provided by the measurement section 620, as depicted in FIG. out In step 1306, the timing parameter estimator 634 captures one cycle of a complete digital representation of the first threshold current crossing time t i-cross1 and the second threshold current crossing time t i-cross2 Regarding the output current waveform i out Search for.

[0095] In step 1308, the threshold current crossing time t i-cross1 and t i-cross2 If not found in step 1306, the method proceeds to step 1310, where the gate drive pulse width is set as the default pulse width or a previously calculated pulse width, and the reset time t reset is set as the default reset time or a previously calculated reset time. Then, in step 1312, the threshold current value i threshold is calculated as described with reference to FIG. 14, and the threshold current i threshold is updated with this calculation in step 1314. The method 1300 then loops back to step 1304 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0096] In step 1308, the threshold current crossing time t i-cross1 and t i-cross2 If is found in step 1306, the method proceeds to step 1316. In step 1316, the reset time is determined to be equal to the second threshold current crossing time (t reset =t i-cross2 In other words, the reset time t reset is the output current waveform iout rises to its positive peak current value and falls to its negative peak current value (first, the threshold current i threshold ), then rises again, the second time to the threshold current i threshold The time taken to reach the target position is set to be the total time it takes.

[0097] Also, in step 1316, the minimum pulse width is determined to be less than the first threshold current crossing time (t pulse_min =t i-cross1 In other words, the minimum pulse width t pulse_min is the output current waveform i out rises to its positive peak current value and then falls, first to a threshold current value i threshold In step 1318, the maximum pulse width is set to be the total time it takes to reach the second threshold current crossing time (t pulse_max =t i-cross2 In other words, the maximum pulse width t pulse_max is the reset time t reset is set to be equal to

[0098] Step 1320 is a step of computing the minimum pulse width t pulse-min and maximum pulse width t pulse_max If the current pulse width is within this range, the current pulse width is kept as the pulse width (step 1322) and the method 1300 then loops back to step 1304 and determines whether the asymmetric periodic current waveform i provided by the measurement section 620 is within the range between out The next cycle of is captured and the method repeats from there.

[0099] In step 1320, the current pulse width is compared to the minimum pulse width t with a predefined tolerance, which is a design choice value. pulse-min and maximum pulse width t pulse_maxIf not, the pulse width is recalculated in step 1324. The pulse width is set to be somewhere between the minimum pulse width and the maximum pulse width. In one embodiment, the pulse width is set as pulse_width=t pulse_min +w0(t pulse_max -t pulse_min ) where w0 is a design option value between 0 and 1. After the pulse width is recalculated in step 1324, the method 1300 loops back to step 1304 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0100] In summary, Figure 11-13 shows the relationship between the gate drive pulse width and the reset time t reset Three different methods for calculating the maximum gate drive pulse width are depicted, which differ mainly in the way in which the maximum gate drive pulse width is calculated. When the one switch, one source configuration of FIG. 7B or the one switch, two source configuration of FIG. 8 are used, the maximum gate drive pulse width is calculated based on the output current waveform i out , i.e., t pulse_max =0.5(t i-cross1 +t i-cross2 ) or the output voltage waveform V out , i.e., t pulse_max =t v-cross When the one switch, one source configuration of FIG. 7A is used, the maximum gate drive pulse width can be calculated by using out , i.e., t pulse_max =t i-cross2 =t reset It is calculated by using

[0101] 14, what is shown is the determination of the threshold current value i in step 1112 of FIG. 11, step 1212 of FIG. 12, and step 1312 of FIG. threshold14 is a flow chart depicting a method 1400 for calculating the threshold current i in any of the methods used in conjunction with the one-switch configurations of FIGS. threshold is used to calculate

[0102] Step 1402 of the method 1400 comprises determining a compensation current value I comp Determines whether the compensation current I comp is the current flowing through the inductor 214 and power supply 216 of the bias supply 208 (FIG. 2) and may not be directly available, for example, if a sensor configured to measure the compensation current value is present. comp is directly available, the threshold current value i threshold In step 1406, the compensation current I comp The negative value of i threshold =w1*I comp where w1 is a designer choice value between 0 and -1.

[0103] Compensation current value I comp If t is not directly available, then in step 1404, t is set to 0 and the reset time t reset (t reset =t i-cross2 ) to the end of period (t4) out The negative mean value of I comp =-k*(t reset from i to the end of the cycle out , where k is a designer-selected value between 0 and 1. The compensation current value I comp After is calculated in step 1404, the threshold current value i is calculated in step 1406 as described above. threshold is used to calculate

[0104] 15, what is shown is the threshold voltage value V V in step 1218 of FIG. 12 when using a bias source having a one switch, one source configuration such as that depicted in FIGS. 7A and 7B. threshold 15 is a flow chart depicting a method 1500 for calculating an output voltage waveform V. out Determines whether the data is DC-coupled or AC-coupled. Output voltage waveform V out When the data is AC-coupled, the threshold voltage value V threshold In step 1504, V supply (first power supply voltage 216). The output voltage waveform V out If the data is DC-coupled, the threshold voltage value V threshold is set to be zero in step 1506.

[0105] 16, what is shown is the threshold voltage value V V in step 1218 of FIG. 12 when using a bias supply having a one switch, two source configuration such as that of FIG. threshold 16 is a flow chart depicting a method 1600 for calculating an output voltage waveform V. out Determines whether the data is DC-coupled or AC-coupled. Output voltage waveform V out When the data is AC-coupled, the threshold voltage value V threshold In step 1604, V supply (first power supply voltage 216) and V rail (second power supply voltage 218). The output voltage waveform V out If the data is DC-coupled, the threshold voltage value V threshold In step 1606, V rail (second power supply voltage 218).

[0106] 17 and 18, shown are examples of switch networks having two-switch configurations that may be implemented in switch network 220 of bias supply 208 (FIG. 2). FIG. 17 depicts a two-switch configuration that may be implemented in a one-source configuration, i.e., bias supply 208 includes only first power supply 216 and is controlled by an associated one-source control system, such as that of FIG. 6. FIG. 18 depicts a two-switch configuration that may be implemented in a two-source configuration, i.e., bias supply 208 includes first power supply 216 and second power supply 218 and is controlled by an associated two-source control system, such as that of FIG. 5.

[0107] 17, shown is a schematic diagram depicting a switch network 1820A, an example of a switch network 220 having two switches S1 and S2, in which the bias supply 208 includes only the first power supply 216 and may be deployed in conjunction with a one-source configuration controlled by an associated one-source control system such as that of FIG. 6. In the variation depicted in FIG. 17, a series combination of a first switch S1 and a first diode D1 is arranged between the feedback node 212 of the bias supply 208 and a node 1862. In addition, a series combination of a second switch S2 and a second diode D2 is arranged between the node 1862 of the bias supply 208 and the feedback node 212. As shown in FIG. 17, a first diode D1 is arranged between the first switch S1 and the node 1862, with its anode coupled to the first switch S1 and its cathode coupled to the node 1862. A second diode D2 is arranged between the second switch S2 and the node 1862, with its cathode coupled to the second switch S2 and its anode coupled to the node 1862. In this arrangement, the cathode of the first diode D1 is coupled to the anode of the second diode D2 at the node 1862.

[0108] 18, shown is a schematic diagram depicting a switch network 1420A, an example of a switch network 220 having two switches S1 and S2, in which the bias source 208 includes a first power source 216 and a second power source 218, and may be deployed in conjunction with a two-source configuration controlled by an associated two-source control system, such as that of FIG. 5. The switch network 1420A couples to the bias source 208 at a node 1050, a feedback node 212, and an output node 210. Also shown for reference within the switch network 1420A is a node 1460. As depicted, the switch network 1420A comprises a first switch S1 arranged in series with a first diode D1 between the node 1050 and a node 1460. The cathode of the diode D1 is coupled to the node 1460, and the anode of the diode D1 is coupled to the switch S1. The switch network 1420A also includes a second switch S2 arranged in series with a second diode D2 between the feedback node 212 and a node 1460. The anode of the diode D2 is coupled to the node 1460 and the cathode of the diode D2 is coupled to the switch S2. In addition, an inductor L1 is positioned between the node 1460 and the output node 210.

[0109] 17 and 18, it should be appreciated that because switch S1 and diode D1 are arranged in series, the order of switch S1 and diode D1 may be swapped. Similarly, because switch S2 and diode D2 are arranged in series, the order of switch S2 and diode D2 may be swapped.

[0110] 19, shown is a graph and timing diagram illustrating aspects of a bias supply comprising a switching network having two switches S1 and S2, such as the switching networks of FIGS. 17 and 18. The switches S1 and S2 are connected to each other to generate the asymmetric periodic voltage and current waveforms V out and i outIn operation, the first diode D1 conducts when the first switch S1 is closed (on), and the second diode D2 conducts when the second switch D2 is closed (on).

[0111] Referring to Figure 19, the output current waveform i out At time t0 (when switch S1 is closed), the first threshold current value (I o The output current waveform i rises from a positive peak current value (which may or may not be equal to i out Then, the output current waveform i drops from the positive peak current value, reaches the first threshold current level, and plateaus. After switch S1 is opened (off), at time t2, switch S2 is closed (on), and the output current waveform i out The output current waveform i drops to a negative peak current value. out Then, the current rises from the negative peak value and reaches a second threshold current value (I o (which may or may not be equal to ). out Then, at time t4, the cycle ends and S1 is closed (on) again, causing a slight negative compensation current -I o gradually becomes flat.

[0112] As depicted, the bias supply 208 disclosed herein provides an asymmetric periodic voltage waveform V out between the output node 210 and the feedback node 212 from time t0 to t4. As shown, an asymmetric periodic voltage waveform V out includes a first portion starting at time t0 with a first negative voltage value until t1, at which time the voltage waveform V rises to a positive peak voltage value. During a second portion from t1 to t3, the voltage waveform V out has a transition slope portion during the dead time from t1 to t2, and then at time t2, the quantity V step The voltage waveform V drops to a third (negative) voltage value at time t3. outA third portion (from time t3 to t4) includes a voltage ramp between a third voltage level and a fourth negative voltage level (at time t4).

[0113] As shown in FIG. 19, the asymmetric periodic voltage waveform has a voltage step V between times t2 and t3. step Equipped with V step is the ion at any energy level -E ion During the third portion of the asymmetric periodic voltage waveform, the sheath voltage corresponds to −(E ion +ΔEion) can become more negative so that ions at the energy level of

[0114] Also, what is shown in FIG. reset (Time t0 to t3) and t ramp (times t3 and t4). As shown, t reset is the asymmetric periodic voltage waveform V out t ramp V out Also shown in FIG. 19 is the third portion of the waveform, which corresponds to the compensation current I comp The compensation current I comp may be provided throughout the application of an asymmetric periodic voltage function, i out is the period during the third part of the asymmetric periodic voltage waveform (t ramp Between comp may or may not be equal to

[0115] The fundamental period (t0-t4) of the asymmetric periodic voltage waveform may be adjusted to adjust the spread of ion energy. As shown in FIG. 19, a complete current cycle occurs between the time t0 and t3 between the first and second portions of the asymmetric periodic voltage waveform. The time between complete current cycles is the time t between t3 and t4. ramp It is.

[0116] 19, switches S1 and S2 may be controlled with an adjustable dead time, which is the time from t1 to t2 (between after switch S1 is opened from a closed position and before switch S2 is closed). out may transition in the ramp profile to a second portion of the asymmetric periodic voltage waveform (during the dead time between times t1 and t2).

[0117] The dead time is controlled by the reset time t reset and reset time t reset and the slope time t ramp The ratio of t adjusts the average power. reset Control of the fundamental switching frequency allows the fundamental switching frequency to be controlled (eg, remain below a level that affects the plasma density within the plasma processing chamber 101).

[0118] Another aspect of control that can be achieved using the bias supply 208 disclosed herein is ion current compensation. More specifically, the length of the dead time, t ramp The length of and / or the period (t0 to t4) of the periodic voltage function may be controlled to control the level of ion current compensation. ramp , dead time, and / or I o The level f of the ion current I ion I o =I ion -(CCh+Cstr1)*slope and I comp =I ion -(CCh+Cstr0+Cstr1)*slope (slope is the output voltage V out , where .gamma. is the slope of the gradient .gamma..times ...

[0119] As shown in FIG. 19, when the ion current is overcompensated, the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t rampDue to the range of sheath voltages between times t3 and t4, there is a distribution of ion energies. However, the ion current is proportional to the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t ramp It should be appreciated that the sheath voltage V may be undercompensated so that it is not too negative during the time frame. s is substantially constant between times t3 and t4. out It is also possible to adjust the slope of the beam, which results in a very narrow distribution of ion energies.

[0120] Dead time and t ramp By adjusting both the frequency of the periodic voltage waveform, t ramp , and the frequency of the periodic voltage waveform. ramp It is also contemplated that the time may be shortened while still being shortened or lengthened.

[0121] To control the bias supply with a two-switch network, two gate drive pulse-width signals are required: a first pulse-width signal to close (ON) and open (OFF) the first switch S1, and a second pulse-width signal to open (ON) and close (OFF) the second switch S2. The timing parameter estimator 634 estimates the output current i out may detect when the current reverses (crosses a threshold current value) for the first and second time and generate separate pulse width signals to the gate drive signal generator 636 to open (off) the switches S1 and S2 at or after these times. Once the current reverses direction, current no longer flows through the active switch and it may be safely opened (off). The second switch S2 is connected to the gate drive signal generator 636 via the gate drive signal generator 636 to generate a voltage output waveform V out But at time t ramp The reset time t resetBefore the gate pulse width, reset time t0 must be calculated. Thus, as in a single switch configuration, there is a range of pulse widths within which the pulse width can fall. In addition, in a two-switch configuration, the time t2 at which the second switch S2 is closed (on) must be calculated. There is no need to calculate when the first switch S1 is closed (on) since it is automatically closed (on) at time t0 (as in a one-switch configuration). Figures 20-22, described below, show the gate pulse widths, reset time t0 for the first and second switches. reset , and the calculation of the closing (on) time for the second switch.

[0122] FIG. 20 is a timing diagram associated with an implementation of the bias supply 208 having two switches, with the gate drive pulse width t pulse1 and t pulse2 , the time for turning on the second switch t2, and the reset time t reset FIG. 20 illustrates various timing parameters used by the timing parameter estimator 634 in calculating the asymmetric periodic output voltage waveform V out A complete digital representation of one cycle of the asymmetric periodic current waveform i out 20 depicts a complete digital representation of one cycle of the voltage and current waveforms. Timing parameter estimator 634 may receive these representations of the voltage and current waveforms, for example, from measurement section 620. In the following description of FIG. 20, times t0-t4 are as shown in the timing diagram of FIG.

[0123] Referring to Figure 20, the output current waveform i out At time t0 (when switch S1 is closed), the first threshold current value i threshold1 The output current waveform i rises from the positive peak current value. out then drops from the positive peak current value to the first threshold current crossing time t i-cross1 In the first threshold current i threshold1After the switch S1 is opened (off), at time t2, the switch S2 is closed (on), and the output current waveform i out The output current waveform i drops to a negative peak current value. out then rises from the negative peak current value until the second threshold current crossing time t i-cross2 In the second threshold current i threshold2 The output current waveform i out Then, a slightly negative compensation current -I comp gradually flattens out until

[0124] The asymmetric periodic voltage waveform V in Figure 20 out includes a first portion starting at time t0 with a first negative voltage value until t1, at which time the voltage waveform V rises to a positive peak voltage value. During a second portion from t2 to t3, the voltage waveform V out has a transition slope portion during the dead time from t1 to t2, and then at time t2, the quantity V step The voltage waveform V drops to a third (negative) voltage value at time t3. out A third portion (from time t3 to t4) of the ramp is constant and negative between a third voltage level and a fourth negative voltage level (at time t4).

[0125] FIG. 21 shows the gate drive pulse width t pulse1 and t pulse2 , the time t2 for closing (turning on) the second switch S2, and the reset time t reset 17 is a flowchart depicting a method 2100 performed by the timing parameter estimator 634 in conjunction with an implementation of the bias source 208 having two switches to calculate V. The method 2100 may be performed in conjunction with a two-switch, single-source configuration, such as the configuration of FIG. 17, or in conjunction with a two-switch, two-source configuration, such as that shown in FIG.

[0126] 21, in step 2102, the timing parameter estimator 634 calculates the default first and second threshold current values ​​i threshold1 and i threshold2, default gate drive pulse width t pulse1 and t pulse2 , and the default reset time t reset In step 2104, the timing parameter estimator 634 loads the output current waveform i out In one embodiment, for example, the estimator 634 captures the asymmetric periodic current waveform i provided by the measurement section 620, as depicted in FIG. out In step 2106, the first and second threshold current values ​​i threshold1 and i threshold2 is calculated as shown in FIG.

[0127] Following calculation of the threshold current value in step 2106, the method 2100 determines a first pulse width t pulse1 and steps 2108-2126 for calculating a time t2 and a second pulse width t pulse2 Steps 2108-2126 for calculating the first pulse width and time for turning on the second switch S2 are described first.

[0128] In step 2108, the timing parameter estimator 634 calculates the output current i out The waveform has a first threshold current value i threshold1 At time t i-cross1 Regarding the output current i out In step 2110, the first threshold current crossing time t i-cross1 If not found, the method proceeds to step 2112, where the first gate drive pulse width t pulse1 as the default or previously calculated pulse width and sets the time t2 for the start of the second pulse (closing of switch 2) as the default or previously calculated time t2. The method 2100 then loops back to step 2104 and calculates the asymmetric periodic current waveform i outThe next cycle of is captured and the method repeats from there.

[0129] In step 2110, a first threshold current crossing time t i-cross1 If found, the method proceeds to step 2114. In step 2114, the minimum first pulse width is determined to be less than the first threshold current crossing time (t pulse1_min =t i-cross1 In other words, the minimum width of the first pulse (the time during which S1 is closed or turned on) is set equal to t0, i out rises to its positive peak current, and then, initially, the first threshold current value i threshold The time taken to descend to the point where the line crosses the line .

[0130] In step 2116, the current first pulse width t pulse1 is the minimum first pulse width t pulse1_min + First pulse width t if it exceeds the tolerance (design option value) pulse1 and time t2 are kept at their current values ​​in step 2118. The method 2100 then loops back to step 2104 and returns the asymmetric periodic current waveform i out In step 2116, the next cycle of the current first pulse width t pulse1 However, with a tolerance, the minimum pulse width t pulse1_min If the first pulse width t pulse1 In step 2120, the minimum first pulse width t pulse1_min +Tolerance(t pulse1 =t pulse1_min + tolerance).

[0131] In step 2122, time t2 (the time for the start of the second pulse to close (turn on) S2) is determined to be equal to the first pulse width t pulse1If +t2 is greater than the tolerance, t2 is kept the same in step 2124. The method 2100 then loops back to step 2104 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0132] In step 2126, the time t2 is set to the first pulse width t pulse1 If the time t2 is less than t, the time t2 is the first pulse width plus the dead time (the time from t1 to t2), that is, t2=t pulse1 +dead time. The method 2100 then loops back to step 2104 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0133] Second pulse width t pulse2 Steps 2128-2140 for calculating the first and second threshold current values ​​i in step 2106 are now described. threshold1 and i threshold2 Following the calculation of the output current i out The waveform has a second threshold current value i threshold2 At time t i-cross2 Starting from time t2, the output current i out In step 2130, the second threshold current crossing time t i-cross2 If not found, the method proceeds to step 2132 and determines the second gate drive pulse width t pulse2 as the default second pulse width or a previously calculated second pulse width, and reset time t reset as the default reset time or a previously calculated reset time. The method 2100 then loops back to step 2104 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0134] In step 2130, the second threshold current crossing time t i-cross2 If found, the method proceeds to step 2134. In step 2134, the minimum second pulse width is determined to be the second threshold current crossing time minus time t2 (t pulse2_min =t i-cross2 In other words, the minimum width of the second pulse (the time during which S2 is closed or turned on) is set equal to t2 from the output current waveform i out falls to its negative peak current value, and then the second threshold current value i threshold2 In addition, the reset time is set to be the total time it takes for the first threshold current crossing time (t reset =t i-cross2 ).

[0135] In step 2136, the current second pulse width t pulse2 However, with a tolerance, the minimum second pulse width t pulse2_min If the second pulse width t pulse2 is held at that current value in step 2138. The method 2100 then loops back to step 2104 and calculates the asymmetric periodic current waveform i provided by the measurement section 620. out The next cycle of is captured and the method repeats from there.

[0136] In step 2136, the current second pulse width t pulse2 However, with a tolerance, the minimum second pulse width t pulse2_min If the second pulse width is less than the minimum second pulse width t pulse2_min +Tolerance(t pulse2 =t pulse2_min + tolerance). The method 2100 then loops back to step 2104 and calculates the asymmetric periodic current waveform i out The next cycle of is captured and the method repeats from there.

[0137] FIG. 22 shows the first and second threshold current values ​​i threshold1 and i threshold2 17 and 18. FIG. 22 is a flowchart depicting a method 2200 for calculating i.e., for calculating the first and second threshold current values ​​in conjunction with the two-switch configuration of FIGS.

[0138] Step 2202 is a compensation current I comp is directly available, e.g. by being directly sensed. comp is the current that flows through the inductor 214 and the power supply 216 of the bias supply 208 (FIG. 2). comp is directly available, the first threshold current i threshold1 In step 2206, the compensation current I comp The negative value of i threshold1 =w1*I comp where w1 is a design option value between 0 and -1. Similarly, the second threshold current i threshold2 is 0 and the compensation current I comp The negative value of i threshold2 =w2*I comp where w2 is a design option value between 0 and -1.

[0139] Compensation current I comp If t is not directly available, then in step 2204, t reset (t reset =t i-cross2 ) to the end of period (t4) out The negative mean value of I comp =-k*(t reset from i to the end of the cycle out , where k is a design option value between 0 and 1. The compensation current I compAfter is calculated in step 2204, the threshold current i is calculated in step 2206 as described above. threshold is used to calculate

[0140] The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in processor executable code encoded in a non-transitory tangible processor-readable storage medium, or in a combination of the two. With reference to FIG. 23, for example, what is shown is a block diagram depicting physical components that may be utilized to realize the control aspects disclosed herein. As shown, a display 2312 and a non-volatile memory 2320 are coupled to a bus 2322, which is also coupled to a random access memory ("RAM") 2324, a processing portion (including N processing components) 2326, a field programmable gate array (FPGA) 2327, and a transceiver component 2328, including N transceivers. Although the components depicted in FIG. 23 represent physical components, FIG. 23 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 23 may be realized by a general structure or distributed among additional physical components. Additionally, it is contemplated that other existing and yet to be developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG.

[0141] The display 2312 generally operates to provide a user interface for a user, and in some implementations, the display is realized by a touch screen display. In general, the non-volatile memory 2320 is a non-transient memory that functions to store (e.g., persistently store) data and processor executable code (including executable code associated with steps resulting in the methods described herein). In some embodiments, for example, the non-volatile memory 2320 includes boot loader code, operating system code, file system code, and non-transient processor executable code to facilitate execution of the method of controlling the switch network of bias supplies. In some implementations, the timing parameter estimator 634 may be realized (at least in part) by the processor executing instructions, which may be stored as processor executable code in the non-volatile memory 2330.

[0142] In many implementations, the non-volatile memory 2320 is realized by a flash memory (e.g., NAND or ONENAND memory), although it is contemplated that other memory types may be utilized as well. While it may be possible to execute code from the non-volatile memory 2320, executable code in the non-volatile memory is typically loaded into RAM 2324 and executed by one or more of the N processing components in the processing portion 2326.

[0143] The N processing components, in association with the RAM 2324, generally operate to execute instructions stored in the non-volatile memory 2320 to enable execution of the algorithms and functions disclosed herein. It should be appreciated that while several algorithms are disclosed herein, some of these algorithms are not represented in a flow chart. Processor executable code for effecting the methods described herein may be stored persistently in the non-volatile memory 2320 and executed by the N processing components associated with the RAM 2324. As one skilled in the art would appreciate, the processing portion 2326 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing components or a combination of hardware and software processing components (e.g., an FPGA or FPGAs including digital logic processing portions).

[0144] Additionally or alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 2320 and accessed (e.g., during boot-up) to configure a field programmable gate array (FPGA) to implement the algorithms disclosed herein.

[0145] The input component 2330 may receive signals (e.g., signals indicative of the current and voltage obtained at the output of the disclosed bias supply). In addition, the input component 2330 may receive phase information and / or synchronization signals between the bias supply 108 and the source generator 112 indicative of one or more aspects of the environment in the plasma processing chamber 101 and / or the synchronized control between the source generator and the single switch bias supply. The signals received at the input component may include, for example, from synchronization signals, power control signals for various generators and power supply units, or control signals from a user interface. Those skilled in the art will readily appreciate that any of a variety of types of sensors, such as, but not limited to, directional couplers and voltage-current (VI) sensors, may be used to sample power parameters such as voltage and current, and signals indicative of the power parameters may be generated in the analog domain and converted to the digital domain.

[0146] As one of ordinary skill in the art would understand in light of this disclosure, the output components may operate to provide one or more analog or digital signals to effect (at least in part) the opening and closing of switches S1 and S2. The output components may also control a voltage source, as described herein.

[0147] The depicted transceiver component 2328 includes N transceiver chains that may be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., Wifi, Ethernet, Profibus, etc.).

[0148] As will be appreciated by those skilled in the art, aspects of the present disclosure may be embodied as a system, method, or computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may all generally be referred to herein as a "circuit," "module," or "system." Additionally, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

[0149] As used herein, the recitation of "at least one of A, B, or C" or "at least one of A, B, and C" is intended to mean "any of A, B, C, or any combination of A, B, and C." The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a bias supply for applying a periodic voltage, comprising: a switch network and at least one power supply configured to apply, in combination, asymmetric periodic voltage and current waveforms; a timing parameter estimator configured to generate a pulse width control signal based on a first crossing time at which the current waveform crosses a threshold current value after dropping from a positive peak current value; a gate drive signal generator configured to provide a gate drive signal to at least one switch of the switch network to control application of the asymmetric periodic voltage waveform in response to the pulse width control signal received from the timing parameter estimator; and a bias supply source comprising:

2. The bias supply of claim 1 , wherein the switch network comprises a single switch.

3. 3. The bias supply of claim 2, wherein the timing parameter estimator determines a minimum pulse width to be the first crossing time at which the current waveform crosses the threshold current value.

4. The timing parameter estimator determining a second crossing time at which the current waveform crosses a threshold value after rising from the negative peak current value; determining a maximum pulse width midway between the first crossing time and the second crossing time; 4. The bias supply of claim 3, wherein the pulse width control signal is controlled to be between the minimum pulse width and the maximum pulse width.

5. The bias supply of claim 4 , wherein the bias supply comprises either one power supply or two power supplies.

6. 5. The bias supply of claim 4, further comprising an inductor in series with the at least one power supply such that a compensation current flows through the inductor, and the threshold current value is determined from the compensation current.

7. The timing parameter estimator determining that the threshold current value is a negative percentage of the compensation current if the compensation current is directly available; 7. The bias supply of claim 6, wherein if the compensation current is not directly available, the compensation current is determined to be a negative average value of the current waveform from the second crossing time to the end of a full cycle, and the threshold current value is determined to be a negative percentage of the determined compensation current.

8. The timing parameter estimator determining a maximum pulse width is a voltage threshold crossing time at which the asymmetric periodic voltage waveform crosses a threshold voltage value after dropping from a positive peak voltage value; controlling the pulse width control signal to be between the minimum pulse width and the maximum pulse width; The bias supply of claim 3 configured to:

9. The bias supply voltage V ｓｕｐｐｌｙ a single power supply having The timing parameter estimator determines whether the threshold voltage value is V when the asymmetric periodic voltage waveform is AC-coupled. ｓｕｐｐｌｙ Determined that 9. The bias supply of claim 8, wherein the timing parameter estimator determines that the threshold voltage value is zero when the asymmetric periodic voltage waveform is DC-coupled.

10. The bias supply voltage V ｓｕｐｐｌｙ a first power supply having a voltage V ｒａｉｌ and a second power source having The timing parameter estimator determines whether the threshold voltage value is V when the asymmetric periodic voltage waveform is AC-coupled. ｓｕｐｐｌｙ and V ｒａｉｌ configured to determine that the sum of The timing parameter estimator determines whether the threshold voltage value is V when the asymmetric periodic voltage waveform is DC-coupled. ｒａｉｌ 9. The bias source of claim 8, configured to determine that:

11. The timing parameter estimator determining a second crossing time at which the current waveform crosses a threshold value after rising from a negative peak current value; determining a maximum pulse width to be the second crossing time; controlling the pulse width control signal to be between the minimum pulse width and the maximum pulse width; The bias supply of claim 3 configured to:

12. The bias supply of claim 11 , wherein the bias supply comprises a single power supply.

13. The bias supply of claim 1 , wherein the switch network comprises two switches.

14. The current waveform is ０ the positive peak current value, the positive peak current value, the positive peak current value, the positive peak current value, the first threshold ... ２ has a relatively flat profile during the dead time up to time t ２ the current begins to fall to a negative peak current value at time t, rises from the negative peak current value, and crosses a second threshold current value at a second threshold current crossing time; 14. The bias supply of claim 13, wherein the timing parameter estimator is configured to determine a minimum first pulse width for controlling a first switch of the switch network to be the first threshold current crossing time, and to control a first pulse width control signal for controlling the first switch to be at least the minimum first pulse width plus a predetermined tolerance.

15. a bias supply for applying a periodic voltage, comprising: a switch network and at least one power supply configured to apply, in combination, asymmetric periodic voltage and current waveforms; A processor and non-volatile memory, the non-volatile memory comprising non-transient processor-executable instructions, the instructions comprising: generating a pulse width control signal based on a first crossing time at which the current waveform crosses a threshold current value after dropping from a positive peak current value; a processor and non-volatile memory comprising instructions for performing a gate drive signal generator configured to provide a gate drive signal to at least one switch of the switch network in response to the pulse width control signal to control application of the asymmetric periodic voltage waveform; a bias supply source comprising:

16. 16. The bias supply of claim 15, wherein the instructions comprise instructions for determining a minimum pulse width to be the first crossing time at which the current waveform crosses the threshold current value.

17. The instruction: determining a second crossing time at which the current waveform crosses a threshold value after rising from a negative peak current value; determining a maximum pulse width halfway between the first crossing time and the second crossing time; controlling the pulse width control signal to be between the minimum pulse width and the maximum pulse width; 17. The bias supply of claim 16, comprising instructions for:

18. The instruction: determining a maximum pulse width is a voltage threshold crossing time at which the asymmetric periodic voltage waveform crosses a threshold voltage value after dropping from a positive peak voltage value; controlling the pulse width control signal to be between the minimum pulse width and the maximum pulse width; 17. The bias supply of claim 16, comprising instructions for:

19. The instruction: determining a second crossing time at which the current waveform crosses a threshold value after rising from a negative peak current value; determining a maximum pulse width to be the second crossing time; controlling the pulse width control signal to be between the minimum pulse width and the maximum pulse width; 17. The bias supply of claim 16, comprising instructions for:

20. The current waveform is ０ the positive peak current value, the positive peak current value, the positive peak current value, the positive peak current value, the first threshold ... ２ has a relatively flat profile during the dead time up to time t ２ the current begins to fall to a negative peak current value at a second threshold current crossing time, and rises from the negative peak current value and crosses a second threshold current value at a second threshold current crossing time, and the command determining a minimum first pulse width for controlling a first switch of the switch network to be the first threshold current crossing time, and controlling a first pulse width control signal for controlling the first switch to be at least the minimum first pulse width plus a predetermined tolerance; 17. The bias supply of claim 16, comprising instructions for:

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