Method and system for reticle enhancement techniques

Abstract

The method incorporates a variable sidewall angle (VSA) into the calculated pattern using mask 3D (M3D) effects. An embodiment includes inputting mask exposure information, calculating mask 2D (M2D) effects from the mask exposure information, and determining an M3D effect from the M2D effects. Determining the M3D effect may include determining the VSA, such as using a neural network. An embodiment may include determining a dose margin from the mask exposure information, calculating the VSA using the dose margin, and calculating a pattern on the substrate using the calculated VSA, where the calculation of the pattern on the substrate includes the mask 3D effects.

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 267,249, entitled "Method for Reticle Enhancement Technology," filed January 28, 2022, which is incorporated by reference in its entirety herein. [Background technology]

[0002] In sub-micron manufacturing, lithography techniques are used to build layers of materials on a substrate to create transistors, diodes, light emitting diodes (LEDS), capacitors, resistors, inductors, sensors, wires, light wires, microelectromechanical systems (MEMS), and other elements that collectively create a device that performs some function. Substrate lithography is a printing process that uses a mask, sometimes called a reticle, to transfer a pattern onto a substrate to create the device. In the production or manufacturing of devices such as integrated circuits or flat panel displays, substrate lithography can be used to manufacture the device. When the device being created is an integrated circuit, the substrate is typically a silicon wafer. In the creation of integrated circuits, the lithography is semiconductor lithography, and in mass production, substrate lithography is typical. Other substrates can include flat panel displays, liquid panel displays, masks for flat panel displays, nanoimprint masters, or other substrates, as well as other masks.

[0003] In semiconductor lithography, a mask or masks may contain a circuit pattern that corresponds to an individual layer of an integrated circuit, or a portion of a layer in a multiple patterning process. This pattern can be imaged onto a predetermined area on a substrate that is coated with a layer of radiation-sensitive material known as photoresist or resist. Once the patterned layer is transferred, the layer may undergo various other processes such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes are used to finish the individual layers of the substrate. If several layers are required, the entire process, or a variation of it, is repeated for each new layer. Eventually, a combination of multiple devices, which may be integrated circuits, will be present on the substrate. These integrated circuits can then be separated from each other by dicing or sawing and mounted in individual packages.

[0004] In the production or manufacturing of semiconductor devices such as integrated circuits, optical lithography may be used to fabricate the semiconductor devices. Optical lithography is a printing process in which a lithographic mask or photomask produced from a reticle is used to transfer a pattern onto a substrate such as a semiconductor or silicon wafer to create an integrated circuit (IC). Other substrates may include flat panel displays, holographic masks, or even other reticles. Traditional optical lithography uses a light source having a wavelength of 193 nm, although extreme ultraviolet (EUV) or X-ray lithography are also considered as types of optical lithography in this application. A reticle or reticles may contain circuit patterns corresponding to individual layers of an integrated circuit, which may be imaged onto predetermined areas on a substrate coated with a layer of radiation-sensitive material known as photoresist or resist. Once the patterned layer is transferred, the layer may undergo various other processes such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes are used to finish off the individual layers of the substrate. If several layers are required, the entire process, or a variation thereof, is repeated for each new layer. Eventually, a combination of multiple devices or integrated circuits will be present on the substrate. These devices can then be separated from one another by dicing or sawing and mounted in individual packages. In the more general case, the pattern on the substrate can be used to define artifacts such as display pixels, holograms, directed self-assembly (DSA) guard bands, or magnetic recording heads. Conventional optical lithography writers typically reduce the pattern on the photomask by a factor of four during the optical lithography process. Thus, the pattern formed on the reticle or mask must be four times larger than the size of the desired pattern on the substrate or wafer.

[0005] Using 193 nm light waves, optical lithography works with refractive optics and transmissive photomasks or reticles. The mask selectively blocks, partially blocks, or transmits light waves on a substrate that is usually resist coated during the lithography process to partially expose or expose different portions of the substrate or different portions of some material on the substrate. Masks are usually 4x magnification of the target substrate dimensions.

[0006] Extreme ultraviolet lithography (EUV) uses light with a wavelength of about 13.5 nm with reflective optics. Some embodiments use an anamorphic mask with a magnification of 8x in one dimension and 4x in the other dimension.

[0007] In general, shorter wavelengths of light can resolve finer geometries, finer spaces between geometries, and higher frequency (density) of features on a substrate. Also, smaller wavelengths of light are generally more difficult to reliably produce and control. Economically, it is best to use the largest wavelength of light that can resolve the size, space, and frequency of features required for the device. Therefore, there is an interest in improving the resolution achievable on a substrate with any given wavelength of light.

[0008] For any lithography of a given resolution, additional techniques such as off-axis illumination, phase-shifting masks, and multiple patterning extend the resolution capabilities. When multiple patterning is used, a single substrate layer is exposed multiple times, each time using a different mask, called a mask layer.

[0009] In lithography, a lithography mask or reticle contains a geometric pattern that corresponds to the circuit components to be fabricated on a substrate. The patterns used to manufacture the reticle may be generated utilizing computer-aided design (CAD) software or programs. In designing the pattern, the CAD program may follow a set of predefined design rules to create the reticle. These rules are set according to process, design, and end-use limitations. An example of an end-use limitation is defining the geometry of a transistor such that it cannot operate satisfactorily at a required power supply voltage. In particular, design rules may define the spacing tolerance between circuit devices or interconnect lines. Design rules are used, for example, to ensure that circuit devices or wires do not interact with each other in undesirable ways. For example, design rules are used to ensure that wires are not too close together and may cause a short. Design rule limitations reflect, among other things, the smallest dimensions that can be reliably fabricated. When referring to these small dimensions, the concept of critical dimensions is usually brought into play. These are defined, for example, as the smallest width of a line or the smallest space between two lines, and these dimensions require precise control.

[0010] One goal of integrated circuit manufacturing by optical lithography is to reproduce the original circuit design on a substrate using a reticle. Integrated circuit manufacturers are always trying to use the area of ​​a semiconductor wafer as efficiently as possible. Engineers continue to reduce the size of circuits to allow integrated circuits to contain more circuit elements and use less power. As the size of the critical dimensions of integrated circuits is reduced and their circuit density increases, the critical dimensions of the circuit pattern or physical design are approaching the resolution limit of the exposure equipment used in traditional optical lithography. As the critical dimensions of the circuit pattern become smaller and approach the resolution value of the exposure equipment, it becomes more difficult to accurately transfer the physical design into the actual circuit pattern that is developed on the resist layer. To further use optical lithography to transfer patterns with features smaller than the wavelength of light used in the optical lithography process, a process known as optical proximity correction (OPC) was developed. OPC modifies the physical design to compensate for distortions caused by effects such as optical diffraction and the optical interaction of features with nearby features. OPC includes all resolution enhancement techniques that are performed on a reticle.

[0011] OPC can add sub-resolution lithographic features to the mask pattern to reduce the difference between the original physical design pattern, i.e., the design, and the final transferred circuit pattern on the substrate. The sub-resolution lithographic features interact with the original pattern in the physical design and with each other to compensate for proximity effects and improve the final transferred circuit pattern. One feature used to improve the transfer of the pattern is the Sub-Resolution Assist Feature (SRAF). Another feature added to improve the transfer of the pattern is called a "serif." Serifs are small features that are placed at the interior and exterior corners of the pattern and can sharpen the corners of the final transferred image. The precision required for the surface manufacturing process of SRAF is often less than the precision required for the pattern that is intended to be printed on the substrate, often referred to as the primary feature. Serifs are part of the primary feature. As the limits of optical lithography extend much further into the sub-wavelength region, OPC features must become more and more complex to compensate for the more delicate interactions and effects. As imaging systems are pushed closer to their limits, the ability to produce reticles with sufficiently fine OPC features becomes important. Adding serifs or other OPC features to a mask pattern is beneficial, but still significantly increases the total feature count of the mask pattern. For example, adding serifs to each corner of a square using conventional techniques adds eight more rectangles to the mask or reticle pattern. Adding OPC features is a very laborious task, requiring costly computation time and making the reticle more expensive. Not only are OPC patterns complex, but optical proximity effects are extensive compared to the minimum line and space dimensions, so the correct OPC pattern at a given location is highly dependent on what other geometry is in the vicinity. Thus, for example, the end of a line will have different sized serifs depending on what is in its vicinity on the reticle. This is even though the objective may be to produce the exact same shape on the wafer. These slight but crucial variations are significant and prevent others from being able to form reticle patterns.It is common to describe the OPC decorated pattern written on the reticle in terms of main features, which are features that reflect the design prior to OPC decoration, and OPC features, which may include serifs, jogs, and SRAFs. Quantifying what slight differences mean, typical slight variations in OPC decoration per neighborhood can be 5%-80% of the size of the main feature. For clarity, note that design variations in OPC are what is being referred to. Manufacturing variations such as corner rounding are also present in the actual surface pattern. What these OPC variations mean when creating substantially the same pattern on a wafer is that the geometry on the wafer is targeted to be the same within a specified tolerance, depending on the details of the feature that that geometry is designed to perform, for example, a transistor or a wire. Nevertheless, typical specifications are in the range of 2%-50% of the main feature. There are also many manufacturing factors that contribute to the variation, but the OPC component of that overall tolerance is often within the stated range. OPC shapes such as sub-resolution assist structures follow various design rules, including rules based on the size of the smallest feature that can be transferred to the wafer using optical lithography. As process nodes continue to shrink, the size of the smallest SRAF on a photomask also shrinks. For example, a 20 nm logic process node requires a 40 nm to 60 nm SRAF on the mask for the highest precision layer.

[0012] Inverse Lithography Technology (ILT) is a process in which a pattern formed on a reticle is calculated directly from a pattern desired to be formed on a substrate, such as a silicon wafer. This may involve simulating an optical lithography process in reverse using the desired pattern on the substrate as an input. The ILT calculated reticle patterns may be purely curvilinear, i.e., not perfectly linear, and may include circular, nearly circular, annular, nearly annular, elliptical and / or nearly elliptical patterns. These ideal ILT curve patterns are difficult and expensive to form on a reticle using conventional techniques, so a linear approximation or linearization of the curved patterns may be used. However, the linear approximation is less accurate compared to the ideal ILT curve patterns. Furthermore, when creating a linear approximation from an ideal ILT curve pattern, the overall calculation time increases compared to the ideal ILT curve pattern. In this disclosure, ILT, OPC, source mask optimization (SMO), and computational lithography are terms used interchangeably.

[0013] EUV optical lithography has a much higher resolution than conventional optical lithography. The very high resolution of EUV greatly reduces the need for OPC processing, resulting in lower mask complexity for EUV than for 193 nm optical lithography. However, because the resolution of EUV is so high, defects in the photomask, such as excessive line edge roughness (LER), are transferred to the wafer. Thus, the accuracy requirements for EUV masks are higher than those for conventional optical lithography. Furthermore, while the shape of an EUV mask is not complicated by the addition of complex SRAFs or serifs required for conventional 193 nm lithography, the shape of an EUV mask is complicated by the addition of several complexities that are unique to EUV manufacturing. Of particular relevance in writing patterns on masks for EUV lithography is the medium-range scattering of charged particles, such as electrons, which can affect a radius of about 2 μm. This medium-range scattering introduces new considerations in the preparation of mask data, because for the first time, influences from neighboring patterns have a significant effect on the shape that a given pattern is cast on the mask surface. Previously, when exposing a mask for use with conventional 193 nm lithography, short-range scattering only affected the pattern being written, while long-range scattering had a large enough effective range that it only affected the size of the pattern, not its detailed shape. This effect made it possible to correct for it by using dose modulation alone. Furthermore, as EUV processing of wafers is more costly, it is desirable to reduce or eliminate multiple patterning. In conventional optical lithography, multiple patterning is used to allow exposure of small features by exposing the pattern of one layer of wafer processing using multiple masks, each containing part of the layer pattern. To reduce or eliminate multiple exposures, a single mask must contain finer patterns. For example, a series of collinear line segments can be double patterned by first writing the long lines, then cutting the lines into line segments with a second mask in conventional lithography.The same layer written with a single mask, such as in EUV lithography, would require a mask containing many smaller line segments. Many more fine patterns must be written on a single mask, and each pattern must be more precise, increasing the need for precision in the EUV mask.

[0014] The mask, made with an electron beam (e-beam) machine that fires electrons at locations where the surface will be coated with photoresist, is then processed to create the desired openings in the mask. The amount of energy delivered to a spot on the mask is called the dose, which by convention may have no energy with dose set at 0.0 and standard dose set at 1.0. The pattern registers when the dose exceeds a certain threshold, by convention often near 0.5. Notably, the variation in critical dimension (CD) is inversely related to the slope of the dose curve at the resist threshold, called the edge slope or dose margin.

[0015] There are several techniques used by e-beam machines. Three common types of charged particle beam lithography are variable shaped beam (VSB), characteristic projection (CP), and multi-beam projection (MBP). The most commonly used system for the production of advanced masks is the VSB. VSB and CP are subcategories of shaped beam charged particle beam lithography, where an electron beam is shaped and directed by a series of apertures to expose a resist-coated surface. MBP uses multiple charged particle beams, while VSB and CP machines generally have a single beam.

[0016] When transferring a mask pattern to a substrate using substrate lithography, it is difficult to print features with sizes similar to or smaller than the wavelength of light used for lithography. The industry has applied various techniques to address the difficulty of reliably printing the desired shape on the substrate. The field of computational lithography has emerged to use computing to enhance substrate lithography, also known as wafer lithography in semiconductor lithography. Reticle enhancement technology (RET) includes computational methods and systems for designing target reticle shapes that will more accurately and more reliably project the desired pattern onto the substrate across manufacturing variations. RET often uses computation to enhance the image on the mask to more accurately and more reliably print the desired substrate pattern while being tolerant to manufacturing variations. Two common techniques for RET are optical proximity correction (OPC) and inverse lithography technology (ILT). OPC and ILT are often iterative optimization algorithms that adjust parameters that define the mask until the predicted pattern on the wafer is within tolerance of a set or range of conditions. OPC manipulates the mask geometry and simulates the pattern on the wafer near the edge of the target. ILT manipulates the transmission of the mask as pixels, while ILT typically simulates the entire pattern on the wafer. This process is known as dense simulation. An iterative optimization algorithm typically consists of (1) evaluating proposed solutions to assign a cost that it seeks to minimize, (2) stopping if the cost is below a cost criterion, (3) computing the gradient for each element of the proposed solution that leads to a lower cost, (4) adjusting the proposed solution according to the computed gradient, and (5) returning to (1). Typically, the cost is defined as a positive value, with zero being the best score, as assumed here. However, alternative cost definitions may be used.

[0017] RET generally means improving the printability of all desired features at standard (expected) manufacturing conditions and within expected manufacturing variations around the standard manufacturing conditions. Because manufacturing processes are not perfect, designs need to be resilient to expected given manufacturing variations. A larger process window means more resilience to manufacturing variations, specifically within acceptable tolerances of pattern mismatch due to defocus and dose variations. Providing sufficient process window for as many features as possible is the goal of RET. The percentage of chips that function as specified after manufacturing is often referred to as yield. Many factors affect yield. An improvement in process window is generally considered by those skilled in the art to correlate to an improvement in yield. Summary of the Invention [Problem to be solved by the invention]

[0018] In an embodiment, a method for a reticle enhancement technique (RET) for transferring a pattern to a substrate includes inputting mask exposure information, the mask exposure information including information for exposing the pattern on the substrate. Two-dimensional (2D) effects of the mask ("M2D effects") are calculated from the mask exposure information. The method further includes determining three-dimensional (3D) effects of the mask ("M3D effects") from the M2D effects using a neural network, the determining the M3D effects including determining a variable sidewall angle (VSA), calculating a calculated pattern on the substrate using the M3D effects, and modifying the mask exposure information based on the calculated pattern on the substrate.

[0019] In an embodiment, a method for calculating a pattern formed on a substrate using optical lithography with a mask includes inputting mask exposure information forming a pattern on the mask, determining a dose margin from the mask exposure information, calculating a variable sidewall angle (VSA) using the dose margin, and calculating a pattern on the substrate using the VSA, wherein calculating the pattern on the substrate includes mask 3D (M3D) effects.

[0020] In an embodiment, a system for reticle enhancement technology (RET) comprises a device configured to receive mask exposure information, a device configured to calculate a mask 2D (M2D) effect from the mask exposure information, a device configured to determine a mask 3D (M3D) effect from the M2D effect using a neural network, and a device configured to calculate a calculated pattern on a substrate using the M3D effects, where the mask exposure information includes information for exposing a pattern on the substrate, and where determining the M3D effect includes determining a variable sidewall angle (VSA). [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram of a chip design processed on a wafer as known in the art. [Diagram 2] A shows an example of a VSB shot versus a multi-beam shot, as known in the art.B shows an example of a VSB shot versus a multi-beam shot, as known in the art. [Diagram 3] 1 illustrates the Mask 3D (M3D) effect of 193i lithography, as known in the art. [Figure 4] 13 illustrates sidewall angles in cross-section of a mask profile, according to an embodiment. [Diagram 5] 1 illustrates a method for determining a variable sidewall angle (VSA), according to an embodiment. [Figure 6] 1 illustrates a method of simulation known in the art. [Figure 7]1 illustrates a method for simulating Masked 3D (M3D) effects using a Deep Learning Network (DLN), according to an embodiment. [Figure 8] 1 illustrates a DLN for generating an M3D effect from an M2D effect, according to an embodiment. [Figure 9] 1 illustrates a DLN for generating M3D images from M2D images, according to an embodiment. [Figure 10] 1 illustrates another DLN for generating M3D images from M2D images, according to an embodiment. [Figure 11] 1 is an exemplary flow of RET, according to an embodiment. [Figure 12] According to an embodiment, there is another embodiment of a method for calculating a pattern to be formed on a substrate using optical lithography with a mask. [Figure 13] FIG. 2 is a block diagram of a computing hardware system that can be used in the present disclosure, according to an embodiment. [Figure 14] FIG. 2 is a block diagram of another embodiment of a computational hardware system, a computational design platform (CDP), according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] In this disclosure, the use of the term wafer lithography refers to substrate lithography in general, i.e., the embodiments will be described with respect to semiconductor lithography as an example for ease of understanding, but also apply to other types of substrate lithography and all reticle enhancement techniques. In this disclosure, the term "substrate" can refer to a mask used in lithography, a silicon wafer, a flat panel display, a liquid panel display, a mask for a flat panel display, a nanoimprint master, or other substrate, or other mask.

[0023] Prior Art

[0024] A conventional semiconductor manufacturing flow 100 is shown in FIG. 1. A chip design is achieved by creating a composite of wafer layers in step 110. In step 120, some of the wafer layers are separated into mask layers. This step is sometimes called the coloring step, where each feature on the wafer layer is colored to reflect the assignment of the feature to a given mask layer. Once the mask layers are separately identified, each mask layer can undergo a RET step 130. A mask data preparation (MDP) step 140 then prepares the data for a mask writer, such as an e-beam machine. This step may include "splitting" the data into trapezoids, rectangles, or triangles. Mask process correction (MPC) geometrically corrects the shapes and / or assigns dose to the shapes to make the resulting shapes on the mask closer to the desired shape. MPC can be performed in step 130, or in step 140, or in step 150, or in any combination of steps 130, 140, and 150. Pixel level dose correction (PLDC) may also be applied in step 150. A mask is created and verified in step 150, which includes steps such as mask writing, mask inspection, metrology, mask defect handling, mask repair, and wafer surface inspection of the mask. In step 160, a wafer is written using successive collections of the mask created in step 150.

[0025] Each step in FIG. 1 may or may not have a verification step to fully verify or sanity check the output of those steps. In the art, some of the steps in FIG. 1 may be performed in different orders or in parallel. An example of pipelining in a semiconductor manufacturing process is when a design is divided into multiple tiles, e.g., an array of equal-sized tiles, and then a first step is performed on a tile, and then a second step is performed on the tile without waiting for other tiles to finish the first step. For example, the RET step 130 and the MDP step 140 may be pipelined to reduce turnaround time. In another example, the MPC of step 140 may be pipelined with the mask fabrication of step 150.

[0026] In wafer lithography, it has been found that when SRAFs are added to a mask that is too small to print itself, the key features are printed with greater fidelity and the process window is improved, but they nevertheless have a beneficial effect on how nearby key features are printed: they are separate features that are not associated with the key feature and are small enough that they are not printed on the substrate.

[0027] Calculating SRAF and key feature corrections is computationally intensive and results are fragile. False additional patterns may be printed, target patterns may not fit well, and process windows may be unnecessarily restricted. Typical RET methods include OPC verification to identify and correct hot spots. Hot spots are areas that (1) require ideal process conditions to print properly and are therefore not resilient to manufacturing variations or (2) do not print properly even under ideal process conditions. Hot spots lead to reduced yield.

[0028] For purposes of this disclosure, a shot is the exposure of a portion of a surface area over a period of time. The area may be composed of multiple discontinuous smaller areas. A shot may be composed of multiple other shots that may or may not overlap and may or may not be exposed simultaneously. A shot may include a predetermined dose or may be dose unspecified. A shot may use a shaped beam, an unshaped beam, or a combination of shaped and unshaped beams. In this disclosure, a charged particle beam system with multiple individually controllable beamlets is referred to as a multi-beam system. In some embodiments, charged particles from a single source may be subdivided to form multiple beamlets. In other embodiments, multiple sources may be used to create multiple beamlets. A set of exposure information may include one or more shots for exposing a mask used in semiconductor lithography.

[0029] ILT often produces unexpected, i.e., non-intuitive, mask patterns that provide superior results. ILT algorithms naturally create curvilinear shapes that contain many SRAFs. Thus, ILT algorithms targeting VSBs spend significant runtime converting the curvilinear shapes into approximations more suitable for VSB writing, a process often referred to as Manhattanization, for example, creating rectangles for each VSB shot 202, 204, 206, 208, and 210 as shown in FIG. 2A. Curvilinear shapes have proven impractical for conventional variable shaped beam (VSB) mask writers with breaks due to the need for so many VSB shots, such as shots 202-210, to expose the curvilinear shapes. For example, as shown in FIG. 2A, pattern 200 is a curvilinear shape formed from multiple VSB shots, such as shots 202-210. Mask writing time is a critical business factor, and VSB writing time scales with the number of VSB shots that need to be printed.

[0030] Curvilinear shapes take time to write using VSB and Manhattanized shapes. FIG. 2B shows how a multi-beam e-beam machine writes curvilinear shapes directly on the mask without additional time. A multi-beam system is a charged particle beam system with multiple individually controllable beamlets that can simultaneously expose pixels on a surface. In FIG. 2B, each pixel 220 of the pattern 200 is exposed by a beamlet of the multi-beam writer. Multi-beam allows ILT to output curvilinear shapes without the need for Manhattanization.

[0031] Multi-beam writing eliminates the need to Manhattanize curvilinear features for VSB writing. However, mask printability and resilience to manufacturing variations are still important considerations for mask features output by ILT. For example, features that are too small or too close together, or have feature contour angles that are too sharp, make the mask too difficult to manufacture reliably, especially across manufacturing variations.

[0032] The energy delivered by electrons from an e-beam machine when exposing a mask pattern is often approximated as a point spread function (PSF). There are many effects that affect how the energy spreads, but in the creation of e-beam based masks for either variably shaped beam or multi-beam writing, a monotonic continuous PSF is a reasonable representation of the energy distribution. In this disclosure, a simple single Gaussian distribution is used as the PSF, as will be readily understood, but the embodiments apply to any suitable PSF.

[0033] When energy is delivered over a large enough area with a Gaussian distribution and standard dose, there is enough dose for the interior of the area to reach the standard dose. However, if the area is small enough, the maximum dose inside the area will be less than the standard dose. Similarly, if the spacing between areas is large enough, the minimum dose will reach zero. However, if the spacing is small enough, the minimum dose will not reach zero. If either the area or the spacing between areas is small, the dose profile is shallow. Mask manufacturing processes are designed to provide sufficient dose margin for reasonable areas and spacings, e.g., 100 nm lines separated by 100 nm spaces, at standard dose for a typical advanced mask for 193i lithography. The smaller the area and spacing, the lower the dose margin at the contour edges of the area. The smaller the area, the worse the dose margin at a constant dose.

[0034] Dose margins are also reduced in a typical mask writing process due to proximity effect correction (PEC). Mask writing with e-beam, whether VSB, CP, or MBP, has a backscattering effect that is well known in the art. Electrons hit the resist surface and secondary electrons emitted by the electrons bounce around and expose the resist in a 10 micrometer scale region around the exposure location. This has the effect of partially exposing the resist in the surrounding 10 micrometer scale region. Backscattering is considered a long-range effect. The aggregate of these partial exposures from all exposures surrounding a given area is significant enough to require correction. Software-based corrections for backscattering and other long-range effects are called PEC and are typically applied along the mask writer during mask writing. PEC essentially reduces the standard dose of a shot (or pixel in the case of MBP) to compensate for the total backscatter dose from the surrounding shots (or pixels). Almost all production masks are written with PEC turned on in the machine. If the dose density in a 10 micrometer scale region is high, the amount of PEC applied is also high. This has the effect of reducing the Gaussian height (or PSF) of the exposure, and therefore reducing the dose margin at the contour edges of that high density region. Thus, a small feature written in an area of ​​high dose density will have a worse dose margin than a feature of the same size written in an area of ​​low dose density.

[0035] Dose margin is important because a lower dose margin means a larger difference in CD for a given dose rate of change. Measuring CD variation versus dose variation is an important measure of resilience to manufacturing variations, since dose margin is known by those skilled in the art to be a good proxy for many, if not the majority, sources of manufacturing variation.

[0036] Mask process corrections, which can be performed offline, pipelined, or in line with the mask writer, may manipulate the shape or dose applied to the mask to correct linearity and improve critical dimension uniformity (CDU) and line edge roughness (LER), among other measures of resilience to manufacturing variations. Improving CDU and LER includes improving dose margins and improving the uniformity of dose margins across the mask features. Dose margin (edge ​​slope) enhancements are disclosed in U.S. Patent No. 8,473,875, "Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography," owned by the assignee of the present application.

[0037] In a typical semiconductor manufacturing process, RET in step 130 of FIG. 1 generates a target mask. If the mask representation does not automatically satisfy all desired mask constraints and characteristics, such as allowable transmission values, minimum feature size, minimum spacing, or sufficient dose margin, among others, it is necessary to introduce terms to add costs associated with violation of these constraints in the assessment of the mask's suitability. In the field of inverse problems, introducing these terms is known as regularization, and is a means of selecting solutions from a potentially infinite set of solutions that match equally well or similarly well to the desired result, but also have other a priori desirable characteristics. An example of Inverse Lithography Technology (ILT) is disclosed in U.S. Pat. No. 10,657,213, entitled "Modeling of a Design in Reticle Enhancement Technology," which is owned by the assignee of the present disclosure and is incorporated herein by reference.

[0038] Semiconductor manufacturing and sub-micron manufacturing generally follow Moore's Law, which predicts that the manufacturing parts of the infrastructure advance together to improve resolution at a relatively predictable and steady rate over time. An important aspect of Moore's Law is that the computing power of the infrastructure scales along Moore's Law. This is because computing bandwidth, computing speed, memory capacity, memory access speed, communication bandwidth, communication speed, capacity and speed of long-term storage (whether solid state or hard disk), etc., become less effective with respect to power consumption and cost, which also follow Moore's Law. The introduction of new manufacturing techniques, such as EUV lithography or MBP-based mask writing, introduces discontinuities in computing requirements. The introduction of new computing techniques, such as faster graphics processing units (GPUs), also introduces discontinuities in computing capabilities and scalability.

[0039] Details of this embodiment

[0040] This disclosure describes a technique for determining mask 3D (M3D) effects. Use of this technique involves calculating variable sidewall angles (VSA) along the contour of the mask. Using VSA allows substrate patterns to be calculated more accurately than if a constant sidewall angle were assumed as in conventional techniques. This allows for more accurate creation of patterns on the substrate, resulting in higher yield production.

[0041] Conventional ILT uses a continuous tone mask to define a grayscale mask for the best process window, which is then converted to the actual mask shape, which is usually Manhattanized to be compatible with printing on a VSB mask writer. However, on the mask, the features printed are not Manhattan, and this disclosure demonstrates that by not considering the actual mask shape, current Manhattan Mask 3D (M3D) approximations using width, shape, and corner libraries are poor predictors of the final areal image.

[0042] Inverse Lithography Techniques (ILT) have long been considered the best way to maximize the overall process window of immersion lithography. Traditionally, ILT patterns are Manhattanized as part of the final optimization step, but with the advent of MBP mask writers, this is no longer necessary. To speed up M3D calculations, deep learning approaches using Convolutional Neural Networks (CNN) can be implemented.

[0043] The current state of the art for M3D correction in ILT or OPC assumes a constant given sidewall angle for every feature on the mask. M3D accounts for the thick mask effect to adjust the lithography simulation results. The difference in the predicted wafer contour between a contour assuming a thin mask (i.e. not considering M3D) and a contour with M3D can have as much as 5 nm of edge placement error (EPE), which is for example a 10 nm critical dimension (CD) difference. At advanced nodes, ILT accuracy is typically required to be better than 1 nm accuracy, so M3D is a significant effect. The importance and need for accuracy for EUV masks is increasing. The additional accuracy achievable by estimating the sidewall angle along the contour and adjusting the M3D prediction based on the different angles improves accuracy, which becomes increasingly important for finer features.

[0044] ILT adds some special considerations to the type of M3D simulation required. First, the inherent ILT shape is curvilinear. If the mask design is Manhattan, there are no sharp corners in the real mask. It is therefore important to simulate the shape of the real mask to get the correct effect. Furthermore, all ILT solutions go through a so-called grayscale mask (continuous-tone mask, or CTM). This CTM does not reflect the real mask topology, so any kind of M3D approximation cannot be made. The CTM needs to be quantized to the real material in order to extract the shape to feed to the M3D simulator. Regularization is a procedure and formulation that allows the CTM to be made into a quantized-tone mask (QTM) using the method described in U.S. Patent No. 7,716,627, "Solution-Dependent Regularization Method for Quantizing Continuous-Tone Lithography Masks," owned by the assignee of this disclosure.

[0045] FIG. 3 shows where the effect of thin masks, or mask 2D (M2D), comes from relative to the M3D effect of thick masks. The left and center images in each row of FIG. 3 are side views, while the right image is a plan view. Looking at the thin mask 300, a plane wave of incident light from a source 318 is incident at normal incidence 302 on the mask 300, which is assumed to be infinitely thin. Under this approximation, the diffraction orders 304 (near field) can be calculated by a simple Fourier transform. This can be compared to the thick mask 310 (top center image), where the mask topology is taken into account. Initially, the diffraction orders 314 of the thick mask 310 are the same as the diffraction orders 304 of the thin mask 300. However, now we need to resolve the standing wave of the incident light 309 on the other side of the mask. A simple ray trace shows that the higher diffraction orders 316 interact with the absorbing material 312 of the mask more than the most central diffraction order, introducing both a reduction in amplitude and a modulation in phase compared to the ideal case of the mask 300.

[0046] In the lower set of images, the off-axis incidence angles 319 for the thin mask 300 and 320 for the thick mask 310 have the same effect as in the upper set of images, except for the effect of an incident plane wave from a light source 328 that is not normally incident on the back side of the mask (off-axis illumination). The higher rightmost diffraction orders 326 interact with more absorbing material 322 than the center and left of the central diffraction order 324. In effect, this represents a source point along the ring, and is more representative of the actual illumination, even though for speed reasons normal incidence 302 from the light source 318 is a common approximation for most M3D engines. The effect of the incidence angles acts to rotate the diffraction orders in the frequency domain. With this in mind, when looking at the ray traces for the thick mask, there is a significant imbalance in the positive and negative orders, creating a complex diffractive system.

[0047] The amount of shadowing can vary depending on the angle of the sidewalls along the contour of the features on the mask. Figure 4 shows a cross section of a thick mask. The thickness 406 is the distance from the top and base 404 of the mask 402. A lateral distance 408 can be measured from the top edge and base. The sidewall angle 410 measures the slope from the base to the top. The larger the distance 408, the shallower the slope of the angle, which can result in unintended changes in the amount and phase of energy expected to reach the substrate, thus affecting the pattern formed on the substrate.

[0048] FIG. 5 is a schematic diagram of a method for determining a variable sidewall angle (VSA) using a neural network, according to an embodiment. A scanning electron microscope (SEM) image 500 is input to a neural network 510. Mask exposure information for an electronic design pattern, sometimes referred to as a computer-aided design (CAD) pattern, is determined. The CAD pattern is represented on a mask that is used to expose the pattern on a substrate. The neural network can be trained to generate a CAD pattern from the SEM image using a SEM, CAD pair, which was generated using another neural network to generate a SEM image from the CAD pattern, for example, as disclosed in U.S. Pat. No. 11,250,199, “Method and Systems for Generating Shape Data for Electronic Designs,” owned by CDLe, an affiliate of D2S, Inc., and incorporated by reference.

[0049] In one embodiment, the measurement of VSA may use both the top 402 and the base 404 of the thick mask shown in FIG. 4. In FIG. 5, a dose map of the top of mask 512 and a dose map of the bottom of mask 514 are determined by a neural network 510. The dose maps represent the patterns exposed with masks 512 and 514. The neural network 510 may be trained to learn to output the top and bottom of the thick mask. The top contour 522 and the bottom contour 524 may be obtained by setting a threshold of 0.5, where the light parts of 512 and 514 are at standard dose (1.0) and the dark parts are at 0 dose. The sidewall angle may be calculated by measuring the lateral distance between the top contour 522 and the bottom contour 524 (lateral distance 408 in FIG. 4) and the predetermined thickness between the top contour 522 and the bottom contour 524 (thickness 406 in FIG. 4).

[0050] In another embodiment, the VSA may be determined as a direct transfer from the dose margin. The dose margin frequently varies with the curved mask, from the straight edges of large features, to the straight edges of small features, to the features with the highest curvature. Because this movement is a statistical effect, local averaging may be used to determine the sidewall angle at any given point along the contour. A neural network 510 may be used to determine the variation in the sidewall angle anywhere along the bottom contour 524. In yet another embodiment, varying the width of the pattern may also contribute to the VSA and may be considered when determining the VSA. The VSA may be pre-calculated and stored in a lookup table by dose margin or width for quick access. Intermediate values ​​may be interpolated.

[0051] FIG. 6 shows the simulation of the diffraction orders or near-field effects using a thin mask and further processing in Fourier space. Typically, a fast Fourier transform (FFT) is an efficient way to simulate an optical image 608. An M2D effect 602 in Fourier space is generated, which represents the M2D effect 600 of the input mask. A set of pre-computed kernels 604 (in real space) of the optical model are also represented in FFT space as expanded kernels 606. An optical image 608 is generated from the inner product of the FFT M2D effect 602 and the expanded kernels 606. An inverse FFT (IFFT) is performed to generate an optical image 610 in real space, and a further simulation (simulation 612) generates the pattern on the substrate.

[0052] ILT is used to generate the M2D effects 602 in FIG. 6. ILT requires a model and also requires that the model be invertible to calculate the gradient of the wafer contour with respect to the non-local mask shape or pixel. Therefore, for ILT to produce M3D effects, ILT must also be invertible. Typically, M3D effects are obtained through rigorous simulation and cannot be inverted.

[0053] In an embodiment, the M3D effect 700 of FIG. 7 may be estimated from the M2D effect 600 using a deep learning network (DLN 650) before computing in Fourier space to generate the optical image 708. Once the M3D effect 700 is generated in real space, simulating the optical image 708 is similar to simulating the M2D effect 602 of FIG. 6. An M3D effect 702 in FFT space is generated that represents the M3D effect 700 of the input mask. A set of pre-computed kernels 704 (in real space) of the optical model are also represented in FFT space as expanded kernels 706. The optical image 708 is generated from the inner product of the FFT M3D effect 702 and the expanded kernels 706. An inverse FFT (IFFT) is performed to generate the optical image 710 in real space, and a further simulation (simulation 712) generates the pattern on the substrate. 6 and 7, the M2D and M3D effects simulations may continue to simulate the patterns on the wafer to determine the accuracy of the mask effects.

[0054] In FIG. 8, for mask 800, ILT simulation data for M2D effect 802 and rigorous simulation data for M3D effect 804 are used to train a deep learning neural network 801 to learn the transfer function from M2D effect 600 to M3D effect 700 in FIG. 7. The 193i light entering and leaving the mask may be represented by complex numbers including amplitude and phase, with X and Y polarizations represented as they enter the mask (Xin, Yin) and exit the mask (Xout, Yout), respectively. The map from M2D XinXout to M3D XinXout is learned during training, as is the case for YinYout. 193i XinYout and YinXout have little effect. For EUV, the full mapping from M2D to M3D is learned: XinXout, XinYout, and YinYout YinXout. Traditionally, sidewall angles are modeled as constants. In an embodiment, the optical model used to simulate the M3D effect includes variable sidewall angles (VSA), so that the simulation of the M3D effect takes the VSA into account.

[0055] In one embodiment, the magnitude of the difference (of the transfer functions) I 2 =(Y t real -Y p real ) 2 +(Y t imag -Y p imag ) 2 、 Root mean square error (rmse) _損失 =√Mean(I 2 ), and max _損失 =Sum((√I 2 The customized loss function using (th) is expressed as follows:

[0056] Loss=α*rmse_loss+β*maximum loss where alpha (α) and beta (β) are constants. For max_loss, pixel values ​​greater than a threshold "th" are penalized.

[0057] In one embodiment, a neural network 900 trained to generate an M3D mask image 960 from an M2D mask effect 910 using a transfer function is shown in FIG. 9. The mask effects 910 and 960, which represent the mask effects of the diffraction orders in the near field of M2D and M3D, respectively, have a halo size of 60 pixels in one example. The neural network 900 includes six layers and blocks in this embodiment, where the first layer 920 is a 2D convolution layer with ReLU, followed by four identical 2D convolution blocks 930. Each of the 2D convolution blocks 930 has three layers, a 2D convolution layer 932 followed by a batch normalization layer 934 and a ReLU layer 936. Skip connections 940 can be used for better gradient propagation. The image is processed through a final 2D convolution layer 950 that outputs an M3D mask image 960.

[0058] In another embodiment, an alternative neural network 1000 for generating M3D effects 1060 from M2D effects 1010 using transfer functions is shown in FIG. 10. In this exemplary configuration of FIG. 10, the neural network 1000 utilizing UNet has a set of four convolution blocks 1020, 1030, 1040, and 1050. The convolution block 1020 has two 2D convolution layers 1022 and 1024 followed by a leaky ReLU layer 1026. The convolution block 1030 has one 2D convolution layer 1032 followed by a batch normalization layer 1034 and a leaky ReLU layer 1036. The convolution block 1040 has one 2D convolution layer 1042 followed by a batch normalization layer 1044, a ReLU layer 1046, and a concatenation layer 1048. The convolution block 1050 has one 2D convolution layer 1052 followed by a hyperbolic tangent layer 1054 and outputs an M3D image 1060. The added complexity of the different blocks of the neural network 1000, as opposed to the identical blocks of the neural network 900, can be used for better accuracy in performing the transfer function.

[0059] Calculating the M3D effects to incorporate variable sidewall angles into the exposure information of the mask as described herein is difficult to achieve. This difficulty is evidenced by the long-standing use of constant sidewall angles in conventional industry practice. The implementation of the present M3D method is not straightforward compared to conventional M2D techniques, as the three-dimensional effects add significant complexity and computationally intensive processes over conventional methods. The disclosed method and system uniquely utilizes mask contours and dose margins to account for the varying values ​​of sidewall angles in the mask, and trains and uses a neural network to accomplish the calculation. The method may include training a deep learning neural network using simulation data of the M2D and M3D effects, which beneficially enables the deep learning neural network to learn a transfer function from the M2D effects to the M3D effects, which may enable the calculation to be accomplished in an efficient manner, i.e., implementation of a VSA.

[0060] FIG. 11 is an exemplary flowchart 1100 of a method for a reticle enhancement technique for transferring a pattern, such as a mask pattern, to a substrate, according to an embodiment of the present disclosure. In step 1110, initial mask exposure information is input, the mask exposure information including information for exposing a pattern on a substrate. The initial mask exposure information may include a first guess, such as applying a constant dose value to the mask pattern, a low pass filter applied to a target substrate pattern, a previously determined mask pattern (e.g., a previously calculated preliminary result), or a low pass filtered mask obtained by other means (e.g., when addressing hot spots in an existing mask design or when investigating a solution provided by another system). The mask exposure information may include optical proximity correction (OPC). The mask exposure information may be for a multi-beam.

[0061] In step 1120, mask 2D (M2D) effects are calculated. That is, step 1120 includes calculating M2D effects from mask exposure information. Calculating M2D effects may include inverse lithography techniques (ILT). In step 1130, mask 3D (M3D) effects are determined from the M2D effects, including calculating sidewall angles at various locations along the contour of the mask. In an embodiment, step 1130 includes determining M3D effects from the M2D effects using a neural network, and determining M3D effects includes determining variable sidewall angles (VSAs). In an embodiment, step 1130 includes determining variable sidewall angles (VSAs) at multiple locations along the contour. It is known that M3D effects vary in magnitude depending on the VSA. The method of the present invention considers the VSA around the contour rather than assuming a constant sidewall angle for the entire pattern as in conventional techniques. As a result, the M3D effects determined in step 1130 are more accurate than with conventional techniques. In some embodiments, calculating the M2D effect in step 1120 includes calculating a dose margin from the mask exposure information, and determining the M3D effect and sidewall angle in step 1130 may use the dose margin (e.g., determining the M3D effect includes calculating a dose margin from the mask exposure information). Determining the sidewall angle may be performed using a neural network, such as the neural networks of Figures 9 and 10. In an embodiment of step 1130, determining the M3D effect uses a transfer function.

[0062] Step 1140 includes calculating a calculated pattern on a substrate using M3D effects. Step 1140 includes calculating a pattern formed on a substrate, taking into account more accurate M3D effects, using a substrate lithography system model, a resist process model, and the substrate pattern is within a design domain. Calculating the calculated pattern on a substrate may include an extreme ultraviolet (EUV) simulation. In some embodiments, the substrate pattern includes a plurality of patterns on a wafer, and the design domain includes a majority of a mask layer of a semiconductor chip, such as an entire mask layer. The substrate lithography system model is used to calculate a pattern to be produced on a substrate by a mask.

[0063] Step 1150 includes modifying the mask pattern based on the substrate pattern, i.e., modifying the mask exposure information based on the calculated pattern on the substrate. The modifying may include an inverse lithography technique (ILT). The VSA may be recalculated using the modified mask pattern. Steps 1120-1150, including calculating M2D effects, determining M3D effects, and modifying, may be repeated until the calculated substrate pattern matches the desired substrate pattern, as indicated by loop "A". For example, the method may include repeating the calculation of M2D effects in step 1120, the determination of M3D effects in step 1130, the calculation of the calculated pattern in step 1140, and the modifying in step 1150.

[0064] It should be noted that variations are possible in flowchart 1100. For example, the VSA of step 1130 can be predetermined and stored in a look-up table. Other calculations can be performed in step 1140 to aid in mask iteration. In some embodiments, flowchart 1100 further includes inputting a target substrate pattern and calculating mask exposure information from the target substrate pattern using a reticle enhancement technique (RET) prior to inputting the mask exposure information, where RET can include an inverse lithography technique.

[0065] The mask pattern may also be further processed to incorporate some MPCs of mask manufacturing effects such as mask etch bias, etc. Step 1130 may include all MPCs.

[0066] 12 is a flow diagram 1200 for calculating a pattern to be formed on a substrate using optical lithography with a mask, such as a method for preparing a reticle for use in manufacturing surfaces such as integrated circuits on a silicon wafer, in accordance with the present invention. In step 1210, mask exposure information, which may also be referred to as a set of shots or a set of mask exposure information, such as a dose map, that will form a pattern on the mask is input. The set of shots may be predetermined, for example, as described in U.S. Pat. No. 9,341,936, which determines the set of shots from a desired substrate pattern.

[0067] In step 1220, a mask pattern is calculated from a set of shots. In step 1230, a dose margin is determined for one or more shots (set of shots) or dose maps from the mask exposure information. The dose margin frequently varies with curved masks, from straight edges of large features, to straight edges of small features, to features with the highest curvature. Step 1240 includes calculating a variable sidewall angle (VSA) using the dose margin. The sidewall angle of the mask correlates with the dose margin. Since this correlation is a statistical effect, local averaging to calculate the variable sidewall angle at any given location along the contour may be performed using the dose margin in step 1240. In one embodiment, the variable sidewall angle may be calculated using a neural network. In other embodiments, the relationship between the dose margin (x) and the sidewall angle (y) is linear, and may be expressed, for example, by the formula (i.e., linear equation) y=a+bx.

[0068] In step 1250, a pattern on a substrate is calculated from the mask pattern using the calculated variable sidewall angle, where calculating the pattern on the substrate includes M3D effects. In some embodiments, calculating the pattern on the substrate includes a lithography simulation. In some embodiments, calculating the pattern on the substrate includes an extreme ultraviolet (EUV) simulation. In some embodiments, the pattern on the substrate is for a semiconductor device.

[0069] A further embodiment of the flow diagram 1200 includes calculating a mask from the mask exposure information, where the step of calculating a pattern on the substrate uses the mask.

[0070] Computing Systems

[0071] In an embodiment, a system for reticle enhancement technology (RET) includes a device configured to calculate mask 2D (M2D) effects from mask exposure information, a device configured to determine mask 3D (M3D) effects from the M2D effects using a neural network, where determining the M3D effects includes determining a variable sidewall angle (VSA), and a device configured to calculate a calculated pattern on a substrate using the M3D effects. In some embodiments, the device configured to calculate the M2D effects and the device configured to determine the M3D effects from the M2D effects using the neural network include a graphics processing unit (GPU).

[0072] The calculation and processing steps described in this disclosure can be implemented using a general-purpose computer with appropriate computer software as a calculation device. Multiple computers or processor cores may be used in parallel. In some embodiments, dedicated hardware devices, used either alone or in multiples, can be used to perform the calculation of one or more steps faster than using a general-purpose computer or processor core. In certain embodiments, the dedicated hardware device may be a graphics processing unit (GPU). In other embodiments, other special-purpose hardware devices may be used as coprocessors, such as digital signal processors (DSPs), tensor processing units (TPUs), field programmable gate arrays (FPGAs), or application specific integrated circuits (ASICs).

[0073] FIG. 13 is a block diagram illustrating an example of a computing hardware device 1300 that may be used to perform the computations described in this disclosure. The computing hardware device 1300 includes a central processing unit (CPU) 1302 to which a main memory 1304 is attached. The CPU 1302 may include, for example, eight processing cores, thereby improving the performance of any portion of multithreaded computer software. The main memory 1304 may be, for example, 64 GB in size. The CPU 1302 is connected to a Peripheral Component Interconnect Express (PCIe) bus 1320. A graphics processing unit (GPU) 1314 may also be connected to the PCIe bus 1320. In the computing hardware device 1300, the GPU 1314 may or may not be connected to a graphics output device such as a video monitor. When not connected to a graphics output device, the GPU 1314 may be used purely as a high-speed parallel computation engine. Computing software may achieve significantly higher performance by using the GPU 1314 for a portion of the computation compared to using the CPU 1302 for all computations. CPU 1302 communicates with GPU 1314 via PCIe bus 1320. In other embodiments (not shown), GPU 1314 may be integrated with CPU 1302 rather than connected to PCIe bus 1320. A disk controller 1308 may also be attached to PCIe bus 1320, with, for example, two disks 1310 connected to disk controller 1308. Finally, a local area network (LAN) controller 1312 may also be attached to the PCIe bus, providing Gigabyte Ethernet (GbE) connectivity to other computers. In some embodiments, computer software and / or design data are stored on disk 1310. In other embodiments, either the computer programs or the design data, or both the computer programs and the design data, may be accessed from other computers or file serving hardware via other connectivity solutions, such as GbE Ethernet or InfiniBand.

[0074] FIG. 14 is another embodiment of a system for performing the computations of the present embodiment. The system 1400, sometimes referred to as a computational design platform (CDP), includes a master node 1410, an optional viewing node 1420, an optional network file system 1430, and a GPU-enabled node 1440. The viewing node 1420 may be absent, alternatively have only one node, or have other numbers of nodes. The GPU-enabled node 1440 may include one or more GPU-enabled nodes forming a cluster. Each GPU-enabled node 1440 may be, for example, a GPU, a CPU, a pair of a GPU and a CPU, multiple GPUs for a CPU, or other combinations of GPUs and CPUs. The GPU and / or CPU may be on a single chip, such as a GPU chip with a CPU accelerated by the GPU on that chip, or a CPU chip with a GPU accelerating the CPU. The GPU may be replaced with other co-processors.

[0075] The master node 1410 and the viewing nodes 1420 may be connected to the network file system 1430 and the GPU-enabled nodes 1440 via switches and high-speed networks such as networks 1450, 1452, and 1454. In an exemplary embodiment, the network 1450 may be a 56 Gbps network, 1452 may be a 1 Gbps network, and 1454 may be a management network. In various embodiments, there may be fewer or more of these networks, and various combinations of types of networks, such as high speed and low speed. The master node 1410 controls the CDP system 1400. An external system may connect to the master node 1410 from an external network 1460. In some embodiments, a job is launched from an external system. The data for the job is loaded into the network file system 1430 before launching the job, and a program is used to dispatch and monitor tasks on the GPU-enabled nodes 1440. The progress of the job can be viewed via a graphical interface, such as the viewing node 1420, or by a user on the master node 1410. Tasks are run on the CPU using scripts that run the appropriate executable on the CPU. The executable connects to the GPU, performs various computational tasks, and then disconnects from the GPU. The master node 1410 can also be used to disable a faulty GPU-enabled node 1440 and then operate as if the node did not exist.

[0076] Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example is provided as an illustration of the present technology, not as a limitation of the present technology. Indeed, while the present specification has been described in detail with respect to certain embodiments of the present invention, it will be appreciated that those skilled in the art, upon gaining an understanding of the foregoing, may readily conceive alternatives, modifications, and equivalents to these embodiments. For example, features illustrated or described as part of one embodiment may be used with another embodiment to yield yet a further embodiment. It is therefore intended that the present subject matter cover such modifications and variations that come within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be implemented by those skilled in the art without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Moreover, those skilled in the art will appreciate that the foregoing description is illustrative only and is not intended to limit the present invention.

Claims

1. 1. A method for reticle enhancement technology (RET) for transferring a pattern to a substrate, the method comprising: inputting mask exposure information including information for exposing the pattern onto the substrate; calculating Mask 2D (M2D) effects from the mask exposure information; and determining a Mask 3D (M3D) effect from the M2D effect using a neural network, the M3D effect including determining a variable sidewall angle (VSA); calculating a calculated pattern on the substrate using the M3D effect; and modifying the mask exposure information based on the calculated pattern on the substrate.

2. The method of claim 1 , wherein the calculating the calculated pattern on the substrate comprises a lithography simulation.

3. The method of claim 1 , wherein the calculating the M2D effects includes inverse lithography techniques (ILT).

4. Inputting a target board pattern; 2. The method of claim 1, further comprising: prior to inputting the mask exposure information, calculating the mask exposure information from the target substrate pattern using a reticle enhancement technique (RET).

5. The method of claim 4 , wherein the RET comprises an inverse lithography technique (ILT).

6. The method of claim 1 , wherein the mask exposure information further comprises optical proximity correction (OPC).

7. The method of claim 1 , wherein the calculation of the calculated pattern on the substrate comprises an extreme ultraviolet (EUV) simulation.

8. The method of claim 1 , wherein the determining the M3D effect comprises calculating a dose margin from the mask exposure information.

9. The method of claim 1 , wherein determining the M3D effect uses a transfer function.

10. The method of claim 1 , wherein the mask exposure information is for multiple beams.

11. The method of claim 1 , further comprising repeating the calculating the M2D effect, the determining the M3D effect, the calculating the calculated pattern, and the modifying.

12. 1. A method for calculating a pattern to be formed on a substrate using optical lithography with a mask, the method comprising: inputting mask exposure information for forming the pattern on the mask; determining a dose margin from the mask exposure information; calculating a variable sidewall angle (VSA) using the dose margin; and calculating the pattern on the substrate using the VSA, wherein the calculating the pattern on the substrate includes Mask 3D (M3D) effects.

13. The method of claim 12 , wherein the variable sidewall angle is calculated using a neural network.

14. The method of claim 12 , wherein the calculating the pattern on the substrate comprises a lithography simulation.

15. The method of claim 12 , wherein the calculating the pattern on the substrate comprises an extreme ultraviolet (EUV) simulation.

16. The method of claim 12 , wherein the pattern on the substrate is for a semiconductor device.

17. The method of claim 12 , further comprising: calculating the mask from the mask exposure information, wherein the calculating the pattern on the substrate uses the mask.

18. 1. A system for reticle enhancement technology (RET), comprising: a device configured to receive mask exposure information, the mask exposure information including information for exposing a pattern onto a substrate; and a device configured to calculate Mask 2D (M2D) effects from the mask exposure information; a device configured to determine a Mask 3D (M3D) effect from the M2D effect using a neural network, wherein determining the M3D effect includes determining a variable sidewall angle (VSA); and and a device configured to calculate a calculated pattern on the substrate using the M3D effect.

19. 20. The system of claim 18, wherein the device configured to calculate the M2D effects and the device configured to determine the M3D effects from the M2D effects using the neural network include a graphics processing unit (GPU).

Images