Mask, lithographic apparatus, and mask manufacturing method

Abstract

The present invention relates to a mask, a lithographic apparatus, and a method for manufacturing a mask, the mask comprising an electrolytic reactive layer (110) in which metal elements are configured to be in the form of deposited metal or dissolved ions, a first control circuit layer (120) provided on a first side of the electrolytic reactive layer (110) and comprising a plurality of first control electrodes (121), and a second control circuit layer (130) provided on a second side of the electrolytic reactive layer (110) opposite the first side. and a second control circuit layer (130) including a first control electrode (121) and a second control electrode (131) including a plurality of second control electrodes (131), wherein a light transmission state of a pixel region of the mask is determined by a control electrode between at least a portion of the first control electrode (121) and at least a portion of the second control electrode (131) contained within the pixel region, and the control electrode controls the light transmission state of the pixel region by controlling an amount of metal deposition in the electrolytic reaction layer (110).

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to Chinese Patent Application No. 202210372723.9, entitled "MASK, LITHOGRAPHIC APPARATUS, AND MANUFACTURING METHOD FOR A MASK," filed on April 11, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates generally to the field of lithography, and more particularly to a mask, a lithographic apparatus, and a method for manufacturing a mask. [Background technology]

[0003] In lithography technology, pattern structures are typically formed using a mask. However, once the mask is prepared, the pattern on the mask cannot be easily changed. Moreover, if there is a defect in the mask or a defect occurs during the process using the mask, it is also difficult to repair the defect. In addition, masks are typically expensive. All of these above factors can lead to an increase in the cost of chips produced using the mask and a complication of the process due to monitoring the defects of the mask. Therefore, there is a need for new masks in chip production technology. Summary of the Invention

[0004] It is an object of the present disclosure to provide a mask, a lithographic apparatus, and a method for manufacturing a mask.

[0005] According to a first aspect of the present disclosure, there is provided a mask comprising: an electrolytic reaction layer, in which metal elements are configured to be in a state of deposited metal or in a state of dissolved ions; a first control circuit layer, the first control circuit layer being provided on a first side of the electrolytic reaction layer and comprising a plurality of first control electrodes; and a second control circuit layer, the second control circuit layer being provided on a second side of the electrolytic reaction layer opposite the first side and comprising a plurality of second control electrodes, wherein a light transmission state of a pixel region of the mask is configured to be determined by a control voltage between at least a portion of the first control electrode and at least a portion of the second control electrode contained within the pixel region, and the control voltage controls the light transmission state of the pixel region by controlling an amount of deposition of metal in the electrolytic reaction layer.

[0006] In some embodiments, the mask further comprises a substrate, and the first control circuitry layer, the electrolytic reaction layer, and the second control circuitry layer are sequentially laminated on the substrate.

[0007] In some embodiments, the substrate comprises at least one of quartz or calcium fluoride.

[0008] In some embodiments, the electrolysis reaction layer comprises an electrolyte layer, a first electrolyte material layer disposed between the first control circuit layer and the electrolyte layer, and a second electrolyte material layer disposed between the electrolyte layer and the second control circuit layer.

[0009] In some embodiments, the electrolyte layer includes a copper-lead electrolyte.

[0010] In some embodiments, the electrolyte layer includes lead perchlorate, copper chloride, copper perchlorate, and lithium perchlorate.

[0011] In some embodiments, the electrolyte layer comprises a copper-silver electrolyte.

[0012] In some embodiments, the electrolyte layer includes copper perchlorate, silver perchlorate, and lithium chloride.

[0013] In some embodiments, the electrolyte layer comprises a solid electrolyte or the electrolyte layer comprises a liquid electrolyte.

[0014] In some embodiments, one of the first electrolyte material layer and the second electrolyte material layer comprises conductive diamond, indium tin oxide, or indium tin oxide modified with platinum nanoparticles.

[0015] In some embodiments, the other of the first and second electrolyte material layers comprises platinum.

[0016] In some embodiments, the electrolyte layer comprises an electrolyte material in the form of a continuous film, the first electrolyte material layer comprises a first electrolyte material in the form of a continuous film, and / or the second electrolyte material layer comprises a second electrolyte material in the form of a continuous film.

[0017] In some embodiments, the electrolyte layer includes a plurality of electrolyte material blocks arranged in an array and the pixel areas of the mask each include one or more electrolyte material blocks; the first electrolyte material layer includes a plurality of first electrolyte material blocks arranged in an array and the pixel areas of the mask each include one or more first electrolyte material blocks; and / or the second electrolyte material layer includes a plurality of second electrolyte material blocks arranged in an array and the pixel areas of the mask each include one or more second electrolyte material blocks.

[0018] In some embodiments, each of the plurality of first control electrodes is connected to a first pole of a controlled power source via a respective first switching device, and each of the plurality of second control electrodes is connected to a second pole of the controlled power source via a respective second switching device.

[0019] In some embodiments, the first control electrodes are each configured to receive a first control signal, and the second control electrodes are each configured to receive a second control signal, to control the light transmission state of the pixel area containing at least a portion of the overlapping first control electrode and at least a portion of the second control electrode.

[0020] In some embodiments, the first control electrode is a first strip electrode extending in a first direction, and the plurality of first control electrodes are arranged in the first control circuit layer and electrically insulated from one another, and the second control electrode is a second strip electrode extending in a second direction perpendicular to the first direction, and the plurality of second control electrodes are arranged in the second control circuit layer and electrically insulated from one another.

[0021] In some embodiments, pixel regions of the mask each comprise at least a portion of a first control electrode and at least a portion of a second control electrode.

[0022] In some embodiments, pixel regions of the mask each comprise at least a portion of a plurality of first control electrodes and at least a portion of a plurality of second control electrodes.

[0023] In some embodiments, the ratio of the area of ​​the region occupied by the first control electrode in the first control circuit layer to the area of ​​the region not occupied by the first control electrode is 100% to 1000%, and / or the ratio of the area occupied by the second control electrode in the second control circuit layer to the area not occupied by the second control electrode is 100% to 1000%.

[0024] In some embodiments, the ratio of the area of ​​the region occupied by the first control electrode in the first control circuit layer to the area of ​​the region not occupied by the first control electrode is equal to the ratio of the area of ​​the region occupied by the second control electrode in the second control circuit layer to the area not occupied by the second control electrode.

[0025] In some embodiments, the plurality of first control electrodes in the first control circuit layer are periodically arranged and / or the plurality of second control electrodes in the second control circuit layer are periodically arranged.

[0026] In some embodiments, the arrangement period of the plurality of first control electrodes in the first control circuit layer is 50 nm to 50 μm, and / or the arrangement period of the plurality of second control electrodes in the second control circuit layer is 50 nm to 50 μm.

[0027] In some embodiments, a spacing period of the first control electrodes in the first control circuitry layer is equal to a spacing period of the second control electrodes in the second control circuitry layer.

[0028] In some embodiments, the first control electrode comprises at least one of indium tin oxide, aluminum doped zinc oxide, conductive diamond, or conductive aluminum nitride, and / or the second control electrode comprises at least one of indium tin oxide, aluminum doped zinc oxide, conductive diamond, or conductive aluminum nitride.

[0029] In some embodiments, the first control circuit layer has a thickness of 10 nm to 100 nm and / or the second control circuit layer has a thickness of 10 nm to 100 nm.

[0030] In some embodiments, the first control electrode has an electrical resistance less than that of the electrolytic reaction layer, and the second control electrode has an electrical resistance less than that of the electrolytic reaction layer.

[0031] In some embodiments, the total thickness of the electrolytic reaction layer, the first control circuitry layer, and the second control circuitry layer is less than 100 μm.

[0032] According to a second aspect of the present disclosure, there is provided a lithographic apparatus comprising: a mask as described above; and a control module configured to generate, according to a layout, a plurality of first control signals to be applied to the plurality of first control electrodes and a plurality of second control signals to be applied to the plurality of second control electrodes, respectively, wherein a light transmission state of pixel regions of the mask corresponds to the layout.

[0033] According to a third aspect of the present disclosure, there is provided a method for manufacturing a mask, the method including: providing a substrate; forming a first control circuit layer having a pattern on the substrate, the first control circuit layer having a plurality of first control electrodes; forming an electrolytic reaction layer on the first control circuit layer; and forming a second control circuit layer having a pattern on the electrolytic reaction layer, the second control circuit layer having a pattern on the electrolytic reaction layer, the second control circuit layer having a pattern on the electrolytic reaction layer, the second control circuit layer having a pattern on the electrolytic reaction layer, the second control circuit layer having a plurality of second control electrodes, wherein a light transmission state of a pixel region of the mask is determined by a control voltage between at least a portion of the first control electrode and at least a portion of the second control electrode contained within the pixel region, and the control voltage controls the light transmission state of the pixel region by controlling an amount of deposition of metal in the electrolytic reaction layer.

[0034] In some embodiments, forming the electrolysis reaction layer on the first control circuit layer includes sequentially laminating a first electrolyte material layer, an electrolyte layer, and a second electrolyte material layer together to form the electrolysis reaction layer, and forming the electrolysis reaction layer on the first control circuit layer, the first electrolyte material layer being disposed between the first control circuit layer and the electrolyte layer.

[0035] In some embodiments, forming the electrolysis reaction layer on the first control circuitry layer includes forming a first electrolyte material layer on the first control circuitry layer, forming an electrolyte layer on the first electrolyte material layer, and forming a second electrolyte material layer on the electrolyte layer.

[0036] The accompanying drawings, which constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0037] The present disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0038] [Figure 1] FIG. 1 is a structural schematic diagram of a mask according to an exemplary embodiment of the present disclosure.

[0039] [Diagram 2] FIG. 2 is a schematic diagram of a control circuit including a first control circuit layer and a second control circuit layer according to an exemplary embodiment of the present disclosure.

[0040] [Diagram 3] FIG. 3 is a schematic diagram of one state of the control circuit for adjusting the light transmission state of the pixel regions of the mask.

[0041] [Figure 4] FIG. 4 is a schematic diagram of the light transmission state of pixel areas of a mask in the state of the control circuit of FIG.

[0042] [Diagram 5] FIG. 5 is a schematic diagram of another state of the control circuit for adjusting the light transmission state of the pixel regions of the mask.

[0043] [Figure 6] FIG. 6 is a schematic diagram of the light transmission state of pixel areas of a mask in the state of the control circuit of FIG.

[0044] [Figure 7] FIG. 7 is a structural schematic diagram of a lithographic apparatus according to an exemplary embodiment of the present disclosure.

[0045] [Figure 8] FIG. 8 is a schematic flow diagram of a method for manufacturing a mask according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] The present disclosure will be described below with reference to the accompanying drawings showing some embodiments of the present disclosure. However, it should be understood that the present disclosure can be presented in many different forms and is not limited to the embodiments described below. Indeed, the embodiments described below are intended to make the disclosure of the present disclosure more complete and fully convey the scope of protection of the present disclosure to those skilled in the art. It should also be understood that the embodiments disclosed herein can be combined in various ways to provide many additional embodiments.

[0047] It should be understood that like reference numerals represent like elements in all drawings, and in the drawings, the size of certain features may be distorted for clarity.

[0048] It should be understood that the terms in this specification are used only to describe certain embodiments and are not intended to limit the present disclosure. All terms (including technical and scientific terms) used in this specification have the meanings commonly understood by those skilled in the art unless otherwise defined. For the sake of brevity and / or clarity, well-known functions or structures may not be described in detail.

[0049] As used herein, the terms "comprising," "comprising," and "containing" indicate the presence of a stated feature but do not exclude the presence of one or more other features. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the terms "between X and Y" and "between about X and Y" should be interpreted to include X and Y. As used herein, the term "between about X and Y" means "between about X and about Y," and the term "about X to Y" as used herein means "about X to about Y."

[0050] As used herein, when an element is described as being "on," "attached," "connected," "coupled," or "in contact with" another element, the element may be directly on, attached, connected, coupled, or in contact with the other element, although intermediate elements may be present. In contrast, when an element is described as being "directly on," "directly attached," "directly connected," "directly coupled," or "in direct contact with" another element, intermediate elements are not present. As used herein, a feature located "adjacent" to another feature may refer to the feature having an overlap with the adjacent feature or being located above or below the adjacent feature.

[0051] As used herein, spatial relationship terms such as "above," "below," "left," "right," "front," "back," "high," and "low" may describe the relationship between one feature and another feature in the accompanying drawings. It should be understood that the spatial relationship terms encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, when a device in the drawings is inverted, a feature that would otherwise be described as being "below" another feature may then be described as being "above" that other feature. The device may also be otherwise oriented (rotated 90 degrees or otherwise) and the relative spatial relationships may be interpreted accordingly.

[0052] In the research of micro-nano devices and the manufacturing process of semiconductor chips, the structure of a desired device or chip is typically formed using a mask-based lithography technique. To form the desired structure, one or more masks may be fabricated in advance according to the layout of the device or chip to be processed and in light of the corresponding processing procedure. In this case, the pattern on each mask may correspond to one layer in the layout or multiple layers that can be prepared in the same procedure. Typically, the mask may comprise a substrate (e.g., quartz glass) that can transmit an exposure beam (e.g., ultraviolet light) to change the properties of the resist (photoresist), and a plating film (e.g., metal chrome film) deposited on the substrate to prevent the ultraviolet light from passing through.

[0053] In the method for manufacturing a mask, a chromium film having a thickness of several tens of nanometers and a resist placed on the chromium film can be successively deposited on a quartz glass, and then a desired pattern can be formed on the resist by direct laser writing or electron beam exposure, and then the chromium exposed from the resist can be wet-etched or dry-etched to form a pattern corresponding to a desired structure on the chromium film. The direct laser writing method is typically used to form a mask having a minimum line width larger than 300 nm, and the electron beam exposure method can be used to form a mask having a minimum line width less than 300 nm.

[0054] Using the above preparation method, the cost of just one mask is about tens of thousands of dollars, and the cost of a complete set of masks for a complete device or chip production process can reach millions of dollars. Moreover, once such a mask is prepared, it is difficult to change its structure. In traditional application scenarios, the single batch quantity of chips including CPU, DRAM, flash memory, and the like is typically on the order of millions or even hundreds of millions, so the mask fabrication cost can be fully shared, and the mask-based lithography process can be widely applied to the fabrication and production of these devices or chips. However, with the development of industries such as IoT, artificial intelligence, and personalized medicine, small batch production of devices or chips is increasingly required, and the number of these devices or chips may be only tens of thousands or even less. If a mask is prepared in advance and these devices or chips are produced based on the mask, it becomes difficult to share the mask fabrication cost by a sufficient number of devices or chips, and as a result, the cost of the devices or chips increases greatly. In addition, when these devices or chips are directly fabricated by laser direct writing, the yield is too low to meet the requirements of mass production, while the minimum line width of laser direct writing, which is about 300 nm, also restricts the improvement of chip integration and performance and the reduction of chip cost by miniaturizing the device. Similarly, when these devices or chips are directly fabricated by electron beam exposure, although it is possible to fabricate smaller and more integrated devices or chips, the yield is still too low to meet the requirements of production volume and the processing cost is very high, which prevents the penetration of these devices and chips into the market.

[0055] In addition, defects in a mask can also significantly increase the production costs of a device or chip: if a small defect is present in a mask, time must be spent to detect and repair the defect, and if a large defect is present in a mask, the entire mask may have to be discarded.

[0056] In order to solve the above problems, meet the requirements of small batch production of chips and high integration of related products, and enable future technologies such as IoT and artificial intelligence to be better penetrated into society, the present disclosure provides a programmable, rewritable and even reusable digital lithography mask. In such a mask, the light transmission state of the corresponding pixel area of ​​the mask can be changed by controlling the deposition state of the metal elements in the electrolytic reaction layer. Thus, the pattern on the same mask can be changed as needed, thereby realizing the reuse of the mask and further reducing the production cost of the device or chip.

[0057] In an exemplary embodiment of the present disclosure as shown in FIG. 1, the mask may include an electrolytically reactive layer 110, a first control circuitry layer 120, and a second control circuitry layer 130.

[0058] The metal elements in the electrolytic reaction layer 110 may be configured to be in a state of deposited metal or in a state of dissolved ions. Generally, when the thickness of the deposited metal reaches tens of nanometers or more, for example 20-100 nm or 50-100 nm, it is enough to block the exposure beam such as ultraviolet light for changing the resist. In other words, the corresponding area in the mask where the metal is deposited becomes light-opaque. In addition, when the metal elements in the electrolytic reaction layer 110 are in a state of dissolved ions, the amount of metal deposited in the corresponding area of ​​the mask is less or almost none, and therefore the area may be light-transmitting, which transmits ultraviolet light or the like for changing the resist. At this time, the transmitted ultraviolet light can help expose the resist in the corresponding area of ​​the device or chip to form the desired device or chip structure.

[0059] In some embodiments as shown in FIG. 1, the electrolysis reaction layer 110 may include an electrolyte layer 111, a first electrolyte material layer 112, and a second electrolyte material layer 113. When the metal elements are in a state of dissolved ions, the metal elements can move in the electrolyte layer 111. By applying an electric field, the metal ions can be moved in a desired direction in the electrolyte layer 111 and precipitated on the corresponding first electrolyte material layer 112 or second electrolyte material layer 113 to form a light non-transmitting region in the mask. In addition, by applying a reverse electric field, the metal precipitated in the first electrolyte material layer 112 or second electrolyte material layer 113 can be dissolved into the electrolyte layer 111 as metal ions to form a light transmitting region in the mask.

[0060] 1, a first electrolyte material layer 112 may be disposed between the first control circuit layer 120 and the electrolyte layer 111, and a second electrolyte material layer 113 may be disposed between the electrolyte layer 111 and the second control circuit layer 130. An electric field applied to an individual pixel region in the electrolytic reaction layer 110 may be controlled by the cooperation of the first control circuit layer 120 and the second control circuit layer 130 to change the light transmission state of the corresponding pixel region, as will be described in more detail below.

[0061] In some embodiments, the electrolytic reaction layer 110 may be based on a bimetallic system with good stability, allowing the mask to undergo multiple state changes without damage. For example, in a mask with an electrolytic reaction layer based on a bimetallic system, the mask may still have a transmittance contrast (transmittance in light-transmitting state / transmittance in light-non-transmitting state) of more than 6 even after 5000 reversible electrolytic plating cycles.

[0062] In one embodiment, the electrolytic reaction layer 110 may be based on a copper-lead (Cu-Pb) electrolyte system. Specifically, the electrolyte layer 111 may include a Cu-Pb electrolyte, specifically lead perchlorate (Pb(ClO4)2), copper chloride (CuCl2), copper perchlorate (Cu(ClO4)2), and lithium perchlorate (LiClO4).

[0063] In another embodiment, the electrolytic reaction layer 110 may be based on a copper-silver (Cu-Ag) electrolyte system. Specifically, the electrolyte layer 111 may include a Cu-Ag electrolyte, such as copper perchlorate (Cu(ClO4)2), silver perchlorate (AgClO4), and lithium chloride (LiCl).

[0064] However, it should be understood that in other embodiments, the electrolytic reaction layer 110 may be based on the deposition and dissolution of different metals and is not limited thereto herein.

[0065] In some embodiments of the present disclosure, the electrolyte layer 111 in the mask may be in a solid or liquid state, in other words, the electrolyte layer 111 may include a solid electrolyte or a liquid electrolyte. In the case where the electrolyte layer 111 is a solid electrolyte, after the electric field applied to the mask is removed, the movement of the metal elements therein may still be well restricted, so that the light-transmitting and light-non-transmitting regions of the mask may be well maintained. In the case where the electrolyte layer 111 is a liquid electrolyte, after the electric field applied to the mask is removed, the light-transmitting and light-non-transmitting regions of the mask may change slowly, so that their stability becomes poorer and poorer (although it should be understood that even when the stability is poor, it may generally satisfy the requirements of lithography). However, at the same time, in the case where the electrolyte layer 111 is a liquid electrolyte, in the process of generating the corresponding light-transmitting and light-non-transmitting regions on the mask, the metal elements may move faster in the liquid electrolyte, so that the switching between the light-transmitting and light-non-transmitting states may be achieved faster. In practical applications, the corresponding electrolyte layer can be selected according to requirements.

[0066] In some embodiments, the first electrolyte material layer 112 and the second electrolyte material layer 113 in the electrolytic reaction layer 110 may be formed using a material that is transparent to ultraviolet light for lithography or the like and has a certain electrical conductivity. In a specific example, one of the first electrolyte material layer 112 and the second electrolyte material layer 113 may include conductive diamond, indium tin oxide (ITO), or platinum (Pt) nanoparticle-modified ITO. Conductive diamond is transparent to ultraviolet light in the wavelength range of 193 nm to 405 nm, and therefore may be used in a mask based on exposure to ultraviolet light in the above wavelength range. On the other hand, ITO is transparent to ultraviolet light in the range of 360 nm to 405 nm and has a certain blocking effect on ultraviolet light of smaller wavelengths, so ITO may be used in a mask based on exposure to ultraviolet light in the wavelength range of 360 nm to 405 nm. Furthermore, by modifying ITO with Pt nanoparticles, the metal can be more uniformly deposited on the corresponding electrolyte material layer, so that each light non-transmitting region formed in the mask can block light more uniformly. In addition, the other of the first electrolyte material layer 112 and the second electrolyte material layer 113 may contain platinum (Pt) to form a counter electrode. When the metal has a sufficiently small thickness (e.g., about 10 nm), the metal can have good transparency to avoid blocking the exposure beam.

[0067] In some embodiments of the present disclosure, the electrolysis reaction layer 110 may be in the form of a continuous film. Specifically, the electrolyte layer 111 in the electrolysis reaction layer 110 may include an electrolyte material in the form of a continuous film, the first electrolyte material layer 112 may include a first electrolyte material in the form of a continuous film, and the second electrolyte material layer 113 may include a second electrolyte material in the form of a continuous film. The electrolysis reaction layer 110 in the form of a continuous film is easy to prepare in a mask, and thus does not have a problem in aligning with other components in the mask (e.g., the first control electrode 121 in the first control circuit layer 120 and the second control electrode 131 in the second control circuit layer 130) during the mask manufacturing process. Therefore, the cost of the mask can be effectively reduced. In addition, by using a material with high electrical resistance, it is possible to avoid electric field interference between adjacent regions in the electrolysis reaction layer 110, so that the light transmission state of each region can be independently controlled.

[0068] However, in some other embodiments, one or more layers in the electrolytically reactive layer 110 may be provided as a plurality of blocks arranged in an array (e.g., a rectangular array) and each pixel region of the mask may include one or more adjacent blocks (e.g., each pixel region may include one block, or each pixel region may include 2 x 2, total of four adjacent blocks) to further improve isolation between individual pixel regions of the mask, avoid electric field interference between adjacent pixel regions, and such that the metal elements in each pixel region are controlled solely or substantially independently by the electric field applied to the pixel region. Specifically, the electrolyte layer 111 may include a plurality of electrolyte material blocks arranged in an array, and each pixel area of ​​the mask may include one or more electrolyte material blocks; and / or the first electrolyte material layer 112 may include a plurality of first electrolyte material blocks arranged in an array, and each pixel area of ​​the mask may include one or more first electrolyte material blocks; and / or the second electrolyte material layer 113 may include a plurality of second electrolyte material blocks arranged in an array, and each pixel area of ​​the mask may include one or more second electrolyte material blocks. However, in this case, the problem of aligning layers in the electrolytic reaction layer 110 or between the electrolytic reaction layer 110 and other components in the mask (e.g., the first control electrode 121 in the first control circuit layer 120 and the second control electrode 131 in the second control circuit layer 130) during the process of preparing the mask must generally be considered, which may lead to an increase in the cost of the mask.

[0069] As shown in Figures 1, 2, 3 and 5, a control circuit similar to a charge-coupled device (CCD) driving circuit in a digital camera or a display driving circuit in a display may be employed to control the light transmission state of each pixel area of ​​the mask. Specifically, a first control circuit layer 120 may be provided on a first side of the electrolytic reaction layer 110, and the first control circuit layer 120 may include a plurality of first control electrodes 121. Similarly, a second control circuit layer 130 may be provided on a second side of the electrolytic reaction layer 110 opposite to the first side, and the second control circuit layer 130 may include a plurality of second control electrodes 131. One of the first control electrode 121 and the second control electrode 131 is similar to a scan line in a CCD driving circuit or a display driving circuit, while the other of the first control electrode 121 and the second control electrode 131 is similar to a data line in a CCD driving circuit or a display driving circuit. At least a portion of each first control electrode 121 may overlap at least a portion of a corresponding second control electrode 131 in the thickness direction of the mask, in which case the intersection region of the first control electrode 121 and the second control electrode 131 of the mask is controlled by the electric field between the first control electrode 121 and the second control electrode 131. That is, the metal element in the electrolyte layer 111 in the intersection region may move under the action of the electric field. The metal element is deposited on the first electrolyte material layer 112 or the second electrolyte material layer 113, or the metal element is detached from the first electrolyte material layer 111 or the second electrolyte material layer 113 and dissolved in the electrolyte layer 111, thereby changing the light transmission state in the intersection region. In other words, the light transmission state of a pixel region of the mask can be configured to be determined by a control voltage between at least a portion of the first control electrode 121 and at least a portion of the second control electrode 131 included in the pixel region, or by a load history of a control voltage between at least a portion of the first control electrode 121 and at least a portion of the second control electrode 131 included in the pixel region.Here, the corresponding portion of the first control electrode 121 and the corresponding portion of the second control electrode 131 overlap in the thickness direction of the mask, and the control voltage controls the amount of metal deposition in the electrolytic reaction layer 110, thereby controlling the light transmission state of the pixel region.

[0070] In some embodiments, each intersection region may be formed as a pixel region (e.g., each minimum shadow region shown in FIGS. 4 and 6 may be considered as a pixel region in a non-light-transmitting state). In other words, each pixel region of the mask may include at least a portion of a first control electrode and at least a portion of a second control electrode (e.g., each pixel region includes a portion of a first control electrode and a portion of a second control electrode that overlap each other). Alternatively, in some other embodiments, a pixel region may be formed by a plurality of intersection regions that are adjacent to each other (e.g., as shown in FIGS. 4 and 6, a region represented by a dashed box including four intersection regions may be considered as a pixel region in a non-light-transmitting state). In other words, each pixel region of the mask may include at least a portion of a plurality of first control electrodes and at least a portion of a plurality of second control electrodes (e.g., includes a portion of each of the two first control electrodes and a portion of each of the two second control electrodes).

[0071] In some embodiments, such as those shown in Figures 2, 3, and 5, each of the plurality of first control electrodes (H1, H2, H3, and H4) may be respectively connected to a first pole (e.g., a cathode as shown in the figures) of a controlled power source via a respective first switching device (SH1, SH2, SH3, and SH4), while each of the plurality of second control electrodes (V1, V2, V3, and V4) may be respectively connected to a second pole (e.g., an anode as shown in the figures) of a controlled power source via a respective second switching device (SV1, SV2, SV3, and SV4). In this way, the voltage applied to each control electrode can be controlled by controlling the on or off state of each switching device, and the light transmission state of each pixel area of ​​the mask is controlled. Furthermore, as described above, in the electrolytic reaction layer 110, even if the applied external electric field is removed, the dissolved or precipitated state of the metal elements in each region can still be maintained, and therefore the light transmission state of each pixel region of the mask can be controlled by stepwise controlling one or more first switching devices and one or more second switching devices. The switching devices may include devices such as, but are not limited to, field effect transistors. In some embodiments, the switching devices may be cooperatively provided in the control circuit layer of the mask. Alternatively, in some other embodiments, the switching devices may be provided outside the mask to avoid interference with the light transmission state of each pixel region of the mask. As described below, in some embodiments, the respective control signals may be directly applied to the control electrodes, thereby omitting the switching devices.

[0072] In an embodiment such as that shown in Figures 3-6, if it is desired to form the light non-transmitting regions shown in Figure 6 (the shaded areas shown in the figures) on the mask, this can be done in two steps.

[0073] First, as shown in Fig. 3, by switching on the switches SH1, SH2, SV1, and SV2 and switching off the switches SH3, SH4, SV3, and SV4, an electric field from the second control electrode V1 toward the first control electrode H1 is applied to the intersection region of the first control electrode H1 and the second control electrode V1, so that the metal ions in the electrolyte layer 111 in the region move toward the first control electrode H1 and are deposited on the first electrolyte material layer 112 in the region. In this way, the intersection region of the first control electrode H1 and the second control electrode V1 of the mask is in a non-light-transmitting state. Similarly, the intersection region of the first control electrode H1 and the second control electrode V2, the intersection region of the first control electrode H2 and the second control electrode V1, and the intersection region of the first control electrode H2 and the second control electrode V2 are all presented in a non-light-transmitting state. However, in other areas of the mask, the above-mentioned electric field is not formed, so that the metal elements in the electrolyte layer 111 can be presented in the form of ions, and the corresponding areas of the mask are light-transmitting. In conclusion, a mask having a pattern as shown in FIG. 4 can be formed.

[0074] Then, as shown in Fig. 5, by switching on the switches SH3, SH4, SV3, and SV4 and switching off the switches SH1, SH2, SV1, and SV2, an electric field from the second control electrode V3 toward the first control electrode H3 is applied to the intersection region of the first control electrode H3 and the second control electrode V3, so that the metal ions in the electrolyte layer 111 in the region move toward the first control electrode H3 and are deposited on the first electrolyte material layer 112 in the region. In this way, the intersection region of the first control electrode H3 and the second control electrode V3 of the mask is in a non-light-transmitting state. Similarly, the intersection region of the first control electrode H3 and the second control electrode V4, the intersection region of the first control electrode H4 and the second control electrode V3, and the intersection region of the first control electrode H4 and the second control electrode V4 are all presented in a non-light-transmitting state. However, in other areas of the mask, since the above electric field is not formed, the metal elements can maintain their original state, so that the intersection area of ​​the first control electrode H1 and the second control electrode V1, the intersection area of ​​the first control electrode H1 and the second control electrode V2, the intersection area of ​​the first control electrode H2 and the second control electrode V1, and the intersection area of ​​the first control electrode H2 and the second control electrode V2 are still maintained in a light non-transmitting state, while the remaining areas are maintained in a light transmitting state. In conclusion, a mask having a pattern as shown in FIG. 6 can be formed.

[0075] In some embodiments, to achieve automatic control of the pattern on the mask, the first control signal applied to each of the first control electrodes and the second control signal applied to each of the second control electrodes can be generated based on one or more mask patterns to be formed. The first control signal and the second control signal can be applied on the first control electrodes and the second control electrodes directly or through respective switching devices (as shown in Figs. 2, 3 and 5). By setting the level states of the first control signal and the second control signal at each time interval, the light transmission state of the pixel area including at least a part of the first control electrode and at least a part of the second control electrode of the overlapping mask can be changed automatically and continuously, and in some cases, the switching device can be omitted or avoid manually changing the on or off state of the individual switching devices.

[0076] It should be understood that in other examples, the mask may include a greater or lesser number of first and second control electrodes. For example, 1000-100000 first control electrodes and 1000-100000 second control electrodes may be formed on the mask to form pixel areas on the order of 1000x1000-100000x100000, but this is not limited thereto. Furthermore, in some embodiments, the different orientations of the first and second poles (anodes and cathodes) of the control power source may cause metal to be deposited on the second electrolyte material layer 131 to form non-light-transmitting regions, but this is not limited thereto. Furthermore, the desired mask pattern may allow the on or off states of different numbers of switching devices connected to different numbers of control electrodes to be controlled separately at each step of forming the mask pattern, but this is not limited thereto.

[0077] In addition, when the pattern on the mask needs to be erased or changed, i.e. when the light-transmitting state of one or more pixel regions on the mask needs to be changed, the controlled power source can be reversed so that the mask can be used for preparing other different structures. That is, the first and second poles (anode and cathode) of the controlled power source are exchanged with the on or off combination of the respective switching devices. As a result, the metal deposited in the light-non-transmitting regions is desorbed and dissolved in the electrolyte layer 111, where it is present in the form of ions. Thus, the regions are converted to a light-transmitting state.

[0078] In order to simplify the structure of the control circuit layer, the light transmission state of each pixel area of ​​the mask is controlled by using as few switching devices or control signals as possible. As shown in Figures 1, 2, 3 and 5, the first control electrode 121 may be a first strip electrode extending in a first direction, and a plurality of first control electrodes 121 may be arranged in the first control circuit layer 120 in a manner electrically insulated from each other, so that the voltage applied to each of the first control electrodes 121 can be controlled individually. Similarly, the second control electrode 131 may be a second strip electrode extending in a second direction perpendicular to the first direction, and a plurality of second control electrodes 131 may be arranged in the second control circuit layer 130 in a manner electrically insulated from each other, so that the voltage applied to each of the second control electrodes 131 can be controlled individually. Furthermore, by providing the first strip electrode and the second strip electrode, the crossing region between the first control electrode and the second control electrode can be conveniently formed without performing complicated alignment in the process of preparing the mask. However, it should be understood that in some other embodiments, the control electrode 131 may be arranged in other shapes to control the light transmission state of each crossing region, as long as the electric field in the thickness direction of the mask applied to the overlapping portion between the first control electrode 121 and the second control electrode 131 can be independently controlled, and this specification is not limited thereto. For example, when the mask has a large area, two or more first strip electrodes or second strip electrodes may be provided in the same horizontal or vertical direction to avoid excessive attenuation of the control signal applied across different regions of the electrodes.

[0079] In some embodiments, the ratio of the area of ​​the region occupied by the first control electrode 121 in the first control circuit layer 120 to the area of ​​the region not occupied by the first control electrode 121 may be 100% to 1000%. Similarly, the ratio of the area of ​​the region occupied by the second control electrode 131 in the second control circuit layer 130 to the area of ​​the region not occupied by the second control electrode 131 may be 100% to 1000%. On the other hand, the larger the ratio, the larger the area of ​​the region occupied by the control electrode in the corresponding control circuit layer, and when the region is set as a non-light-transmitting region, the better the effect of blocking ultraviolet light. In particular, in the case where one pixel region is formed by multiple intersection regions, the smaller the gap between adjacent electrodes in the pixel region, the better the light blocking performance. However, a small interval between control electrodes in the same control circuit layer may cause increased difficulty in preparing a control electrode array. For example, the proximity effect or the like may cause the spacing between adjacent control electrodes to be smaller than the designed spacing or even to be almost zero, thereby causing short circuit or the like between adjacent electrodes. On the other hand, the smaller the above ratio, the more helpful it is to control the difficulty in preparing the control electrode array, but when the spacing between the control electrodes in the same control circuit layer is large, the blocking effect of ultraviolet light may also be reduced. Especially in the case where a pixel area is formed by multiple intersection areas, when it is desired to adjust the pixel area to a light non-transmitting area, the gap between the control electrodes may cause a certain percentage of light leakage.

[0080] In some embodiments, the ratio of the area of ​​the region occupied by the first control electrode 121 to the area of ​​the region not occupied by the first control electrode 121 in the first control circuit layer 120 may be equal to the ratio of the area of ​​the region occupied by the second control electrode 131 to the area of ​​the region not occupied by the second control electrode 131 in the second control circuit layer 130. In this way, each intersection area has substantially the same distribution in the horizontal and vertical directions, which helps simplify the mask preparation process.

[0081] In some embodiments, the first control electrodes 121 in the first control circuit layer 120 may be periodically arranged, and similarly, the second control electrodes 131 in the second control circuit layer 130 may be periodically arranged. In this way, the size of each intersection area or each pixel area may be equal to each other. Furthermore, the arrangement period of the first control electrodes 121 in the first control circuit layer 120 may be 50 nm to 50 μm, and similarly, the arrangement period of the second control electrodes 131 in the second control circuit layer 130 may be 50 nm to 50 μm. For example, in a specific example, the arrangement period of the first control electrodes 121 in the first control circuit layer 120 may be 5 μm, and / or the arrangement period of the second control electrodes 131 in the second control circuit layer 130 may be 5 μm. It should be appreciated that the smaller the placement period of the control electrodes, the greater the pattern accuracy that the mask can achieve, but the mask fabrication process can also be more difficult and the fabrication costs can be higher.

[0082] In some embodiments, the arrangement period of the plurality of first control electrodes 121 in the first control circuit layer 120 may be equal to the arrangement period of the plurality of second control electrodes 131 in the second control circuit layer 130. In this way, each intersection area has substantially the same distribution in the horizontal and vertical directions, which helps simplify the mask preparation process.

[0083] In order to avoid the interference of the control circuit layer with the light transmission state of the mask, the first control electrode 121 and the second control electrode 131 may be formed using a material that is transparent to ultraviolet light and has a certain electrical conductivity. For example, in some embodiments, the first control electrode 121 may include at least one of indium tin oxide (ITO), aluminum doped zinc oxide, conductive diamond, or conductive aluminum nitride (AlN). Similarly, the second control electrode 131 may include at least one of indium tin oxide (ITO), aluminum doped zinc oxide, conductive diamond, or conductive aluminum nitride (AlN). In some embodiments, the thickness of the first control circuit layer 120 may be 10 nm to 100 nm. Similarly, the thickness of the second control circuit layer 130 may be 10 nm to 100 nm. In addition, the electrical resistance of the first control electrode 121 is generally smaller than that of the electrolytic reaction layer 110, and the electrical resistance of the second control electrode 131 is also generally smaller than that of the electrolytic reaction layer 110. This allows the desired electric field to be distributed substantially uniformly in the area corresponding to the control electrode, thus avoiding the electric field interference between adjacent intersection areas or pixel areas. In addition, the total thickness of the electrolytic reaction layer 110, the first control circuit layer 120, and the second control circuit layer 130 can be less than 100 μm, thereby avoiding the mask switching between the light-transmitting state and the light-non-transmitting state being too slow due to excessive thickness.

[0084] Furthermore, in some embodiments of the present disclosure as shown in FIG. 1, the mask may further include a substrate 140. In this case, the first control circuit layer 120, the electrolytic reaction layer 110, and the second control circuit layer 130 may be successively laminated on the substrate 140. In other words, the substrate 140 may function as a support for the various layers thereon. The substrate 140 may be made of quartz glass, calcium fluoride glass, or the like that is transparent to ultraviolet light.

[0085] In the mask of the present disclosure, the transparent control electrode array is utilized to control the metal and complex ions in the electrolytic reaction layer between the transparent control electrode array, realizing reversible electrolytic plating of metal film, thereby adjusting the light transmission state of each pixel area of ​​the mask. In this way, the corresponding mask pattern can be directly written and directly formed based on the data file of the desired device or chip structure, and the mask pattern on the same mask can also be erased for mask reuse. This improves the mask usage efficiency, reduces the device or chip fabrication cost, and avoids a series of problems caused by the high mask cost in traditional lithography. In the exemplary embodiment of the present disclosure, the period of the control electrode array in the control circuit layer is 100 nm or less, which can meet the requirements of the 28 nm process node when combined with 4x reduction projection exposure. Furthermore, it can also meet the requirements of the 14 nm or more advanced process node when combined with technology such as LELE (Lithography Etch Lithography Etch) process. Therefore, reliable and low-cost small batch production of highly integrated chips can be achieved.

[0086] In an exemplary embodiment of the present disclosure, a lithography apparatus is also provided. As shown in FIG. 7, the lithography apparatus may include the above-mentioned mask 100 and a control module 200. The control module 200 may be configured to generate a plurality of first control signals applied to a plurality of first control electrodes 121 and a plurality of second control signals applied to a plurality of second control electrodes 131 according to a layout, so that the light transmission states of pixel regions of the mask 100 respectively correspond to respective layers in the layout. Specifically, the control module 200 may include a digital control unit 210 for generating a plurality of mask patterns corresponding to one or more layers in the layout of the device or chip, and for generating the respective first control signals and the second control signals according to the respective mask patterns, and a mask driving unit 220 for respectively changing the light transmission states of each pixel region of the mask according to each of the sets of the first control signals and the second control signals.

[0087] In the lithography apparatus of the present disclosure, when a mask with a line width accuracy of 100 nm is employed along with a technique such as 4x reduction projection and LELE, each exposure area is approximately 0.25×0.25 mm by utilizing a pixel area of ​​10000×10000. 2 Under these conditions, the lithography machine can achieve a 1 cm resolution with 1600 times control and synchronization of dynamic adjustments and exposures of the mask combined with 1-2 nm grade workpiece stage positioning. 2 Exposure of a grade chip can be completed within about 10 minutes. With a linewidth accuracy of 32 nm, this exposure speed is more than 100 times faster than that of the most advanced electron beam exposure machines. In conclusion, the fabrication of complex devices or chips can be efficiently and accurately completed through a single or a few reusable and rewritable masks, which reduces the fabrication cost of the devices or chips and facilitates rapid update, mass production, and better market penetration of the devices or chips.

[0088] In an exemplary embodiment of the present disclosure, a method for manufacturing a mask is also provided, which may include, as shown in FIG. a step S810 of providing a substrate; Step S820: forming a first control circuit layer having a pattern on the substrate, the first control circuit layer comprising a plurality of first control electrodes; Step S830 of forming an electrolysis reaction layer on the first control circuit layer; and Form a patterned second control circuit layer on the electrolysis reaction layer, step S840, where the second control circuit layer comprises a plurality of second control electrodes, step S840. In this case, the light transmission state of the pixel region of the mask is configured to be determined by a control voltage between at least a portion of the first control electrode and at least a portion of the second control electrode contained within the pixel region, and the control voltage controls the light transmission state of the pixel region by controlling the amount of metal deposition in the electrolytic reaction layer.

[0089] In the process of forming the patterned first and second control circuit layers, the patterned first and second control circuit layers may be formed by laser direct writing or electron beam direct writing, or may be formed by other mask-based lithography. When parameters such as the ratio of the area occupied by the control electrodes to the area not occupied by the control electrodes, the period of the control electrode array, and similar parameters in the first and second control circuit layers are equal, the first and second control circuit layers can be formed in different directions (e.g., perpendicular to each other) using the same mask, reducing the fabrication cost.

[0090] Moreover, in some embodiments, forming the electrolytic reaction layer on the first control circuitry layer includes: sequentially laminating a first electrolyte material layer, an electrolyte layer, and a second electrolyte material layer together to form the electrolysis reaction layer; forming an electrolysis reaction layer on the first control circuitry layer, with the first electrolyte material layer disposed between the first control circuitry layer and the electrolyte layer.

[0091] When the first electrolyte material layer, the electrolyte layer, and the second electrolyte material layer are in the form of a continuous film, the formation of the electrolysis reaction layer is thus very simple and low-cost. However, if there is a pattern in the first electrolyte material layer, the electrolyte layer, or the second electrolyte material layer, the corresponding patterned layer may be formed by laser direct writing, electron beam direct writing, or may be formed based on other masks. If the first electrolyte material layer, the electrolyte layer, and the second electrolyte material layer have the same patterning aspect, a composite of the first electrolyte material layer, the electrolyte layer, and the second electrolyte material layer may be first formed by lamination, and then the composite may be patterned.

[0092] Alternatively, in some other embodiments, forming the electrolytic reaction layer on the first control circuitry layer comprises: forming a first electrolyte material layer over the first control circuitry layer; forming an electrolyte layer on the first electrolyte material layer; forming a second layer of electrolyte material over the electrolyte layer.

[0093] When the electrolytic reaction layers are so formed, corresponding material, either in the form of a continuous film or patterned, can conveniently be laminated to each layer as required.

[0094] Although the exemplary embodiments of the present disclosure have been described, those skilled in the art will understand that many variations and modifications may be made to the exemplary embodiments of the present disclosure without essentially departing from the spirit and scope of the present disclosure. Therefore, all such variations and modifications are included within the scope of protection of the present disclosure as defined in the claims. The present disclosure is defined by the appended claims, and the equivalents of these claims are also included therein.

Claims

1. A mask, the mask comprising: an electrolytic reaction layer in which the metal elements are configured to be in the form of deposited metals or dissolved ions; a first control circuit layer, the first control circuit layer being disposed on a first side of the electrolytic reaction layer, the first control circuit layer including a plurality of first control electrodes; a second control circuit layer disposed on a second side of the electrolytic reaction layer opposite the first side, the second control circuit layer comprising a plurality of second control electrodes; A mask, wherein the light transmission state of a pixel region of the mask is determined by a control voltage between at least a portion of the first control electrode and at least a portion of the second control electrode contained within the pixel region, and the control voltage controls the light transmission state of the pixel region by controlling an amount of metal deposition in the electrolytic reaction layer.

2. The mask comprises: The mask of claim 1 , further comprising a substrate, the first control circuitry layer, the electrolytic reaction layer, and the second control circuitry layer being sequentially layered on the substrate.

3. The mask of claim 2 , wherein the substrate comprises at least one of quartz or calcium fluoride.

4. The electrolytic reaction layer is An electrolyte layer; a first electrolyte material layer disposed between the first control circuit layer and the electrolyte layer; 10. The mask of claim 1, further comprising: a second electrolyte material layer disposed between the electrolyte layer and the second control circuitry layer.

5. The mask of claim 4, wherein the electrolyte layer comprises a copper-lead electrolyte.

6. 6. The mask of claim 5, wherein the electrolyte layer comprises lead perchlorate, copper chloride, copper perchlorate, and lithium perchlorate.

7. The mask of claim 4, wherein the electrolyte layer comprises a copper-silver electrolyte.

8. 8. The mask of claim 7, wherein the electrolyte layer comprises copper perchlorate, silver perchlorate, and lithium chloride.

9. the electrolyte layer comprises a solid electrolyte; or The mask of claim 4 , wherein the electrolyte layer comprises a liquid electrolyte.

10. 5. The mask of claim 4, wherein one of the first electrolyte material layer and the second electrolyte material layer comprises conductive diamond, indium tin oxide, or indium tin oxide modified with platinum nanoparticles.

11. The mask of claim 10 , wherein the other of the first and second electrolyte material layers comprises platinum.

12. the electrolyte layer comprises an electrolyte material in the form of a continuous film; the first electrolyte material layer comprises a first electrolyte material in the form of a continuous film; and / or The mask of claim 4 , wherein the second electrolyte material layer comprises a second electrolyte material in the form of a continuous film.

13. the electrolyte layer includes a plurality of electrolyte material blocks arranged in an array, and each pixel area of ​​the mask includes one or more electrolyte material blocks; the first electrolyte material layer includes a plurality of first electrolyte material blocks arranged in an array, and each pixel area of ​​the mask includes one or more first electrolyte material blocks; and / or 5. The mask of claim 4, wherein the second electrolyte material layer includes a plurality of second electrolyte material blocks arranged in an array, and pixel areas of the mask each include one or more of the second electrolyte material blocks.

14. each of the plurality of first control electrodes is connected to a first pole of a controlled power source via a respective first switching device; and 2. The mask of claim 1, wherein each of the plurality of second control electrodes is respectively connected to a second pole of the controlled power source via a respective second switching device.

15. 2. The mask of claim 1, wherein first control electrodes are each configured to receive a first control signal, and second control electrodes are each configured to receive a second control signal, to control the light transmission state of the pixel area containing at least a portion of the overlapping first control electrode and at least a portion of the second control electrode.

16. the first control electrode is a first strip-shaped electrode extending in a first direction, and the plurality of first control electrodes are disposed in the first control circuit layer and electrically insulated from one another; and 2. The mask of claim 1, wherein the second control electrode is a second strip electrode extending in a second direction perpendicular to the first direction, and the plurality of second control electrodes are arranged in the second control circuit layer and electrically insulated from one another.

17. 17. The mask of claim 16, wherein pixel regions of the mask each comprise at least a portion of one first control electrode and at least a portion of one second control electrode.

18. 17. The mask of claim 16, wherein pixel regions of the mask each comprise at least a portion of a first plurality of control electrodes and at least a portion of a second plurality of control electrodes.

19. The ratio of the area of ​​the first control circuit layer occupied by the first control electrodes to the area of ​​the first control circuit layer not occupied by the first control electrodes is between 100% and 1000%; and / or 17. The mask of claim 16, wherein a ratio of an area of ​​the second control circuit layer occupied by the second control electrodes to an area of ​​the second control circuit layer not occupied by the second control electrodes is between 100% and 1000%.

20. 17. The mask of claim 16, wherein a ratio of an area of ​​the first control circuit layer occupied by the first control electrode to an area of ​​the first control circuit layer not occupied by the first control electrode is equal to a ratio of an area of ​​the second control circuit layer occupied by the second control electrode to an area of ​​the second control circuit layer not occupied by the second control electrode.

21. the first control electrodes in the first control circuit layer are periodically arranged; and / or The mask of claim 16 , wherein the plurality of second control electrodes in the second control circuitry layer are arranged periodically.

22. The arrangement period of the plurality of first control electrodes in the first control circuit layer is 50 nm to 50 μm, and / or 22. The mask of claim 21, wherein the arrangement period of the plurality of second control electrodes in the second control circuit layer is 50 nm to 50 μm.

23. 22. The mask of claim 21, wherein a spacing period of the plurality of first control electrodes in the first control circuitry layer is equal to a spacing period of the plurality of second control electrodes in the second control circuitry layer.

24. the first control electrode comprises at least one of indium tin oxide, aluminum doped zinc oxide, conductive diamond, or conductive aluminum nitride; and / or 10. The mask of claim 1, wherein the second control electrode comprises at least one of indium tin oxide, aluminum doped zinc oxide, conductive diamond, or conductive aluminum nitride.

25. the thickness of the first control circuit layer is between 10 nm and 100 nm; and / or The mask of claim 1 , wherein the second control circuit layer has a thickness of 10 nm to 100 nm.

26. The electrical resistance of the first control electrode is smaller than that of the electrolytic reaction layer; and The mask of claim 1 , wherein the electrical resistance of the second control electrode is less than that of the electrolytic reaction layer.

27. The mask of claim 1 , wherein the total thickness of the electrolytic reaction layer, the first control circuitry layer, and the second control circuitry layer is less than 100 μm.

28. 1. A lithographic apparatus comprising: A mask according to any one of claims 1 to 27; a control module configured to generate a plurality of first control signals to be applied to the plurality of first control electrodes and a plurality of second control signals to be applied to the plurality of second control electrodes, respectively, according to a layout, wherein light transmission states of pixel regions of the mask correspond to the layout.

29. 1. A method of manufacturing a mask, the method comprising: Providing a substrate; forming a first control circuit layer on the substrate having a pattern, the first control circuit layer comprising a plurality of first control electrodes; forming an electrolytic reaction layer on the first control circuit layer; forming a patterned second control circuit layer on the electrolytic reaction layer, the second control circuit layer comprising a plurality of second control electrodes; A method in which a light transmission state of a pixel region of the mask is configured to be determined by a control voltage between at least a portion of the first control electrode and at least a portion of the second control electrode contained within the pixel region, and the control voltage controls the light transmission state of the pixel region by controlling an amount of deposition of metal in the electrolytic reaction layer.

30. forming the electrolytic reaction layer on the first control circuit layer; sequentially laminating a first electrolyte material layer, an electrolyte layer, and a second electrolyte material layer together to form the electrolysis reaction layer; 30. The method of claim 29, further comprising forming the electrolysis reaction layer on the first control circuitry layer, the first electrolyte material layer being disposed between the first control circuitry layer and the electrolyte layer.

31. forming the electrolytic reaction layer on the first control circuit layer; forming a first layer of electrolyte material over the first control circuitry layer; forming an electrolyte layer on the first layer of electrolyte material; 30. The method of claim 29, further comprising forming a second layer of electrolyte material over the electrolyte layer.

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