3D Resonators with Embedded Capacitors for Wideband Filters

Abstract

The integrated circuit (IC) includes a substrate and a first through-substrate via (TSV) in the substrate. The first TSV includes a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate constructed from a first metallization layer on an inner surface of the first TSV. The first MIM capacitor includes a MIM insulator layer on the first plate. The first MIM capacitor includes a second plate constructed from a second metallization layer on the MIM insulator layer. The IC includes a 3D inductor having a second TSV in the substrate. The 3D inductor includes a first trace on a first surface of the substrate coupled to a first end of the second TSV. The 3D inductor further includes a second trace on a second surface of the substrate and coupled to a second end of the second TSV and a second end of the first TSV.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. patent application Ser. No. 17 / 682,868, filed Feb. 28, 2022, entitled “CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER,” the disclosure of which is incorporated herein by reference in its entirety.

[0002] Aspects of the present disclosure relate to semiconductor devices, and more particularly, to capacitor-embedded 3D resonators for wideband filters. [Background technology]

[0003] Wireless communication devices incorporate radio frequency (RF) modules that facilitate the communications and features users expect. As wireless systems become more prevalent and include more capabilities, chips become more complex. Fifth generation (5G) new radio (NR) wireless communication devices incorporate the latest generation of electronic dies housed in smaller modules with smaller interconnects. Design challenges include using passive devices that directly impact analog RF performance considerations, including mismatch, noise, and RF performance.

[0004] Passive devices may involve high performance capacitor and inductor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors and inductors. Integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn junction capacitors, metal-insulator-metal (MIM) capacitors, poly-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures.

[0005] Mobile RF transceiver designs to support 5G NR communication devices involve wideband filters that may be implemented using resonators constructed with MIM capacitors and inductors. The communications enhancements defined by 5G NR communication devices involve wideband filters implemented with high quality (high Q) resonators, higher power thermal handling capabilities, and smaller die sizes. Meeting these specifications for implementing wideband filters in 5G NR communication devices using 2D inductors as well as traditional MIM capacitors can be challenging. High Q MIM capacitors and high Q inductors for implementing 3D resonators for wideband filters are desired. Summary of the Invention

[0006] The integrated circuit (IC) includes a substrate and a first through-substrate via (TSV) in the substrate. The first TSV includes a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate constructed from a first metallization layer on an inner surface of the first TSV. The first MIM capacitor includes a MIM insulator layer on the first plate. The first MIM capacitor includes a second plate constructed from a second metallization layer on the MIM insulator layer. The IC includes a 3D inductor. The 3D inductor includes a second TSV in the substrate. The 3D inductor includes a first trace on a first surface of the substrate coupled to a first end of the second TSV. The 3D inductor further includes a second trace on a second surface of the substrate and coupled to a second end of the second TSV and a second end of the first TSV.

[0007] A method for fabricating a 3D resonator includes depositing a first metallization layer on an inner surface of an opening of a first through-substrate via (TSV) in a substrate as a first plate of a first metal-insulator-metal (MIM) capacitor embedded in the first TSV. The method also includes depositing a dielectric layer on the first plate of the first MIM capacitor. The method further includes depositing a second metallization layer on the dielectric layer as a second plate of the first MIM capacitor. The method also includes forming a second TSV in the substrate. The method further includes depositing a first trace on a first surface of the substrate, the first trace coupled to a first end of the second TSV. The method also includes depositing a second trace on a second surface of the substrate opposite the first surface, the second trace coupled to a second end of the second TSV opposite the first end and to the second end of the first TSV.

[0008] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure are described below. Those skilled in the art will appreciate that the present disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed characteristic of the present disclosure, both as to its composition and method of operation, together with further objects and advantages thereof, will be better understood by considering the following description in connection with the accompanying drawings. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended to define the scope of the present disclosure.

[0009] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0010] [Figure 1]FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module employing an integrated passive device (IPD) filter. [Diagram 2] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module employing an integrated passive device (IPD) filter for a chipset. [Diagram 3] FIG. 1 is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module including a semiconductor die and an integrated passive device (IPD) filter die, in accordance with an embodiment of the present disclosure. [Figure 4] FIG. 1 illustrates a radio frequency integrated circuit (RFIC) chip including a capacitor-embedded 3D resonator for a wideband filter, according to an embodiment of the present disclosure. [Figure 5A] 5 is a schematic diagram further illustrating the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 according to an embodiment of the present disclosure. [Figure 5B] 5 is a schematic diagram further illustrating the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 according to an embodiment of the present disclosure. [Figure 6A] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6B] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6C] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6D] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6E]5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6F] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6G] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6H] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 6I] 5A-5C further illustrate side views of the cross-type metal-insulator-metal (MIM) capacitor of FIG. 4 in different interconnection schemes according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a process flow diagram illustrating a method for fabricating a cross-type metal-insulator-metal (MIM) capacitor according to an embodiment of the present disclosure. [Figure 8] FIG. 1 is a block diagram illustrating an example wireless communication system in which the configurations of the present disclosure may be advantageously employed. [Figure 9] FIG. 1 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The following detailed description, taken in conjunction with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0012] As described herein, the use of the term "and / or" is intended to indicate an "inclusive or," and the use of the term "or" is intended to indicate an "exclusive or." The term "exemplary" as used throughout this description means "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other exemplary configurations. The term "coupled" as used throughout this description means "directly or indirectly connected through an intervening electrical, mechanical, or other connection (e.g., a switch)," and is not necessarily limited to a physical connection. In addition, a connection can be such that objects are permanently connected or releasably connected. A connection can be through a switch. The term "adjacent" as used throughout this description means "adjacent, in close proximity, next to, or nearby." The term "on" as used throughout this description means "directly on" in some configurations and "indirectly on" in other configurations.

[0013] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) are migrating to deep sub-micron process nodes due to cost and power consumption issues. Mobile RF transceiver designs are complicated by added circuit functionality to support enhanced communications, such as fifth-generation (5G) new radio (NR) communications systems. Additional design challenges for mobile RF transceivers include the use of passive devices, which directly impacts analog RF performance considerations, including mismatch, noise, and other performance considerations.

[0014] Passive devices in mobile radio frequency (RF) transceivers may include high performance capacitor and inductor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors and integrated inductors. Integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn junction capacitors, metal-insulator-metal (MIM) capacitors, poly-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures. Capacitors are generally passive elements used in integrated circuits to store charge. For example, parallel plate capacitors are often made using plates or structures that are conductive with an insulating material between the plates.

[0015] An inductor is an example of an electrical device used to temporarily store energy in a magnetic field in a coil of wire according to an inductance value, which is a measure of the ratio of voltage to the rate of change of current passing through the inductor. When the current through the inductor changes, energy is temporarily stored in the magnetic field in the coil. In addition to their magnetic field storage capabilities, inductors are often used in alternating current (AC) electronic devices, such as wireless devices. For example, mobile RF transceiver designs include the use of wideband filters with inductors and capacitors to meet bandwidth specifications at sub-6 gigahertz frequencies (e.g., Frequency Range 1 (FR1)).

[0016] A radio frequency front-end (RFFE) module may include a 5G wideband FR1 filter including MIM capacitors and inductors. The design of a 5G wideband FR1 filter may involve the use of resonators constructed with MIM capacitors and inductors. Meeting the bandwidth extension defined by 5G NR FR1 involves wideband filters implemented with high quality (high Q) resonators, higher power thermal handling capabilities, and smaller die sizes. It may be difficult to meet the bandwidth extension defined by 5G NR FR1 using traditional 2D inductors as well as MIM capacitors. High Q MIM capacitors and high Q inductors for implementing 3D resonators with reduced form factors for implementing 5G wideband FR1 filters are desired.

[0017] Various aspects of the present disclosure provide a capacitor-embedded 3D resonator for a wideband filter. The process flow for fabricating the capacitor-embedded 3D resonator for a wideband filter may include a front-end-of-line (FEOL) process, a middle-of-line (MOL) process, and a back-end-of-line (BEOL) process. It should be understood that the term "layer" includes a film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described, the term "substrate" may refer to a substrate of a diced or undiced wafer. Similarly, the terms "chip" and "die" may be used interchangeably.

[0018] As described, a back-end-of-line (BEOL) interconnect layer may refer to a conductive interconnect layer (e.g., first interconnect layer (M1) or metal 1 M1, metal 2 (M2), metal 3 (M3), metal 4 (M4), etc.) for electrically coupling to a front-end-of-line (FEOL) active device of an integrated circuit. Various BEOL interconnect layers are formed in corresponding BEOL interconnect layers where a lower BEOL interconnect layer uses a thinner metal layer compared to an upper BEOL interconnect layer. The BEOL interconnect layer may be electrically coupled to a middle-of-line (MOL) interconnect layer, for example, M1 may be connected to an oxide diffusion (OD) layer of the integrated circuit. The MOL interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of the integrated circuit. A BEOL first via (V2) may connect M2 to M3 or other layers of the BEOL interconnect layer.

[0019] Some aspects of the present disclosure integrate capacitors in through-substrate vias (TSVs). For example, the TSVs may be through-alumina vias (TAVs) when implemented in an alumina substrate, such as an alumina ribbon ceramic (ARC) substrate, to provide improved thermal conductivity (Tσ). In some aspects of the present disclosure, the wideband filter includes a capacitor-embedded 3D resonator. For example, the 3D resonator is implemented as an inductor-capacitor (LC) resonator in an interconnect-less configuration. In these aspects of the present disclosure, the 3D resonator exhibits a reduced design form factor by implementing a metal-insulator-metal (MIM) capacitor in the TSV.

[0020] In some embodiments of the present disclosure, the 3D inductors of the 3D resonators are implemented using interconnected TSVs and traces on both sides of the substrate. In these embodiments of the present disclosure, the traces of the 3D inductors can be coupled to TSV-embedded capacitors on either side of the substrate. This configuration provides flexibility in routing RF signal pins, whether on the first side of the substrate or on the opposite second side, through the series connection of the TSV-embedded capacitors. The performance of the 3D resonators can be improved when implemented using high-Q 3D inductors. These embodiments of the present disclosure integrate 3D resonators (e.g., capacitor (C) series and LC parallel resonators) for ladder topology wideband filters.

[0021] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module 100 employing a filter 104 (e.g., a wideband filter implemented with a capacitor-embedded 3D resonator). The RFFE module 100 includes a power amplifier 102, a filter 104, and a radio frequency (RF) switch module 106. The power amplifier 102 amplifies a signal(s) to a certain power level for transmission. The filter 104 filters the input / output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other similar parameters. Additionally, the RF switch module 106 may select certain portions of the input signal to pass to the remainder of the RFFE module 100.

[0022] The radio frequency front-end (RFFE) module 100 also includes a tuner circuit 112 (e.g., a first tuner circuit 112A and a second tuner circuit 112B), a diplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuit 112 (e.g., a first tuner circuit 112A and a second tuner circuit 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuit 112 may perform impedance tuning (e.g., voltage standing wave ratio (VSWR) optimization) for the antenna 114. The RFFE module 100 also includes a passive combiner 108 coupled to a wireless transceiver (WTR) 120. The passive combiner 108 combines the detected power from the first tuner circuit 112A and the second tuner circuit 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides the information to a modem 130 (e.g., a mobile station modem (MSM)). The modem 130 provides a digital signal to an application processor (AP) 110.

[0023] As shown in FIG. 1, the diplexer 190 is located between the tuner components of the tuner circuit 112 and the capacitor 116, the inductor 118, and the antenna 114. The diplexer 190 may be disposed between the antenna 114 and the tuner circuit 112 to provide high system performance from the radio frequency front end (RFFE) module 100 to a chipset including the wireless transceiver 120, the modem 130, and the application processor 110. The diplexer 190 also performs frequency domain multiplexing for both high and low band frequencies. After the diplexer 190 performs its frequency multiplexing function on the input signal, the output of the diplexer 190 is sent to an optional inductor / capacitor (LC) network including the capacitor 116 and the inductor 118. The LC network may provide additional impedance matching components for the antenna 114, if necessary. A signal having a particular frequency is then transmitted or received by the antenna 114. Although single capacitors and inductors are shown, multiple components are contemplated.

[0024] 2 is a schematic diagram of a radio frequency integrated circuit (RFIC) chip 200 having a wireless local area network (WLAN) (e.g., Wi-Fi) module 150 and a radio frequency front-end (RFFE) module 170 for a chipset 210. The Wi-Fi module 150 includes a first diplexer 162 that communicatively couples an antenna 164 to a WLAN module 152. A first RF switch 160 communicatively couples the first diplexer 162 to the WLAN module 152. The RFFE module 170 includes a second diplexer 190 that communicatively couples an antenna 192 to a wireless transceiver (WTR) 120 via a filter 172 (e.g., a wideband filter implemented using a capacitor-embedded 3D resonator). A second RF switch 180 communicatively couples the second diplexer 190 to the filter 172.

[0025] The WTR 120 and the WLAN module 152 of the Wi-Fi module 150 are coupled to a modem (Mobile Station Modem (MSM), e.g., a baseband modem) 130, which is powered by a power source 202 via a power management integrated circuit (PMIC) 140. The chipset 210 also includes capacitors 144 and 148 and inductor(s) 146 to provide signal quality. Each of the PMIC 140, the modem 130, the WTR 120, and the WLAN module 152 includes a capacitor (e.g., 142, 132, 122, and 154) and operates according to a clock 204. Additionally, the inductor 146 couples the modem 130 to the PMIC 140. The shape and arrangement of the various inductor and capacitor components in the RFIC chip 200 can reduce electromagnetic coupling between the components. The design of RFFE module 170 includes filter 172, which may be a wideband filter implemented using a capacitor-embedded 3D resonator, for example as shown in FIG. 3, according to an embodiment of the present disclosure.

[0026] 3 is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module 300 including a semiconductor die and an integrated passive device (IPD) filter die according to an embodiment of the present disclosure. In this example, the RFFE module 300 includes a semiconductor die 350 and an IPD filter die 320 supported by a substrate 310. The semiconductor die 350 may be an active die having a semiconductor substrate 360 ​​(e.g., an active silicon substrate) coupled to package balls 302 via a back-end-of-line (BEOL) layer 370. The BEOL layer 370 includes multiple BEOL metallization layers (M1, M2, M3, ..., Mn) on the semiconductor substrate 360 ​​(e.g., a diced silicon wafer). A redistribution layer 312 is coupled to the package balls 302.

[0027] The IPD filter die 320 includes a substrate 330 (e.g., a passive substrate) coupled to package balls 302 via back-end-of-line (BEOL) layers 340. A redistribution layer 312 is coupled to the IPD filter die 320 via package balls 302. In some aspects of the disclosure, the substrate 330 is constructed from glass and the IPD filter die 320 is a glass-substrate integrated passive device (GIPD) filter die. The IPD filter die 320 may implement a fifth-generation (5G) new radio (NR) wideband frequency range 1 (FR1) filter.

[0028] The design of 5G wideband FR1 filters may involve the use of resonators constructed of metal-insulator-metal (MIM) capacitors and inductors. Meeting the bandwidth extensions defined by 5G NR FR1 involves wideband filters implemented with high quality (high Q) resonators, higher power thermal handling capabilities, and smaller die sizes. Meeting these bandwidth extensions defined by 5G NR FR1 may be difficult using traditional 2D inductors as well as MIM capacitors. Aspects of the present disclosure are directed to high Q MIM capacitors and high Q inductors for implementing 3D resonators with reduced form factors for implementing 5G wideband FR1 filters. In some aspects of the present disclosure, the IPD filter die 320 includes a capacitor-embedded 3D resonator for a wideband filter, as further shown in FIG. 4.

[0029] FIG. 4 illustrates a radio frequency integrated circuit (RFIC) chip including a capacitor-embedded 3D resonator for a wideband filter according to an embodiment of the disclosure. Typically, the RFIC chip 400 includes a substrate 402 and a first through-substrate via (TSV) 410 in the substrate 402. In some embodiments of the disclosure, the first TSV 410 includes a first metal-insulator-metal (MIM) capacitor 420 embedded in the first TSV 410. In this example, the first MIM capacitor 420 includes a first plate comprised of a metallization layer on an inner surface of the first TSV 410. The first MIM capacitor 420 also includes a MIM insulator layer on the first plate of the first MIM capacitor 420. In addition, the second plate of the first MIM capacitor 420 is comprised of a metallization layer on the MIM insulator layer. The formation of the first MIM capacitor 420 is further illustrated in FIGS. 6A-6I.

[0030] 4, the RFIC chip 400 includes a 3D inductor 430 coupled to a first MIM capacitor 420 embedded in a first TSV 410 according to an embodiment of the present disclosure. In this example, the 3D inductor 430 includes a second TSV 440 in the substrate 402. The 3D inductor 430 is comprised of a first trace 432 on a first surface of the substrate 402 and coupled to a first end 442 of the second TSV 440. The 3D inductor 430 is also comprised of a second trace 434 on a second surface of the substrate 402 opposite the first surface of the substrate 402. In this example, the second trace 434 is coupled to a second end 444 of the second TSV 440 opposite the first end 442. In some aspects of the disclosure, a second trace 434 is coupled to a second end of the first TSV 410 and contacts the 3D inductor 430 to the first MIM capacitor 420.

[0031] The RFIC chip 400 further includes a third TSV 450 in the substrate 402 with a second MIM capacitor 460 embedded within the third TSV 450. In this example, the second MIM capacitor 460 is comprised of a first plate comprised of a metallization layer on the inner surface of the third TSV 450. The second MIM capacitor 460 also includes an MIM insulator layer on the first plate and a second plate comprised of a metallization layer on the MIM insulator layer. The RFIC chip 400 also includes a third trace 416 on the first surface of the substrate 402 coupled to a first end 412 of the first TSV 410 and a first end 452 of the third TSV 450. In these aspects of the disclosure, the third trace 416 couples the second MIM capacitor 460 to the first MIM capacitor 420 embedded within the first TSV 410.

[0032] As further shown in FIG. 4 , the 3D inductor 430 includes a fourth TSV 470 in the substrate 402 and having a first end 452 coupled to the first trace 432. The 3D inductor 430 also includes a fourth trace 436 on a second surface of the substrate 402. In this example, the fourth trace 436 is coupled to a second end 474 of the fourth TSV 470 opposite the first end 472. The 3D inductor 430 further includes a fifth TSV 480 in the substrate 402 and having a second end 484 coupled to the fourth trace 436. The 3D inductor 430 also includes a fifth trace 438 on the first surface of the substrate 402 for coupling a first end 482 of the fifth TSV 480 to a first end 452 of the third TSV 450. The fifth trace 438 completes the formation of the 3D inductor 430 by coupling to a first end 482 of the fifth TSV 480 and a first end 452 of the third TSV 450, which is also coupled to the first TSV 410 via the third trace 416.

[0033] The RFIC chip 400 further includes a sixth TSV 490 in the substrate 402, with a third MIM capacitor 496 embedded within the sixth TSV 490. In this example, the third MIM capacitor 496 has a first plate constructed from a metallization layer on the inner surface of the sixth TSV 490. The third MIM capacitor 496 also includes an MIM insulator layer on the first plate and a second plate constructed from a metallization layer on the MIM insulator layer. The RFIC chip 400 further includes a sixth trace 456 on the second surface of the substrate 402 and coupled to the second end 454 of the third TSV 450 and the second end 494 of the sixth TSV 490. In addition, a seventh trace 498 is coupled to the first end 492 of the sixth TSV 490. In these aspects of the disclosure, the sixth trace 456 provides a series connection between the second MIM capacitor 460 and the third MIM capacitor 496 .

[0034] 5A and 5B are schematic diagrams of a C series inductor / capacitor (LC) parallel resonator according to an embodiment of the present disclosure. FIG. 5A shows a schematic diagram of a C series LC parallel resonator 500 that enables the formation of a wideband filter, such as a fifth generation (5G) new radio (NR) frequency range 1 (FR1) wideband filter. In this example, a first capacitor 520 and a second capacitor 560 are coupled in series and parallel to an inductor 530 to form an LC circuit 510. In addition, a third capacitor 596 is coupled to the LC circuit 510 to form the C series LC parallel resonator 500.

[0035] FIG. 5B illustrates a capacitor-embedded 3D resonator 550 constructed from the RFIC chip 400 of FIG. 4 overlaid with the C series LC parallel resonator 500 of FIG. 5A according to an embodiment of the disclosure. In this example, a 3D inductor 430 is coupled between a first metal-insulator-metal (MIM) capacitor 420, a second MIM capacitor 460, and a third MIM capacitor 496 coupled in series to form the C series LC parallel resonator 500 of FIG. 5A. In some embodiments of the disclosure, the C series LC parallel resonator 500 of FIG. 5A is configured as a 3D resonator implemented using interconnected capacitor-embedded through-substrate vias (TSVs) (e.g., 410, 450, and 490) and traces (e.g., 432, 434, 436, and 438) on both sides of the substrate 402.

[0036] In these aspects of the disclosure, the traces (e.g., 432, 434, 436, and 438) of the 3D inductor 430 can be coupled to the TSV-embedded capacitors (e.g., 410, 450, and 490) on either side of the substrate 402. This configuration provides flexibility in routing RF signal pins through the series connection of the TSV-embedded capacitors (e.g., 410, 450, and 490), whether on the first side or the opposite second side of the substrate 402. The performance of the capacitor-embedded 3D resonator is improved by implementing the 3D inductor 430 using a high-Q 3D inductor. In these aspects of the disclosure, 3D resonators (e.g., capacitor (C) series and LC parallel resonators) for ladder topology wideband filters, for example, as formed in Figures 6A-6I, are integrated.

[0037] 6A-6I illustrate a process 600 for fabricating a capacitor-embedded 3D resonator according to an embodiment of the disclosure. FIGS. 6A-6I may use similar reference numbers to those of the RFIC chip 400, as shown in FIG. 4. FIG. 6A illustrates step 1 of the process 600, in which a first surface 404 of a substrate 402 is bonded to a first carrier substrate 602 using a first bonding adhesive 604. In this example, the substrate 402 is shown as an alumina substrate, such as an alumina ribbon ceramic (ARC) substrate, or other similar substrate material having a desired thermal conductivity.

[0038] 6B illustrates step 2 of process 600, in which an initial conductive layer 610 is plated onto the second surface 406 of the substrate 402. In this example, plating of the initial conductive layer 610 is performed by plating copper (Cu) onto the second surface 406 of the substrate 402 as an initial redistribution layer (RDL-A).

[0039] 6C illustrates step 3 of process 600, in which the first carrier substrate 602 is peeled away from the first surface 404 of the substrate 402. In addition, a second carrier substrate 606 is bonded to the second surface 406 of the substrate 402, including the initial conductive layer 610, using a second bonding adhesive 612.

[0040] 6D illustrates step 4 of process 600, in which a via opening 640 is formed in substrate 402 to expose initial conductive layer 610. In this example, laser drilling is performed to form a back via according to a TSV-final process to expose the inner surface 408 of the via opening 640 as well as the initial conductive layer 610.

[0041] 6E illustrates step 5 of process 600, in which a first conductive layer 650 is plated on the first surface 404 of the substrate 402 and on the inner surface 408 of the via opening 640. In this example, plating of the first conductive layer 650 is performed by plating copper (Cu) as a first redistribution layer (RDL-1) on the first surface 404 of the substrate 402. Plating of the first conductive layer 650 may also include formation of a first pad 652. In some aspects of the disclosure, the first conductive layer 650 provides a first plate of a through-substrate-via (TSV) embedded metal-insulator-metal (MIM) capacitor (e.g., 420, 460, and 496), for example, as shown in FIG.

[0042] FIG. 6F illustrates step 6 of process 600, in which a dielectric layer 660 is deposited on the first conductive layer 650 including the first pad 652. A patterning process is then performed on the dielectric layer 660 to expose portions of the first conductive layer 650 and the first pad 652. In this example, deposition of the dielectric layer 660 may be performed using plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiNx) on the first conductive layer 650 and the first pad 652. Alternatively, deposition of the dielectric layer 660 may be performed using plasma enhanced atomic layer deposition (ALD) of aluminum oxide (Al2O3) on the first conductive layer 650 and the first pad 652, or other similar dielectric material for supporting a high-Q capacitor. In some embodiments of the present disclosure, the dielectric layer 660 provides an insulator layer for the TSV-embedded MIM capacitors (eg, 420, 460, and 496), for example as shown in FIG.

[0043] 6G illustrates step 7 of process 600, in which a second conductive layer 670 is plated on the dielectric layer 660 and exposed portions of the first conductive layer 650 and the first pad 652. In this example, plating of the second conductive layer 670 is performed by plating copper (Cu) as a second redistribution layer (RDL-2) on the surfaces of the dielectric layer 660 and the first conductive layer 650. Plating of the second conductive layer 670 may also include forming a first via (V1) and a second pad 672 on the first pad 652. In some aspects of the disclosure, the second conductive layer 670 provides a second plate of a TSV-embedded MIM capacitor (e.g., 420, 460, and 496), for example, as shown in FIG.

[0044] 6H illustrates step 8 of process 600 in which a dry film fill layer 680 is deposited over the second conductive layer 670, as well as the dielectric layer 660, the first conductive layer 650, and the exposed portions of the first surface 404 of the substrate 402. A pad opening process is then performed to expose the second pads 672.

[0045] 6I illustrates step 9 of process 600 in which the second carrier substrate 606 is peeled away from the substrate 402 to complete the embedded capacitor in the 3D TSV inductor / resonator process flow. A process for fabricating a capacitor-embedded 3D resonator is shown, for example, in FIG.

[0046] FIG. 7 is a process flow diagram illustrating a method for fabricating a 3D resonator according to an embodiment of the present disclosure. The method 700 begins at block 702, where a first metallization layer is deposited on an inner surface of a first through-substrate via (TSV) opening in a substrate as a first plate of a first metal-insulator-metal (MIM) capacitor embedded in the first TSV. For example, as shown in FIG. 4, the first MIM capacitor 420 includes a first plate composed of a metallization layer on the inner surface of the first TSV 410. As shown in FIG. 6E, a first conductive layer 650 is plated on the first surface 404 of the substrate 402 and on the inner surface 408 of the via opening 640. In this example, plating of the first conductive layer 650 is performed by plating copper (Cu) as a first redistribution layer (RDL-1) on the first surface 404 of the substrate 402 and on the inner surface 408 of the via opening 640.

[0047] In block 704, a dielectric layer is deposited on the first plate of the first MIM capacitor. As shown in FIG. 4, the first MIM capacitor 420 also includes a MIM insulator layer on the first plate of the first MIM capacitor 420. As shown in FIG. 6F, a dielectric layer 660 is deposited on the first conductive layer 650 including the first pad 652. A patterning process is then performed on the dielectric layer 660 to expose a portion of the first conductive layer 650 and the first pad 652. In this example, the deposition of the dielectric layer 660 may be performed using plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiNx) on the first conductive layer 650 and the first pad 652. Alternatively, the deposition of the dielectric layer 660 may be performed using plasma enhanced atomic layer deposition (ALD) of aluminum oxide (Al2O3) on the first conductive layer 650 and the first pad 652.

[0048] Referring again to FIG. 7, in block 706, a second metallization layer is deposited on the dielectric layer as a second plate of the first MIM capacitor. For example, as shown in FIG. 4, the second plate of the first MIM capacitor 420 is composed of a metallization layer on the MIM insulator layer. As shown in FIG. 6G, a second conductive layer 670 is plated on the dielectric layer 660 and the exposed portions of the first conductive layer 650 and the first pad 652. In this example, plating of the second conductive layer 670 is performed by plating copper (Cu) on the surfaces of the dielectric layer 660 and the first conductive layer 650 as a second redistribution layer (RDL-2). In some aspects of the present disclosure, the second conductive layer 670 provides a second plate of a TSV-embedded MIM capacitor (e.g., 420, 460, and 496), for example, as shown in FIG. 4.

[0049] At block 708, a second TSV is formed in the substrate. For example, as shown in FIG. 4, the 3D inductor 430 includes a second TSV 440 in the substrate 402. At block 710, a first trace is deposited on a first surface of the substrate and coupled to a first end of the second TSV. For example, as shown in FIG. 4, the 3D inductor 430 is comprised of a first trace 432 on the first surface of the substrate 402 and coupled to a first end 442 of the second TSV 440.

[0050] At block 712, a second trace is deposited on a second surface of the substrate opposite the first surface and coupled to a second end of the second TSV opposite the first end and to a second end of the first TSV. For example, as shown in FIG. 4, the 3D inductor 430 is also comprised of a second trace 434 on the second surface of the substrate 402 opposite the first surface of the substrate 402. In this example, the second trace 434 is coupled to a second end 444 of the second TSV 440 opposite the first end 442. In some aspects of the disclosure, the second trace 434 is coupled to a second end of the first TSV 410 and contacts the 3D inductor 430 to the first MIM capacitor 420.

[0051] In some aspects of the present disclosure, the 3D inductors of the 3D resonators are implemented using interconnected TSVs and traces on both sides of the substrate. In these aspects of the present disclosure, the traces of the 3D inductors can be coupled to TSV-embedded capacitors on either side of the substrate. This configuration provides flexibility in routing RF signal pins, whether on the first side of the substrate or on the opposite second side, through the series connection of the TSV-embedded capacitors. The performance of the 3D resonators can be improved when implemented using high-Q 3D inductors. These aspects of the present disclosure integrate 3D resonators (e.g., capacitor (C) series and inductor / capacitor (LC) parallel resonators) for ladder topology wideband filters.

[0052] According to a further aspect of the present disclosure, an integrated circuit (IC) includes a first TSV. In one configuration, the first TSV has a means for storing charge. In one configuration, the charge storage means may be a first MIM capacitor 420, as shown in FIG. 4. In another aspect, said means may be any structure or any material configured to perform the functions recited by said means.

[0053] FIG. 8 is a block diagram illustrating an exemplary wireless communication system 800 in which an aspect of the present disclosure may be advantageously employed. For illustrative purposes, FIG. 8 shows three remote units 820, 830, and 850 and two base stations 840. It will be appreciated that the wireless communication system may have more remote units and base stations than this. The remote units 820, 830, and 850 include integrated circuit (IC) devices 825A, 825C, and 825B that include the disclosed capacitor-embedded 3D resonators. It should be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed capacitor-embedded 3D resonators. FIG. 8 shows forward link signals 880 from the base station 840 to the remote units 820, 830, and 850, and reverse link signals 890 from the remote units 820, 830, and 850 to the base station 840.

[0054] In FIG. 8, remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a stationary remote unit in a wireless local loop system. For example, the remote units may be portable data units such as mobile phones, handheld personal communication systems (PCS) units, personal digital assistants, stationary data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, or other devices that store or retrieve data or computer instructions, or combinations thereof. Although FIG. 8 illustrates remote units according to aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, including the disclosed capacitor-embedded 3D resonators.

[0055] FIG. 9 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components, such as the capacitor-embedded 3D resonators disclosed above. The design workstation 900 includes a hard disk 901 that contains operating system software, support files, and design software, such as Cadence or OrCAD. The design workstation 900 also includes a display 902 to facilitate design of a circuit 910 or a radio frequency (RF) component 912, such as a cross-type capacitor. A storage medium 904 is provided for tangibly storing the design of the circuit 910 or the RF component 912 (e.g., the capacitor-embedded 3D resonator). The design of the circuit 910 or the RF component 912 may be stored on the storage medium 904 in a file format, such as GDSII or GERBER. The storage medium 904 may be a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a hard disk, a flash memory, or other suitable device. Additionally, the design workstation 900 includes a drive device 903 for receiving input from or writing output to a storage medium 904 .

[0056] The data recorded on the storage medium 904 may define logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams and net circuits associated with logic simulations. Providing the data on the storage medium 904 facilitates the design of the circuit 910 or radio frequency (RF) component 912 by reducing the number of processes for designing a semiconductor wafer.

[0057] The following numbered clauses describe example implementations. 1. A substrate; A first through-substrate via (TSV) in a substrate, a first metal-insulator-metal (MIM) capacitor, the MIM capacitor comprising: a first plate comprised of a first metallization layer on an inner surface of the first TSV; a MIM insulator layer on the first plate; a second plate comprised of a second metallization layer on the MIM insulator layer; a first through-substrate via (TSV); A 3D inductor a second TSV in the substrate; and a first trace on the first surface of the substrate coupled to a first end of the second TSV; a second end of the second TSV opposite the first end, and a second trace on a second surface of the substrate opposite the first surface coupled to the second end of the first TSV; a 3D inductor, An integrated circuit (IC). 2. a third TSV in the substrate, a second MIM capacitor, the second MIM capacitor comprising: a third plate constructed from the first metallization layer on the inner surface of the third TSV; a MIM insulator layer on the third plate; a fourth plate comprising a second metallization layer on the MIM insulator layer; Including, The third TSV, a third trace on the first surface of the substrate and coupled to a first end of the first TSV and a first end of the third TSV; The IC of clause 1 further comprising: 3. 3D inductor, a fourth TSV in the substrate and having a first end coupled to the first trace; a fourth trace on the second surface of the substrate, the fourth trace coupled to a second end of the fourth TSV; a fifth TSV in the substrate, the fifth TSV having a second end coupled to the fourth trace; a fifth trace on the first surface of the substrate and coupled to a first end of the fifth TSV and a first end of the third TSV; The IC described in clause 2 further comprises: 4. a sixth TSV in the substrate, a third MIM capacitor, the third MIM capacitor comprising: a fifth plate comprised of the first metallization layer on the inner surface of the sixth TSV; a MIM insulator layer on the fifth plate; a sixth plate comprising a second metallization layer on the MIM insulator layer; Including, The sixth TSV, a sixth trace on the second surface of the substrate and coupled to a second end of the third TSV and a second end of the sixth TSV; The IC of clause 3 further comprising: 5. The IC of clause 4, further comprising a seventh trace on the first surface of the substrate and coupled to a first end of the sixth TSV. 6. The IC of any of clauses 2-5, wherein the first trace is coupled to a first end of the third TSV and to a third trace. 7. The IC of any one of clauses 1-6, wherein the substrate comprises alumina. 8. The IC of any one of clauses 1 to 7, wherein the IC is integrated into an integrated passive device (IPD). 9. The IC of clause 8, wherein the IPD is integrated into a wideband filter. 10. The IC of clause 9, wherein the wideband filter is integrated into a radio frequency front-end (RFFE) module. 11. A method for fabricating a 3D resonator comprising: depositing a first metallization layer on an interior surface of an opening of a first through-substrate via (TSV) in a substrate as a first plate of a first metal-insulator-metal (MIM) capacitor embedded in the first TSV; depositing a dielectric layer on a first plate of a first MIM capacitor; depositing a second metallization layer over the dielectric layer as a second plate of the first MIM capacitor; forming a second TSV in the substrate; depositing a first trace on a first surface of the substrate, the first trace coupled to a first end of the second TSV; depositing a second trace on a second surface of the substrate opposite the first surface, the second trace coupled to a second end of the second TSV opposite the first end and to the second end of the first TSV; A method comprising: 12. depositing a first metallization layer on an interior surface of an opening of a third TSV in the substrate as a first plate of a second MIM capacitor embedded in the third TSV; depositing a dielectric layer on a first plate of a second MIM capacitor; depositing a second metallization layer over the dielectric layer as a second plate of a second MIM capacitor; depositing a third trace on the first surface of the substrate and coupled to a first end of the first TSV and a first end of a third TSV; 12. The method of claim 11, further comprising: 13. forming a fourth TSV in the substrate and having a first end coupled to the first trace; depositing a fourth trace on the second surface of the substrate, the fourth trace coupled to a second end of the fourth TSV; forming a fifth TSV in the substrate, the fifth TSV having a second end coupled to the fourth trace; forming a fifth trace on the first surface of the substrate and coupled to a first end of the fifth TSV and a first end of the third TSV; 13. The method of claim 12, further comprising: 14. depositing a first metallization layer on an interior surface of an opening of a sixth TSV in the substrate as a first plate of a third MIM capacitor embedded in the sixth TSV; depositing a dielectric layer on a first plate of a third MIM capacitor; depositing a second metallization layer over the dielectric layer as a second plate of a third MIM capacitor; depositing a sixth trace on the second surface of the substrate and coupled to a second end of the third TSV and a second end of the sixth TSV; 14. The method of claim 13, further comprising: 15. The method of claim 14, further comprising depositing a seventh trace on the first surface of the substrate and coupled to a first end of the sixth TSV. 16. The method of any of clauses 12-15, wherein the first trace is coupled to a first end of a third TSV and to a third trace. 17. The method of any one of clauses 11-16, wherein the substrate comprises alumina. 18. The method of any of clauses 11-17, further comprising integrating the 3D resonator into an integrated passive device (IPD). 19. The method of claim 18, further comprising integrating the IPD into a wideband filter. 20. The method of clause 19, further comprising integrating a wideband filter into a radio frequency front-end (RFFE) module.

[0058] For a firmware and / or software implementation, the methods may be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media tangibly embodying instructions may be used in implementing the methods described herein. For example, software code may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. The term "memory" as used herein may refer to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory, and is not limited to a specific type or number of memories, or to a specific type of medium on which the memory is stored.

[0059] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with data structures and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where disks typically reproduce data magnetically while discs reproduce data optically using lasers. Combinations of the above are also intended to be included within the scope of computer readable media.

[0060] In addition to storage on a computer-readable medium, the instructions and / or data may be provided as signals on a transmission medium included in a communications device. For example, a communications device may include a transceiver having signals indicative of the instructions and data. The instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0061] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made in the specification without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "top" and "bottom" are used in reference to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, top becomes bottom and bottom becomes top. In addition, if in landscape orientation, top and bottom may refer to the side of the substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the processes, machines, manufactures, compositions, means, methods, and steps described herein. As one skilled in the art would readily appreciate from this disclosure, any existing or later developed process, machine, manufacture, composition, means, method, or step that performs substantially the same function or achieves substantially the same results as the corresponding configurations described herein may be utilized in accordance with the present disclosure. Accordingly, it is intended that the appended claims include within their scope such processes, machines, manufactures, compositions, means, methods, or steps.

[0062] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as a departure from the scope of the present disclosure.

[0063] The various example logic blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0064] The steps of a method or algorithm described in relation to the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a register, a hard disk, a removable disk, a compact disk read only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside in a user terminal. Alternatively, the processor and the storage medium may reside in a user terminal as discrete components.

[0065] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code means specified in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. In addition, any connection may be properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where disks typically reproduce data magnetically while discs reproduce data optically using lasers. Combinations of the above are also intended to be included within the scope of computer readable media.

[0066] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0067] 100 RFFE Modules 102 Power Amplifier 104 Filters 106 RF Switch Module 108 Passive Combiner 110 Application Processor 112 Tuner circuit 112A First Tuner Circuit 112B Second Tuner Circuit 114 Antenna 115 Ground terminal 116 Capacitor 118 Inductor 120 Wireless Transceiver 130 Modem 144 Capacitor 146 Inductor 148 Capacitor 150 Wi-Fi Module 152 WLAN Module 160 First RF Switch 162 First Diplexer 164 Antenna 170 RFFE Modules 172 Filters 180 Second RF Switch 190 Second Diplexer 192 Antenna 200 RFIC chips 202 Power supply 204 Clock 210 Chipset 300 RFFE Modules 302 Package Ball 310 Substrate 312 Redistribution layer 320 IPD filter die 330 Substrate 340 BEOL layer 350 Semiconductor Dies 360 Semiconductor Substrate 370 BEOL layer 400 RFIC chips 402 Substrate 404 First Surface 406 Second Surface 408 Inside 410 First TSV 412 First end 416 The Third Trace 420 First MIM capacitor 430 D inductor 432 First Trace 434 Second Trace 436 The Fourth Trace 438 The Fifth Trace 440 Second TSV 442 First End 444 Second End 450 3rd TSV 452 First End 454 Second End 456 The Sixth Trace 460 Second MIM Capacitor 470 4th TSV 472 First End 474 Second End 480 5th TSV 482 First End 484 Second End 490 6th TSV 492 First End 494 Second End 496 The third MIM capacitor 498 The Seventh Trace 500 parallel resonators 510 LC Circuit 520 First Capacitor 530 Inductor 550 D resonator 560 Second Capacitor 596 Third Capacitor 600 processes 602 first carrier substrate 604 First bonding adhesive 606 Second Carrier Substrate 610 Initial Conductive Layer 612 Secondary bonding adhesive 640 via opening 650 First conductive layer 652 First Pad 660 Dielectric layer 670 Second conductive layer 672 Second Pad 680 Dry Film Filling Layer 800 Wireless Communication System 820 Remote Unit 825A Integrated Circuit (IC) Devices 825C Integrated Circuit (IC) Devices 830 Remote Unit 840 base station 850 Remote Unit 880 forward link signal 890 Reverse Link Signal 900 Design Workstation 901 Hard Disk 902 Display 903 Drive unit 904 Storage medium 910 Circuit 912 RF Components

Claims

1. A substrate; a first through-substrate via (TSV) in the substrate, the first TSV comprising: a first metal-insulator-metal (MIM) capacitor, a first plate composed of a first metallization layer on an inner surface of the first TSV; a MIM insulator layer on the first plate; a second plate comprising a second metallization layer on the MIM insulator layer; a first MIM capacitor including: a first through-substrate via (TSV), A 3D inductor a second TSV in the substrate; and a first trace on a first surface of the substrate coupled to a first end of the second TSV; a second end of the second TSV opposite the first end, and a second trace on a second surface of the substrate opposite the first surface coupled to the second end of the first TSV; a 3D inductor, a third TSV in the substrate, the third TSV comprising: a second MIM capacitor, a third plate constructed from the first metallization layer on an inner surface of the third TSV; the MIM insulator layer on the third plate; a fourth plate composed of the second metallization layer on the MIM insulator layer; a second MIM capacitor including a third TSV, a third trace on the first surface of the substrate and coupled to a first end of the first TSV and a first end of the third TSV; An integrated circuit (IC) comprising:

2. The 3D inductor a fourth TSV in the substrate and having a first end coupled to the first trace; a fourth trace on the second surface of the substrate, the fourth trace coupled to a second end of the fourth TSV; a fifth TSV in the substrate, the fifth TSV having a second end coupled to the fourth trace; a fifth trace on the first surface of the substrate and coupled to a first end of the fifth TSV and the first end of the third TSV; The IC of claim 1 further comprising:

3. a sixth TSV in the substrate, the sixth TSV comprising: a third MIM capacitor, a fifth plate constructed from the first metallization layer on an inner surface of the sixth TSV; the MIM insulator layer on the fifth plate; a sixth plate composed of the second metallization layer on the MIM insulator layer; a third MIM capacitor including a sixth TSV including: a sixth trace on the second surface of the substrate and coupled to a second end of the third TSV and a second end of the sixth TSV; The IC of claim 2 further comprising:

4. The IC of claim 3 , further comprising: a seventh trace on the first surface of the substrate and coupled to a first end of the sixth TSV.

5. 2. The IC of claim 1, wherein the first trace is coupled to the first end of the third TSV and to the third trace.

6. The IC of claim 1 , wherein the substrate comprises alumina.

7. the IC is integrated into an integrated passive device (IPD); the IPD is integrated into a wideband filter; The IC of claim 1 , wherein the wideband filter is integrated into a radio frequency front end (RFFE) module.

8. 1. A method for fabricating a 3D resonator, comprising: depositing a first metallization layer on an interior surface of an opening of a first through-substrate via (TSV) in a substrate as a first plate of a first metal-insulator-metal (MIM) capacitor embedded in the first TSV; depositing a dielectric layer on the first plate of the first MIM capacitor; depositing a second metallization layer over the dielectric layer as a second plate of the first MIM capacitor; forming a second TSV in the substrate; depositing a first trace on a first surface of the substrate, the first trace coupled to a first end of the second TSV; depositing a second trace on a second surface of the substrate opposite the first surface, the second trace coupled to a second end of the second TSV opposite the first end and to a second end of the first TSV; depositing the first metallization layer on an interior surface of an opening of the third TSV in the substrate as a first plate of a second MIM capacitor embedded in the third TSV; depositing the dielectric layer on the first plate of the second MIM capacitor; depositing the second metallization layer over the dielectric layer as a second plate of the second MIM capacitor; depositing a third trace on the first surface of the substrate and coupled to a first end of the first TSV and a first end of the third TSV; A method comprising:

9. forming a fourth TSV in the substrate and having a first end coupled to the first trace; depositing a fourth trace on the second surface of the substrate, the fourth trace coupled to a second end of the fourth TSV; forming a fifth TSV in the substrate, the fifth TSV having a second end coupled to the fourth trace; forming a fifth trace on the first surface of the substrate and coupled to a first end of the fifth TSV and the first end of the third TSV; The method of claim 8 further comprising:

10. depositing the first metallization layer on an interior surface of an opening of the sixth TSV in the substrate as a first plate of a third MIM capacitor embedded in the sixth TSV; depositing the dielectric layer on the first plate of the third MIM capacitor; depositing the second metallization layer over the dielectric layer as a second plate of the third MIM capacitor; depositing a sixth trace on the second surface of the substrate and coupled to a second end of the third TSV and a second end of the sixth TSV; 10. The method of claim 9, further comprising:

11. 11. The method of claim 10, further comprising depositing a seventh trace on the first surface of the substrate and coupled to a first end of the sixth TSV.

12. 9. The method of claim 8, wherein the first trace is coupled to the first end of the third TSV and to the third trace.

13. The method of claim 8 , wherein the substrate comprises alumina.

14. further comprising integrating the 3D resonator into an integrated passive device (IPD); further comprising integrating the IPD into a wideband filter; The method of claim 8 , further comprising integrating the wideband filter into a radio frequency front end (RFFE) module.

Images