A 3D non-volatile memory floorplan architecture.

Abstract

A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, the first semiconductor structure including a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, each memory plane having a plurality of bit lines oriented in a bit line direction on the first semiconductor structure, a memory plane boundary, and a fixed position, each page buffer circuit having a buffer circuit boundary, the first semiconductor structure and the second semiconductor structure being bonded to each other in a facing orientation, and a first memory plane boundary of the first memory plane and a first page buffer circuit boundary of the first page buffer circuit are vertically aligned with each other such that a first portion of the first page buffer circuit boundary is offset from the first memory plane boundary in the bit line direction such that it does not overlap an area defined by the first memory plane boundary.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Patent Application PCT / CN2023 / 076142, entitled “THREE-DIMENSIONAL NON-VOLATILE MEMORY FLOORPLAN ARCHITECTURE,” filed on February 15, 2023, which claims the benefit of priority to U.S. Provisional Application No. 63 / 436,445, filed on December 30, 2022, both of which are incorporated by reference in their entireties herein.

[0002] This disclosure relates to the layout and arrangement of page buffers in three-dimensional (3D) non-volatile memories. [Background technology]

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become more difficult and costly. As a result, the memory density of planar memory cells approaches an upper limit.

[0004] 3D configurations of memory cells, in which the memory cells are stacked vertically relative to a substrate, have been developed for use in memory devices. Vertical stacking of memory cells has the desirable effect of allowing higher bit densities in memory arrays, but this applies primarily to the density of the memory array. Summary of the Invention [Means for solving the problem]

[0005] According to one aspect of the disclosure, a three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, the first semiconductor structure including a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, each memory plane having a plurality of bit lines oriented in a bit line direction on the first semiconductor structure, a memory plane boundary, and a fixed location, each page buffer circuit having a page buffer circuit boundary, the first semiconductor structure and the second semiconductor structure are bonded to each other in a face-to-face orientation, a projection of the first page buffer circuit boundary of the first page buffer circuit onto the 3D memory array overlaps a first portion of an area defined by the first memory plane boundary and overlaps a first portion of an area defined by the second memory plane boundary, and the first memory plane boundary and the second memory plane boundary are adjacent in a first direction. In some implementations, the first direction may be a bit line direction.

[0006] In some implementations of the 3D memory, a projection of a second page buffer circuit boundary of the second page buffer circuit onto the 3D memory array overlaps a second portion of the area defined by the first memory plane boundary.

[0007] In some implementations of the 3D memory, the projection of the second page buffer circuit boundary onto the 3D memory array is adjacent to the projection of the pad circuit onto the 3D memory array in the bit line direction.

[0008] In some implementations of the 3D memory, the first semiconductor structure further includes a pad circuit.

[0009] In some implementations, the 3D memory further includes a first bonding dielectric layer having a plurality of conductive first bonding contacts disposed above the 3D memory array of the first semiconductor structure, and a second bonding dielectric layer having a plurality of conductive second bonding contacts disposed above the plurality of page buffer circuits of the second semiconductor structure, wherein the first memory plane on the first semiconductor structure is electrically coupled to the first page buffer circuit on the second semiconductor structure through the at least one first bonding contact and the at least one second bonding contact.

[0010] In some implementations of the 3D memory, the at least one first bonding contact and the at least one second bonding contact each include copper.

[0011] In some implementations of the 3D memory, a first bit line of a first memory plane of a plurality of memory planes on a first semiconductor structure is electrically coupled to a first page buffer circuit on a second semiconductor structure through at least one first bonding contact and at least one second bonding contact.

[0012] In some implementations of a 3D memory, each memory plane comprises floating gate flash memory cells.

[0013] In some implementations of a 3D memory, each memory plane comprises charge trapping flash memory cells.

[0014] In some implementations, the 3D memory further includes a third page buffer circuit of the plurality of page buffer circuits, the third page buffer circuit having a third page buffer circuit boundary, and a fourth page buffer circuit of the plurality of page buffer circuits, the fourth page buffer circuit having a fourth page buffer circuit boundary, wherein an area defined by the third page buffer circuit boundary is completely overlaid by an area defined by the second memory plane boundary, wherein an area defined by the fourth page buffer circuit boundary is completely overlaid by an area defined by the second memory plane boundary, wherein the pad circuitry is disposed below the first memory plane, and wherein the pad circuitry is not disposed below the second memory plane.

[0015] According to another aspect of the disclosure, a method of making a 3D memory includes providing a first semiconductor structure having a 3D memory array, the 3D memory array including a plurality of memory planes, each memory plane having a plurality of bit lines arranged in a bit line direction; providing a second semiconductor structure having a plurality of page buffer circuits; and bonding the first semiconductor structure and the second semiconductor structure in a face-to-face orientation, wherein at least one page buffer circuit of the plurality of page buffer circuits is vertically aligned with a corresponding memory plane of the plurality of memory planes such that a projection of the at least one page buffer circuit of the plurality of page buffer circuits intersects a memory plane boundary of the corresponding memory plane of the plurality of memory planes in the bit line direction.

[0016] In some implementations, the method of making a 3D memory further includes forming one or more interconnect layers above the 3D memory array and forming a first bonding dielectric layer above the one or more interconnect layers having a plurality of conductive first bonding contacts, the one or more interconnect layers providing at least a portion of at least one conductive path between bitlines of the 3D memory array and the first bonding contacts of the first bonding dielectric layer.

[0017] In some implementations, the method of making a 3D memory further includes forming one or more interconnect layers above the plurality of page buffer circuits and forming a second bonding dielectric layer having a plurality of conductive second bonding contacts disposed above the one or more interconnect layers, the one or more interconnect layers providing at least a portion of at least one conductive path between the first page buffer circuit and the second bonding contacts of the second bonding dielectric layer.

[0018] In some implementations, the 3D memory array is a non-volatile memory array.

[0019] In some implementations, the 3D memory array is a flash memory array.

[0020] In some implementations, the method of making a 3D memory further includes disposing a first page buffer circuit at a location on the second semiconductor structure such that after bonding, the first page buffer circuit is aligned in a vertical direction with the first memory plane such that a first portion of the first page buffer circuit does not overlap the first memory plane in a bit line direction.

[0021] According to a further aspect of the present disclosure, a memory system includes a printed circuit board having an edge connector, a non-volatile memory controller device disposed on the printed circuit board, and a plurality of non-volatile memory devices disposed on the printed circuit board and coupled to the non-volatile memory controller device, at least one of the non-volatile memory devices including a first semiconductor structure having a 3D memory array, the 3D memory array including a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, each memory plane having a plurality of bit lines oriented in a bit line direction and having a memory plane boundary, each page buffer circuit having a page buffer circuit boundary, the first semiconductor structure and the second semiconductor structure being bonded to each other in a face-to-face orientation, the first memory plane boundary and the first page buffer circuit boundary being vertically aligned with each other such that the first page buffer circuit boundary is offset from the first memory plane boundary in the bit line direction and a first portion of the first page buffer circuit does not overlap an area defined by the first memory plane boundary.

[0022] In some implementations, a second portion of the first page buffer circuit boundary overlaps a portion of the area defined by the first memory plane boundary.

[0023] In some implementations, at least one of the non-volatile memory devices further includes a first bonding dielectric layer having a plurality of conductive first bonding contacts and a second bonding dielectric layer having a plurality of conductive second bonding contacts.

[0024] In some implementations, the conductive path between the at least one bit line and the at least one page buffer circuit includes a first of the first bonding contacts and a first of the second bonding contacts.

[0025] These exemplary implementations are mentioned not to limit or define the disclosure, but to provide examples and aid in understanding the disclosure. Additional implementations are discussed below in the Detailed Description of the Invention, where further description is provided.

[0026] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate implementations of the present invention and, together with the description, serve to further explain the principles of the disclosure and to enable those skilled in the art to make and use the implementations of the disclosure. [Brief description of the drawings]

[0027] [Figure 1A] FIG. 2 is a block diagram illustrating a first semiconductor structure and a second semiconductor structure before being bonded to form a 3D memory device. [Figure 1B] FIG. 2 is a block diagram illustrating a first semiconductor structure and a second semiconductor structure after being bonded face-to-face to form a 3D memory device. [Figure 1C] FIG. 2 is a block diagram illustrating a bonding layer of a first semiconductor structure and a bonding layer of a second semiconductor structure aligned to be bonded face-to-face to form a 3D memory device, but prior to bonding. [Figure 1D] FIG. 2 is a block diagram illustrating a bonding layer of a first semiconductor structure and a bonding layer of a second semiconductor structure after being bonded face-to-face to form a 3D memory device. [Figure 1E] FIG. 1 is a schematic diagram illustrating a portion of an exemplary memory cell array of a NAND architecture non-volatile memory device. [Figure 1F] FIG. 1 is a block diagram of an exemplary 3D memory device. [Diagram 2] FIG. 1 is a high-level block diagram of a semiconductor structure in which a 3D memory array is disposed, the 3D memory array including multiple memory planes in a general arrangement, before being bonded face-to-face to another semiconductor structure having page buffer circuitry. [Diagram 3]FIG. 1 is a high level block diagram illustrating placement of page buffer circuitry on a semiconductor structure prior to face-to-face bonding to another semiconductor structure having a 3D memory array disposed thereon. [Figure 4A] FIG. 1 is a high-level block diagram showing multiple memory planes in a general arrangement and the location of a page buffer circuit of one semiconductor structure relative to the memory planes of another semiconductor structure after the two semiconductor structures have been bonded face-to-face to one another. [Figure 4B] FIG. 1 illustrates a first configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a first block of pad circuits of the second semiconductor structure, with the first semiconductor structure and the second semiconductor structure bonded face-to-face to one another. [Figure 4C] A diagram showing a second configuration of four abutting memory planes of the first semiconductor structure, eight page buffer circuits of the second semiconductor structure, and a second block of pad circuits of the second semiconductor structure, with the first semiconductor structure and the second semiconductor structure bonded face-to-face to each other. [Figure 4D] FIG. 13 illustrates a third configuration of four abutting memory planes of the first semiconductor structure, eight page buffer circuits of the second semiconductor structure, and a second block of pad circuits of the second semiconductor structure, in which two of the page buffer circuits cross the memory plane boundary in the bit line direction and the first semiconductor structure and the second semiconductor structure are bonded face-to-face to one another. [Figure 4E] A diagram showing a fourth configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a first block of pad circuits of the second semiconductor structure, in which the first semiconductor structure and the second semiconductor structure are bonded face-to-face to each other. [Figure 4F] A diagram showing a fifth configuration of four abutting memory planes of the first semiconductor structure, eight page buffer circuits of the second semiconductor structure, and a second block of pad circuits of the second semiconductor structure, in which the first semiconductor structure and the second semiconductor structure are bonded face-to-face to each other. [Figure 4G]FIG. 13 illustrates a sixth configuration of four abutting memory planes of the first semiconductor structure, eight page buffer circuits of the second semiconductor structure, and a second block of pad circuits of the second semiconductor structure, in which two of the page buffer circuits cross the memory plane boundary in the bit line direction and the first semiconductor structure and the second semiconductor structure are bonded face-to-face to one another. [Figure 5A] 1 is a flow diagram of a method for making a 3D memory according to the present disclosure. [Figure 5B] 1 is a flow diagram of an alternative method for making a 3D memory according to the present disclosure. [Figure 6] FIG. 1 is a high level block diagram of a memory system according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present disclosure will be described with reference to the accompanying drawings.

[0029] To facilitate an understanding of the structure and fabrication methods of floorplan architectures for 3D non-volatile memories according to the present disclosure, various illustrative examples and implementations are presented herein.

[0030] It should be noted that references herein to "one implementation," "implementation," "exemplary implementation," "several implementations," and the like, indicate that a described implementation may include a particular feature, structure, or characteristic, but not all implementations will include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same implementation. Furthermore, when a particular feature, structure, or characteristic is described in connection with an implementation, it is within the knowledge of one of ordinary skill in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0031] Generally, terms may be understood, at least in part, from usage in context. For example, when the term "one or more" is used herein, it may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular use, or may be understood to convey a plural use, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of elements, but instead allows for the presence of additional elements not necessarily explicitly described, again depending at least in part on the context.

[0032] It should be readily understood that the meanings of "on," "above," and "covering" in this disclosure should be interpreted in the broadest sense, such that "on" not only means "directly on" something, but also includes the meaning "on" something with an intermediate or intervening layer, and "above" or "covering" not only means "on" or "covering" something, but also includes the meaning "on" or "covering" something without an intermediate or intervening layer (i.e., directly on top of something).

[0033] Additionally, spatially relative terms such as "below," "downward," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0034] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. Materials added onto the substrate may be patterned or left unpatterned. Additionally, substrates may include a wide array of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0035] As used herein, the term "layer" refers to a material portion that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer can be a region of a homogeneous or heterogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers, and / or can have one or more layers on the substrate, above the substrate, and / or below the substrate. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0036] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for a component or process operation, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may result from slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to the value of a given quantity that may vary based on a particular technology node associated with the semiconductor device. Based on a particular technology node, the term "about" may refer to, for example, a value of a given quantity that varies within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0037] As used herein, the term "3D memory device" refers to a semiconductor device having memory cells that may be arranged vertically on a laterally oriented substrate to allow for an increased number of memory cells in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral sides of the laterally oriented substrate.

[0038] As used herein, the abbreviation "CMOS" refers to complementary metal-oxide semiconductor. The "CMOS" process refers to a semiconductor manufacturing process that creates both n-channel and p-channel field effect transistors on the same substrate. A "CMOS circuit" refers to an electrical circuit that includes both n-channel and p-channel field effect transistors.

[0039] FIG. 1A is a block diagram illustrating a pair of semiconductor structures 100A including a first semiconductor structure 102 and a second semiconductor structure 114 before being bonded to form a 3D memory device. The first semiconductor structure 102 may be a die, and the second semiconductor structure 114 may be a die. The first semiconductor structure 102 includes a substrate 104, a memory array 106, an interconnect layer 108 disposed above the memory array 106, and a hybrid bonding layer 112 disposed above the interconnect layer 108. In some implementations, the substrate 104 may be, but is not limited to, a silicon substrate, and the memory array 106 may be, but is not limited to, a NAND flash memory array. In some implementations, the memory array 106 may be, but is not limited to, a 3D NAND flash memory array having a plurality of NAND strings oriented vertically relative to the substrate 104, and each of the vertically oriented NAND strings may include a plurality of non-volatile memory cells. The non-volatile memory cells may be, but are not limited to, charge trapping memory cells or floating gate memory cells. The interconnect layer 108 may include multiple levels of interconnect lines, each of which may be electrically connected to a vertically adjacent level by one or more vias. The hybrid bonding layer 112 may be a dielectric layer having a plurality of first bonding contacts disposed thereon. The second semiconductor structure 114 includes a substrate 116, a page buffer circuit 118, an interconnect layer 120 disposed above the page buffer circuit 118, and a hybrid bonding layer 122 disposed above the interconnect layer 120. In some implementations, the page buffer circuit 118 is a CMOS circuit. The interconnect layer 120 may include multiple levels of interconnect lines, each of which may be electrically connected to a vertically adjacent level by one or more vias. The hybrid bonding layer 112 may be a dielectric layer having a plurality of second bonding contacts disposed thereon. The first semiconductor structure 102 and the second semiconductor structure 114 are configured to be bonded face-to-face such that the hybrid bonding layer 122 and the hybrid bonding layer 112 are bonded to each other.

[0040] FIG. 1B is a block diagram illustrating the first semiconductor structure 102 and the second semiconductor structure 114 after being bonded face-to-face to form a 3D memory device 100B. In this bonding configuration, one or more first bonding contacts of the hybrid bonding layer 112 are in electrical contact with one or more corresponding second bonding contacts or hybrid bonding layers 122. It will be appreciated that the orientation of the memory device 100B shown in FIG. 1B with the first semiconductor structure 102 at the bottom and the second semiconductor structure 114 at the top is exemplary and not limiting. That is, the 3D memory device 100B may be oriented such that the second semiconductor structure 114 is at the bottom with the hybrid bonding layer 122 of the second semiconductor structure 114 provided as its top layer, and the first semiconductor structure 102 is at the top with the hybrid bonding layer 112 of the first semiconductor structure 102 provided as its bottom layer. In this alternative orientation, the memory array 106 is located on top of the 3D memory device 100B. In various manufacturing processes, after the first semiconductor structure 102 and the second semiconductor structure 114 are bonded, the substrate may be partially or completely removed from at least one of the semiconductor structures and the new semiconductor layer formed thereon. Details of the addition of the first and second bonding contacts are described below in connection with Figures 1C and 1D.

[0041] FIG. 1C illustrates a first semiconductor structure 102 with a more detailed representation of a hybrid bonding layer 112 and a second semiconductor structure 114 with a more detailed representation of a hybrid bonding layer 122, where the first semiconductor structure 102 and the second semiconductor structure 114 are aligned before being bonded so as to be bonded face to face to form a 3D memory device. As illustrated in FIG. 1C, the hybrid bonding layer 112 of the first semiconductor structure 102 has a plurality of first bonding contacts 124 disposed thereon. Also illustrated are interconnect lines from the interconnect layer 108. In this exemplary implementation, one or more of the first bonding contacts may be in electrical contact with the interconnect lines of the interconnect layer 108. The interconnect lines from the interconnect layer 108 form an electrical path from at least the memory array 106 of the first semiconductor structure 102 to the one or more first bonding contacts 124.

[0042] 1C , the hybrid bonding layer 122 of the second semiconductor structure 114 has a plurality of second bonding contacts 126 disposed thereon. The second semiconductor structure 114 further includes interconnect lines from the interconnect layer 120. In this exemplary implementation, the one or more bonding contacts may be in electrical contact with the interconnect lines of the interconnect layer 120. The interconnect lines from the interconnect layer 120 form an electrical path from at least the page buffer circuit 118 of the second semiconductor structure 114 to the one or more second bonding contacts 126.

[0043] 1D is similar to FIG. 1C but illustrates the hybrid bonding layer 112 of the first semiconductor structure 102 and the hybrid bonding layer 122 of the second semiconductor structure 114 after they have been bonded face-to-face to form a 3D memory device. As such, the first bonding contacts 124 may be in electrical contact with corresponding ones of the second bonding contacts 126. The electrical connection between the first bonding contacts 124 and the second bonding contacts 126 allows electrical signals to pass between the first semiconductor structure 102 and the second semiconductor structure 114.

[0044] FIG. 1E is a schematic diagram illustrating a portion of an exemplary memory cell array and peripheral circuitry of a NAND architecture non-volatile memory device 100E. The memory device 100E may include a memory cell array 130 and peripheral circuitry 132 coupled to the memory cell array 130. The memory cell array 130 may be a NAND flash memory cell array in which memory cells 136 are arranged in an array of NAND memory strings 138, each extending vertically above a substrate. In some implementations, each NAND memory string 138 includes a plurality of serially coupled and vertically stacked memory cells 136. As shown in FIG. 1E, the NAND memory strings 138 are coupled to a bit line 146 by a bit line select transistor 142. A gate terminal of the bit line select transistor 142 is coupled to a bit line select signal 143. The NAND memory strings 138 are coupled to a common source line 144 by a source select transistor 140. A gate terminal of the source select transistor 140 is coupled to a source select signal 145.

[0045] The NAND memory strings 138 may be arranged into multiple blocks 134, each of which may have a common source line 144. In some implementations, each block 134 is the basic data unit for erase operations, i.e., all memory cells 136 on the same block 134 are erased simultaneously. To erase memory cells 136 in a selected block 134, the source lines 144 coupled to the selected block 134 as well as to unselected blocks 134 in the same plane as the selected block 134 may be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or more). The memory cells 136 of adjacent NAND memory strings 138 may be coupled through word lines 148 that select which row of memory cells 136 is affected by read and program operations. In some implementations, each word line 148 is coupled to a page 150 of memory cells 136, the page 150 being the basic data unit for read and program operations. The size of one page 150 in bits can be related to the number of NAND memory strings 138 coupled by word lines 148 in one block 134 .

[0046] 1E , the memory cell array 130 may include an array of memory cells 136 in multiple rows and multiple columns in each block 134. According to some implementations, a row of memory cells 136 corresponds to one or more pages 150 and a column of memory cells corresponds to a NAND memory string 138. The multiple rows of memory cells 136 may be respectively coupled to word lines 148 and the multiple columns of memory cells 136 may be respectively coupled to bit lines 146. The peripheral circuits 132 may be coupled to the memory cell array 130 through the bit lines 146 and the word lines 148.

[0047] FIG. 1F is a block diagram of an exemplary 3D memory device 100F, showing a memory cell array 160, a page buffer 162, a column decoder / bit line driver 164, a row decoder / word line driver 166, a voltage generator 168, a control logic block 170, a register block 172, an interface 174, and a data bus 176.

[0048] The page buffer 162 may be configured to read data from the memory cell array 160 and program (write) data to the memory cell array 160 according to control signals from the control logic block 170. In one example, the page buffer 162 may store one or more pages of program data (write data) to be programmed into a target row of the memory cell array 160. In another example, the page buffer 162 may verify the programmed target memory cells of the memory cell array 130 in each program / verify loop (cycle) in a program operation to ensure that the data is properly programmed into the target memory cells of the memory cell array 160. In yet another example, the page buffer 162 may sense low-power signals from data lines representing data bits stored in memory cells of the memory cell array 160 and amplify the small voltage swing to a recognizable logic level in a read operation.

[0049] In a program operation, the page buffer 162 may include a storage module (e.g., a latch) for temporarily storing one of the N-bit data received from the data bus 176 (e.g., in the form of Gray code) and providing the one of the N-bit data through a corresponding bit line to a corresponding target memory cell of the memory cell array 160. In a read operation, the page buffer 162 may be configured to read one or more (M) bits of the one of the N-bit data.

[0050] The column decoder / bit line driver 164 may be configured to be controlled by the control logic block 170 and to select one or more NAND memory strings 138 by applying a bit line voltage generated from a voltage generator 168. The row decoder / word line driver 166 may be configured to be controlled by the control logic block 170 and the select / deselect block 134 of the memory cell array 130 and the select / deselect word lines 148 of the block 134. The row decoder / word line driver 166 may be further configured to drive the word lines 148 using the word line voltage generated from the voltage generator 168.

[0051] As part of the peripheral circuits 132, the control logic block 170 may be coupled to other peripheral circuits and configured to control the operation of the other peripheral circuits. The register block 172 may be coupled to include status registers, command registers, and address registers for storing status information, command operation codes, and command addresses to control the logic block 170 and control the operation of each peripheral circuit. The interface 174 may be coupled to the control logic block 170 and act as a control buffer to buffer and relay control commands received from the host to the control logic block 170 and buffer and relay status information received from the control logic block 170 to the host. The interface 174 may also be coupled to the column decoder / bit line driver 164 via a data bus 176 and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the memory cell array 160.

[0052] 2 is a high-level block diagram of an exemplary semiconductor structure 202 having a 3D memory array 204 disposed thereon before being bonded face-to-face to another semiconductor structure having a page buffer circuit. In this exemplary implementation, the 3D memory array 204 includes four memory planes 206-1, 206-2, 206-3, and 206-4, which are shown in a general configuration in which the memory planes do not abut. In this exemplary implementation, the memory planes 206-1, 206-2, 206-3, and 206-4 are each a 3D NAND flash memory plane having multiple vertically oriented NAND strings, each of which may include multiple non-volatile memory cells. The non-volatile memory cells of the memory planes 206-1, 206-2, 206-3, and 206-4 may be, but are not limited to, charge trapping memory cells or floating gate memory cells. In this exemplary implementation, each memory plane 206-1, 206-2, 206-3, and 206-4 has a corresponding memory plane boundary 207-1, 207-2, 207-3, and 207-4, as shown in FIG. 2. The NAND strings of memory plane 206-1 are disposed in an area defined by memory plane boundary 207-1. The NAND strings of memory plane 206-2 are disposed in an area defined by memory plane boundary 207-2. The NAND strings of memory plane 206-3 are disposed in an area defined by memory plane boundary 207-3. The NAND strings of memory plane 206-4 are disposed in an area defined by memory plane boundary 207-4.

[0053] 2, circuit block 208 represents additional circuitry that may be included on semiconductor structure 202 outside of 3D memory array 204. The additional circuitry of circuit block 208 may include, but is not limited to, interface logic, control logic, voltage generators, etc. It will be understood that for clarity, FIG. 2 does not show interconnect lines 108 disposed above 3D memory array 204 and circuit block 208, nor does it show hybrid bonding layer 112 disposed above interconnect layer 108.

[0054] 3 is a high-level block diagram illustrating the placement of page buffer circuits on an exemplary semiconductor structure 302 prior to face-to-face bonding to the semiconductor structure 202 (see FIG. 2). A first page buffer circuit 304A and a second page buffer circuit 304B are disposed on the semiconductor structure 302. The first page buffer circuit 304A has a first page buffer circuit boundary 305A, and the second page buffer circuit 304B has a second page buffer circuit boundary 305B. The circuitry of the first page buffer circuit 304A is disposed within an area defined by the first page buffer circuit boundary 305A. The circuitry of the second page buffer circuit 304B is disposed within an area defined by the second page buffer circuit boundary 305B. It will be understood that for purposes of clarity, FIG. 3 does not show the interconnect layer 120 disposed above the first page buffer circuit 304A and the second page buffer circuit 304B, and does not show the hybrid bonding layer 122 disposed above the interconnect layer 120.

[0055] 4A-4G illustrate the placement of memory planes, page buffer circuits, and pad circuits relative to one another, illustrating the advantages of the cross-plane page buffer circuit layout configuration of the 3D non-volatile memory floorplan architecture disclosed herein.

[0056] FIG. 4A is a high-level block diagram illustrating the position of the page buffer circuit 304A and the page buffer circuit 304B with respect to their respective vertical alignment with the memory planes 206-1 and 206-2 after the semiconductor structures 202 and 302 are bonded together in a face-to-face orientation. In this exemplary implementation, the memory planes have an overall configuration in which the memory planes are non-butting. It will be understood that for clarity, FIG. 4A does not show the interconnect layers 108, 120 and does not show the hybrid bonding layers 112, 122. In other words, although the interconnect layers 108, 120 and the hybrid bonding layers 112, 122 are physically disposed vertically between the memory planes 206-1, 206-2 and the page buffer circuits 304A, 304B, the intervening ones are not shown in FIG. 4 for the purpose of clarifying the position of the page buffer circuits with respect to the memory planes. FIG. 4A is essentially a flipped view of FIG. 3 placed on top of FIG. 2. 4A can thus show the location of the page buffer circuits 304A, 304B relative to the memory planes 206-1 and 206-2 after the semiconductor structures 202, 302 are bonded together in a facing orientation. In this example implementation, two page buffer circuits are shown in FIG. 4A, but this is not a limitation of the disclosure and there may be more or less page buffer circuits. In some implementations, there is at least one page buffer circuit for each memory plane in the memory cell array.

[0057] 4A, it can be seen that the first page buffer circuit 304A is aligned such that a first portion of the first page buffer circuit 304A overlaps a portion of the first memory plane 206-1 such that the union of the first page buffer circuit 304A and the first memory plane 206-1 defines a first region 412A-3. Further, a second portion of the first page buffer circuit 304A overlaps a region between the first memory plane 206-1 and the second memory plane 206-2 such that the union of the first memory plane 206-1 and the second memory plane 206-2 defines a second region 412A-2. Further, a third portion of the page buffer circuit 304A overlaps the portion of the second memory plane 206-2 such that the union of the third portion and a portion of the second memory plane 206-2 defines a third region 412A-1. In FIG. 4A, the first page buffer circuit 304A is offset in the y direction relative to the first memory plane 206-1. In this example implementation, the y direction is the bit line direction. In some implementations, the first region 412A-1 may be larger than the second region 412A-2. In some implementations, the first region 412A-1 may be larger than the third region 412A-3.

[0058] With further reference to the example implementation of FIG. 4A, it can be seen that the second page buffer circuit 304B is aligned with the 3D memory array 204 such that the second page buffer circuit 304B is completely overlaid by the first memory plane 206-1.

[0059] By arranging the first page buffer circuit 304A so that it is offset in the bit line direction to overlap the adjacent second memory plane 206-2 in the bit line direction, additional routing space is provided between the first and second page buffer circuits, which advantageously reduces routing congestion.

[0060] FIG. 4B illustrates a first exemplary configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a first block of pad circuits of the second semiconductor structure. The first and second semiconductor structures are bonded together in a face-to-face orientation. That is, memory plane 1, memory plane 2, memory plane 3, and memory plane 4 are disposed on the first semiconductor structure, and the eight page buffer circuits, along with a first block of pad circuits, are disposed on the second semiconductor structure. FIG. 4B illustrates the relative spatial arrangement of the memory planes, page buffer circuits, and pad circuits after the first and second semiconductor structures are bonded face-to-face. The positions of the page buffer circuits and pad circuits are illustrated in these figures by projecting the page buffer circuits and pad circuits onto a 3D memory array (which itself includes four memory planes on the first semiconductor structure). In this first configuration, the projections of the page buffer circuits are located at the bottom left and top right of memory plane 1, the top left and bottom right of memory plane 2, the top left and bottom right of memory plane 3, and the bottom left and top right of memory plane 4.

[0061] As shown in FIG. 4B, memory plane 1 of the first semiconductor structure has two page buffer circuits PB associated with it, memory plane 2 has two page buffer circuits PB associated with it, and memory plane 4 has two page buffer circuits PB associated with it. Each page buffer circuit is positioned such that its projection is located within the memory plane boundary of the memory plane associated with it, i.e., memory plane 1, memory plane 2, memory plane 3, or memory plane 4. Because each page buffer circuit is coupled to the bit lines of its associated memory plane, positioning the page buffer circuits such that their projection is located within the memory plane boundary is useful in shortening the length of the connection path between the page buffer circuits of the second semiconductor structure and the memory plane bit lines of the first semiconductor structure. Also shown in FIG. 4B is a first block of pads circuitry, positioned such that its projection is located outside the memory plane boundary of any of memory plane 1, memory plane 2, memory plane 3, and memory plane 4. In the example of Figure 4B, a first block of pads circuitry is positioned such that its projection is adjacent to memory plane 2 and memory plane 4. However, this first configuration does not provide an optimal layout size for the second semiconductor structure. A configuration that provides an improved layout size for the second semiconductor structure is shown in Figure 4C.

[0062] 4C illustrates a second exemplary configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a second block of pad circuits of the second semiconductor structure, the first semiconductor structure and the second semiconductor structure being bonded to one another in a face-to-face orientation.

[0063] The second configuration of FIG. 4C is similar in some respects to the first configuration of FIG. 4B. The memory plane 1 of the first semiconductor structure has two page buffer circuits PB associated with it, the memory plane 2 has two page buffer circuits PB associated with it, the memory plane 3 has two page buffer circuits PB associated with it, and the memory plane 4 has two page buffer circuits PB associated with it. Each page buffer circuit is arranged such that its projection lies within the memory plane boundary of the memory plane associated with it, i.e., memory plane 1, memory plane 2, memory plane 3, or memory plane 4. Because each page buffer circuit is coupled to the bit lines of its associated memory plane, arranging the page buffer circuits such that their projection onto the 3D memory array lies within the memory plane boundary is useful in reducing the length of the connection paths between the page buffer circuits and the memory plane bit lines.

[0064] However, the second configuration of FIG. 4C differs from the configuration of FIG. 4B in several ways. In particular, it can be seen that the first block of pad circuitry shown in FIG. 4B has been removed and replaced with a second block of pad circuitry that is positioned to be located inside the memory plane boundary of memory plane 2 and memory plane 4. Furthermore, in FIG. 4C, one of the page buffer circuits projected onto each of memory planes 2 and 4, i.e., two page buffer circuits in total in this example, is shifted in the y-direction (bit line direction) to provide space for locating the projection of the pad circuitry inside the memory plane boundary of memory planes 2 and 4. However, in this second configuration, the distance 422 between the first and second page buffer circuits is less than the distance 420 in the first configuration of FIG. 4B. Since the space between the first and second page buffer circuits is smaller compared to the first configuration, there is less space to route signals. The space available for circuitry and / or interconnects is shown as dashed box E′. A configuration that provides both an improved layout size for the second semiconductor structure and additional routing space between the first and second page buffer circuits is shown in FIG. 4D.

[0065] FIG. 4D illustrates a third exemplary configuration of four abutting memory planes of the first semiconductor structure, eight page buffer circuits of the second semiconductor structure, and a second block of pad circuits of the second semiconductor structure. Each of the two page buffer circuits crosses a corresponding memory plane boundary in the bit line direction, and the first and second semiconductor structures are joined to each other in a face-to-face orientation. The third configuration of FIG. 4D differs from the second configuration of FIG. 4C in several respects. In particular, the projection of the first page buffer circuit boundary is shifted in the y direction, i.e., in the bit line direction, compared to the first page buffer circuit boundary shown in FIG. 4C. The shifting of the relative positions of the aforementioned projections corresponds to a shift in the actual placement of the first page buffer circuit on the second semiconductor structure. Thus, the distance 424 is longer compared to the distance 422, thereby increasing the routing space between the first and second page buffer circuits. Additionally, the space available for circuitry and / or interconnects (shown as dashed box E) is increased compared to the configuration of FIG. 4C.

[0066] 4E-4G are similar to FIGS. 4B-4D, but show alternative arrangements of page buffers relative to the memory planes.

[0067] FIG. 4E illustrates a fourth exemplary configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a first block of pad circuits of the second semiconductor structure. The first and second semiconductor structures are bonded to each other in a face-to-face orientation. In this fourth configuration, the location of the page buffer circuits and the pad circuits are shown by their projections onto a 3D memory array (which itself includes four memory planes on the first semiconductor structure). In this fourth configuration, the projections of the page buffer circuits are located at the top left and bottom right of memory plane 1, the bottom left and top right of memory plane 2, the bottom left and top right of memory plane 3, and the top left and bottom right of memory plane 4. A distance 440 is shown between the projections of the page buffer circuits on memory plane 2. The projections of the pad circuits are located outside the memory plane boundaries. This fourth configuration does not provide an optimal layout size for the second semiconductor structure. A configuration that provides an improved layout size for the second semiconductor is shown in FIG. 4F.

[0068] FIG. 4F illustrates a fifth exemplary configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a second block of pad circuits of the second semiconductor structure. The first and second semiconductor structures are bonded to each other in a face-to-face orientation. It can be seen that the first block of pad circuits illustrated in FIG. 4E has been removed and replaced with a second block of pad circuits arranged such that its projection onto the 3D memory array lies inside the memory plane boundaries of memory plane 2 and memory plane 4. However, moving the pad circuits in this way indicates that the space available for circuitry and / or interconnections between the second block of pad circuits and the page buffer circuits corresponding to the projections at the top right of memory plane 2 and the top left of memory plane 4 (illustrated as dashed box D′) is now reduced compared to the fourth configuration of FIG. 4E. A configuration that provides both an improved layout size for the second semiconductor structure and additional space for circuitry and / or interconnections between the various page buffer circuits and pad circuits is illustrated in FIG. 4G.

[0069] FIG. 4G illustrates a sixth exemplary configuration of four abutting memory planes of a first semiconductor structure, eight page buffer circuits of a second semiconductor structure, and a second block of pad circuits of the second semiconductor structure. Two of the page buffer circuits cross the memory plane boundary in the bit line direction, and the first and second semiconductor structures are joined to each other in a face-to-face orientation. The configuration of FIG. 4G differs from the configuration of FIG. 4F at least in that the projection of the page buffer circuits at the top right of memory plane 2 has been moved beyond the memory plane boundary of memory plane 2 in the bit line direction, and the projection of the page buffer circuits at the top left of memory plane 4 has been moved beyond the memory plane boundary of memory plane 4 in the bit line direction. In this way, the space available for circuits and / or interconnections between the second block of pad circuits and the page buffer circuits corresponding to the projections at the top right of memory plane 2 and the top left of memory plane 4 (shown as dashed box D) is advantageously increased compared to the fourth configuration of FIG. 4E.

[0070] FIG. 5A is a flow diagram of an exemplary method 500A of making a 3D memory according to the present disclosure. The method 500A includes providing a first die having a first substrate and a 3D memory array disposed on the first substrate, the 3D memory array including a plurality of memory planes, and forming a first bonding dielectric layer, e.g., a hybrid bonding dielectric layer, above the 3D memory array, having a plurality of conductive first bonding contacts disposed thereon, in step 504. In some implementations, one or more interconnect layers may be disposed above the 3D memory array and below the first bonding dielectric layer. In some implementations, the first bonding contacts include copper. In some implementations, the first substrate may be, but is not limited to, a silicon substrate. The 3D memory array may be, but is not limited to, a NAND flash memory having vertically oriented NAND strings. The vertically oriented NAND strings may include flash memory cells, such as, for example, charge trapping memory cells or floating gate memory cells.

[0071] The method 500A further includes providing 506 a second die having a second substrate and a plurality of page buffer circuits disposed on the second substrate, and forming 508 a second bonding dielectric layer having a plurality of conductive second bonding contacts disposed above the page buffer circuits of the second die. In some implementations, the page buffer circuits are CMOS circuits. In some implementations, the second substrate may be, but is not limited to, a silicon substrate. In some implementations, the second bonding contacts include copper. In some implementations, one or more interconnect layers may be disposed above the page buffer circuits and below the second bonding dielectric layer. The method 500A further includes step 510 of bonding the first die and the second die such that the first and second bonding dielectric layers are bonded to each other in a facing orientation, and at least one page buffer of the plurality of page buffers on the second die is vertically aligned with a corresponding memory plane of the plurality of memory planes on the first die such that a projection of a page buffer circuit of the at least one page buffer of the plurality of page buffers on the second die intersects a memory plane boundary of the corresponding memory plane of the plurality of memory planes on the first die. In some implementations, the at least one page buffer intersects the memory plane boundary in the bit line direction. In some implementations, the bonding of the first die and the second die is hybrid bonding. In some implementations, after bonding, a first one of the first bonding contacts is in electrical contact with a first one of the second bonding contacts.

[0072] 5B is a flow diagram of an exemplary method 500B of making a 3D memory according to the present disclosure. The method 500B includes providing 522 a first semiconductor structure having a 3D memory array, the 3D memory array including a plurality of memory planes, each memory plane having a plurality of bit lines arranged in a bit line direction, and providing 524 a second semiconductor structure having a plurality of page buffer circuits. In some implementations, the 3D memory array may be, but is not limited to, a NAND flash memory having vertically oriented NAND strings, the vertically oriented NAND strings may include flash memory cells, such as, for example, charge trapping memory cells or floating gate memory cells. In some implementations, the first semiconductor structure includes a first substrate, which may be, but is not limited to, a silicon substrate. In some implementations, the page buffer circuit is a CMOS circuit, and the second semiconductor structure includes a substrate. The method 500B further includes a step 526 of bonding the first and second semiconductor structures face-to-face, where at least one page buffer circuit of the plurality of page buffer circuits is vertically aligned with a corresponding memory plane of the plurality of memory planes such that a projection of the at least one page buffer circuit of the plurality of page buffer circuits intersects a memory plane boundary of the corresponding memory plane of the plurality of memory planes in a bit line direction. In some implementations, bonding the first and second semiconductor structures may be accomplished by hybrid bonding.

[0073] FIG. 6 is a high-level block diagram of a memory system 600 according to the present disclosure. Various components of the memory system 600 may be assembled in a housing 602. The various components of the memory system 600 may include one or more non-volatile memories, such as, but not limited to, a flash memory 604, a controller, such as, but not limited to, a flash memory controller 606, and a control logic and host interface block 608. It will be appreciated that the control logic and host interface block 608 may alternatively be partitioned into two or more blocks of circuitry. It will be further appreciated that the memory system 600 may include multiple discrete electrical components, such as, but not limited to, resistors, capacitors, and diodes. By way of example, but not limited to, resistors may be included to provide termination resistance for impedance matching on high speed lines. The memory system 600 may be a universal flash storage (UFS) device, a solid state drive (SSD), or a similar non-volatile storage product. That is, the memory system 600 may be implemented and packaged as different types of electronic products.

[0074] With further reference to FIG. 6 , the flash memory 604 may be, but is not limited to, a 3D NAND flash memory including a plurality of flash memory cells. The flash memory cells may be, for example, charge trapping memory cells or floating gate memory cells. The flash memory 604 is coupled to a flash memory controller 606. The memory controller 606 may be configured to control operations of the flash memory 604, such as read, erase, and program operations. The memory controller 606 may be configured to manage various functions related to data stored in or to be stored in the flash memory 604, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 606 is further configured to process error correction codes (ECCs) related to data read from or written to the flash memory 604. Other suitable functions may be performed by the memory controller 606, such as, for example, formatting the flash memory 604. The memory controller 606 in combination with the control logic and host interface block 608 can communicate with external devices according to a particular communication protocol. For example, the memory controller 606 in combination with the control logic and host interface block 608 may communicate with external devices through at least one of a variety of interface protocols, such as, but not limited to, a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA (SATA) protocol, a Parallel ATA (PATA) protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0075] The above description of specific implementations reveals the general nature of the disclosure, so that those skilled in the art can easily modify and / or adapt various applications of such specific implementations by applying knowledge within the art without undue experimentation and without departing from the general concept of the disclosure. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It should be understood that the words and terms used herein are for purposes of description and not limitation, and that the words or terms used herein should be interpreted by those skilled in the art in light of the teaching and guidance provided above.

[0076] The implementation of the present disclosure has been described above using functional building blocks illustrating implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and relationships thereof are appropriately implemented.

[0077] The "Summary" and "Abstract" describe one or more implementations of the present disclosure rather than all implementations contemplated by the inventors and are therefore not intended to limit the scope of the disclosure and the appended claims.

[0078] The scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0079] While specific configurations have been described, it should be understood that this is done for illustrative purposes only. Thus, other configurations may be used without departing from the scope of the present disclosure. Also, the subject matter described in this disclosure may be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, modified, and rearranged with one another in a manner consistent with the scope of the present disclosure. [Explanation of symbols]

[0080] 100A Semiconductor structure 100B 3D Memory Device 100E Non-volatile Memory Device 100F 3D Memory Device 102 First semiconductor structure 104 Substrate 106 Memory Array 108 Interconnection Layer 112 Hybrid Bonding Layer 114 Second Semiconductor Structure 116 Board 118 Page Buffer Circuit 120 Interconnect Layer 122 Hybrid Bonding Layer 124 First Bonding Contact 126 Second Bonding Contact 130 Memory Cell Array 132 Peripheral Circuits 134 Blocks 136 memory cells 138 NAND memory strings 140 Source select transistor 142 Bit line select transistor 143 Bit line selection signal 144 Common Source Line 145 Source Selection Signal 146 bit lines 148 word lines 150 pages 160 Memory Cell Array 162 page buffer 164 Column Decoder / Bit Line Driver 166 Row Decoder / Word Line Driver 168 Voltage Generator 170 Control Logic Block 172 Register Block 174 Interface 176 Data Bus 202 Semiconductor Structure 204 3D Memory Array 206-1, 206-2, 206-3, 206-4 Memory Planes 207-1, 207-2, 207-3, 207-4 Memory plane boundaries 208 Circuit Block 302 Semiconductor Structure 304A First page buffer circuit 304B Second page buffer circuit 305A First page buffer circuit boundary 305B Second page buffer circuit boundary 412A-1 The third area 412A-2 Second Area 412A-3 First Area 420 distance 422 distance 424 distance 440 distance 500A method 600 Memory System 602 Housing 604 Flash Memory 606 Flash Memory Controller 608 Control Logic and Host Interface Block

Claims

1. 1. A three-dimensional (3D) memory, comprising: a first semiconductor structure having a 3D memory array, the 3D memory array including a plurality of memory planes; a second semiconductor structure having a plurality of page buffer circuits; Each memory plane has a plurality of bit lines oriented in a bit line direction on the first semiconductor structure, a memory plane boundary, and a fixed location; Each page buffer circuit has a page buffer circuit boundary; the first semiconductor structure and the second semiconductor structure are bonded to one another in a face-to-face orientation; a projection of a first page buffer circuit boundary of a first page buffer circuit onto the 3D memory array overlaps a first portion of an area defined by a first memory plane boundary and overlaps a first portion of an area defined by a second memory plane boundary, the first memory plane boundary and the second memory plane boundary being adjacent in a first direction.

2. 2. The 3D memory of claim 1, wherein a projection of a second page buffer circuit boundary of a second page buffer circuit onto the 3D memory array overlaps a second portion of the area defined by the first memory plane boundary, and the first direction is the bit line direction.

3. 3. The 3D memory of claim 2, wherein the projection of the second page buffer circuit boundary onto the 3D memory array is adjacent in the bit line direction to a projection of a pad circuit onto the 3D memory array.

4. The 3D memory of claim 3 , wherein the second semiconductor structure further comprises a pad circuit.

5. a first bonding dielectric layer having a plurality of conductive first bonding contacts disposed over the 3D memory array of the first semiconductor structure; a second bonding dielectric layer having a plurality of conductive second bonding contacts disposed over the plurality of page buffer circuits of the second semiconductor structure; 4. The 3D memory of claim 3, wherein a first memory plane of the plurality of memory planes on the first semiconductor structure is electrically coupled to a first page buffer circuit on the second semiconductor structure through at least one first bonding contact and at least one second bonding contact.

6. 6. The 3D memory of claim 5, wherein the at least one first bonding contact and the at least one second bonding contact each comprise copper.

7. 6. The 3D memory of claim 5, wherein a first bit line of the first memory plane of the plurality of memory planes on the first semiconductor structure is electrically coupled to a first page buffer circuit on the second semiconductor structure through at least one of the plurality of conductive first bonding contacts and at least one of the plurality of conductive second bonding contacts.

8. The 3D memory of claim 3 , wherein each memory plane comprises floating gate flash memory cells.

9. The 3D memory of claim 3 , wherein each memory plane comprises charge trapping flash memory cells.

10. a third page buffer circuit of the plurality of page buffer circuits, the third page buffer circuit having a third page buffer circuit boundary; a fourth page buffer circuit of the plurality of page buffer circuits, the fourth page buffer circuit having a fourth page buffer circuit boundary; 4. The 3D memory of claim 3, wherein an area defined by the third page buffer circuit boundary is completely overlapped by an area defined by the second memory plane boundary, and an area defined by the fourth page buffer circuit boundary is completely overlapped by the area defined by the second memory plane boundary.

11. 1. A method of making a three-dimensional (3D) memory, comprising: providing a first semiconductor structure having a 3D memory array, the 3D memory array including a plurality of memory planes, each memory plane having a plurality of bit lines arranged in a bit line direction; providing a second semiconductor structure having a plurality of page buffer circuits; and bonding the first semiconductor structure and the second semiconductor structure in a face-to-face orientation, wherein the at least one page buffer circuit of the plurality of page buffer circuits is vertically aligned with a corresponding memory plane of the plurality of memory planes such that a projection of the at least one page buffer circuit of the plurality of page buffer circuits intersects a memory plane boundary of the corresponding memory plane of the plurality of memory planes in the bit line direction.

12. forming one or more interconnect layers above the 3D memory array; forming a first bonding dielectric layer over the one or more interconnect layers, the first bonding dielectric layer having a plurality of conductive first bonding contacts; 12. The method of claim 11, wherein the one or more interconnect layers provide at least a portion of at least one conductive path between a bitline of the 3D memory array and a first bonding contact of the first bonding dielectric layer.

13. forming one or more interconnect layers above the plurality of page buffer circuits; forming a second bonding dielectric layer having a plurality of conductive second bonding contacts disposed above the one or more interconnect layers; 12. The method of claim 11, wherein the one or more interconnect layers provide at least a portion of at least one conductive path between a first page buffer circuit and a second bonding contact of the second bonding dielectric layer.

14. The method of claim 11 , wherein the 3D memory array is a non-volatile memory array.

15. The method of claim 11 , wherein the 3D memory array is a flash memory array.

16. 12. The method of claim 11, further comprising: disposing the first page buffer circuit at a location on a second semiconductor structure such that after bonding, the first page buffer circuit is vertically aligned with a first memory plane such that a first portion of the first page buffer circuit does not overlap the first memory plane in a bit line direction.

17. 1. A memory system comprising: A memory controller device; a plurality of non-volatile memory devices coupled to the memory controller device; At least one of the non-volatile memory devices a first semiconductor structure having a three dimensional (3D) memory array, the 3D memory array including a plurality of memory planes; a second semiconductor structure having a plurality of page buffer circuits; Each memory plane has a plurality of bit lines oriented in a bit line direction and has a memory plane boundary; Each page buffer circuit has a page buffer circuit boundary; the first semiconductor structure and the second semiconductor structure are bonded to one another in a face-to-face orientation; a first memory plane boundary and a first page buffer circuit boundary are vertically aligned with one another such that the first page buffer circuit boundary is offset from the first memory plane boundary in the bit line direction and such that a first portion of the first page buffer circuit boundary does not overlap an area defined by the first memory plane boundary.

18. 20. The memory system of claim 17, wherein a second portion of the first page buffer circuitry boundary overlaps a portion of the area defined by the first memory plane boundary.

19. At least one of the non-volatile memory devices a first bonding dielectric layer having a plurality of conductive first bonding contacts; 20. The memory system of claim 18 further comprising: a second bonding dielectric layer having a plurality of conductive second bonding contacts.

20. 20. The memory system of claim 19, wherein a conductive path between at least one bit line and at least one page buffer circuit includes a first one of the plurality of conductive first bonding contacts and a first one of the plurality of conductive second bonding contacts.

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