Multi-layer coating for corrosion resistance
Patent Information
- Application Number
- JP2024552758
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-03-10
- Filing Date
- 2023-03-09
- Publication Date
- 2025-03-13
Smart Images
Figure 2025507056000001_ABST
Abstract
Description
[Background technology]
[0001]
[0001] The present technology relates to processes and systems for coating components. More particularly, the present technology relates to systems and methods for coating substrates with multi-layer corrosion resistant coatings. [Technical field]
[0002]
[0002] Semiconductor processing systems may include multiple components used to support substrates, deliver forming and removing materials, and define processing regions and flow paths. These components are exposed to high and low temperatures, high and low pressures, and a variety of corrosive and erosive materials. Thus, multiple processing chambers contain the materials being processed or coated. However, as processing systems and chambers become more complex, the components incorporated within the system may become multi-component devices that may include complex geometries and features throughout the components. Such features may in turn be exposed to environmental conditions and materials that may cause damage to the components.
[0003]
[0003] Thus, there is a need for improved systems and components that can be used to produce high quality devices and structures. This need, and others, are addressed by the present technique. Summary of the Invention
[0004]
[0004] An embodiment of the present technology includes a coating method including forming a bond layer on a metal substrate, the bond layer including an oxide of a metal in the metal substrate. The coating method further includes depositing a stress buffer layer on the bond layer, the stress buffer layer being characterized by a coefficient of thermal expansion (CTE) of the stress buffer layer being less than the CTE of the metal substrate and the CTE of the bond layer. The coating method also includes depositing an environmental barrier layer on the stress buffer layer, the ratio of the CTE of the metal substrate to the CTE of the environmental barrier layer being greater than or about 20:1, and the environmental barrier layer including silicon oxide.
[0005] In an embodiment, the CTE of the metal substrate is 10×10 -6 / °C or greater than about 10 x 10 -6 In a further embodiment, the CTE of the environmental barrier layer is 0.5×10 -6 / °C or less than about 0.5×10 -6 / °C. In yet a further embodiment, the metal substrate comprises stainless steel and the oxide of the metal in the bonding layer comprises chromium oxide. In an additional embodiment, the bonding layer is formed on the metal substrate by thermal oxidation of the metal in the metal substrate. In yet an additional embodiment, the bonding layer further comprises exposing the metal substrate to an atmospheric atmosphere comprising ozone. In a further embodiment, the stress buffer layer comprises aluminum oxide. In yet a further embodiment, the stress buffer layer and the environmental layer are deposited by atomic layer deposition.
[0006]
[0006] Additional embodiments of the present technology include a method of forming a multi-layer coating on a metal substrate. The method includes forming a bond layer on the metal substrate, the bond layer characterized by a thickness less than or about 10 nm. The method also includes depositing a stress buffer layer on the bond layer, the stress buffer layer characterized by a thickness less than or about 50 nm. The method also includes depositing an environmental barrier layer on the stress buffer layer, the environmental barrier layer characterized by a thickness greater than or about 50 nm. The multi-layer coating increases the corrosion resistance of the metal substrate to at least one halogen.
[0007] In an embodiment, the metal substrate comprises stainless steel and the bonding layer comprises chromium oxide. In a further embodiment, the stress buffer layer comprises aluminum oxide and is characterized by a CTE greater than the CTE of the environmental barrier layer and less than the CTE of the metal substrate. In yet a further embodiment, the environmental barrier layer comprises silicon dioxide and the multi-layer coating increases the corrosion resistance of the metal substrate to chlorine. In an additional embodiment, the environmental barrier layer comprises hafnium oxide and the multi-layer coating increases the corrosion resistance of the metal substrate to halogen-containing compounds. In a further embodiment, the metal substrate is incorporated into a component of a semiconductor manufacturing device that is exposed to at least one halogen.
[0008]
[0008] A further embodiment of the present technology includes a coated metal structure comprising a metal substrate. The coated metal structure further includes a multi-layer coating including a bond layer positioned on the metal substrate, the bond layer including an oxide of the metal in the metal substrate. The multi-layer coating also includes a stress buffer layer positioned on the bond layer and an environmental barrier layer positioned on the stress buffer layer. The stress buffer layer is characterized by a CTE that is greater than the CTE of the environmental barrier layer and less than the CTE of the metal substrate.
[0009] In an embodiment, the metal substrate comprises stainless steel and the bond layer comprises chromium oxide. In a further embodiment, the environmental barrier layer comprises silicon dioxide. In yet a further embodiment, the ratio of the CTE of the metal substrate to the CTE of the environmental barrier layer is greater than or about 20:1. In an additional embodiment, the bond layer is characterized by a thickness of about 10 nm or less and the environmental barrier layer is characterized by a thickness of about 50 nm or more.
[0010]
[0010] The present technology offers numerous advantages over conventional corrosion resistant coatings for metal parts exposed to highly corrosive environments. Embodiments of the present technology form corrosion resistant coatings that can withstand both highly corrosive halogen-containing atmospheric atmospheres and large changes in temperature without significant corrosive etching or stress breakdown. In embodiments, the multi-layer corrosion resistant coating includes a stress buffer layer that reduces the stress caused by a metal substrate with a large CTE on a ceramic oxide with a small CTE. This reduces stress breakdown in the corrosion resistant ceramic oxide layer due to temperature cycling with large temperature changes. Corrosion resistant ceramic oxides such as silicon dioxide can withstand corrosion from aggressive chlorine-containing species over many temperature cycles in, for example, semiconductor manufacturing equipment. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the following description and accompanying drawings.
[0011] A further understanding of the nature and advantages of the disclosed techniques may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]
[0012] [Figure 1] 1 illustrates selected steps of a method for forming a component, according to some embodiments of the present technique. [Diagram 2]
[0013] 1 is a schematic cross-sectional view of a portion of a component coated with a multi-layer corrosion resistant coating in accordance with an embodiment of the present invention. [Diagram 3]
[0014] 4 is a schematic cross-sectional view of a portion of a component coated with a multi-layer corrosion resistant coating in accordance with an additional embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0013]
[0015] Some of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and are not to be considered to scale unless specifically stated to scale. Additionally, as schematic diagrams, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated content for illustrative purposes.
[0014]
[0016] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.
[0015] Detailed Description
[0017] Semiconductor processing involves the creation of intricately patterned materials on substrates. The processes include remote and in situ formation and removal processes utilizing corrosive materials, including hot gas and ionized plasmas of halogen-containing compounds, radicals, and ions. For example, etching processes often involve contacting substrates with halogen-containing liquid, gas, or plasma etchants that flow into the processing area of processing equipment. The halogen-containing etchants are intended to etch wafers and other device substrates, but also react with the walls of the processing chamber and other equipment components, resulting in corrosion of the equipment. When equipment components are made of metals such as stainless steel, the halogen-containing materials can react quickly, causing wear on the equipment and being a source of contaminants. Over time, corrosion increases downtime of processing equipment as well as increasing repair and replacement costs for the equipment.
[0016]
[0018] The deposition process may also use plasma enhanced processes or rapid thermal processing to form or deposit materials on the substrate, which may also be deposited on the chamber components. This may require a cleaning step after the substrate is removed from the chamber. The cleaning process may include utilizing one or more halogen-containing precursors or plasma effluents of these precursors to remove materials deposited on the surfaces in the processing chamber. While the cleaning targets the deposited materials, the surfaces of many chamber components that are exposed may be attacked as well. For example, once the substrate is removed from the processing chamber, the central region of the substrate support is no longer exposed to residual deposition materials. When the cleaning process begins, pits may form or other removal may occur in the substrate support, which may reduce the planarity and integrity of the chuck. Many of these chamber components include multiple components bonded together to create channels, flow paths, or sealed regions within the components. Individual pieces or combined device components within the chamber may feature any number of internal features, including channels, apertures, and various other topographies.
[0017]
[0019] The prior art continues to strive to limit both corrosion and erosion to chamber components, and tends to replace components periodically due to damage caused by one or both of these mechanisms. Some processes may include a seasoning process prior to processing of semiconductor substrates, which can create additional difficulties. For example, the seasoning process may be performed on multiple portions of the substrate support, but may not be performed completely on the backside or stem, and thus components of the substrate support, such as the base plate or stem, may still be exposed to processing and cleaning materials. In addition, the seasoning process typically deposits a coating of 100 nanometers or less. This may require seasoning replacement for each substrate being processed, which can increase waiting times and reduce the likelihood of uniform or complete coverage. The prior art has attempted to protect many of these components with coatings that are less reactive to corrosive materials and / or more resistant to plasma bombardment.
[0018]
[0020] One conventional technique for improving corrosion resistance is to coat components with silicon oxide. Metal components coated with silicon oxide have significantly increased resistance to corrosion in chlorine-containing processing environments. Silicon dioxide is significantly less reactive with chlorine-containing compounds, ions, and radicals than the metal in the component. Unfortunately, silicon dioxide has a significantly lower coefficient of thermal expansion than the metal in the component. When the component is exposed to large changes in temperature during the manufacturing process, the metal expands and contracts more than the silicon dioxide coating. The mechanical stress caused by the different coefficients of thermal expansion of the two materials can cause stress fractures in the silicon dioxide coating. Another problem is that stress fractures can open a path for chlorine-containing gases and plasmas to reach and corrode the underlying metal in the component. In some cases, the mechanical stresses caused by thermal cycling can separate the silicon dioxide coating from the component, leaving gaps that trap corrosive chlorine-containing materials against the metal surface of the component. Another challenge that adds to the complexity of applying silicon dioxide coatings to metal substrates is the poor adhesion of metal oxide coatings to metal substrates, due in part to the low surface energy of the silicon dioxide coating layer that leads to delamination of the coating layer when the component is in use.
[0019]
[0021] Embodiments of the present technology address these and other problems with a coating chamber component having a multi-layer corrosion resistant coating that reduces the mechanical stress felt by the external environmental barrier layer during thermal cycling. In an embodiment, the multi-layer coating includes a stress buffer layer formed between the outer environmental barrier layer and a bond layer that is in direct contact with the metal surface of the component. In an additional embodiment, the bond layer is a self-structured layer between the metal substrate and the stress buffer layer that includes a coating stack foundation that increases the adhesion of the metal substrate to the outermost surface of the bond layer. In yet a further embodiment, the stress buffer layer is characterized by a coefficient of thermal expansion between the CTE of the environmental layer and the CTE of the metal in the component. When a component coated with the present multi-layer coating undergoes large temperature changes, the buffer layer reduces the mechanical stress felt by the environmental barrier layer from large changes in the volume of the metal in the component. The reduced mechanical stress felt by the environmental barrier layer during thermal cycling reduces stress fractures in the barrier layer. In addition, residual in-plane residual stresses do not cause the stress buffer layer and the environmental barrier layer to separate from the metal substrate due to the presence of the bond layer. This enables the environmental barrier layer to maintain an impenetrable barrier for corrosive gases and plasmas present in the processing environment during the manufacturing process. Metal components coated with the present multi-layer corrosion resistant coatings can have a significantly longer useful life with less maintenance than components coated with conventional corrosion resistant coatings.
[0020]
[0022] The following disclosure identifies specific materials, components, and coating methods according to embodiments of the present technology. It is readily understood that the described methods, materials, components, and systems are applicable to various other methods, materials, components, and systems used for the manufacture of semiconductor devices, as well as the manufacture of other types of devices in which components within a manufacturing system or apparatus are protected by a corrosion-resistant coating. Thus, the present technology is not limited to the described coating methods, materials, components, and systems. The present disclosure describes non-limiting steps of exemplary coating methods and typical components that may be coated according to embodiments of the present technology.
[0021]
[0023] FIG. 1 illustrates selected steps of a method 100 of coating a semiconductor component substrate according to an embodiment of the present technology. Many steps of the method 100 may be performed in any number of chambers or systems, including, for example, an oxidation chamber and an atomic layer deposition chamber, and any combination of the systems described, or they may be configured to perform the steps described for the method 100. The method 100 may include one or more steps prior to the first step described, including processing to manufacture or prepare one or more parts or components to be joined, as well as components already joined. For example, upstream processing may include casting or processing a metal component, as well as preparing one or more surfaces for a coating step. The method 100 may further include optional steps that may or may not be specifically associated with an embodiment of the present method. For example, some embodiments of the present coating method, providing a broader or alternative scope of the method, may include one or more steps that do not occur or occur at different times in other embodiments of the method.
[0022]
[0024] The method 100 will be described in connection with a cross-sectional view of a portion of a component 200 shown in FIG. 2. The component 200 includes an embodiment of the present multi-layer corrosion resistant coating positioned on a surface of a substrate 205 forming at least a portion of the component. In the embodiment shown in FIG. 2, the multi-layer coating is a three-layer coating including a bonding layer 210, a stress buffer layer 215, and an environmental barrier layer 220. It should be understood that additional layers may be formed below the substrate layer 205 and above the environmental barrier layer 220. It should also be understood that the interface between the layers may or may not have a distinct boundary. For example, a portion of the interface may include a combination of materials from two adjacent layers, such as the bonding layer 210 and the stress buffer layer 215. In an embodiment of the present technology, the coated component includes one or more substrate surfaces on which the multi-layer coating is formed. The substrate surface includes an exposed surface of the substrate that forms a bonding layer of the multi-layer coating. The substrate may include one or more metals that are incorporated into at least a portion of the component, such as the walls of the component. In embodiments, the metal substrate may be or include any number of components or sections of components. In additional embodiments, the metal substrate may be incorporated into components of a semiconductor processing system that is used to perform semiconductor manufacturing processes using corrosive liquids, gases, and plasmas and undergoes large changes in temperature. In yet another embodiment, the metal substrate may be incorporated into components of semiconductor manufacturing equipment such as base plates or edge rings, fluid delivery components such as showerheads or cover plates, structural components such as spacers or liners, and other single or multi-piece components of semiconductor manufacturing equipment that may be coated by the present method. The components may be substantially planar or include complex geometries that may include channels, apertures, or other features on one or more surfaces of the components. The components may be made of any number of materials that may be or include aluminum, carbon, chromium, copper, iron, magnesium, manganese, nickel, silicon, titanium, or zinc.The components may be or include alloys, such as iron alloys, which may include any number of materials. In many embodiments, the metal substrate in the component includes stainless steel, such as 316 stainless steel. Although the following description refers to stainless steel, which may be a material from which components according to embodiments of the present technology are made, it should be understood that the present technology may be used with any iron alloy, as well as any number of other metal alloys that may be used in semiconductor processing chambers or systems.
[0023]
[0025] In an embodiment, the method 100 may include preparing a surface of the substrate 205 in step 105. In a further embodiment, the preparation may include one or more of removing an existing coating from the substrate surface, roughening the substrate surface, smoothing the substrate surface, exposing the substrate surface to an oxidizing environment, exposing the substrate surface to a passivating environment, and exposing the substrate surface to an etching environment, among others. In some embodiments, the substrate surface preparation step 105 may be omitted since the substrate surface has already been pretreated to form a bonding layer. In other embodiments, the method 100 includes step 105 to allow the bonding layer 210 to be formed on the prepared surface of the substrate 205 of sufficient quality within a target time.
[0024]
[0026] In further embodiments, the substrate surface preparation step 105 may include removing oxides, organics, oils, soil, particulates, debris, and / or other contaminants from the surface of the substrate 205. In further embodiments, the preparation may include, among others, blasting or texturing the surface, exposing the surface to reduced pressure, solvent cleaning the surface, acid cleaning the surface, wet cleaning the surface, plasma cleaning the surface, and sonicating the surface. The prepared surface of the substrate 205 may be characterized by faster formation of a bonding layer on the surface and stronger bonding compared to an unprepared substrate surface.
[0025]
[0027] In further embodiments, preparing the substrate surface may include blasting or otherwise exposing the surface to one or more abrasive particulates, such as beads, sand, and carbonates, among others. In embodiments, the particulate exposure may remove oxides and other contaminants from the substrate surface and may also provide a textured surface to the substrate 205. In further embodiments, preparing the substrate surface may include placing the component 200 in a chamber within a pulsed push-pull gas circulation system and exposing the substrate surface of the component to at least one cycle of a purge gas, such as nitrogen, argon, helium, and mixtures thereof. In further embodiments, the component 200 may be exposed to at least one vacuum purge to remove particulates and other debris from the substrate surface. In still further embodiments, the component 200 is placed in a plasma chamber and the substrate surface is exposed to one or more plasmas, such as hydrogen-containing plasmas, oxygen- or ozone-containing plasmas, and nitrogen-containing plasmas, among others. In still further embodiments, the plasma may be generated in situ or may be generated remotely outside of the chamber holding component 200 and delivered to the chamber.
[0026]
[0028] In further embodiments, the substrate surface preparation may include removing one or more organic and oxide compounds from the surface of the substrate 205. In additional embodiments, the organic and oxide compounds may be removed from the surface by reducing plasma, such as hydrogen plasma. In further embodiments, the reduced organic and oxide compounds may be degassed from the surface and exposed to ozone. In still further embodiments, the substrate surface preparation may include wet cleaning to remove organic compounds from the surface. In embodiments, the wet cleaning may include immersing the substrate surface in an alkaline degassing solution, rinsing, exposing the surface to an acid clean (e.g., sulfuric acid, phosphoric acid, or hydrochloric acid), rinsing again, and exposing the surface to a deionized water sonication bath. In additional embodiments, the substrate surface preparation may include wet cleaning to remove oxide compounds from the surface. In embodiments, the wet cleaning may include exposing the substrate surface to a dilute acid solution (e.g., acetic acid or hydrochloric acid), rinsing, and exposing the surface to deionized water in a sonication bath. In further embodiments, the preparation of the substrate surface may include a preparation step for removing particles from the substrate surface. In embodiments, such particle removal preparation may include exposing the substrate surface to sonication (e.g., megasonics) and / or supercritical carbon dioxide cleaning, followed by a purge gas (e.g., N 2 , Ar, He, or a combination thereof) and a vacuum purge to remove particles from the surface and dry the surface. In still further embodiments, preparing the substrate surface may include exposing the surface to a heating step and a drying step. In embodiments, the heating step may include exposing the substrate surface to a temperature above room temperature. In further embodiments, the elevated temperature may be characterized as a temperature of about 50° C. or higher, about 75° C. or higher, about 100° C. or higher, about 125° C. or higher, about 150° C. or higher, about 175° C. or higher, about 200° C. or higher, or higher. In further embodiments, the heating step may include exposing the substrate surface to a heat lamp or placing the component in an oven.
[0027]
[0029] The method 100 may further include forming a bonding layer 210 on the surface of the substrate 205 at step 110. In an embodiment, the bonding layer 210 may be formed by having the component including the substrate surface in an environment that forms an oxide of at least one metal in the component. In a further embodiment, the oxide forming environment may include one or more oxidizing agents in contact with the substrate surface. In an additional embodiment, the oxidizing agent may be water (e.g., water vapor), molecular oxygen (O), or other oxidizing agents, among others. 2 ), atomic oxygen (O), oxygen ion, ozone (O 3 ), nitrous oxide, peroxide-containing compounds (e.g., H 2 O 2 ), and hydroxide-containing compounds (e.g., alcohols). In further embodiments, the oxidizer can be incorporated into the oxidizing gas mixture. In yet further embodiments, the oxidizer or oxidizing gas mixture can be energized to form an oxidizing plasma.
[0028]
[0030] In additional embodiments, the bonding layer 210 may be formed on the surface of the substrate 205 by thermal oxidation of the substrate. In yet additional embodiments, the formation of the bonding layer 210 by thermal oxidation may be followed by thermal passivation of the bonding layer. In further embodiments, the bonding layer 210 may be formed on the surface of the substrate 205 by chemical passivation of the metal substrate using an acid solution, such as nitric acid or citric acid, among others. In yet further embodiments, the bonding layer 210 may be formed on the surface of the substrate 205 by ozone passivation of the metal substrate. In additional embodiments, the bonding layer 210 may be formed on the surface of the substrate 205 by atomic layer deposition.
[0029]
[0031] In embodiments, the at least one metal that is oxidized on the surface of the substrate 205 to form a metal oxide in the bonding layer 210 may include chromium, aluminum, silicon, titanium, iron, nickel, zirconium, and hafnium, among others. In further embodiments, the metal oxide in the bonding layer comprises chromium oxide (e.g., Cr) at a level of about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 95% or more, or more, by weight of the total metal oxide in the bonding layer. 2 O 3 In further embodiments, the tie layer may be formed to a thickness of about 20 nm or less, about 15 nm or less, about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, or even less.
[0030]
[0032] In some embodiments, at least a portion of the bonding layer 210 may be formed by depositing a metal oxide directly onto the metal-containing surface of the substrate 205. In embodiments, the deposition process may include a vapor deposition process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), thermal chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PE-CVD), among others. In further embodiments, the deposition process may include a vapor deposition process that provides a metal-containing reactant and an oxidation reactant to a deposition processing region. In still further embodiments, the reactants react in the deposition processing region to deposit at least a portion of the bonding layer 210 on the surface of the substrate 205. In further embodiments, the metal-containing reactant may include a chromium-containing reactant, an aluminum-containing reactant, a silicon-containing reactant, a titanium-containing reactant, an iron-containing reactant, a nickel-containing reactant, a zirconium-containing reactant, and a hafnium-containing reactant, among others. In further embodiments, the chromium-containing reactant may include one or more of a chromium cyclopentadiene compound, a chromium carbonyl compound, a chromium acetylacetonate compound, a chromium diazadienyl compound, a substitute thereof, a complex thereof, an abduct thereof, a salt thereof, or any combination thereof. In further embodiments, the chromium-containing reactant may include bis(cyclopentadiene)chromium (Cp2 Cr), bis(pentamethylcyclopentadiene)chromium ((Me 5 Cp) 2 Cr), bis(isopropylcyclopentadiene)chromium ((iPrCp) 2 Cr), bis(ethylbenzene)chromium ((EtBz) 2 Cr), chromium hexacarbonyl (Cr(CO) 6 ), Chromium acetylacetonate (Cr(acac) 3 , also known as tris(2,4-pentanedione)chromium), chromium hexafluoroacetylacetonate (Cr(hfac) 3 ), chromium(III) tris(2,2,6,6-tetramethyl-3,5-heptanedionate) {Cr(tmhd) 3}, chromium(II) bis(1,4-ditertbutyldiazadienyl), an isomer thereof, a complex thereof, an abduct thereof, a salt thereof, or any combination thereof. In an embodiment, the chromium-containing reactant may be represented by the chemical formula: TIFF2025507056000002.tif36170, where each R and R' is independently H, C1-C6 alkyl, aryl, acyl, alkylamide, hydrazide, silyl, aldehyde, keto, C2-C4 alkenyl, alkynyl, or substituted thereof. In some embodiments, each R is independently a C1-C6 alkyl selected from methyl, ethyl, propyl, butyl, or an isomer thereof, and R' is H. In still further embodiments, R is methyl and R' is H, R is ethyl and R' is H, R is iso-propyl and R' is H, or R is tert-butyl and R' is H.
[0031]
[0033] The method 100 further includes depositing a stress buffer layer 215 on the bonding layer 210 in step 110. In an embodiment, the stress buffer layer 210 is characterized by a CTE of the stress buffer layer that is less than the CTE of the substrate 205 on which the bonding layer 210 is formed. In an additional embodiment, the CTE of the stress buffer layer is greater than the CTE of the environmental barrier layer 220 that is deposited on the surface of the stress buffer layer 215 opposite the surface in contact with the bonding layer 210. The intermediate CTE of the stress buffer layer 215, which is less than the CTE of the substrate of the component and greater than the CTE of the environmental barrier layer 220, reduces mechanical stress on the environmental barrier layer when the coated component undergoes large changes in temperature. The reduced mechanical stress on the environmental barrier layer 220 reduces the frequency and size of stress fractures in the environmental barrier layer that can create paths for corrosive gases, plasmas, and other materials to reach the underlying coating layers and the surface of the substrate 205. In embodiments, the stress buffer layer 215 may include a metal oxide composition having a CTE less than the CTE of the metal substrate and greater than the CTE of the environmental barrier layer. In additional embodiments, the stress buffer layer 215 may include one or more metal oxides selected from aluminum oxide, chromium oxide, and titanium oxide, among others. In further embodiments, the stress buffer layer 215 may include a metal oxide composition having a CTE less than about 10×10 -6 / ℃ or less, approximately 9×10 -6 / ℃ or less, approximately 8×10 -6 / ℃ or less, about 7×10 -6 / ℃ or less, approximately 6×10 -6 / ℃ or less, approximately 5×10 -6 The stress buffer layer may be characterized by a CTE of 100 / °C or less.
[0032]
[0034] In embodiments, the reduction in stress in the environmental barrier layer 220 can also be mitigated by the thickness of the stress buffer layer 215. The further the environmental barrier layer 220 is from the substrate surface, the less stress there is on the environmental barrier layer due to the difference in CTE between the barrier layer and the substrate 205. In additional embodiments, the stress buffer layer 215 can be characterized by a thickness of about 10 nm or more, about 20 nm or more, about 30 nm or more, about 40 nm or more, about 50 nm or more, about 60 nm or more, about 70 nm or more, about 80 nm or more, about 90 nm or more, about 100 nm or more, or more.
[0033]
[0035] In additional embodiments, the stress buffer layer 215 may be deposited by a vapor deposition process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), thermal chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PE-CVD), among others. In further embodiments, the deposition process may include a vapor deposition process that provides a metal-containing reactant and an oxidation reactant to a deposition processing area exposed to at least a portion of the bonding layer formed on the substrate surface. The metal-containing reactant and the oxidation reactant deposit a metal oxide-containing stress buffer layer on the bonding layer.
[0034]
[0036] In further embodiments, the stress buffer layer 215 may be deposited by an atomic layer deposition process that provides an aluminum-containing reactant and an oxidizing reactant to a deposition processing region, where the aluminum-containing reactant and the oxidizing reactant form an aluminum oxide-containing stress buffer layer on at least a portion of the bonding layer 210. In further embodiments, the aluminum-containing reactant may include, among others, one or more aluminum alkyl compounds, one or more aluminum alkoxy compounds, and one or more aluminum acetylacetonate compounds. In still further embodiments, the aluminum-containing reactant may include, among others, trimethylaluminum, triethylaluminum, tripropylaluminum, tributylaluminum, trimethoxyaluminum, triethoxyaluminum, tripropoxyaluminum, tributoxyaluminum, aluminum acetylacetonate (Al(acac), also known as tris(2,4-pentanedione)aluminum). 3 ), aluminum hexafluoroacetylacetonate (Al(hfac) 3 ), and aluminum tris(dipivaloylmethanate) (DPM 3 Al;(C 11 H 19 O 2 ) 3 In additional embodiments, the oxidation reactants can include water (e.g., steam), oxygen (O 2 ), atomic oxygen (O), ozone (O 3 ), nitrous oxide, one or more peroxides, one or more alcohols, plasmas thereof, or any combination thereof. In further embodiments, one or both of the aluminum-containing reactant and the oxidation reactant are coupled to one or more carrier gases, such as nitrogen (N), among others. 2 ), argon, helium, neon, and hydrogen (H 2 ).
[0035]
[0037] In further embodiments, the atomic layer deposition of the stress buffer layer 215 may include one or more cycles of exposing the component having the bonding layer to a metal-containing reactant, performing a purge-pump step of the deposition processing region to remove residual metal-containing reactant, exposing the component to an oxidizing reactant, and performing another purge-pump step to remove residual oxidizing reactant from the deposition processing region. In still further embodiments, the ALD process may include about 1 or more cycles, about 2 or more cycles, about 3 or more cycles, about 4 or more cycles, about 5 or more cycles, about 8 or more cycles, about 10 or more cycles, about 15 or more cycles, about 20 or more cycles, about 30 or more cycles, about 50 or more cycles, about 80 or more cycles, about 100 or more cycles, or more than that. In still further embodiments, each cycle may deposit a portion of the stress buffer layer 215 characterized by a thickness of about 10 nm or less, about 7.5 nm or less, about 5 nm or less, about 2.5 nm or less, about 1 nm or less, about 0.5 nm or less, about 0.1 nm or less, or even less.
[0036]
[0038] The method 100 also includes depositing an environmental barrier layer 220 at step 120. In an embodiment, the environmental barrier layer 220 may be characterized by a higher corrosion resistance to one or more corrosive substances as compared to the substrate 205 of the component 200. In a further embodiment, the one or more corrosive substances may include one or more halogens, such as fluorine, chlorine, and bromide. In a further embodiment, the halogens may be included in halogen-containing compounds, radicals, or ions incorporated in a halogen-containing liquid, solution, precursor, gas, or plasma, among other halogen-containing media. In still further embodiments, the halogen etch rate ratio between the substrate surface and the environmental barrier layer 220 may be characterized as being about 10:1 or greater, about 50:1 or greater, about 100:1 or greater, about 200:1 or greater, about 300:1 or greater, about 400:1 or greater, about 500:1 or greater, about 600:1 or greater, about 700:1 or greater, about 800:1 or greater, about 900:1 or greater, about 1000:1 or greater, or greater.
[0037]
[0039] In embodiments, the corrosion resistance of the coated component 200 is increased by increasing the thickness of the environmental barrier layer 220. The more material a corrosive substance must penetrate or remove to reach the surface of the substrate 205, the longer the coated component can withstand the corrosive effects of the corrosive substance. In further embodiments, the environmental barrier layer 220 can be characterized by a thickness of about 50 nm or more, about 75 nm or more, about 100 nm or more, about 125 nm or more, about 150 nm or more, about 175 nm or more, about 200 nm or more, about 225 nm or more, about 250 nm or more, about 275 nm or more, about 300 nm or more, about 350 nm or more, about 400 nm or more, about 450 nm or more, about 500 nm or more, or more. In embodiments in which the environmental barrier layer 220 is the outermost layer of a multi-layer coating on the component 200, the multi-layer coating may be characterized by a thickness of about 500 nm or more, about 600 nm or more, about 700 nm or more, about 800 nm or more, about 900 nm or more, about 1000 nm or more, or greater.
[0038]
[0040] In additional embodiments, the environmental barrier layer 220 may include silicon oxide, such as silicon dioxide. In further embodiments, the silicon oxide (e.g., SiO 2) may be about 50% by weight or more, about 60% by weight or more, about 70% by weight or more, about 80% by weight or more, about 90% by weight or more, about 95% by weight or more, or more, of the total weight of the environmental barrier layer. In still further embodiments, the environmental barrier layer 220 may be deposited by a vapor deposition process, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), thermal chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition (PE-CVD), among others. In further embodiments, the deposition process may include a vapor deposition process that provides a semiconductor-containing or metal-containing reactant and an oxidizing reactant to a deposition processing area exposed to at least a portion of the stress buffer layer 215 formed on the component 200. The semiconductor-containing or metal-containing reactant and the oxidizing reactant deposit the oxide-containing environmental barrier layer 220 on the stress buffer layer 215. In additional embodiments, the semiconductor-containing or metal-containing reactant may include a silicon-containing reactant, such as, inter alia, a silane, a silicon chloride, a silicon cyanate, an oxysilane, or an aminosilane. In yet another embodiment, the silane may include, inter alia, one or more of a silane, a disilane, a trisilane, a tetrasilane, a pentasilane, and a hexasilane. In yet a further embodiment, the silicon chloride may include, inter alia, one or more of a monocyclosilane, a dicyclosilane, a trichlorosilane, a tetrachlorosilane, and a hexachlorosilane. In a further embodiment, the silicon cyanate may include, inter alia, a tetraisocyanatosilane. In yet a further embodiment, the oxysilane may include, inter alia, a tetraethoxysilane. In an additional embodiment, the aminosilane may include, inter alia, a tris(dimethylamino)silane.
[0039]
[0041] In further embodiments, the silicon-oxide-containing environmental barrier layer 220 may increase the corrosion resistance of the coated component to chlorine-containing corrosive substances. In embodiments, these chlorine-containing corrosive substances include, among others, hydrogen chloride or hydrochloric acid (HCl), molecular chlorine (Cl 2), chlorine radicals (Cl), and one or more of oxygen-chlorine compounds, nitrogen-chlorine compounds, and carbon-chlorine compounds. In additional embodiments, the silicon-oxide-containing environmental barrier layer 220 may reduce the corrosion rate of the coated component by chlorine-containing corrosive agents compared to the corrosion rate of the substrate 205 of the uncoated component. In yet another embodiment, the silicon-oxide-containing environmental barrier layer 220 may reduce the corrosion rate of the coated component to about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, about 5% or less, about 1% or less, or less than the corrosion rate of the uncoated component.
[0040]
[0042] In yet further embodiments, the environmental barrier layer 220 may include hafnium oxide. In further embodiments, the hafnium oxide (e.g., HfO 2 ) may be about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 95% or more, or more, by weight of the total weight of the environmental barrier layer. In still further embodiments, the hafnium-oxide-containing environmental barrier layer 220 may be deposited by a vapor deposition process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), thermal chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PE-CVD), among others. In further embodiments, the deposition process may include a vapor deposition process that provides a hafnium-containing reactant and an oxidizing reactant to a deposition processing area exposed to at least a portion of the stress buffer layer 215 formed on the component 200. In additional embodiments, the hafnium-containing reactant may include a hafnium cyclopentadiene compound, a hafnium amino compound, a hafnium alkyl compound, and a hafnium alkoxy compound, among others. In a further embodiment, the hafnium-containing reactant is, inter alia, bis(methylcyclopentadiene)dimethylhafnium ((MeCp) 2 HfMe 2 ), bis(methylcyclopentadiene)methylmethoxyhafnium ((MeCp)2 Hf(OMe)(Me)), bis(cyclopentadiene)dimethylhafnium ((Cp) 2 HfMe 2 ), tetra(tert-butoxy)hafnium, hafnium isopropoxide ((iPrO) 4 Hf), tetrakis(dimethylamino)hafnium (TDMAH), tetrakis(diethylamino)hafnium (TDEAH), and tetrakis(ethylmethylamino)hafnium (TEMAH).
[0041]
[0043] In further embodiments, the hafnium-oxide-containing environmental barrier layer 220 may increase the corrosion resistance of the coated component to halogen-containing corrosives. These halogen-containing corrosives include, among others, chlorine-containing corrosives, fluorine-containing corrosives, and corrosives containing a mixture of chlorine and fluorine. In additional embodiments, the chlorine-containing corrosives may include, among others, one or more of hydrogen chloride or hydrochloric acid (HC1), molecular chlorine (Cl2), chlorine radicals (Cl), compounds containing oxygen and chlorine, compounds containing nitrogen and chlorine, and compounds containing carbon and chlorine. In further embodiments, the fluorine-containing corrosives may include, among others, hydrogen fluoride or hydrofluoric acid (HF), molecular fluorine (F), and / or other compounds containing hydrogen fluoride (HF). 2 ), fluorine radicals (F), as well as oxygen-fluorine compounds and nitrogen-fluorine compounds (e.g., NF 3 ), and carbon-fluorine compounds (e.g., CF 4 In yet further embodiments, the corrosive material containing a mixture of chlorine and fluorine may include, among others, carbon-chlorine-fluorine containing compounds, such as CCl 2 F 2In additional embodiments, the hafnium-oxide-containing environmental barrier layer 220 may reduce the corrosion rate of the coated component by a halogen-containing corrosive agent as compared to the corrosion rate of the uncoated component's substrate 205. In yet other embodiments, the hafnium-oxide-containing environmental barrier layer 220 may reduce the corrosion rate of the coated component to about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, about 5% or less, about 1% or less, or less than the corrosion rate of the uncoated component.
[0042]
[0044] In some embodiments, the environmental barrier layer 220 may include two or more layers made of different oxide materials (not shown). For example, the environmental barrier layer 220 may include a first barrier layer made of silicon dioxide and a second barrier layer made of hafnium oxide. In additional embodiments, the environmental barrier layer 220 may be a multi-layer barrier including alternating layers of silicon oxide and hafnium oxide. In embodiments, a multi-layer coating including an environmental barrier layer may feature at least three layers, at least four layers, at least five layers, at least six layers, or more layers. In additional embodiments, the environmental barrier layer 220 may be a single layer made of a mixture of two or more oxide materials, such as a mixture of silicon dioxide and hafnium oxide. In yet other embodiments, the environmental barrier layer 220 may further include one or more additional metals, such as oxides of aluminum, chromium, magnesium, nickel, titanium, and zirconium, among others.
[0043]
[0045] The method 100 may also optionally further include annealing the multi-layer coating formed on the surface of the substrate 205 in step 125. In embodiments, the annealing step may include one or more of thermal annealing, plasma annealing, ultraviolet annealing, or laser annealing, among others. In additional embodiments, the annealing may increase the density of one or more layers of the multi-layer coating. In further embodiments, the annealing may increase the crystallinity and slightly change the composition of one or more layers of the multi-layer coating.
[0044]
[0046] In embodiments, annealing may include heating the component coated with the as-deposited multi-layer coating to a temperature of about 100° C. or higher, about 200° C. or higher, about 300° C. or higher, about 400° C. or higher, about 500° C. or higher, or higher. In further embodiments, annealing may include exposing the coated component to an oxidizing, neutral, or reducing environment. In embodiments, an oxidizing environment is oxygen (O 2 ) and the neutral environment is nitrogen (N 2 ) and the reducing environment is hydrogen (H 2), respectively. In further embodiments, the annealing environment can be a low pressure environment characterized by a pressure of about 700 Torr or less, about 600 Torr or less, about 500 Torr or less, about 400 Torr or less, about 300 Torr or less, about 200 Torr or less, about 100 Torr or less, about 50 Torr or less, about 25 Torr or less, about 10 Torr or less, about 1 Torr or less, about 0.1 Torr or less, about 0.01 Torr or less, about 0.001 Torr or less, or lower. In further embodiments, the annealing environment can be an atmospheric or high pressure environment characterized by a pressure of about 760 Torr or more, about 1000 Torr or more, about 1500 Torr or more, about 2000 Torr or more, about 2500 Torr or more, about 3000 Torr or more, about 3500 Torr or more, or more. In still further embodiments, the duration of annealing may be about 1 minute or more, about 5 minutes or more, about 10 minutes or more, about 30 minutes or more, about 60 minutes or more, about 90 minutes or more, about 180 minutes or more, or longer. In embodiments where the annealing duration is short, such as spike annealing, the annealing duration may be characterized as about 15 seconds or less, about 10 seconds or less, about 5 seconds or less, about 1 second or less, about 0.1 seconds or less, about 0.01 seconds or less, about 0.001 seconds, or less.
[0045]
[0047] In embodiments, the layers of the multi-layer corrosion resistant coating formed on the substrate 205 and optionally annealed may be characterized by additional properties that increase the corrosion resistance of the coating. In additional embodiments, the multi-layer coating may be characterized by an increased hardness compared to coatings formed by conventional methods. In still further embodiments, the present multi-layer coating may be characterized by a Vickers hardness of about 1000 or more, about 1200 or more, about 1400 or more, about 1600 or more, about 1800 or more, about 2000 or more, or more. In addition, the multi-layer coating may be characterized by improved dielectric breakdown voltage characteristics that may facilitate the use of the coating on components that may operate as electrodes in semiconductor processing systems. For example, coatings according to embodiments of the present technology may be characterized by a dielectric breakdown of about 20 V / μm or more, and may be characterized by a dielectric breakdown of about 25 V / μm or more, about 30 V / μm or more, about 35 V / μm or more, about 40 V / μm or more, or more. In some embodiments, this feature can be further enhanced by performing one or more post-processing steps.
[0046]
[0048] 3 is a cross-sectional view of a portion of a component 300 coated with a multi-layer corrosion resistant coating according to additional embodiments of the present invention. The substrate 305 of the component 300 includes a step that demonstrates conformality of the bonding layer 310, the stress buffer layer 315, and the environmental barrier layer 320 to steps, trenches, holes, channels, fluid paths, tubes, and openings, among other features of the substrate of the component. In embodiments, the present technology includes forming a conformal coating that may extend to any of a variety of features and aspects of the component. In embodiments, the conformality of the coating may be characterized by a small variation in thickness of the multi-layer coating on orthogonal surfaces of the step of the substrate 305. In embodiments, the variation in thickness of the multi-layer coating between orthogonal surfaces is characterized by about 10% or less, about 7.5% or less, about 5% or less, about 2.5% or less, about 1% or less, or less.
[0047]
[0049] In additional embodiments, the component 300 may include one or more apertures (not shown) characterized by an aspect ratio (i.e., height to width ratio) of about 1:1 or more, about 2:1 or more, about 3:1 or more, about 4:1 or more, about 5:1 or more, about 6:1 or more, about 7:1 or more, about 8:1 or more, about 10:1 or more, or more. In yet another embodiment, the multi-layer coating may be characterized by high uniformity of the inner walls of the apertures compared to other portions of the coating. In embodiments, the uniformity of the multi-layer coating between the inner walls of the apertures and other portions of the coating may be characterized by having thicknesses within 90% of each other, within 92% of each other, within 94% of each other, within 96% of each other, within 98% of each other, within 99% of each other, or essentially equal to each other within the error of any measurement device or technique being used.
[0048]
[0050] The present technology includes a metal-containing component coated with a multi-layer coating that provides the component with increased corrosion resistance. In an embodiment, the multi-layer coating includes a stress buffer layer that reduces mechanical stress experienced by the outer environmental barrier layer from differences in thermal expansion coefficients between the ceramic material in the barrier layer and the metal substrate of the component. In an additional embodiment, the multi-layer coating also includes a tie layer that increases adhesion of the stress buffer layer and the environmental barrier layer to the metal substrate of the component. The combination of the tie layer, stress buffer layer, and environmental barrier layer makes the multi-layer coating less susceptible to fracture and delamination experienced by conventional single-layer ceramic coatings formed directly on the substrate surface of the metal-containing component. In an embodiment, device manufacturing components coated with the present multi-layer coatings have extended service life compared to uncoated components and components coated with a single layer anti-corrosion coating.
[0049]
[0051] In the above description, for purposes of explanation, numerous details are presented in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.
[0050]
[0052] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the principles of the embodiments. In addition, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Therefore, the above description should not be interpreted as limiting the scope of the technology.
[0051]
[0053] Where a range of values is provided, unless the context clearly indicates otherwise, each intervening value between the upper and lower limits of that range is to be understood as specifically disclosed to the smallest unit of the lower limit. All narrower ranges between any stated or unstated intervening values in a stated range, as well as any other stated or intervening value in such stated range, are included. The upper and lower limits of such narrower ranges may be individually included or excluded from the range, and each range in which either or both of the limits are included in the narrower range, or neither of the narrower ranges, is also encompassed by this technology, subject to any limits specifically excluded in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
[0052]
[0054] As used in the specification and claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a layer" includes a plurality of such layers, a reference to "the precursor" includes a reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.
[0053]
[0055] Furthermore, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," as used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.
Claims
1. forming a bond layer on a metal substrate, the bond layer comprising an oxide of a metal in the metal substrate; depositing a stress buffer layer on the bonding layer, the stress buffer layer characterized by a coefficient of thermal expansion (CTE) less than a CTE of the stress buffer layer of a metal substrate and a CTE of the bonding layer; depositing an environmental barrier layer on the stress buffer layer, wherein a ratio of a CTE of the metal substrate to a CTE of the environmental barrier layer is about 20:1 or greater, and the environmental barrier layer comprises silicon oxide; A coating method comprising the steps of:
2. The CTE of the metal substrate is about 10×10 －６ 2. The coating method according to claim 1, wherein the temperature is 100° C. or higher.
3. The CTE of the environmental barrier layer is about 0.5×10 －６ 2. The coating method according to claim 1, wherein the temperature is 0.15 to 1.5° C. or less.
4. The method of claim 1 , wherein the metal substrate comprises stainless steel and the oxide of the metal in the bond layer comprises chromium oxide.
5. The method of claim 1 , wherein the bond layer is formed on the metal substrate by thermal oxidation of the metal in the metal substrate.
6. 6. The method of claim 5, wherein forming the bond layer further comprises exposing the metal substrate to an atmospheric atmosphere containing ozone.
7. The method of claim 1 , wherein the stress buffer layer comprises aluminum oxide.
8. The method of claim 1 , wherein the stress buffer layer and the environmental barrier layer are deposited by atomic layer deposition.
9. 1. A method for forming a multi-layer coating on a metal substrate, comprising: forming a bonding layer on the metal substrate, the bonding layer being characterized by a thickness of about 10 nm or less; depositing a stress buffer layer on the bonding layer, the stress buffer layer characterized by a thickness of about 50 nm or less; depositing an environmental barrier layer on the stress buffer layer, the environmental barrier layer characterized by a thickness of about 50 nm or greater; wherein the multi-layer coating increases the corrosion resistance of the metal substrate to at least one halogen.
10. The method of claim 9 , wherein the metal substrate comprises stainless steel and the bond layer comprises chromium oxide.
11. 10. The method of claim 9, wherein the stress buffer layer comprises aluminum oxide, the stress buffer layer being characterized by a CTE greater than a CTE of an environmental barrier layer and less than a CTE of a metal substrate.
12. 10. The method of claim 9, wherein the environmental barrier layer comprises silicon dioxide and the multi-layer coating increases the corrosion resistance of the metal substrate to chlorine.
13. 10. The method of claim 9, wherein the environmental barrier layer comprises hafnium oxide, and the multi-layer coating increases the corrosion resistance of the metal substrate to halogen-containing compounds.
14. 10. The method of claim 9, wherein the metal substrate is incorporated into a component of a semiconductor manufacturing equipment that is exposed to the at least one halogen.
15. A metal substrate; a bonding layer positioned on the metal substrate, the bonding layer comprising an oxide of a metal in the metal substrate; a stress buffer layer positioned on the bonding layer; an environmental barrier layer positioned on the stress buffer layer; wherein the stress buffer layer is characterized by a CTE that is greater than a CTE of the environmental barrier layer and less than a CTE of the metal substrate.
16. 16. The coated metal structure of claim 15, wherein the metal substrate comprises stainless steel and the bond layer comprises chromium oxide.
17. The coated metal structure of claim 15 , wherein the stress buffer layer comprises aluminum oxide.
18. The coated metal structure of claim 15 , wherein the environmental barrier layer comprises silicon dioxide.
19. 16. The coated metal structure of claim 15, wherein the ratio of the CTE of the metal substrate to the CTE of the environmental barrier layer is about 20:1 or greater.
20. 16. The coated metal structure of claim 15, wherein the bond layer is characterized by a thickness of about 10 nm or less and the environmental barrier layer is characterized by a thickness of about 50 nm or more.