Package Having Substrate With Buried Escape and Surface Escape Interconnects - Patent application

Abstract

A package including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate, the substrate including at least one dielectric layer and a plurality of interconnects including a plurality of escape interconnects, the plurality of escape interconnects including a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 684,327, filed in the United States Patent Office on March 1, 2022, the entire contents of which are incorporated by reference herein as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates. [Background technology]

[0003] The package may include a substrate and an integrated device. The substrate may include a plurality of interconnects. The integrated device may be coupled to the interconnects of the substrate. There is a continuing need to provide smaller packages with a higher density of interconnects between the substrate and the integrated device. Summary of the Invention

[0004] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates.

[0005] One embodiment provides a package including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects including a plurality of escape interconnects. The plurality of escape interconnects includes a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect.

[0006] Another embodiment provides a package comprising a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate, the substrate including at least one dielectric layer, a means for a first buried escape interconnect, a means for a second buried escape interconnect, and a means for a surface escape interconnect, the means for the surface escape interconnect being disposed between the means for the first buried escape interconnect and the means for the second buried escape interconnect.

[0007] Another embodiment provides a method for manufacturing a package. The method includes providing a substrate, the substrate comprising at least one dielectric layer and a plurality of interconnects including a plurality of escape interconnects, the plurality of escape interconnects including a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect. The method includes bonding a first integrated device to the substrate. The method includes bonding a second integrated device to the substrate.

[0008] Various features, nature and advantages may become apparent from the following detailed description when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a plan view of a package including an integrated device and a substrate having escape interconnects. [Diagram 2] 1 shows a plan view of a substrate having buried escape interconnects and surface escape interconnects. [Diagram 3] 1 shows a perspective view of a substrate having buried escape interconnects and surface escape interconnects. [Figure 4] 1 shows another perspective view of a substrate having buried escape interconnects and surface escape interconnects. [Diagram 5] 1 shows a longitudinal / side cross-sectional view of a package including an integrated device and a substrate having escape interconnects through section AA. [Figure 6] 1 shows a longitudinal / side cross-sectional view of a package including an integrated device and a substrate with escape interconnects through cross section BB. [Figure 7] 1 shows a longitudinal / side cross-sectional view of a package including an integrated device and a substrate with escape interconnects through section CC. [Figure 8] 1 shows a longitudinal / side cross-sectional view of a package including an integrated device and a substrate with escape interconnects through cross section BB. [Figure 9A] 1 illustrates an exemplary sequence for manufacturing a substrate having escape interconnects. [Figure 9B] 1 illustrates an exemplary sequence for manufacturing a substrate having escape interconnects. [Figure 9C] 1 illustrates an exemplary sequence for manufacturing a substrate having escape interconnects. [Figure 9D] 1 illustrates an exemplary sequence for manufacturing a substrate having escape interconnects. [Figure 10] 1 illustrates an exemplary flow diagram of a method for manufacturing a substrate having escape interconnects. [Figure 11] 1 illustrates an exemplary sequence for manufacturing a package that includes a substrate having escape interconnects. [Figure 12] 1 illustrates an exemplary flow diagram of a method for manufacturing a package that includes a substrate having escape interconnects. [Figure 13] Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects including a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect disposed between the first embedded escape interconnect and the second embedded escape interconnect. The third escape interconnect is disposed on a different layer than the first embedded escape interconnect and the second embedded escape interconnect. The third escape interconnect can be a surface escape interconnect. The third escape interconnect can be embedded in a solder resist layer. The third escape interconnect can be an intermediate interconnect between the first embedded escape interconnect and the second embedded escape interconnect. The first buried escape interconnect and the second buried escape interconnect can be disposed in at least one dielectric layer of the substrate. The use of the first buried escape interconnect, the second buried escape interconnect, and the third escape interconnect can help provide a high density of escape interconnects between two or more integrated devices coupled to the substrate while at the same time providing an improved yield in the manufacture of the substrate, which helps to reduce the overall cost of the substrate and the package. The use of the escape interconnect can help to provide a smaller package.

[0012] Exemplary Package with Substrate Including Escape Interconnects FIG. 1 shows a plan view of a package 100 including a substrate having escape interconnects. The package 100 includes a substrate 102, an integrated device 103, and an integrated device 105. The substrate 102 includes a plurality of escape interconnects 107. The integrated device 103 (e.g., a first integrated device) and the integrated device 105 (e.g., a second integrated device) can be configured to be electrically coupled to each other via the plurality of escape interconnects 107 of the substrate 102. The plurality of escape interconnects 107 can provide a plurality of electrical paths between the integrated device 103 and the integrated device 105. For example, the plurality of escape interconnects 107 can provide a plurality of electrical paths for input / output (I / O) signals / currents between the integrated device 103 and the integrated device 105. As further described below in at least FIG. 2, the plurality of escape interconnects 107 can include embedded escape interconnects and surface escape interconnects. The surface escape interconnect may be an intermediate escape interconnect between two buried escape interconnects. The plurality of escape interconnects 107 may be configured as a bridge interconnect (e.g., a bridge escape interconnect) between the integrated device 103 and the integrated device 105. The plurality of escape interconnects 107 may include a means for buried escape interconnect (e.g., a means for a first buried escape interconnect, a means for a second buried escape interconnect) and a means for a surface escape interconnect.

[0013] 5, the substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, a solder resist layer 140, and a solder resist layer 142. The plurality of escape interconnects 107 may be part of the plurality of interconnects 122 of the substrate 102.

[0014] 2 shows a cross-sectional plan view of a portion of the substrate 102. The substrate 102 includes a region 201, a first bump region 203 for a first integrated device (e.g., integrated device 103), and a second bump region 205 for a second integrated device (e.g., integrated device 105). A bump region can be a region of the substrate where a solder interconnect (e.g., 132) and / or a pillar interconnect (e.g., 130) from an integrated device can be coupled to an interconnect of the substrate. For example, the first bump region 203 can be a region of the substrate 102 where a solder interconnect (e.g., 132) and / or a pillar interconnect (e.g., 130) can be coupled to a plurality of interconnects 230. In another example, the second bump region 205 can be a region of the substrate 102 where a solder interconnect (e.g., 152) and / or a pillar interconnect (e.g., 150) can be coupled to a plurality of interconnects 250.

[0015] Region 201 may be a part of an escape region for substrate 102. Region 201 of substrate 102 may be located between an edge (e.g., a first edge) of a first integrated device (e.g., 103) and an edge (e.g., a second edge) of a second integrated device (e.g., 105). The first edge of the first integrated device (e.g., 103) and the second edge of the second integrated device (e.g., 105) may be parallel to each other. The first edge of the first integrated device (e.g., 103) may face the second edge of the second integrated device (e.g., 105), or vice versa. Region 201, first bump region 203, and second bump region 205 are regions of substrate 102 that include escape interconnects. Substrate 102 includes a plurality of escape interconnects 107, a plurality of interconnects 230, and a plurality of interconnects 250. As will be further described below in at least FIG. 5, the plurality of escape interconnects 107, the plurality of interconnects 230, and the plurality of interconnects 250 may be considered part of a plurality of interconnects 122 of substrate 102.

[0016] The plurality of interconnects 230 includes interconnect 230a, interconnect 230b, interconnect 230c, interconnect 230d, and interconnect 230e. The plurality of interconnects 230 may include pad interconnects (e.g., pads). The interconnects 230a, interconnect 230b, interconnect 230d, and interconnect 230e may be embedded interconnects (e.g., embedded pad interconnects) in a dielectric layer of the substrate 102. The interconnect 230c may be a surface interconnect (e.g., surface pad interconnect) disposed on the dielectric layer of the substrate 102. The interconnect 230c may be covered by a solder resist layer. The plurality of interconnects 230 may be bonded to solder interconnects (e.g., 132) and / or pillar interconnects of an integrated device (e.g., 103).

[0017] The plurality of interconnects 250 includes interconnect 250a, interconnect 250b, interconnect 250c, interconnect 250d, and interconnect 250e. The plurality of interconnects 250 may include pad interconnects (e.g., pads). The interconnects 250a, interconnect 250b, interconnect 250d, and interconnect 250e may be embedded interconnects (e.g., embedded pad interconnects) in a dielectric layer of the substrate 102. The interconnect 250c may be a surface interconnect (e.g., surface pad interconnect) disposed on the dielectric layer of the substrate 102. The interconnect 250c may be covered by a solder resist layer. The plurality of interconnects 250 may be bonded to solder interconnects (e.g., 152) and / or pillar interconnects of an integrated device (e.g., 105).

[0018] The plurality of escape interconnectors 107 includes escape interconnector 107a, escape interconnector 107b, escape interconnector 107c, escape interconnector 107d, and escape interconnector 107e. The plurality of escape interconnectors 107 may include escape trace interconnectors (e.g., escape traces). The escape interconnector 107a, escape interconnector 107b, escape interconnector 107d, and escape interconnector 107e may be embedded escape interconnectors (e.g., embedded escape trace interconnectors). The escape interconnector 107a, escape interconnector 107b, escape interconnector 107d, and escape interconnector 107e may be examples of a means for embedded escape interconnection (e.g., a means for a first embedded escape interconnection, a means for a second embedded escape interconnection). The escape interconnect 107c may be a surface escape interconnect (e.g., a surface escape trace interconnect) disposed on a dielectric layer of the substrate 102. The escape interconnect 107c may be covered by a solder resist layer. The escape interconnect 107c may be an example of a means for surface escape interconnection. The escape interconnect 107c may be considered as an intermediate escape interconnect (e.g., an intermediate escape trace interconnect) between two adjacent buried escape interconnects (e.g., 107b, 107d). The escape interconnect 107c may be considered to be between the escape interconnect 107b and the escape interconnect 107d even if a portion of the escape interconnect 107c is disposed on a different metal layer than the escape interconnect 107b and the escape interconnect 107d. At least a portion of the escape interconnect 107c (e.g., surface escape interconnect) is adjacent to and parallel to at least a portion of the first embedded interconnect (e.g., escape interconnect 107b) and is also adjacent to and parallel to at least a portion of the second embedded interconnect (e.g., escape interconnect 107d).A first embedded interconnect (e.g., escape interconnect 107b) may face a first side of a surface escape interconnect (e.g., 107c), and a second embedded interconnect (e.g., escape interconnect 107d) may face a second side of the surface escape interconnect (e.g., 107c). Escape interconnect 107b and escape interconnect 107d may be considered as adjacent embedded escape interconnects with a surface interconnect (e.g., escape interconnect 107c) between them. The spacing between escape interconnect 107c and escape interconnect 107b may be smaller than the spacing between escape interconnect 107d and escape interconnect 107b. Similarly, the spacing between escape interconnect 107c and escape interconnect 107d may be smaller than the spacing between escape interconnect 107d and escape interconnect 107b. In some implementations, the substrate 102 may include several repeating configurations of a first buried escape interconnect, a surface escape interconnect, and a second buried escape interconnect, as shown in FIG. 2.

[0019] Escape interconnect 107a is coupled to interconnect 230a and to interconnect 250a. Escape interconnect 107b is coupled to interconnect 230b and to interconnect 250b. Escape interconnect 107c is coupled to interconnect 230c and to interconnect 250c. Escape interconnect 107d is coupled to interconnect 230d and to interconnect 250d. Escape interconnect 107e is coupled to interconnect 230e and to interconnect 250e.

[0020] The escape interconnector 107b, the escape interconnector 107c, and the escape interconnector 107d may be disposed and / or extend between the interconnector 230a and the interconnector 230e. The escape interconnector 107b, the escape interconnector 107c, and the escape interconnector 107d may be disposed and / or extend between the interconnector 250a and the interconnector 250e. A portion of the escape interconnector 107b, a portion of the escape interconnector 107c, and a portion of the escape interconnector 107d are parallel to each other. For example, a portion of the escape interconnector 107b, a portion of the escape interconnector 107c, and a portion of the escape interconnector 107d located in the region 201 may be parallel to each other.

[0021] Escape interconnect 107a, escape interconnect 107b, escape interconnect 107d, and escape interconnect 107e may be disposed on a metal layer (e.g., a first metal layer, a second metal layer), and escape interconnect 107c may be disposed on another metal layer (e.g., a first metal layer, a second metal layer) different from the metal layer on which escape interconnect 107a, escape interconnect 107b, escape interconnect 107d, and escape interconnect 107e are disposed. Escape interconnects, such as buried escape interconnects and / or surface escape interconnects, may be interconnects configured to provide an electrical path between two adjacent integrated devices coupled to a surface (e.g., a first surface, a second surface) of a substrate.

[0022] The width of the escape interconnect 107a, the escape interconnect 107b, the escape interconnect 107c, the escape interconnect 107d, and the escape interconnect 107e may be in the range of about 10 to 15 micrometers. The spacing (S) between the escape interconnect 107b and the escape interconnect 107c may be in the range of about 10 to 15 micrometers. For example, the spacing (S) between the escape interconnect 107b and the escape interconnect 107c in the region 201 of the substrate 102 may be in the range of about 10 to 15 micrometers. In another example, the spacing (S) between the escape interconnect 107b and the escape interconnect 107c in the region between the interconnect 230a and the interconnect 230e may be in the range of about 10 to 15 micrometers. In another example, the spacing (S) between the escape interconnect 107b and the escape interconnect 107c in the region between the interconnect 250a and the interconnect 250e can be in the range of about 10 to 15 micrometers. The spacing (S) between the escape interconnect 107c and the escape interconnect 107d can be in the range of about 10 to 15 micrometers. For example, the spacing (S) between the escape interconnect 107c and the escape interconnect 107d in the region 201 of the substrate 102 can be in the range of about 10 to 15 micrometers. In another example, the spacing (S) between the escape interconnect 107c and the escape interconnect 107d in the region between the interconnect 230a and the interconnect 230e can be in the range of about 10 to 15 micrometers. In another example, the spacing (S) between escape interconnect 107c and escape interconnect 107d in the region between interconnect 250a and interconnect 250e can be in the range of about 10 to 15 micrometers. In some implementations, the spacing (S) value mentioned above can be a minimum spacing value. Thus, for example, the escape interconnects mentioned above can have a minimum spacing in the range of about 10 to 15 micrometers. Thus, in some implementations, the escape interconnects mentioned above can have a spacing value greater than 15 micrometers.In some implementations, the above width values ​​may be minimum width values. Thus, for example, the escape interconnects may have a minimum width in the range of about 10 to 15 micrometers. Thus, in some implementations, the escape interconnects may have a width value greater than 15 micrometers.

[0023] 2 illustrates several repeating patterns / configurations / placements of interconnects (e.g., escape interconnects) between two integrated devices. For example, a first configuration of interconnects may include escape interconnect 107a, escape interconnect 107b, escape interconnect 107c, and escape interconnect 107d. Note that the first configuration of interconnects may also include interconnect 230a, interconnect 230b, interconnect 230c, interconnect 230d, interconnect 250a, interconnect 250b, interconnect 250c, and / or interconnect 250d.

[0024] The second configuration of interconnects may include escape interconnects arranged in a similar manner to escape interconnect 107a, escape interconnect 107b, escape interconnect 107c, and escape interconnect 107d. The second configuration of interconnects may include interconnects arranged in a similar manner to escape interconnect 107a, escape interconnect 107b, escape interconnect 107c, escape interconnect 107d, interconnect 230a, interconnect 230b, interconnect 230c, interconnect 230d, interconnect 250a, interconnect 250b, interconnect 250c, and / or interconnect 250d.

[0025] The third configuration of interconnects may include escape interconnects arranged in a similar manner to escape interconnect 107a, escape interconnect 107b, escape interconnect 107c, and escape interconnect 107d. The third configuration of interconnects may include interconnects arranged in a similar manner to escape interconnect 107a, escape interconnect 107b, escape interconnect 107c, escape interconnect 107d, interconnect 230a, interconnect 230b, interconnect 230c, interconnect 230d, interconnect 250a, interconnect 250b, interconnect 250c, and / or interconnect 250d.

[0026] Figure 3 shows a perspective top view of a portion of the substrate 102. Figure 4 shows a perspective bottom view of a portion of the substrate 102. The substrate 102 includes a dielectric layer 120, a plurality of interconnects 302a, a plurality of interconnects 302b, a plurality of interconnects 302c, a plurality of interconnects 302d, and a plurality of interconnects 302e.

[0027] The plurality of interconnects 302a may represent and / or include the interconnect 230a, the escape interconnect 107a, and the interconnect 250a. The plurality of interconnects 302b may represent and / or include the interconnect 230b, the escape interconnect 107b, and the interconnect 250b. The plurality of interconnects 302c may represent and / or include the interconnect 230c, the escape interconnect 107c, and the interconnect 250c. The plurality of interconnects 302d may represent and / or include the interconnect 230d, the escape interconnect 107d, and the interconnect 250d. The plurality of interconnects 302e may represent and / or include the interconnect 230e, the escape interconnect 107e, and the interconnect 250e.

[0028] The plurality of interconnects 302a, the plurality of interconnects 302b, the plurality of interconnects 302d, and the plurality of interconnects 302e may be embedded within the dielectric layer 120. The plurality of interconnects 302c may be disposed on (e.g., above) a surface of the dielectric layer 120 of the substrate 102. The plurality of interconnects 302c may be surface interconnects.

[0029] At least a portion of the plurality of interconnects 302c is located between the plurality of interconnects 302b and the plurality of interconnects 302d. The plurality of interconnects 302c can be considered an intermediate interconnect between two buried interconnects (e.g., two buried escape interconnects). The plurality of interconnects 302c is disposed on a different metal layer than the plurality of interconnects 302a, the plurality of interconnects 302b, the plurality of interconnects 302d, and the plurality of interconnects 302e. The width, minimum width, spacing, and / or minimum spacing as described with respect to the interconnects and / or escape interconnects of FIG. 2 are also applicable to the plurality of interconnects 302a, the plurality of interconnects 302b, the plurality of interconnects 302c, the plurality of interconnects 302d, and the plurality of interconnects 302e.

[0030] In some implementations, the escape interconnects include interconnects that extend into the area between a first set of pads for a first integrated device and into the area between a second set of pads for a second integrated device. For example, escape interconnects 107b, 107c, and 107d extend into the area (i) between interconnect 230a and interconnect 230e (which may be a pad coupled to integrated device 103 via a solder interconnect) and (ii) between interconnect 250a and interconnect 250e (which may be a pad coupled to integrated device 105 via a solder interconnect). Interconnects 230c and interconnect 250c may be both surface and buried interconnects. That is, for example, a portion (e.g., a first portion) of interconnect 230c can be disposed on the same metal layer as escape interconnect 107c, and another portion (e.g., a second portion) of interconnect 230c can be disposed on the same metal layer as interconnect 230a, interconnect 230b, and / or interconnect 230d. Similarly, a portion (e.g., a first portion) of interconnect 250c can be disposed on the same metal layer as escape interconnect 107c, and another portion (e.g., a second portion) of interconnect 250c can be disposed on the same metal layer as interconnect 250a, interconnect 250b, and / or interconnect 250d. An example in which pad interconnects can be both surface interconnects and buried interconnects is shown in Figures 3 and 4 with respect to interconnects from multiple interconnects 302c.

[0031] Providing a surface escape interconnect (e.g., a surface escape trace interconnect) between two buried escape interconnects (e.g., two buried escape trace interconnects) helps to provide a high density of interconnects and improved manufacturing yields during manufacturing of a substrate, which may help to reduce the overall cost of the substrate and / or package. The manufacturing process of a substrate may produce interconnects that are not placed in the correct location. Using a surface escape interconnect between two buried escape interconnects helps to ensure and provide a functional substrate even if the escape interconnects are not placed exactly where they are designed, since at least a portion of the surface escape interconnect is located on a different metal layer than the buried escape interconnect.

[0032] 5 shows a longitudinal cross-sectional view of the package 100 along the line AA. The package 100 includes an integrated device 105 and a substrate 102. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, a solder resist layer 140, a solder resist layer 142, and a plurality of solder interconnects 110. The integrated device 105 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of pillar interconnects 150 and / or a plurality of solder interconnects 152. For example, the integrated device 105 is coupled to a plurality of interconnects 122 of the substrate 102 via a plurality of pillar interconnects 150 and / or a plurality of solder interconnects 152. The plurality of solder interconnects 152 includes solder interconnects 152 and solder interconnects 152b. It should be noted that the package 100 also includes an integrated device 103 (not shown). 6, the integrated device 103 is coupled to the substrate 102 via a plurality of pillar interconnects 130 and / or a plurality of solder interconnects 132. For example, the integrated device 103 is coupled to a plurality of interconnects 122 of the substrate 102 via a plurality of pillar interconnects 130 and / or a plurality of solder interconnects 132.

[0033] The plurality of interconnects 122 includes interconnect 122a, interconnect 122b, interconnect 122c, interconnect 122d, interconnect 122e, and interconnect 122f. Interconnect 122a and interconnect 122b may represent pad interconnects (e.g., adjacent pad interconnects). In some implementations, interconnect 122a and / or interconnect 122b may represent interconnect 250a and / or interconnect 250e, as described in FIG. 2. In some implementations, interconnect 122b may represent escape interconnect 107c (e.g., a surface escape interconnect), as described in FIG. 2. In some implementations, interconnect 122d may represent escape interconnect 107b (e.g., a buried escape interconnect), as described in FIG. 2. In some implementations, the interconnect 122e may represent the escape interconnect 107d (eg, an embedded escape interconnect) as described in FIG.

[0034] Solder interconnect 152a can be bonded to interconnect 122a. Solder interconnect 152b can be bonded to interconnect 122b. Interconnect 122c can be covered by solder resist layer 140. Solder interconnect 152a and solder interconnect 152b can be disposed laterally relative to interconnect 122c. Interconnect 122c is disposed on a different metal layer than interconnects 122a, 122b, 122d, and 122e.

[0035] A solder resist layer 140 is disposed on a first side (e.g., top side) and / or a first surface of the substrate 102. A solder resist layer 142 is disposed on a second side (e.g., bottom side) and / or a second surface of the substrate 102. A plurality of solder interconnects 110 are coupled to a second surface (e.g., bottom side) of the substrate 102. The plurality of solder interconnects 110 are coupled to a plurality of interconnects 122 (e.g., interconnect 122f).

[0036] In some implementations, at least a portion of a first surface (e.g., top surface, surface facing away from the central portion of the substrate) of interconnect 122d (e.g., first buried escape interconnect) and at least a portion of a first surface (e.g., top surface, surface facing away from the central portion of the substrate) of interconnect 122e (e.g., second buried escape interconnect) may be flush with at least a portion of a second surface (e.g., bottom surface, surface facing the central portion of the substrate) of interconnect 122c (e.g., surface escape interconnect, third escape interconnect, third surface escape interconnect). At least a portion of interconnect 122c may be considered to be between at least a portion of interconnect 122d and at least a portion of interconnect 122e. When interconnect 122c is considered to be between interconnect 122d and interconnect 122e, it may mean that interconnect 122c exists between two imaginary vertical planes that extend vertically from the surface of the substrate through interconnect 122d and interconnect 122e, which may start from interconnect 122d and / or interconnect 122e and extend in a direction away from an interior and / or central portion of the substrate.

[0037] 6 shows a longitudinal cross-sectional view of the package 100 along the line BB. The package 100 includes a substrate 102, an integrated device 103, and an integrated device 105. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 includes an interconnect 122g and an interconnect 122h. The interconnect 122g may represent an embedded escape interconnect. The interconnect 122h may be embedded in the at least one dielectric layer 120 and may also protrude from the at least one dielectric layer 120. That is, a portion of the interconnect 122h is located in the at least one dielectric layer 120, and a portion of the interconnect 122h is present outside the dielectric layer 120. A portion of the interconnect 122h may be located laterally with respect to the solder resist layer 140. A portion of the interconnect 122h may be on the same metal layer as the interconnect 122g. The interconnect 122h may be similar to the interconnect 250c. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of pillar interconnects 130 and / or a plurality of solder interconnects 132. The integrated device 105 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of pillar interconnects 150 and / or a plurality of solder interconnects 152. The integrated device 103 is configured to be electrically coupled to the integrated device 105 via the interconnect 122g of the substrate 102. Electrical paths for input / output (I / O) signals and / or currents between integrated device 103 and integrated device 105 may include pillar interconnects from multiple pillar interconnects 130, solder interconnects from multiple solder interconnects 132, interconnect 122g, solder interconnects from multiple solder interconnects 152, and pillar interconnects from multiple pillar interconnects 150.

[0038] 7 shows a longitudinal cross-sectional view of the package 100 taken along the CC cross section. The package 100 includes a substrate 102, an integrated device 103, and an integrated device 105. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 includes an interconnect 122i. The interconnect 122i may represent a surface escape interconnect (e.g., 107c). The interconnect 122i may represent an intermediate escape interconnect.

[0039] FIG. 8 shows a longitudinal cross-sectional view of the package 800 along the line BB. The package 800 is similar to the package 100 and includes similar components to the package 100. As shown in FIG. 8, the substrate of the package 800 includes a post interconnect (e.g., a post). The package 800 includes a substrate 102, an integrated device 103, and an integrated device 105. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 includes an interconnect 122j. The interconnect 122j may represent a surface interconnect (e.g., 250c). The interconnect 122j may include a pad (e.g., a pad interconnect) and a post (e.g., a post interconnect). A solder interconnect from the plurality of solder interconnects 152 is coupled to the interconnect 122j (e.g., a solder interconnect is coupled to a post of the interconnect 122j).

[0040] The integrated device (e.g., 103, 105) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may include a chiplet. Chilets may be manufactured using a process that provides better yields compared to other processes used to manufacture other types of integrated devices, which may lower the overall cost of manufacturing the chiplet. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects having different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., one or more integrated devices).Using several chiplets to perform several functions can reduce the overall cost of the package compared to using a single chip to perform all of the package's functions.

[0041] The substrate may have a different number of metal layers. Different implementations may use different substrates. The substrate may include an embedded trace substrate (ETS). At least one dielectric layer 120 may include a prepreg. One example of fabricating the substrate is further described below in Figures 9A-9D.

[0042] The package (e.g., 100, 800) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 800) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 100) may be configured to transmit and receive signals having different frequencies and / or different communication protocols.

[0043] Having described various substrates having escape interconnects, the sequence and method for manufacturing substrates having escape interconnects will now be described below.

[0044] Exemplary sequence for manufacturing a substrate with escape interconnects 9A-9D show an example sequence for preparing or manufacturing a substrate. In some implementations, the sequence of FIG. 9A-9D can be used to prepare or manufacture a substrate 102 as described in this disclosure.

[0045] 9A-9D may combine one or more steps to simplify and / or clarify the sequence for preparing or manufacturing the substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be swapped or substituted without departing from the spirit of the disclosure. Different implementations may manufacture the substrate in different ways.

[0046] As shown in FIG. 9A, stage 1 shows the state after the core layer 900 is prepared. The core layer 900 includes a metal layer 901. The metal layer 901 may include a seed layer (e.g., a copper seed layer). Another metal layer may be disposed on the other side of the core layer. Note that the following process is described through a manufacturing process that forms interconnects and a dielectric layer on one side of the core layer. However, in some implementations, the interconnects and the dielectric layer may be formed on both sides of the core layer 900. The core layer 900 is an example of a carrier used as a base. In some implementations, other carriers, such as glass or quartz, may be used.

[0047] Stage 2 shows the state after interconnects 902 are formed over the core layer 900 and the metal layer 901. The interconnects 902 may be patterned from the metal layer. Plating and etching processes may be used to form the metal layer and the interconnects. At least some of the interconnects 902 may include escape interconnects (e.g., buried escape interconnects).

[0048] Stage 3 shows the state after a dielectric layer 920 is formed over the core layer 900 and the interconnects 902. The dielectric layer 920 may include polyimide. A deposition process and / or a lamination process may be used to form the dielectric layer 920. However, different implementations may use different materials for the dielectric layer.

[0049] Stage 4 shows the state after a number of cavities 910 have been formed in the dielectric layer 920. The number of cavities 910 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0050] Stage 5 shows the state after interconnects 912 have been formed in and over dielectric layer 920. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0051] Stage 6 shows the state after another dielectric layer 922 is formed over the dielectric layer 920. The dielectric layer 922 can be the same material as the dielectric layer 920. However, different implementations can use different materials for the dielectric layer. A deposition process and / or lamination process can be used to form the dielectric layer 922.

[0052] 9B, stage 7 shows the state after a number of cavities 930 have been formed in the dielectric layer 922. The cavities 930 can be formed using an etching process or a laser process.

[0053] Stage 8 shows the state after interconnects 914 have been formed in and over dielectric layer 922. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0054] Stage 9 shows the state after another dielectric layer 924 is formed over dielectric layer 922. Dielectric layer 924 can be the same material as dielectric layer 920. However, different implementations can use different materials for the dielectric layer. A deposition process and / or lamination process can be used to form dielectric layer 924.

[0055] Stage 10 shows the state after a number of cavities 940 have been formed in the dielectric layer 924. The cavities 1440 may be formed using an etching process or a laser process.

[0056] 9C, stage 11 shows the state after interconnects 916 have been formed in and over dielectric layer 924. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0057] Some or all of the interconnects 902, 912, 914, and / or 916 may define a plurality of interconnects 122 in the substrate 102. The dielectric layers 920, 922, 924 may be represented by at least one dielectric layer 120.

[0058] Stage 12 shows the state after the core layer 900 has been peeled (e.g., removed, ground away) from the metal layer 901 and dielectric layer 120, leaving a substrate 102 having a plurality of interconnects 122 and the metal layer 901.

[0059] Stage 13 shows the state after a mask 970 has been formed over metal layer 901. Mask 970 can be formed using a deposition process.

[0060] As shown in FIG. 9D, step 14 shows after mask 970 has been exposed and developed to form the mask pattern.

[0061] Stage 15 shows the state after metal layer 901 has been etched (e.g., photoetched) to form an interconnect and mask 970 has been removed. For example, metal layer 901 can be etched to form interconnect 122c, which can be a surface escape interconnect.

[0062] Stage 16 shows the state after a solder resist layer 140 is formed on a first surface of at least one dielectric layer 120 and a solder resist layer 142 is formed on a second surface of at least one dielectric layer 120. Stage 16 may show substrate 102 including interconnect 122a, interconnect 122b, interconnect 122c, interconnect 122d, and interconnect 122e. Some of the interconnects from the plurality of interconnects 122 may be buried escape interconnects and surface escape interconnects.

[0063] 1 is an exemplary flow diagram of a method for manufacturing a substrate with escape interconnects; In some implementations, manufacturing a substrate includes several processes. Figure 10 shows an example flow diagram of a method 1000 for preparing or manufacturing a substrate. In some implementations, the method 1000 of Figure 10 can be used to prepare or manufacture the substrate 102.

[0064] It should be noted that the method of Figure 10 may combine one or more processes to simplify and / or clarify the method for preparing or manufacturing a substrate, and in some implementations, the order of the processes may be changed or modified.

[0065] The method provides (at 1005) a core layer 900 including a metal layer 901. Different implementations may use different materials for the core layer. Note that the core layer is one example of a carrier that may be used. However, other carriers may be used. For example, the carrier may include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 9A illustrates and describes one example of a state after a core layer having a metal layer is provided.

[0066] The method forms (at 1010) a metal layer over the core layer 900 and the metal layer 901. The metal layer can be patterned to form interconnects 902. A plating process can be used to form the metal layer and the interconnects. The interconnects 902 can include escape interconnects (e.g., buried escape interconnects). Stage 2 of Figure 9A illustrates and describes one embodiment of the state after the metal layer and the interconnects 902 have been formed.

[0067] The method forms (at 1015) a dielectric layer 920 over the core layer 900, the metal layer 901, and the interconnect 902. The dielectric layer 920 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 910) in the dielectric layer 920. The plurality of cavities may be formed using an etching process (e.g., a photoetching process) or a laser process. Steps 3 and 4 of FIG. 9A illustrate and describe one embodiment of forming the dielectric layer and the cavities in the dielectric layer.

[0068] The method forms (at 1020) an interconnect in and over the dielectric layer. For example, interconnect 912 may be formed in and over dielectric layer 920. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and / or within the dielectric layer. Step 5 of Figure 9A illustrates and describes one embodiment of forming an interconnect in and over the dielectric layer.

[0069] The method forms (at 1025) a dielectric layer 922 over the dielectric layer 920 and the interconnect. The dielectric layer 922 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 930) in the dielectric layer 922. The plurality of cavities may be formed using an etching process or a laser process. Steps 6 and 7 in Figures 9A and 9B illustrate forming the dielectric layer and the cavities in the dielectric layer.

[0070] The method forms (at 1030) an interconnect in and / or over the dielectric layer. For example, the interconnect 914 may be formed. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and within the dielectric layer. Step 8 of Figure 9B illustrates and describes one embodiment of forming an interconnect in and over the dielectric layer.

[0071] The method may continue by forming additional dielectric layer(s) and additional interconnects as described at 1025 and 1030. Steps 9-11 of Figures 9B and 9C illustrate and describe one embodiment of forming additional interconnects in and over the dielectric layers.

[0072] Once all of the dielectric layer(s) and additional interconnects have been formed, the method may proceed to peel (at 1035) the core layer (e.g., 900) from the dielectric layer 920 (e.g., removing, grinding away), leaving the substrate. Step 12 in Figure 9C illustrates and describes one embodiment of the state after the core layer has been peeled away.

[0073] The method may also form an interconnect by forming (at 1035) an interconnect on a surface of at least one dielectric layer 120. A masking, exposing, developing, etching, and mask removal process may be used to form the surface interconnect. The surface interconnect may include a surface escape interconnect. The surface interconnect may be formed from the metal layer 901. Steps 13-15 of Figures 9C and 9D illustrate and describe one embodiment of forming a surface interconnect.

[0074] The method may include forming (at 1040) a solder resist layer (e.g., 140, 142) on the substrate. The solder resist layer may be formed using a lamination, coating, and / or exposure process. Step 16 of Figure 9D illustrates and describes one embodiment of a state after the solder resist layer is formed.

[0075] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0076] Exemplary sequence for manufacturing a package including a substrate with escape interconnects 11 illustrates an exemplary sequence for preparing or manufacturing a package including a substrate with an escape interconnect. In some implementations, the sequence of FIG. 11 can be used to prepare or manufacture a package 100 including a substrate with an escape interconnect as described in this disclosure.

[0077] It should be noted that the sequence of FIG. 11 may combine one or more steps to simplify and / or clarify the sequence for preparing or manufacturing the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure. The sequence of FIG. 11 may be used to manufacture packages one at a time, or to manufacture several packages at once (as part of a wafer).

[0078] As shown in FIG. 11, stage 1 shows a state after the substrate 102 is prepared. The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 may be manufactured using a process similar to that shown in FIGS. 9A-9D. However, different implementations may use different processes to manufacture the substrate 102. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 may include buried escape interconnects and surface escape interconnects, as described at least in FIGS. 2-8. The plurality of escape interconnects may include a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer.

[0079] Stage 2 shows the state after the integrated device 105 is bonded to the first surface (e.g., top surface) of the substrate 102. The integrated device 105 can be bonded to the substrate 102 via the pillar interconnects 150 and the solder interconnects 152. The pillar interconnects 150 and / or the solder interconnects 152 are bonded to the interconnects 122. A solder reflow process can be used to bond the integrated device 105 to the escape interconnects via the pillar interconnects 150 and the solder interconnects 152. The same implementation can also bond more than one integrated device to the substrate 102. For example, the integrated device 103 can be bonded to the first surface of the substrate 102 via the pillar interconnects 130 and the solder interconnects 132. Integrated device 103 may be configured to be electrically coupled to integrated device 105 via embedded escape interconnects and surface escape interconnects of substrate 102, as described above in at least Figures 2-8.

[0080] Stage 3 shows the state after the plurality of solder interconnects 110 have been bonded to the substrate 102. The plurality of solder interconnects 110 may be bonded to interconnects disposed on the second surface of the at least one dielectric layer 120. A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate 102. Stage 3 may show the package 100. The packages (e.g., 100) described in this disclosure may be manufactured one at a time or may be manufactured integrally as part of one or more wafers and then singulated into individual packages.

[0081] 1 is an exemplary flow diagram of a method for manufacturing a package including a substrate with escape interconnects; In some implementations, manufacturing a package including a substrate with escape interconnects includes several processes. Figure 12 shows an example flow diagram of a method 1200 for preparing or manufacturing a package including a substrate with escape interconnects. In some implementations, the method 1200 of Figure 12 can be used to prepare or manufacture the package 100 of Figure 1 described in this disclosure. However, the method 1200 can also be used to prepare or manufacture any of the packages described in this disclosure (e.g., 800).

[0082] It should be noted that the method of Figure 12 may combine one or more processes to simplify and / or clarify a method for preparing or manufacturing a package that includes a substrate with escape interconnects. In some implementations, the order of the processes may be changed or modified.

[0083] The method provides (at 1205) a substrate (e.g., 102) having an escape interconnect. The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 may include an escape interconnect. For example, the plurality of escape interconnects may include a first buried trace, a second buried trace, and a third trace. The third trace is disposed between the first buried trace and the second buried trace. The third trace is a surface trace. The plurality of escape interconnects may include a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer. Different implementations may prepare different substrates. A process similar to that shown in FIGS. 9A-9D may be used to manufacture the substrate 102. However, different implementations may use different processes to manufacture the substrate 102. Stage 1 of FIG. 11 illustrates and describes one example of preparing a substrate with escape interconnects.

[0084] The method includes (at 1210) bonding at least one integrated device (e.g., 103) to a first surface of a substrate (e.g., 102). For example, the integrated device 103 may be bonded to the substrate 102 via a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The plurality of pillar interconnects 130 and the plurality of solder interconnects 132 are bonded to a plurality of interconnects (e.g., 122a). A solder reflow process may be used to bond the integrated device 103 to the plurality of interconnects via the plurality of pillar interconnects 130 and the plurality of solder interconnects 132. Stage 2 of FIG. 11 illustrates and describes one embodiment of an integrated device being bonded to a substrate.

[0085] The method continues (at 1215) by bonding a plurality of solder interconnects (e.g., 150) to a second surface of the substrate (e.g., 102). A solder reflow process may be used to bond the plurality of solder interconnects to the substrate. Step 3 of Figure 11 illustrates and describes one embodiment of bonding the solder interconnects to the substrate.

[0086] Exemplary Electronic Devices FIG. 13 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1302, a laptop computer device 1304, a fixed location terminal device 1306, a wearable device 1308, or an autonomous vehicle 1310 may include a device 1300 as described herein. The device 1300 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1302, 1304, 1306, and 1308, and the vehicle 1310 illustrated in FIG. 13 are merely examples. Other electronic devices may also be equipped with device 1300, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, portable data units such as handheld personal communication system (PCS) units, personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0087] One or more of the components, processes, features, and / or functions shown in Figures 1-8, 9A-9D, and / or 10-13 may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1-8, 9A-9D, and / or 10-13 and corresponding descriptions thereof in this disclosure are not limited to dies and / or ICs. In some implementations, devices and / or integrated devices may be manufactured, fabricated, prepared, and / or produced using Figures 1-8, 9A-9D, and / or 10-13 and corresponding descriptions thereof in this disclosure. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0088] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0089] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. Use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The term "encapsulating" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component and vice versa.As described in this disclosure, a first component disposed "over" a second component can mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be disposed above (e.g., above) a first surface of the second component, and a third component may be disposed above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed above another component, the term "over" as used herein can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on (e.g., on a surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0090] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), a ground, and / or a power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0091] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0092] In the following, further examples are described to facilitate understanding of the invention.

[0093] Aspect 1: A package comprising a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects including a plurality of escape interconnects. The plurality of escape interconnects includes a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect.

[0094] Aspect 2: The package of aspect 1, wherein the third escape interconnect comprises a surface escape interconnect.

[0095] Example 3: The package of Examples 1 and 2, wherein the second integrated device is configured to be electrically coupled to the first integrated device via a plurality of escape interconnects.

[0096] Aspect 4: A package of aspects 1 to 3, wherein the first buried escape interconnect includes a first buried escape pad and a first buried trace, the second buried escape interconnect includes a second buried escape pad and a second buried escape trace, and the third escape interconnect includes a first surface escape pad and a first surface escape trace.

[0097] Aspect 5: The package of aspect 4, wherein the second integrated device is configured to be electrically coupled to the first integrated device via the first buried escape pad, the first buried escape trace, the second buried escape pad, the second buried escape trace, the first surface escape pad, and the first surface escape trace.

[0098] Aspect 6: The package of aspect 5, wherein a first electrical path between the first integrated device and the second integrated device includes a first buried escape pad and a first buried escape trace, a second electrical path between the first integrated device and the second integrated device includes a second buried escape pad and a second buried escape trace, and a third electrical path between the first integrated device and the second integrated device includes a first surface escape pad and a first surface escape trace.

[0099] Aspect 7: The package of Aspects 1-6, wherein the minimum width of the first embedded escape interconnect, the second embedded escape interconnect, and the third escape interconnect is in the range of about 10-15 micrometers. In some implementations, the minimum width is the width of the first embedded escape interconnect, the second embedded escape interconnect, and the third escape interconnect.

[0100] Aspect 8: The package of Aspects 1-7, wherein a first minimum spacing between the first embedded escape interconnect and the third escape interconnect is in a first range of about 10-15 micrometers and a second minimum spacing between the second embedded escape interconnect and the third escape interconnect is in a second range of about 10-15 micrometers. In some implementations, the first minimum spacing is the first spacing between the first embedded escape interconnect and the third escape interconnect. In some implementations, the second minimum spacing is the second spacing between the second embedded escape interconnect and the third escape interconnect.

[0101] Example 9: The package of Examples 1-8, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0102] Aspect 10: A package of aspects 1-9, wherein a portion of the third escape interconnect is arranged parallel to a portion of the first buried escape interconnect and a portion of the second buried escape interconnect, and the third escape interconnect is arranged on a different metal layer than the first buried escape interconnect and the second buried escape interconnect.

[0103] A package comprising: a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate, the substrate including at least one dielectric layer, a means for a first buried escape interconnection, a means for a second buried escape interconnection, and a means for a surface escape interconnection, the means for the surface escape interconnection being disposed between the means for the first buried escape interconnection and the means for the second buried escape interconnection.

[0104] Example 12: The package of example 11, wherein the means for surface escape interconnection includes an intermediate escape interconnect.

[0105] Example 13: The package of examples 11 and 12, wherein the second integrated device is configured to be electrically coupled to the first integrated device via the means for the first embedded escape interconnection, the means for the second embedded escape interconnection, and the means for the surface escape interconnection.

[0106] Example 14: A package of Examples 11-13, wherein the means for the first buried escape interconnection includes a first buried escape pad and a first buried trace, the means for the second buried escape interconnection includes a second buried escape pad and a second buried escape trace, and the means for the surface escape interconnection includes a first surface escape pad and a first surface escape trace.

[0107] Example 15: The package of example 14, wherein the second integrated device is configured to be electrically coupled to the first integrated device via the first buried escape pad, the first buried escape trace, the second buried escape pad, the second buried escape trace, the first surface escape pad, and the first surface escape trace.

[0108] Example 16: The package of example 15, wherein a first electrical path between the first integrated device and the second integrated device includes a first buried escape pad and a first buried escape trace, a second electrical path between the first integrated device and the second integrated device includes a second buried escape pad and a second buried escape trace, and a third electrical path between the first integrated device and the second integrated device includes a first surface escape pad and a first surface escape trace.

[0109] Embodiment 17: The package of embodiments 11 to 16, wherein the widths of the first means for buried escape interconnection, the means for second buried escape interconnection, and the means for surface escape interconnection are in the range of approximately 10 to 15 micrometers.

[0110] Embodiment 18: A package of embodiments 11-17, wherein a first spacing between the means for the first buried escape interconnection and the means for the surface escape interconnection is in a first range of approximately 10 to 15 micrometers, and a second spacing between the means for the second buried escape interconnection and the means for the surface escape interconnection is in a second range of approximately 10 to 15 micrometers.

[0111] Example 19: The package of Examples 11-18, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0112] Embodiment 20: A package of embodiments 11 to 19, wherein a portion of the means for surface escape interconnection is arranged in parallel with a portion of the means for the first buried escape interconnection and a portion of the means for the second buried escape interconnection, and the means for surface escape interconnection is arranged on a different metal layer than the means for the first buried escape interconnection and the means for the second buried escape interconnection.

[0113] Aspect 21: A method for manufacturing a package. The method includes preparing a substrate, the substrate including at least one dielectric layer and a plurality of interconnects including a plurality of escape interconnects. The plurality of escape interconnects includes a first buried escape interconnect, a second buried escape interconnect, and a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect. The method includes bonding a first integrated device to the substrate. The method includes bonding a second integrated device to the substrate.

[0114] Example 22: The method of example 21, wherein the second integrated device is configured to be electrically coupled to the first integrated device via a plurality of escape interconnects.

[0115] Aspect 23: The method of aspects 21 and 22, wherein a portion of the third escape interconnect is arranged parallel to a portion of the first buried escape interconnect and a portion of the second buried escape interconnect, and the third escape interconnect is arranged on a different metal layer than the first buried escape interconnect and the second buried escape interconnect.

[0116] Various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0117] 100 packages 102 Substrate 103 Integrated Devices 105 Integrated Devices 107 Escape Interconnector 107a~e Escape interconnector 110 Interconnector 120 Dielectric layer 122 Interconnector 122a~j Interconnectors 130 Pillar interconnector 132 Interconnector 140 Resist layer 142 Resist layer 150 Pillar Interconnector 152 Interconnector 152a Interconnector 152b Interconnector 201 areas 203 First Bump Area 205 Second Bump Area 230 Interconnector 230a~e Interconnectors 250 Interconnectors 250a~e Interconnector 302a~e Interconnectors 800 packages 900 Core Layer 901 Metal layer 902 Interconnector 910 Cavity 912 Interconnector 914 Interconnector 916 Interconnector 920 Dielectric layer 922 Dielectric layer 924 Dielectric layer 930 Cavity 940 Cavity 970 Mask 1300 devices 1302 Mobile Phone Devices 1304 Laptop Computer Devices 1306 Fixed Location Terminal Device 1308 Wearable Devices 1310 Autonomous Vehicles 1310 Vehicle 1440 Cavity

Claims

1. A substrate, at least one dielectric layer; a plurality of interconnects including a plurality of escape interconnects, wherein the plurality of escape interconnects include: a first embedded escape interconnect; a second embedded escape interconnect; and a substrate including a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; the first buried escape interconnect and the second buried escape interconnect are embedded in the at least one dielectric layer; the third escape interconnect comprises a surface escape interconnect; package.

2. The package of claim 1 , wherein the second integrated device is configured to be electrically coupled to the first integrated device via the plurality of escape interconnects.

3. the first buried escape interconnect includes a first buried escape pad and a first buried trace; the second buried escape interconnect includes a second buried escape pad and a second buried escape trace; the third escape interconnect includes a first surface escape pad and a first surface escape trace; The package of claim 1.

4. 4. The package of claim 3, wherein the second integrated device is configured to be electrically coupled to the first integrated device via the first buried escape pad, the first buried escape trace, the second buried escape pad, the second buried escape trace, the first surface escape pad, and the first surface escape trace.

5. a first electrical path between the first integrated device and the second integrated device including the first buried escape pad and the first buried escape trace; a second electrical path between the first integrated device and the second integrated device including the second buried escape pad and the second buried escape trace; a third electrical path between the first integrated device and the second integrated device includes the first surface escape pad and the first surface escape trace; 5. The package of claim 4.

6. 10. The package of claim 1, wherein the first buried escape interconnect, the second buried escape interconnect, and the third escape interconnect have a minimum width in the range of approximately 10 to 15 micrometers.

7. a first minimum spacing between the first buried escape interconnect and the third escape interconnect in a first range of approximately 10 to 15 micrometers; a second minimum spacing between the second buried escape interconnect and the third escape interconnect in a second range of about 10 to 15 micrometers; The package of claim 1.

8. The package of claim 1 , wherein the first integrated device comprises a first chiplet and the second integrated device comprises a second chiplet.

9. a portion of the third escape interconnector is disposed in parallel with a portion of the first buried escape interconnector and a portion of the second buried escape interconnector; the third escape interconnect is disposed on a different metal layer than the first buried escape interconnect and the second buried escape interconnect; The package of claim 1.

10. 1. A method for manufacturing a package, comprising: at least one dielectric layer; a plurality of interconnects including a plurality of escape interconnects, wherein the plurality of escape interconnects include: a first embedded escape interconnect; a second embedded escape interconnect; and providing a substrate including a third escape interconnect disposed between the first buried escape interconnect and the second buried escape interconnect; bonding a first integrated device to the substrate; and bonding a second integrated device to the substrate; the first buried escape interconnect and the second buried escape interconnect are embedded in the at least one dielectric layer; The method, wherein the third escape interconnect comprises a surface escape interconnect.

11. The method of claim 10 , wherein the second integrated device is configured to be electrically coupled to the first integrated device via the plurality of escape interconnects.

12. a portion of the third escape interconnector is disposed in parallel with a portion of the first buried escape interconnector and a portion of the second buried escape interconnector; the third escape interconnect is disposed on a different metal layer than the first buried escape interconnect and the second buried escape interconnect; The method of claim 10.

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