Electronic devices with improved board-level reliability

Abstract

The electronic device (100) includes a semiconductor die (120), a package structure (108) surrounding the semiconductor die (120), and conductive leads (110) having first and second surfaces (131, 132). The first surface (131) has a bilayer (111, 112) exposed along a bottom side (105) of the package structure (108), and the second surface (132) is exposed along another side (101) of the package structure (108). The bilayer (111, 112) includes first and second plating layers (111, 112), with the first plating layer (111) on and in contact with the first surface (131) of the conductive lead (110) and the second plating layer (112) on and in contact with the first plating layer (111) and exposed along the bottom side (105) of the package structure (108). The first plating layer (111) includes cobalt and the second plating layer (112) includes tin.

Description

[Technical field]

[0001] Copper integrated circuit leads can be tin plated prior to soldering to a printed circuit board to reduce degradation of material properties and improve shelf life. However, tin plating of bare copper leads can affect the board level reliability (BLR) of electronic systems due to cracks and material defects in the solder joints of the integrated circuit leads and the solder pads of the printed circuit board. Heat dissipation through die attach structures is also important to reduce degradation and improve operation of electronic devices at high temperatures for smaller, more highly integrated systems with smaller features and higher currents. Summary of the Invention

[0002] In one aspect, an electronic device includes a semiconductor die, a package structure surrounding the semiconductor die, and conductive leads having first and second surfaces, the first surface having a bilayer exposed along a bottom side of the package structure and the second surface exposed along another side of the package structure, the bilayer including first and second plating layers, the first plating layer on and in contact with the first surface of the conductive leads, the second plating layer on and in contact with the first plating layer, exposed along the bottom side of the package structure, the first plating layer including cobalt, and the second plating layer including tin.

[0003] In another aspect, a method includes forming a first plating layer comprising cobalt on first surfaces of conductive leads exposed along bottom sides of molded structures in a panel array of a future electronic device, forming a second plating layer comprising tin on the first plating layer, and separating the electronic device from the panel array with the conductive leads exposed along the bottom sides of respective package structures and second surfaces of the conductive leads exposed along a first side of the package structures.

[0004] In yet another aspect, an electronic device includes a semiconductor die, a die attach pad, a plated copper layer, and a package structure. The semiconductor die has a side and a metal layer on the side of the semiconductor die, the metal layer comprising nickel. The die attach pad has an opening, and the semiconductor die is attached to the die attach pad with the side of the semiconductor die facing the opening in the die attach pad. The plated copper layer extends over and is in contact with the metal layer, the plated copper layer extends from the metal layer in a direction away from the semiconductor die and into the opening in the die attach pad, and the package structure surrounds a portion of the semiconductor die.

[0005] In another aspect, a method includes attaching a semiconductor die to a die attach pad with a metal layer along a side of the semiconductor die comprising nickel facing an opening in the die attach pad, forming a package structure enclosing a portion of the semiconductor die and exposing the opening in the die attach pad, the method further includes performing an electroless plating process to form a plated copper layer on and in contact with the metal layer on the side of the semiconductor die, the plated copper layer extending from the metal layer in a direction away from the semiconductor die and into the opening in the die attach pad, and performing a package separation process to separate the electronic device from the panel array. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view of an electronic device.

[0007] [Figure 1A] FIG. 2 is a bottom view of the electronic device of FIG.

[0008] [Figure 1B] FIG. 2 is a partial cross-sectional side view of the electronic device of FIGS. 1 and 1A.

[0009] [Diagram 2] 1 is a flow chart of a method for manufacturing an electronic device.

[0010] [Diagram 3] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing a manufacturing process according to FIG. 2. [Figure 4] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing a manufacturing process according to FIG. 2. [Diagram 5] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing a manufacturing process according to FIG. 2. [Figure 6] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing a manufacturing process according to FIG. 2. [Figure 7] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing a manufacturing process according to FIG. 2. [Figure 8] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing a manufacturing process according to FIG. 2.

[0011] [Figure 9] FIG. 1 is a perspective view of an electronic device.

[0012] [Figure 9A] FIG. 2 is a bottom view of the electronic device.

[0013] [Figure 9B] FIG. 9B is a cross-sectional side view of the electronic device of FIG. 9 and FIG. 9A.

[0014] [Figure 10] 1 is a flow chart of a method for manufacturing an electronic device.

[0015] [Figure 11] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 12] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 13] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 14] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 15] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 16] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 17] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. [Figure 18] 11 is a partial cross-sectional side view of the electronic device of FIGS. 9-9B undergoing manufacturing processing according to the method of FIG. 10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. Also, the term "couple" includes an indirect or direct electrical or mechanical connection, or a combination thereof. For example, if a first device couples to or is coupled to a second device, the connection may be through a direct electrical connection, or may be through an indirect electrical connection via one or more intervening devices and connections.

[0017] 1-1B show an electronic device 100 with electroplated copper leads using cobalt and tin after molding to improve BLR performance with electroplated cobalt having minimal defects and larger grain size that provides a diffusion barrier layer against copper and tin interdiffusion. Since cobalt and copper have very low solubility in each other, the formation of intermetallic compounds (IMCs) such as Cu3Sn and Cu6Sn5 is slowed down resulting in higher BLR performance. Cobalt-tin intermetallic compounds also have high fracture toughness and high ductility resulting in solder voids at the interface and reducing the likelihood of cracking at the interface between the cobalt copper IMC and the matte plated tin. The described example allows copper integrated circuit leads to be tin plated prior to soldering to a printed circuit board to reduce degradation of material properties and improve shelf life while improving the BLR of the electronic system once the electronic device is soldered to a host printed circuit board.

[0018] The electronic device 100 of FIGS. 1-1B is shown in an example position in three-dimensional space having respective first, second, and third mutually orthogonal directions X, Y, and Z. The electronic device 100 has opposing first and second sides 101 and 102 spaced apart from one another along the first direction X and extending along a second direction Y. The electronic device 100 also includes third and fourth sides 103 and 104 spaced apart from one another along the second direction Y, a bottom side 105, and a top side spaced apart from the bottom side 105 along the third direction Z. The electronic device 100 includes a molded packaging structure 108 including sides 101-106. In the illustrated example, the bottom and top sides 105 and 106 are generally planar and extend in an XY plane of the first and second directions X and Y, respectively.

[0019] The electronic device 100 includes conductive leads 110 (e.g., copper) along lateral sides 101-104, forming a quad flat no-lead (QFN) package structure. In another implementation, the device has conductive leads on two opposing sides, providing a dual flat no-lead (DFN) package structure (not shown). As best shown in FIG. 1B, each conductive lead 110 has a first surface 131 and a second surface 132. The first surface 131 has a bilayer exposed outside the package structure 108 along a bottom side 105 of the package structure 108, and the second surface 132 is exposed outside the package structure 108 along a first side 101 of the package structure 108. The bilayer includes a first plating layer 111 and a second plating layer 112. The first plating layer 111 is on the first surface 131 of the conductive lead 110 and is in contact with the first surface 131. The first plating layer 111 includes cobalt. In one example, the first layer 111 has a thickness along the third direction Z of approximately 0.5 μm or more and approximately 2.0 μm or less. The second plating layer 112 is on and in contact with the first plating layer 111, and the second plating layer 112 is exposed outside the package structure 108 along a bottom side of the package structure 108. The second plating layer 112 includes tin, such as, for example, matte tin with a matte finish. FIG. 1B illustrates a partial cross-sectional view of an example conductive lead 110 along a first side 101 of the electronic device 100. The conductive leads on the other sides 102-104 of the electronic device 100 are similarly configured. As shown in FIG. 1, the electronic device 100 also includes a semiconductor die 120 surrounded by the package structure 108. Semiconductor die 120 has conductive bond pads electrically connected to respective leads 110 by bond wires 122 .

[0020] FIG. 2 illustrates a method 200 for manufacturing an electronic device, and FIGS. 3-8 illustrate an electronic device 100 undergoing a manufacturing process according to method 200. Method 200 includes a die attach process at 202. FIG. 3 illustrates an example in which a die attach process 300 is performed to attach a semiconductor die 120 to a die attach pad 114 of a starting leadframe strip (e.g., copper) that also includes future leads 110. Die attach pad 114 has a lower surface 302, and leads 110 have a lower first surface 131, as shown in FIG. 3. In one example, the starting leadframe has a plurality of future device portions arranged in a panel array 301 of rows and columns (not shown) of future electronic devices 100. Die attach process 300 includes simultaneous or sequential placement of a plurality of semiconductor dies 120 onto respective die attach pads 114 of panel array 301.

[0021] The method 200 continues at 204 with forming electrical connections, including electrically coupling one or more conductive terminals (e.g., bond pads) of the die 120 to the respective conductive leads 110, as well as any die-to-die connections required for a given electronic device design (e.g., die-to-die connections for a multi-chip module or MCM device, not shown). FIG. 4 illustrates an example in which a wire bonding process 400 is performed to form bond wires 122 between respective conductive bond pads of the semiconductor die 120 and associated ones of the conductive leads 110 of the starting lead frame in the panel array 301. The method 200 also includes performing at 206 a molding process to form a molded package structure 108 that encloses the semiconductor die 120 and the bond wires 122. FIG. 5 illustrates an example in which a molding process 500 is performed to form a molded package structure 108 that encloses the semiconductor die 120 and the bond wires 122.

[0022] At 208, the method 200 includes performing a first plating process to plate the first surfaces 131 of the conductive leads 110 with a first plating layer 111 comprising cobalt. Figure 6 illustrates an example in which a first plating process 600 is performed to form the first plating layer 111 on the first surfaces 131 of the conductive leads 110 exposed along the bottom side 105 of the molded structures 108 in the panel array 301 of the future electronic device 100. The first plating process 600, in one example, is an electroplating process that forms the first plating layer 111 on the exposed first surfaces 131 of the conductive leads 110 to a thickness of approximately 0.5 μm or more and approximately 2.0 μm or less, where the first plating layer 111 comprises cobalt. As discussed above, post-molding plating of the exposed first surface 131 of the underlying conductive lead 110 with cobalt prior to plating with matte tin improves BLR performance by reducing defects and including larger grain sizes that provide a diffusion barrier layer against copper and tin interdiffusion in subsequent tin plating.

[0023] The method 200 continues with matte tin plating at 210. FIG. 7 shows an example where a second plating process 700 is performed to form a second plating layer 112 comprising tin on the first plating layer 111. In one example, the second plating process 700 is an electroless plating process that forms the second plating layer 112 on the first plating layer 111. Since cobalt and copper have very low solubility in each other, the presence of cobalt in the first plating layer 111 slows down the formation of crack-prone intermetallic compounds (IMCs), such as Cu3Sn and Cu6Sn5, in the bilayer, resulting in higher BLR performance. Cobalt-tin intermetallic compounds also have high fracture toughness and high ductility, resulting in solder voids at the interface and reducing the likelihood of cracking at the interface between the cobalt copper IMC and the matte plated tin. The described examples allow copper integrated circuit leads to be tin plated prior to soldering to a printed circuit board to reduce degradation of material properties and improve shelf life, while improving the BLR of the electronic system once the electronic device is soldered to a host printed circuit board.

[0024] The method 200 continues with package separation at 212 of Figure 2. Figure 8 illustrates an example in which a package separation process 800 is performed to separate the electronic devices 100 from the panel array 301, for example, by sawing, laser cutting, or other suitable processing along lines 802. The separation process 800 separates the individual semiconductor devices 100 with the cobalt and tin plated surfaces 131 of the conductive leads 110 exposed along the bottom side of each package structure 108. The package separation process 800 exposes the second surfaces 132 of the conductive leads 110 along the sides 101-104 of the package structures 108.

[0025] 9-9B show an electronic device 900 with enhanced bottom side heat dissipation through plated copper structures in the openings of the die attach pad. Good heat dissipation through the die attach structures helps to reduce device degradation and improve device operation at high temperatures. The electronic device 900 is shown in an example position in three-dimensional space having respective first, second, and third mutually orthogonal directions X, Y, and Z. The electronic device 900 has opposing first and second sides 901 and 902 spaced apart from one another along a first direction X and extending along a second direction Y. The electronic device 900 also includes third and fourth sides 903 and 904 spaced apart from one another along the second direction Y, a bottom side 905, and a top side spaced apart from the bottom side 905 along a third direction Z. The electronic device 900 includes a molded package structure 908 including sides 901-906. In the illustrated example, the bottom and top sides 905 and 906 are generally planar and extend in an XY plane in first and second directions X and Y, respectively.

[0026] The electronic device 900 includes conductive leads 910 (e.g., copper) along sides 901-904 to form a quad flat no-lead (QFN) package structure. In another implementation, the device has conductive leads on two opposing sides to provide a dual flat no-lead (DFN) package structure (not shown). As best shown in FIG. 9B, each conductive lead 910 has an exposed bottom surface 931 along a bottom surface 905 of the package structure 908, and the conductive leads 910 on the other sides 902-904 of the electronic device 900 are similarly configured.

[0027] As shown in Figures 9 and 9B, electronic device 900 is surrounded by a package structure 908 and also includes a plated copper layer 911 to facilitate heat transfer downward from a semiconductor die 920 attached to a die attach pad 914. Die attach pad 914 has an opening 916 below a portion of semiconductor die 920. In the example of Figure 9B, die attach pad 914 has a recessed ledge 918 surrounding opening 916, and semiconductor die 920 is attached to ledge 918 of die attach pad 914. Semiconductor die 920 has conductive bond pads electrically connected to respective leads 910 by bond wires 922. Package structure 908 surrounds at least a portion of semiconductor die 920.

[0028] 9B, semiconductor die 920 has a bottom side 921 and a metal layer 923 including nickel that extends to bottom side 921 of semiconductor die 120. In one example, metal layer 923 has a thickness along third direction Z of approximately 50 nm. Semiconductor die 920 is attached to the die attach pad with side 921 of semiconductor die 920 facing opening 916 of die attach pad 914. In this example, second metal layer 919 (e.g., pad) including nickel extends over and contacts ledge 918 of the die attach pad. Second metal layer 919 also contacts metal layer 923 and plated copper layer 911. In another implementation, ledge 918 and second metal layer 919 are omitted and semiconductor die 120 is attached to the top side of the die attach pad. The metal layer 923 facilitates electroless plating to form the plated copper layer 911 during fabrication following the molding operation. The plated copper layer 911 extends from the metal layer 923 downward into the opening 916 of the die attach pad along a third direction Z away from the semiconductor die 920. In one example, the plated copper layer 911 extends to the bottom side 905 of the electronic device 900 to enable soldering to a host printed circuit board (not shown). The second metal layer 923, if included, also facilitates electroless plating to form the plated copper layer 911. In the illustrated example, the plated copper layer 911 extends over and contacts the metal layer 923. The second metal layer 919 is thicker than the metal layer 923 along the third direction Z.

[0029] 10-18, FIG. 10 illustrates a method 1000 for manufacturing an electronic device, and FIGS. 11-18 illustrate an electronic device 900 undergoing a manufacturing process according to the method 1000. The method 1000 includes spot printing a second metal layer 919 onto a ledge 918 of a die attach pad 914 of a starting leadframe panel or strip. FIGS. 11 and 11A illustrate an example of a starting leadframe panel array 1101 including a plurality of future device areas arranged in an array of rows and columns (not shown). Each future device area of ​​the leadframe panel array 1101 includes a die attach pad structure 914 with an opening 916 and a recessed ledge feature 918 laterally surrounding the opening 916. In FIGS. 12 and 12A, a printing or other deposition process 1200 is performed to deposit nickel onto selected portions of the ledge 918 to form the second metal layer 919 thereon.

[0030] Method 1000 continues with a die attach process at 1002 of Figure 10. In the illustrated implementation, bottom side 921 of semiconductor die 920 includes nickel metal layer 923. In one example, metal layer 923 has a thickness along third direction Z of approximately 50 nm, with second metal layer 919 being thicker than metal layer 923. Figures 13 and 13A show an example of the process at 1002 in which an automated pick-and-place die attach process 1300 is performed that attaches bottom side 921 of semiconductor die 920 to die attach pad 914 with nickel metal layer 923 along bottom side 921 of semiconductor die 920 facing opening 916 of die attach pad 914. In the illustrated example having a die attach pad ledge 918 and a second metal layer 919 thereon, a semiconductor die 920 is attached to the die attach pad 914 with a peripheral portion of the metal layer 923 along a side 921 of the semiconductor die 920 resting on and in contact with the second metal layer 919 on the ledge 918 of the die attach pad 914.

[0031] Method 1000 continues at 1004 with electrical connections including electrically coupling one or more conductive terminals (e.g., bond pads) of die 920 to respective conductive leads 910, as well as forming any inter-die connections required for a given electronic device design. FIGS. 14 and 14A show an example in which a wire bonding process 1400 is performed to form bond wires 922 between respective conductive bond pads of semiconductor die 920 and associated ones of the conductive leads 910 of the starting lead frame in the panel array 1101. Method 1000 also includes performing at 1006 a molding process to form a molded package structure 908 that encloses at least a portion of semiconductor die 920 and bond wires 922. FIG. 15 shows an example in which a molding process 1500 is performed to form a molded package structure 908 that encloses semiconductor die 920 and bond wires 922 and exposes die attach pad openings 916.

[0032] Method 100 further includes, at 1008 and 1010, electroless plating to form plated copper layer 911 on and in contact with metal layer 923 on side 921 of semiconductor die 920 such that plated copper layer 911 extends in a third direction Z away from semiconductor die 920 from metal layer 923 into opening 916 of die attach pad. FIGS. 16 and 17 show an example in which a deposition process 1600 is performed in FIG. 16 to apply a semi-solid gel 1602 to the backside of semiconductor die 920 in opening 916. Gel 1602 in this example is impregnated with an electroless copper solution. In FIG. 17, a thermal process 1700 is performed to apply heat to grow electroless copper from nickel metal layers 919 and 923 to form plated copper layer 911 on and in contact with metal layer 923 on side 921 of semiconductor die 920.

[0033] The method 1000 also includes performing a package separation process at 1012 to separate the manufactured electronic devices 900 from the starting panel array 1101. Figure 18 shows an example in which a package separation process 1800 is performed to separate the electronic devices 900 from the panel array 1101, for example, by sawing, laser cutting, or other suitable processing along lines 1802. The separation process 1800 separates the individual semiconductor devices 900 with the bottom sides 931 of the conductive leads 910 exposed along the bottom sides 905 of the respective package structures 908, and the package separation process 1800 exposes the sides of the conductive leads 910 along the sides 901-904 of the package structures 908 as shown in Figures 9-9B above.

[0034] The above examples are merely illustrative of some possible implementations of the various aspects of the present description, and equivalent variations and / or modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Unless otherwise indicated, "about," "approximately," or "substantially" preceding a value means within + / - 10% of the stated value. Modifications may be made to the examples described, and other implementations are possible, within the scope of the claims of this application.

Claims

1. 1. An electronic device comprising: a semiconductor die; a package structure surrounding the semiconductor die; a conductive lead having a first surface and a second surface; a bilayer on a first surface of the conductive lead, the bilayer being exposed outside the package structure along a bottom surface of the package structure, the bilayer including a first layer on the first surface of the conductive lead and a second layer on the first layer, the first layer including cobalt and the second layer including tin; Including, The electronic device, wherein the first surface of the conductive leads and the bottom surface of the package structure are coplanar.

2. 10. The electronic device of claim 1, The electronic device, wherein the first layer has a thickness of 0.5 μm or more and 2.0 μm or less.

3. 1. A method of manufacturing an electronic device, comprising: plating a first layer comprising cobalt onto first surfaces of conductive leads exposed along a bottom surface of the molded structure in a panel array of future electronic devices; plating a second layer comprising tin onto the first layer; singulating electronic devices from the panel array, the conductive leads being exposed along a bottom surface of each package structure; Including, The method wherein second surfaces of the conductive leads are exposed along a sidewall of the package structure.

4. 4. The method of claim 3, The method, wherein plating the first layer comprises electroplating the first layer having a thickness of 0.5 μm or more and 2.0 μm or less on the first surface of the conductive lead.

5. 5. The method of claim 4, The method wherein plating the second layer comprises electrolessly plating the second layer onto the first layer.

6. 4. The method of claim 3, The method wherein plating the second layer comprises electrolessly plating the second layer onto the first layer.

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