Generation of multi-plane reads to read pages on the plane of the storage die for the page to be read

Abstract

A memory controller, system, and method are provided for generating a multi-plane read for reading a page on a plane of a storage die for a page to be read. The memory controller determines a plane for a read for the page. A storage die of the multiple storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages. The page to be read is implemented within the page on the plane. The memory controller determines a threshold voltage for the page in the determined plane and determines a derived threshold voltage from the determined threshold voltage. The derived threshold voltage is used to perform a multi-plane read of the page from the determined plane.

Description

[Technical field]

[0001] The present invention relates to a memory controller, system, and method for generating a multi-plane read for reading a page on the plane of a storage die for the page to be read. [Background technology]

[0002] A solid-state storage device (e.g., a solid-state drive or SSD) may consist of one or more packages of non-volatile memory dies implementing NAND memory cells, with each die consisting of storage cells organized into pages, pages organized into blocks, and blocks stored within planes of the storage die.

[0003] In NAND flash memory devices, a page cannot be updated without erasing the entire block of pages and writing the data to a new location. To free up a block of pages, pages with valid data in use on the block must be aggregated and written to a new block to fill all pages on that new block, and then the block that previously stored the scattered pages can be erased and made available for new data.

[0004] There is a need in the art for improved techniques for reading data from a plane on a storage die as part of a garbage collection or other process. Summary of the Invention

[0005] A memory controller, system, and method are provided for generating a multi-plane read for reading a page on a plane of a storage die for a page to be read. The memory controller determines a plane for a read for the page. A storage die of the multiple storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages. The page to be read is implemented within the page on the plane. The memory controller determines a threshold voltage for the page in the determined plane and determines a derived threshold voltage from the determined threshold voltage. The derived threshold voltage is used to perform a multi-plane read of the page from the determined plane.

[0006] According to one aspect of the invention, there is provided a memory controller coupled to a plurality of storage dies having pages of data, the memory controller implementing logic for performing an operation on the storage dies, the operation being determining a plane for a read for the page, where one storage die of the plurality of storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages, and the page to read is implemented within the page on the plane, the memory controller including determining a plane; determining a threshold voltage for the page in the determined plane; determining a derived threshold voltage from the determined threshold voltage; and using the derived threshold voltage to perform a multi-plane read of the page from the determined plane.

[0007] According to another aspect of the invention, there is provided a system comprising a storage device, the storage device comprising a plurality of storage dies having pages of data, and a memory controller coupled to the storage dies, the memory controller implementing logic for performing an operation on the storage dies, the operation being determining a plane for a read for the page, where a storage die of the plurality of storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages, and the page to read is implemented within the page on the plane, the system including determining a plane, determining a threshold voltage for the page in the determined plane, determining a derived threshold voltage from the determined threshold voltage, and using the derived threshold voltage to perform a multi-plane read of the page from the determined plane.

[0008] According to another aspect of the invention, there is provided a method implemented in a memory controller for performing a multi-plane read for a plurality of storage dies having a page of data, the method including determining a plane for a read for the page, where a storage die of the plurality of storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages, and the page to be read is implemented within a page on a plane, determining a plane, determining a threshold voltage for the page in the determined plane, determining a derived threshold voltage from the determined threshold voltage, and using the derived threshold voltage to perform a multi-plane read of the page from the determined plane. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 illustrates one embodiment of a non-volatile memory storage device. [Figure 2A]FIG. 1 illustrates one embodiment of operations performed by a storage controller to generate and queue multi-plane reads to read pages from planes of a storage die as part of a garbage collection or other process. [Figure 2B] FIG. 1 illustrates one embodiment of operations performed by a storage controller to generate and queue multi-plane reads to read pages from planes of a storage die as part of a garbage collection or other process. [Diagram 3] FIG. 2C illustrates one embodiment of garbage collection logic for implementing the operations of FIGS. 2A and 2B to generate and queue multi-plane reads as part of the garbage collection process to rewrite valid data in a memory storage device for consolidation in a new location. [Figure 4] FIG. 2 illustrates a computing environment in which the components of FIG. 1 can be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] One technique for improving the programming bandwidth of NAND flash memory divided into planes of pages is through multi-plane operations such as multi-plane reads. In a multi-plane read, data is read sequentially for each of the memory planes. The program time to read multiple pages of multiple planes using a multi-plane read is equal to the time to read one page of the memory. The described embodiments provide an improved technique for generating a multi-plane read for reading pages from planes on a storage die that generates a multi-plane read for lanes up to the plane that has the page to read without having to determine a programmable starting lane. This allows a multi-plane read to be generated efficiently by using the lowest available physical lane as the starting lane.

[0011] The described embodiments further improve the process of generating multi-plane reads to read a page by determining the threshold voltage for a single page shift offset for all of the multi-plane reads for the page. Additionally, when a page is not stored on multiple planes on a lane, and multi-plane reads cannot be used, the collection of threshold voltage information is optimized since this information is not collected.

[0012] Additionally, the described embodiments provide improved techniques for determining common derived threshold voltages for a page type for use in a multi-plane read for planes having pages of that page type. If the derived threshold voltages determined for use in a multi-plane read do not satisfy certain constraints on the high and low threshold voltages given for the page type on the plane, a decision is made to use a single-plane read instead of a multi-plane read to avoid using derived threshold voltages that deviate sufficiently from the high and low threshold voltages for the page type of the pages to be read on the plane.

[0013] Figure 1 shows multiple groups of devices 1061, 1062...106 n FIG. 1 illustrates one embodiment of a non-volatile memory storage device 100 having a non-volatile memory controller 102 including a host interface 104 that transfers blocks of data and I / O commands between the non-volatile memory storage device 100 and a host system 108. Each of the devices 1061, 1062...106 n As shown with respect to device 1061, a semiconductor device may include multiple targets 110, with each target 110 having one or more dies 112. Each die 112 may be organized as multiple planes 1140, 1141, 1142, 1143. In the exemplary embodiment of FIG. 1, there are four planes per die 112. Each plane 114 iA NAND implementation contains multiple blocks, each block containing multiple pages of storage cells. In a NAND implementation, the cells forming a page may include floating gate transistors, and the cells within a block are connected to a grid connected via bit lines through their source / drain, and word lines connect through their control gates. All cells within a word line are programmed / read simultaneously, and all cells in a block are erased simultaneously.

[0014] The non-volatile memory controller 102 includes one or more storage controllers 116 for performing read and write operations to pages within the planes 1140, 1141, 1142, 1143 of the die 112. The storage controller 116, such as a flash memory controller, includes a flash translation layer (FTL) 118 for managing the mapping between logical addresses and physical addresses within the pages implemented within the planes 1140, 1141, 1142, 1143. The state machine 120 includes firmware / hardware logic for generating reads and writes to cells within the planes. The state machine 120 is configured to control the read and write operations of a single plane 114. i The device 1062...1064 may generate single plane reads, which are read requests sent to pages in multiple planes 1140, 1141, 1142, 1143, or multi-plane reads, which are read requests sent to pages in multiple planes 1140, 1141, 1142, 1143. The storage controller 116 includes multiple separate lanes 122 for each of the planes 1140, 1141, 1142, 1143 in the die 112, for example, 20 separate lanes for each plane 1140, 1141, 1142, 1143 in the die. n may have the same configuration and lines 122 as shown for device 1061.

[0015] The hardware interface 124 can be used to independently read the block page parameter (BPT) table via connection 125 from each page in the planes 1140, 1141, 1142, 1143 to determine read threshold voltages for one or more shift offsets in the page for reading during garbage collection. The number of threshold voltages for the shift offsets depends on the type of page being read. For example, for a quad level cell (QLC) where there are four bit layers per cell, the top page may have five threshold voltages for shift offsets S0, S1, S2, S3, and S4, the lower page and the upper page may have only one threshold voltage for shift offset S0, and the extra page may have three threshold voltages for shift offsets S0, S1, and S2. Thus, depending on the page type, there may be one or more read threshold voltages for different shift offsets. There may also be different shift offset numbers for different cell levels, such as single level cell (SLC), multi-level cell (MLC), tri-level cell (TLC), or other levels of cell level numbers.

[0016] For a multi-plane read, the state machine 120 determines one common threshold voltage for each shift offset depending on the page type and uses it to perform the multi-plane read for all pages of the page type in the plane. The storage controller 116 can include comparators 126 that are loaded with threshold voltages as determined by the hardware interface 124 for all planes 1140, 1141, 1142, 1143 to be read. In the described embodiment, one comparator 126 is used for all shift offsets for hardware efficiency. In an alternative embodiment, there may be a separate comparator 126 for each shift offset of threshold voltages from the planes. The comparators 126 can then perform a pairwise comparison of each pair of threshold voltages for the shift offsets to determine a high and low threshold voltage for the shift offset. This comparison is performed for the threshold voltages for each shift page offset read from the block page parameter table for each page in the valid planes 1140, 1141, 1142, 1143 read by the hardware interface 124. The state machine 120 can then determine a common threshold voltage to use for the shift offsets, e.g., S0, S1, S2, S3, S4, etc., by finding the midpoint of the high and low threshold voltages. This common threshold voltage calculated for each shift offset can then be used to perform a multi-plane read for pages of the page type on the planes 1140, 1141, 1142, 1143.

[0017] The non-volatile memory controller 102 may further include a buffer 128, such as a dynamic random access memory (DRAM) or other volatile or non-volatile memory device, for storing information generated and used by the storage controller 116 during read, write and garbage collection operations.

[0018] When preparing to read a page for garbage collection, the state machine 120 may generate in the buffer 128 a plane vector 130 that includes a matrix with a column for each plane 1140, 1141, 1142, 1143 to read and an entry / row for each lane 122 for the plane. The value in each entry indicates whether there is a valid plane on the lane represented by the entry, where a "1" can indicate a valid plane and a "0" can indicate no valid plane. The state machine 120 may further generate in the buffer 128 a super plane vector 132 with a single column, where each entry contains the OR of all entries in a row across all columns, i.e., the OR of all plane values ​​for one lane. A value of "1" in an entry of the super plane vector 132 indicates that there is at least one valid plane 1140, 1141, 1142, 1143 on the lane identified by that entry, and a value of "0" indicates that there is no valid plane on the lane identified by that entry.

[0019] The buffer 128 stores the logical address to which the I / O request is directed, and the devices 1061, 1062...1063 where the data at the logical address is stored. n The FTL 118 may further store a logical-to-physical address table 134 that provides a mapping of a logical address within the device to a physical address within the device. The logical address may include a logical block address (LBA) or other logical address known in the art. The FTL 118 uses the logical-to-physical address table 134 to determine the physical location within the device where the data is to be stored.

[0020] This architecture of the storage controller 116 and hardware interface 124 can be repeated for different dies, targets, and devices.

[0021] Non-volatile memory storage device 100 may function as both a memory device and / or a storage device (e.g., a solid state drive (SSD)) in a computing system and may be used to perform the role of a volatile memory device and a non-volatile storage medium in a computing system. In one embodiment, non-volatile memory storage device 100 may include a non-volatile memory storage device.

[0022] In one embodiment, the storage device 100 may include a block addressable memory device, such as one based on NAND or NOR technology. The memory device may use two-dimensional or three-dimensional NAND arrays. In one embodiment, the memory device may be or include a memory device using chalcogenide glass, multi-threaded level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory incorporating memristor technology, resistive memory including metal oxide based, oxygen vacancy based and conductive bridge random access memory (CB-RAM), or spin-transfer torque (STT)-MRAM, spintronic magnetic junction memory based devices, magnetic tunnel junction (MTJ) based devices, DW (domain wall) and SOT (spin orbit transfer) based devices, thyristor based memory devices, or any combination of the above, or other memories. A memory device may refer to the die itself or the packaged memory product, or both.

[0023] The host interface 104 connects the non-volatile memory storage device 100 to a host system 108. The non-volatile memory storage device 100 may be located or embedded within the host 108, as shown and described with respect to elements 408 or 410 of FIGURE 4, or the non-volatile memory storage device 100 may be external to the host system. The host interface 104 may include a bus interface such as a Peripheral Component Interconnect Express (PCIe) interface, a Serial AT Attachment (SATA), a Non-Volatile Memory Express (NVMe), or the like.

[0024] The host interface 104, the buffer 128, the one or more hardware interfaces 124, and the one or more storage controllers 116 may communicate via one or more interfaces 136, such as a PCIe or other type of bus or interface. In alternative embodiments, the connections between any of the components 104, 116, 124, 126 may include direct lines or paths rather than a shared bus.

[0025] Because flash memory is erased before it can be rewritten, a garbage collection process is used with NAND flash memory devices to consolidate valid data that has been written to a page in the memory device into a new page. Because data cannot be rewritten in place, to rewrite data in flash memory, the page of data must be read, updated, and written to a new location. The page with the source of the data copied to the new location can then be erased and reused.

[0026] 2A and 2B show devices 1061, 1062...106 n1 illustrates one embodiment of operations performed by the storage controller 116, including the comparator 126 and state machine 120, to perform a multi-plane read of a page from as part of a garbage collection or other operation. When a read operation for garbage collection or other process to read a page is initiated (at block 200), the storage controller 116 sets (at block 202) a variable i for page i that is implemented as a page on a plane 1140, 1141, 1142, 1143 to zero. For each lane 122 to a plane on the die 112, a determination is made (at block 204) of a valid plane 1140, 1141, 1142, 1143 on the lane that has page i to read. In a particular embodiment, there may be four planes 1140, 1141, 1142, 1143 on the die 112, and there may be 20 lanes 122 to each plane 1140, 1141, 1142, 1143. In alternative embodiments, there may be a different number of planes on each die 112. A storage controller 116, such as state machine 120, may generate (at block 206) a plane vector 130 that includes a matrix with a column for each plane 1140, 1141, 1142, 1143, and an entry / row for each lane, where each lane and plane entry indicates whether there is a valid plane, represented by the column, on that lane, represented by the row, of the page i to be read. A super plane vector 132 is generated (at block 208) that includes a single row vector with an entry for each lane. Each entry in the super plane vector 132 includes an OR of the values ​​in each plane column of the entry / row plane vector 130 to indicate whether the lane has at least one valid plane, e.g., a "1", or has no valid planes, e.g., a "0".

[0027] If the plane vector 130 (at block 210) indicates that page i is not implemented on multiple valid planes on one or more lanes, i.e., implemented on only one plane (only one plane in the plane vector 130 is shown as having a valid plane on each lane), the state machine 120 switches (at block 212) to a single plane read mode to generate and queue a single plane read for page i on lane 122 up to the valid plane with page i. Control then passes (at block 214) to block 256 in FIG. 2B to consider the next page to read. In a further embodiment, the super plane vector 132 may be first examined to determine if any lane has a valid plane for the page, and if so, control passes to block 210 to examine the plane vector 130. If there are no valid planes for lanes up to page i, control may pass to processing the next page.

[0028] If the plane vector 130 indicates (at block 210) that page i is implemented on multiple valid planes 1140, 1141, 1142, 1143 on the lane 122, the state machine 120 interacts with the hardware interface 124 to access (at block 216) the block page parameter table (BPT) for page i on all valid planes 1140, 1141, 1142, 1143 to determine one or more read voltage thresholds for one or more shift offsets of the page i type on page i on each valid plane 1140, 1141, 1142, 1143. The state machine 120 loads (at block 218) the threshold voltages read from page i on the valid planes 1140, 1141, 1142, 1143 into the comparator 126 for each shift offset of the page i type. There may be one comparator 126 for each shift offset of the page i type. Thus, if there are threshold voltages for shift offsets S0, S1, S2 read from page i on four valid planes, the comparator 126 will be loaded with 12 threshold voltages. For each shift offset of a page i type, the state machine 120 loads (at block 220) the comparator 126 with predefined threshold voltages of one or more invalid planes so that the comparator 126 includes threshold voltages for comparison of all planes and shift offsets. Invalid planes include planes that do not provide for page i being read on the lane being considered. Control then passes (at block 222) to block 224 in FIG. 2B.

[0029] The loaded comparator 126 determines (at block 226) from the loaded threshold voltages a high and low threshold voltage for each shift offset of the page type of page i to be read. The comparator 126 may perform a pairwise comparison of each pair of threshold voltages for the shift offsets to determine a high and low threshold voltage for the shift offset. The state machine 120 may then determine (at block 228) a derived threshold voltage for each shift offset as the midpoint of the high and low threshold voltages determined by the comparator 126 for the shift offset, e.g., S0, S1, S2, S3, etc. Derivations and calculations other than the midpoint may be used to determine a derived or common threshold voltage for use in a multi-plane read for all valid planes on the lane. After the derived threshold voltages for use in a multi-plane read of the shift offsets of the page i type are generated, a determination may be made whether the derived threshold voltage falls within a tolerance range of high and low threshold voltages for the shift offsets.

[0030] To verify the derived threshold voltages, for each shift offset of a page i type, the state machine 120 determines (at block 230) the difference of the midpoint derived threshold voltage for each of the high and low threshold voltages for the shift offset. If (at block 232) the high or low difference for any shift offset of the page i type exceeds one or more difference thresholds, indicating that the derived threshold voltage deviates too far from the high and low thresholds, the state machine 120 generates and queues (at block 234) a single plane read for page i on lane 122 to the valid planes 1140, 1141, 1142, 1143 with page i. Control then proceeds to block 256 of FIG. 2B to consider the next page to read. There may be different difference thresholds for the high and low differences and different shift offsets, or there may be one or more common difference thresholds.

[0031] If (at block 232) the high or low difference of all the shift offsets does not exceed the difference threshold, indicating the derived threshold voltages are within the acceptable deviation, then variable j for plane j is set to zero (at block 236) and variable k for lane k of lane 122 is set to zero (at block 238). If (at block 240) the plane vector 130 indicates that plane j is valid on lane k and (at block 242) the plane vector 130 indicates that plane j is the only valid plane on lane k, then state machine 120 queues (at block 244) a single plane read for page i on plane j on lane k. If (at block 242) the plane vector 130 indicates that plane j is not the only valid plane on lane k, then state machine 120 generates (at block 246) a multi-plane read to read page i on plane j on lane k using the derived threshold voltages, e.g., midpoints, for each shift offset of the page i type. This multi-plane read can be queued for later processing when all multi-plane reads for the page on the lane have been received. From block 240, block 244, or the "no" branch of block 246, control passes to block 248 for processing the next lane of page i.

[0032] If lane k is not the last lane 122 (at block 248), then k is incremented (at block 250) and control passes to block 240 to determine whether to issue a multi-plane read for the next lane k of plane j. If plane k is the last lane (at block 248) and plane j is not the last plane 1143 (at block 252), then j is incremented (at block 254) and control passes to block 240 to determine whether to issue a multi-plane read for the next lane k of plane j. p2A to generate a multi-plane read for the next page to read. If plane j is the last plane 1143 (at block 252) and page i is not the last plane to read (at block 256), then i is incremented (at block 258) and control proceeds to block 210 of FIG. 2A to generate a multi-plane read for the next page to read. If page i is the last page to read (at block 256), control ends.

[0033] According to the embodiment of operation of FIGS. 2A and 2B, state machine 120 accesses the shift offset threshold voltages for the pages in the multi-plane read using hardware interface 124 for use in calculating a common derived threshold voltage for each page offset of the page type upon a determination that the multi-plane read is to be performed. In this manner, the page offset threshold voltages are determined via hardware interface 124 prior to generating the multi-plane read. Further, according to the described embodiment, for each page to be read, each plane and all lanes up to the plane are processed to determine whether a multi-plane read should be issued if there are multiple planes on the lane providing the page for the page to be read. If there are not multiple planes on the lane, a single plane read is issued for that lane and control proceeds to consideration of the next lane for the plane and page. Because multi-plane reads are generally more efficient than single-plane reads, the described embodiment provides improved efficiency to maximize the number of multi-plane reads that can be issued to read pages on multiple planes.

[0034] FIG. 3 illustrates an embodiment of logic components comprised of circuitry and / or firmware for implementing a garbage collection unit 300 within a storage controller 116. A recirculating read engine 302 may implement the logic of FIGS. 2A and 2B to generate a multi-plane or single-plane read for each lane up to each page and each of the planes that have the page for the page to be read. The recirculating read engine 302 stores each generated multi-plane or single-plane read in a lane queue 304. Once all multi-plane reads for a lane and page have been received, the lane queue for that lane sends the multi-plane or single-plane read to the storage die 112 that has the planes 1140, 1141, 1142, 1143 to be read. Upon issuing a multi-plane read, the state machine 120 may set a flag to inform the lane queue 304 that the read is a multi-plane read and may set a count to indicate the number of planes for which the multi-plane read for lane k and page i will be generated. The lane queue 304 waits until all multi-plane reads for lane k and page i have been received, and once the full count of planes has been received, it sends all queued multi-plane reads to the storage die 112 to read page i from the valid planes 1140, 1141, 1142, 1143 on lane k.

[0035] When pages on different planes for a lane are read, the read pages are stored in resurface pool data 306. A resurface write engine 308 generates write requests to write all read pages in resurface pool data 306 into write cache 310. The write requests added to write cache 310 are then sent to write the read data to new storage locations on the storage die as part of the garbage collection process.

[0036] 4 illustrates one embodiment of a system 400 in which the non-volatile memory storage device 100 of FIG. 1 may be deployed as a system memory device 408 and / or a storage device 410. The system 400 includes a processor 404 in communication over a bus 406 with a system memory device 408 in which programs, operands and parameters being executed by the processor 404 are cached, and a storage device 410, which may include a solid state drive (SSD) that stores programs, operands, parameters and user data that may be loaded into the system memory 408 for execution by the processor 404. The processor 404 may also communicate with input / output (I / O) devices 412a, 412b, which may include input devices (e.g., keyboard, touch screen, mouse, etc.), display devices, graphics cards, ports, network interfaces, etc. The memory 408 and storage device 410 may be coupled to an interface on the motherboard of the system 400, may be mounted on the motherboard of the system 400, may be deployed in an external memory device, or may be accessible over a network.

[0037] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block of the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a special-purpose hardware-based system that performs the specified functions or actions or executes a combination of special-purpose hardware and computer instructions.

[0038] Designation letters such as i, j, k, p, n, among others, used to designate the number of instances of an element, when used with the same or different elements, can indicate variable numbers of instances of that element.

[0039] The terms "one embodiment," "embodiment," "embodiments," "the embodiment," "the embodiments," "one or more embodiments," "some embodiments," and "one embodiment" mean "one or more, but not all, embodiments of the invention," unless expressly specified otherwise.

[0040] Unless expressly stated otherwise, the terms "including," "comprising," and "having" and variations thereof mean "including, but not limited to."

[0041] An enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0042] The terms "a," "an," and "the" mean "one or more," unless expressly specified otherwise.

[0043] Devices that are in communication with each other need not be in continuous communication with each other unless explicitly specified otherwise In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediary means.

[0044] A description of an embodiment having several components in communication with each other does not imply that all such components are required, to the contrary, a variety of optional components have been described to illustrate the wide variety of possible embodiments of the present invention.

[0045] Where a single device or article is described herein, it will be readily appreciated that two or more devices / articles (whether they cooperate or not) may be used in place of the single device / article. Similarly, where two or more devices or articles are described herein (whether they cooperate or not), it will be readily appreciated that a single device / article may be used in place of the two or more devices or articles, or a different number of devices / articles may be used in place of the number of devices or programs shown. The functionality and / or features of a device may alternatively be embodied by one or more other devices not explicitly described as having such functionality / features. Thus, other embodiments of the present invention need not include the device itself.

[0046] The above description of various embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description, but rather by the appended claims. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the scope of the invention, the invention resides in the claims appended hereto.

Claims

1. 1. A memory controller coupled to a plurality of storage dies having pages of data, the memory controller implementing logic for performing operations on the storage dies, the operations comprising: determining a plane for reading a page, wherein a storage die of the storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages, and the page to read is implemented within a page on the plane; determining a threshold voltage for the page in the determined plane; determining a derived threshold voltage from the determined threshold voltage; using the derived threshold voltages to perform a multi-plane read of the page from the determined planes.

2. 2. The memory controller of claim 1, wherein the derived threshold voltages are used to read the page from the determined plane as part of a garbage collection operation for reading the page from the determined plane in order to write valid data from the read page to a page at a different location within the storage die.

3. The memory controller is coupled to the plane on the storage die through a plurality of lanes, the plane being read by issuing a multi-plane read through one of the lanes, the operation comprising: for each number of lanes to the plane, 2. The memory controller of claim 1, further comprising: determining valid planes accessible through the lanes having the lane number, wherein the determined planes read by the multi-plane read include the determined valid planes.

4. The operation includes: maintaining a plane vector for each of the planes including a value for each of the lanes up to the plane indicating whether the plane is valid for each of the lanes; and maintaining a superplane vector including a value for each of the lanes that includes an OR of the values ​​for the planes for each of the lanes indicating which lanes have at least one valid plane; Determining the valid plane for each lane includes: determining whether the super plane vector indicates there is at least one valid plane for the lane; and in response to a determination that the super plane vector indicates that there is at least one valid plane for the lane, processing the plane vector to determine the valid plane for the lane, wherein a multi-plane read targets the page for reading for each valid plane indicated in the plane vector for a lane indicated in the super plane vector as having a valid plane on the lane.

5. 4. The memory controller of claim 3, wherein determining the threshold voltage and determining the derived threshold voltage are performed for the page to be read and are used for the multi-plane read for the page on the lanes to the planes, determining the threshold voltage includes determining the threshold voltage for the page to be read on the determined valid plane, and determining the derived threshold voltage is determined from the threshold voltage read for the page to be read on the determined valid plane.

6. Determining the threshold voltages for the page to be read in the determined plane includes determining a high threshold voltage and a low threshold voltage for a page type of the page to be read in the determined plane, the operation comprising: determining whether a difference between the derived threshold voltage and the high threshold voltage and between the derived threshold voltage and the low threshold voltage exceeds at least one difference threshold; 2. The memory controller of claim 1, further comprising: generating a single plane read for the page from the determined plane in response to at least one of the derived threshold voltage and the difference between the high threshold voltage and the low threshold voltage exceeding the at least one difference threshold, wherein using the derived threshold voltage for the multi-plane read is performed in response to determining that the difference between the derived threshold voltage and the high threshold voltage and the low threshold voltage does not exceed the at least one difference threshold.

7. 7. The memory controller of claim 6, wherein the derived threshold voltage comprises a midpoint between the high threshold voltage and the low threshold voltage for the page in the plane being determined.

8. Determining the threshold voltage for the page in the determined plane includes: determining a page type of the page to be read in the plane, where different page types provide different numbers of threshold voltages with different shift offsets; determining threshold voltages from the pages to be read within the plane for the different shift offsets; 2. The memory controller of claim 1, further comprising: for each threshold voltage provided for a shift offset of the page type of the page to be read, determining a derived threshold voltage from the threshold voltages for the shift offset, wherein at least one derived threshold voltage for at least one shift offset used to read the page in the plane is used for the multi-plane read of the page in the plane.

9. 9. The memory controller of claim 8, wherein determining the derived threshold voltage from the threshold voltages for each shift offset is performed by a comparator that compares each pair of the threshold voltages pairwise to determine a high threshold voltage and a low threshold voltage for the shift offset for use in determining the derived threshold voltage for each shift offset.

10. 2. The memory controller of claim 1, wherein the operations further include, if at least one of the planes to be read is an invalid plane, determining the threshold voltage of a valid plane, and using a predefined threshold for at least one invalid plane to determine the derived threshold voltage.

11. 1. A system comprising: a storage device, the storage device comprising: a plurality of storage dies having pages of data; a memory controller coupled to the storage die, the memory controller implementing logic for performing operations on the storage die, the operations comprising: determining a plane for reading a page, wherein a storage die of the storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages, and the page to read is implemented within a page on the plane; determining a threshold voltage for the page in the determined plane; determining a derived threshold voltage from the determined threshold voltage; and using the derived threshold voltages to perform a multi-plane read of the page from the determined planes.

12. The memory controller is coupled to the plane on the storage die through a plurality of lanes, the plane being read by issuing a multi-plane read through one of the lanes, the operation comprising: for each number of lanes to the plane, 12. The system of claim 11, further comprising: determining valid planes accessible through the lanes having the lane number, wherein the determined planes read by the multi-plane read include the determined valid planes.

13. Determining the threshold voltages for the page to be read in the determined plane includes determining a high threshold voltage and a low threshold voltage for a page type of the page to be read in the determined plane, the operation comprising: determining whether a difference between the derived threshold voltage and the high threshold voltage and between the derived threshold voltage and the low threshold voltage exceeds at least one difference threshold; 12. The system of claim 11, further comprising: generating a single plane read for the page from the determined plane in response to at least one of the derived threshold voltage and the difference between the high threshold voltage and the low threshold voltage exceeding the at least one difference threshold, and using the derived threshold voltage for the multi-plane read is performed in response to determining that the difference between the derived threshold voltage and the high threshold voltage and the low threshold voltage does not exceed the at least one difference threshold.

14. Determining the threshold voltage for the page in the determined plane includes: determining a page type of the page to be read in the plane, where different page types provide different numbers of threshold voltages with different shift offsets; determining threshold voltages from the pages to be read within the plane for the different shift offsets; 12. The system of claim 11, further comprising: for each threshold voltage provided for a shift offset of the page type of the page to be read, determining a derived threshold voltage from the threshold voltage for the shift offset, wherein at least one derived threshold voltage for at least one shift offset used to read the page in the plane is used for the multi-plane read of the page in the plane.

15. 15. The system of claim 14, wherein the memory controller includes a comparator, and determining the derived threshold voltage from the threshold voltages for each shift offset is performed by the comparator comparing each pair of the threshold voltages pairwise to determine a high threshold voltage and a low threshold voltage for the shift offset for use in determining the derived threshold voltage for each shift offset.

16. A processor; 12. The system of claim 11, further comprising a system memory, wherein program code and user data are loaded from said storage device into said system memory for processing by said processor.

17. 1. A method, implemented in a memory controller, for performing a multi-plane read to multiple storage dies having a page of data, comprising: determining a plane for reading a page, wherein a storage die of the storage dies includes a plurality of planes having a plurality of blocks, the blocks having pages, and the page to read is implemented within a page on the plane; determining a threshold voltage for the page in the determined plane; determining a derived threshold voltage from the determined threshold voltage; and using the derived threshold voltages to perform a multi-plane read of the page from the determined planes.

18. The memory controller is coupled to the planes on the storage die through a plurality of lanes, and the planes are read by issuing a multi-plane read through one of the lanes, and the method includes: For each number of lanes to the plane, 20. The method of claim 17, further comprising determining valid planes accessible through the lanes having the lane number, wherein the determined planes read by the multi-plane read include the determined valid planes.

19. Determining the threshold voltages for the page to be read in the determined plane includes determining a high threshold voltage and a low threshold voltage for a page type of the page to be read in the determined plane, the operation comprising: determining whether a difference between the derived threshold voltage and the high threshold voltage and between the derived threshold voltage and the low threshold voltage exceeds at least one difference threshold; 18. The method of claim 17, further comprising: generating a single plane read for the page from the determined plane in response to at least one of the derived threshold voltage and the difference between the high threshold voltage and the low threshold voltage exceeding the at least one difference threshold, and wherein using the derived threshold voltage for the multi-plane read is performed in response to determining that the difference between the derived threshold voltage and the high threshold voltage and the low threshold voltage does not exceed the at least one difference threshold.

20. Determining the threshold voltage for the page in the determined plane includes: determining a page type of the page to be read in the plane, where different page types provide different numbers of threshold voltages with different shift offsets; determining threshold voltages from the pages to be read within the plane for the different shift offsets; 18. The method of claim 17, comprising: for each threshold voltage provided for a shift offset of the page type of the page to be read, determining a derived threshold voltage from the threshold voltage for the shift offset, wherein at least one derived threshold voltage for at least one shift offset used to read the page in the plane is used for the multi-plane read of the pages in the plane.

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