Self-Aligned Back Contact Integration of Transistors

Abstract

Provided is a semiconductor device. The semiconductor device comprises a transistor including a plurality of source / drain epitaxies. The semiconductor device further comprises at least one backside power rail beneath the transistor. The semiconductor device further comprises a backside interlayer dielectric (ILD) located between the plurality of source / drain epitaxies and the at least one power rail. The semiconductor device further comprises a first backside contact connecting the first source / drain epitaxy to the at least one backside power rail. The semiconductor device further comprises one or more contact placeholders formed beneath other source / drain epitaxies.

Description

[Technical field]

[0001] The present invention relates generally to semiconductor fabrication methods and resulting structures, and more particularly to backside interconnects that deliver power to field effect transistors in semiconductor devices and methods of forming same. [Background technology]

[0002] In integrated circuits, transistors such as metal oxide semiconductor field effect transistors (MOSFETs) have a source and a drain formed in an active region of a semiconductor layer by implanting n-type or p-type impurities into the layer of semiconductor material. Disposed between the source and drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are separated by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses a complementary and symmetric pair of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and drain, and current flows from the source to the drain through the channel region. Current flow is induced in the channel region by a voltage applied to the gate electrode through a power distribution network. Summary of the Invention

[0003] Embodiments of the invention include methods of fabrication and corresponding structures. Some embodiments of the invention include a semiconductor device. The semiconductor device comprises a transistor including a plurality of source / drain epitaxies. The semiconductor device further comprises at least one backside power rail beneath the transistor. The semiconductor device further comprises a backside inter-layer dielectric (ILD) located between the plurality of source / drain epitaxies and the at least one power rail. The semiconductor device further comprises a first backside contact connecting the first source / drain epitaxy to the at least one backside power rail. The semiconductor device further comprises one or more contact placeholders formed beneath other source / drain epitaxies.

[0004] Advantageously, the semiconductor device can overcome concerns associated with conventional designs. For example, unlike designs having backside power distribution network and frontside buried power rails, embodiments of the present invention do not unduly limit the size of the buried power rails. Additionally, unlike designs using frontside VBPR to deliver power to transistors from buried power rails, embodiments of the present invention do not suffer from middle-of-line (MOL) congestion and / or routing limitations. Furthermore, embodiments of the present invention allow source / drain epitaxy access to M1 signal lines through other (e.g., adjacent) CMOS cells. Also, embodiments of the present invention can be fabricated using self-aligned processes to ensure strong connections between the transistor source / drain epitaxy and the buried backside power rail.

[0005] In an optional embodiment, the semiconductor device further includes a secondary device region that includes one or more other devices selected from the group consisting of ESD diodes, BJTs, and passive devices. Advantageously, embodiments of the present invention allow the transistor region and the secondary device region to be easily integrated, allowing the semiconductor and secondary devices to be fabricated at the same level.

[0006] In another optional embodiment, the first back contact has a two-step shape, where the first back contact has a large top critical dimension (CD) and a small bottom CD. Advantageously, the two-step shape can facilitate self-alignment of the back contact with the source / drain epitaxy.

[0007] In another optional embodiment, each source / drain epitaxy of the multiple sources / drains is either connected to a backside power rail through a backside contact or to a contact placeholder. Advantageously, the use of a contact placeholder in the source / drain epitaxy allows for easy self-alignment of the backside contact, which can be formed by replacing one of the contact placeholders during the fabrication of the backside power rail.

[0008] Further embodiments of the invention include a nanosheet transistor. The nanosheet transistor includes a plurality of source / drain epitaxies. The nanosheet transistor further includes a backside ILD below the plurality of source / drain epitaxies. The nanosheet transistor further includes a first contact connecting the first source / drain epitaxy to a backside power rail, the first contact extending through the backside ILD. The nanosheet transistor further includes a contact placeholder in contact with the second source / drain epitaxy. The contact placeholder is disposed between the second source / drain epitaxy and the backside ILD.

[0009] Additional embodiments of the invention include semiconductor devices. The devices include a backside power distribution network (BSPDN) and one or more backside power rails connected to the BSPDN. The devices further include an ILD opposite the BSPDN and above the one or more backside power rails. The devices further include one or more nanosheet transistors. Each nanosheet transistor includes at least one backside contact connecting a first source / drain epitaxy of the respective nanosheet transistor to the backside power rail. The backside contact extends from the source / drain epitaxy through the backside ILD. Each nanosheet transistor further includes at least one placeholder contact connected to a second source / drain epitaxy.

[0010] Additional embodiments of the invention include fabrication methods, systems, and computer program products. The fabrication method includes forming an etch stop layer on a substrate. The method further includes forming a Si epitaxy layer on the etch stop layer. The method further includes forming one or more transistor regions and one or more secondary device regions on the Si epitaxy layer. The method further includes forming a backside contact placeholder under a source / drain region of the one or more transistors. The method further includes forming a middle-of-line (MOL) section and a BEOL section. The method further includes removing the substrate selectively to the etch stop layer. The method further includes removing the etch stop layer and the Si epitaxy layer from the one or more transistor regions. The method further includes forming a backside ILD. The method further includes forming one or more backside contacts through the backside ILD. The method further includes forming one or more backside power rails and a backside power distribution network on the one or more backside contacts.

[0011] The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention.

[0012] The drawings included in this disclosure are incorporated in and are a part of this specification. They illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. The drawings are merely illustrative of typical embodiments and are not intended to be limiting of the invention. [Brief description of the drawings]

[0013] [Figure 1] 1A-1C show plan views of an exemplary nanosheet transistor according to an embodiment of the present invention, showing cross-sectional views Y1, Y2, and X of the following figures. [Diagram 2] 1A-1D illustrate cross-sectional views of an exemplary semiconductor device at intermediate stages in a fabrication process in accordance with an embodiment of the present invention. [Diagram 3] 3 illustrates a cross-sectional view of the example semiconductor device of FIG. 2 following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 4A] 4 illustrates a cross-sectional view of the semiconductor device of FIG. 3 following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 4B] 4 illustrates a cross-sectional view of the semiconductor device of FIG. 3 following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 4C] 4 illustrates a cross-sectional view of the semiconductor device of FIG. 3 following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 5A] 4B illustrates a cross-sectional view of the semiconductor device of FIG. 4A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 5B] 4C illustrates a cross-sectional view of the semiconductor device of FIG. 4B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 5C] 4D illustrates a cross-sectional view of the semiconductor device of FIG. 4C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 6A]5B illustrates a cross-sectional view of the semiconductor device of FIG. 5A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 6B] 5C illustrates a cross-sectional view of the semiconductor device of FIG. 5B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 6C] 5D illustrates a cross-sectional view of the semiconductor device of FIG. 5C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 7A] 6B illustrates a cross-sectional view of the semiconductor device of FIG. 6A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 7B] 6C illustrates a cross-sectional view of the semiconductor device of FIG. 6B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 7C] 6D illustrates a cross-sectional view of the semiconductor device of FIG. 6C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 8A] 7B illustrates a cross-sectional view of the semiconductor device of FIG. 7A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 8B] 7C illustrates a cross-sectional view of the semiconductor device of FIG. 7B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 8C] 7D illustrates a cross-sectional view of the semiconductor device of FIG. 7C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 9A] 8B illustrates a cross-sectional view of the semiconductor device of FIG. 8A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 9B] 8C illustrates a cross-sectional view of the semiconductor device of FIG. 8B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 9C] 8D illustrates a cross-sectional view of the semiconductor device of FIG. 8C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 10A] 9B illustrates a cross-sectional view of the semiconductor device of FIG. 9A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 10B]9C illustrates a cross-sectional view of the semiconductor device of FIG. 9B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 10C] 9D illustrates a cross-sectional view of the semiconductor device of FIG. 9C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 11A] 10B illustrates a cross-sectional view of the semiconductor device of FIG. 10A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 11B] 10C illustrates a cross-sectional view of the semiconductor device of FIG. 10B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 11C] 10C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 12A] 11B illustrates a cross-sectional view of the semiconductor device of FIG. 11A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 12B] 11B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 12C] 11D illustrates a cross-sectional view of the semiconductor device of FIG. 11C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 13A] 12B illustrates a cross-sectional view of the semiconductor device of FIG. 12A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 13B] 12C illustrates a cross-sectional view of the semiconductor device of FIG. 12B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 13C] 12D illustrates a cross-sectional view of the semiconductor device of FIG. 12C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 14A] 13B illustrates a cross-sectional view of the semiconductor device of FIG. 13A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 14B] 13C illustrates a cross-sectional view of the semiconductor device of FIG. 13B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 14C]13D illustrates a cross-sectional view of the semiconductor device of FIG. 13C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 14D] 4 illustrates another cross-sectional view of a semiconductor device following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 15A] 14B illustrates a cross-sectional view of the semiconductor device of FIG. 14A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 15B] 14C illustrates a cross-sectional view of the semiconductor device of FIG. 14B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 15C] 14D illustrates a cross-sectional view of the semiconductor device of FIG. 14C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 15D] 14D following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 16A] 15B illustrates a cross-sectional view of the semiconductor device of FIG. 15A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 16B] 15C illustrates a cross-sectional view of the semiconductor device of FIG. 15B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 16C] 15D illustrates a cross-sectional view of the semiconductor device of FIG. 15C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 16D] 15D after performing additional fabrication operations in accordance with an embodiment of the present invention. [Figure 17A] 16B illustrates a cross-sectional view of the semiconductor device of FIG. 16A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 17B] 16C illustrates a cross-sectional view of the semiconductor device of FIG. 16B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 17C] 16D illustrates a cross-sectional view of the semiconductor device of FIG. 16C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 17D]16D following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 18A] 17B illustrates a cross-sectional view of the semiconductor device of FIG. 17A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 18B] 17C illustrates a cross-sectional view of the semiconductor device of FIG. 17B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 18C] 17D illustrates a cross-sectional view of the semiconductor device of FIG. 17C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 18D] 17D after performing additional fabrication operations in accordance with an embodiment of the present invention. [Figure 19A] 18B illustrates a cross-sectional view of the semiconductor device of FIG. 18A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 19B] 18C illustrates a cross-sectional view of the semiconductor device of FIG. 18B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 19C] 18D illustrates a cross-sectional view of the semiconductor device of FIG. 18C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 19D] 18D following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 20A] 19B illustrates a cross-sectional view of the semiconductor device of FIG. 19A following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 20B] 19C illustrates a cross-sectional view of the semiconductor device of FIG. 19B following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 20C] 19D illustrates a cross-sectional view of the semiconductor device of FIG. 19C following additional fabrication operations in accordance with an embodiment of the present invention. [Figure 20D] 19D after performing additional fabrication operations in accordance with an embodiment of the present invention. [Figure 21]1 illustrates a flow chart of an exemplary method for forming a semiconductor device in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] While the embodiments described herein are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It will be understood, however, that the particular embodiments described are not to be construed in a limiting sense. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention.

[0015] Embodiments of the present invention relate generally to semiconductor fabrication methods and resulting structures, and more particularly to backside interconnects for delivering power to field effect transistors in semiconductor devices and methods for making same, although the invention is not necessarily limited to such applications, various aspects of the invention can be understood by considering various examples thereof.

[0016] Various embodiments of the present invention are described herein with reference to the associated drawings in which like numbers refer to the same components. Alternative embodiments may be devised without departing from the scope of the present invention. It is noted that in the following description and drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are shown. Those connections and / or positional relationships can be direct or indirect unless otherwise specified, and the disclosure is not intended to be limited in this respect. Thus, the connection of entities can refer to direct or indirect connections, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, in this description, reference to forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant properties and functions of layer "A" and layer "B" are not significantly altered by the intermediate layers.

[0017] The following definitions and abbreviations are used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "including," "including," "having," "having," "containing," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or device.

[0018] For purposes of explanation below, the terms "top", "bottom", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the described structures and methods as oriented in the drawings. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, and an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating or semiconducting layer at the interface between the two elements. It should be noted that the term "selective to", e.g., "a first element selective to a second element", means that the first element can be etched and the second element can act as an etch stop.

[0019] As used herein, the articles "a" and "an" preceding an element or component are intended to be open-ended with regard to the number of instances (i.e., occurrences) of the element or component. Thus, "a" or "an" should be read as including one or at least one, and the singular form of an element or component also includes the plural, unless the number is clearly meant to be singular.

[0020] As used herein, the term "invention" or "present invention" is an open-ended term and is not intended to refer to any single embodiment of a particular invention, but rather encompasses all possible combinations described in the specification and claims.

[0021] The terms "about," "substantially," "approximately," "slightly less than," and variations thereof are intended to include the degree of error associated with the measurement of the particular quantity, based on the equipment available at the time of this application. For example, "about" may include a range of ±8%, 5%, or 2% of a given value.

[0022] For purposes of explanation below, when a first surface is said to be located "opposite" a second surface, the first surface is distinct from the second surface and the first surface is spaced apart from the second surface, and when the surfaces are substantially planar, the first surface is substantially parallel to the second surface.

[0023] Of course, as used herein, "an embodiment" refers to one or more embodiments that share a common aspect. For example, a "first embodiment" may include one or more embodiments that are related by virtue of sharing a first common aspect, function, or feature, or a combination thereof. Similarly, a "second embodiment" may include one or more embodiments that are related by virtue of sharing a second common aspect, function, or feature, or a combination thereof. Furthermore, a particular embodiment having both a first common aspect, function, or feature, or a combination thereof, and a second common aspect, function, or feature, or a combination thereof, may be considered to be both a first embodiment and a second embodiment.

[0024] For the sake of brevity, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Additionally, various operations and process steps described herein may be incorporated into more comprehensive procedures or processes that include additional steps or functions not described in detail herein. In particular, because the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are described only briefly herein or omitted entirely, without providing details of the well-known processes.

[0025] In general, the various processes used to form the microchips that will be packaged into ICs fall into four general categories: deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0026] Deposition is any process by which material is grown, coated, or otherwise transferred onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Another deposition technique is plasma enhanced chemical vapor deposition (PECVD), a process that uses energy in a plasma to drive reactions at the wafer surface that require higher temperatures than would otherwise be associated with conventional CVD. Energetic ion bombardment during PECVD deposition may improve the electrical and mechanical properties of the film.

[0027] Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry), chemical-mechanical planarization (CMP), etc. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to dry plasma etching methods that utilize a remote wide beam ion / plasma source to remove substrate material by means of physically inert and / or chemically reactive gases. Like other dry plasma etching techniques, IBE has advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal damage to the substrate. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses a chemically reactive plasma to remove material deposited on the wafer. In RIE, plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma bombard and react with the wafer surface, removing material.

[0028] Semiconductor doping is generally the modification of electrical properties by doping, for example, the source and drain of a transistor, by diffusion or by ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. Selective doping of different regions of a semiconductor substrate allows the conductivity of the substrate to be modified by the application of a voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices.

[0029] Semiconductor lithography is the formation of three-dimensional relief images or patterns on a semiconductor substrate for subsequent transfer of the pattern to a substrate. In semiconductor lithography, the patterns are formed with light-sensitive polymers called photoresists. The steps of lithography and etching pattern transfer are repeated multiple times to build the complex structures that make up the circuit's transistors and the many wires that connect millions of transistors. Each pattern printed on the wafer is aligned to an already formed pattern, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0030] Turning now to an overview of the technology more specifically related to embodiments of the present invention, an integrated circuit (IC) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material. More specifically, a small chip may incorporate many small transistors, and interconnects may be used to electrically connect two or more circuit elements (such as transistors) on the chip. Interconnects may also be used to power the transistors through a power distribution network (PDN) that utilizes buried power rails and via-to-buried power rails (VBPR). The result is circuits that are orders of magnitude smaller, faster, and cheaper than circuits constructed from discrete electronic components.

[0031] A field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current in a semiconductor. A FET is a device that has three terminals: source, gate, and drain. A FET controls the flow of current by application of a voltage to the gate, which in turn changes the conductivity between the drain and source. More specifically, a FET controls the flow of electrons (or holes) from source to drain by affecting the size and shape of a conductive channel created and influenced by the voltage (or lack of voltage) applied between the gate and source terminals. (For simplicity, this discussion assumes that the body and source are connected.) This conductive channel is the stream through which electrons flow from source to drain.

[0032] FETs are also known as unipolar transistors because they involve a single carrier type operation. In other words, FETs use either electrons or holes as charge carriers in their operation, but not both. The source / drain of the FET is doped to create an n-type semiconductor (in this case the FET may be called an NFET) or a p-type semiconductor (in this case the FET may be called a PFET). When a voltage applied to the gate of the FET is greater than the threshold voltage, charge carriers in the channel region of the FET accumulate, activating the FET (e.g., current can flow between the source and drain).

[0033] There are many types of field effect transistors. Gate-all-around (GAA) FETs are non-planar (3D) transistors designed with gate material surrounding the channel region on all sides, thus increasing contact between the gate and the channel and improving electrical control above the channel. GAAFETs may be PFETs or NFETs. Gate-all-around n-type semiconductors may also be referred to herein as GAA NFETs. Similarly, gate-all-around p-type semiconductors may also be referred to herein as GAA PFETs.

[0034] A nanosheet transistor is a type of GAA transistor in which one or more sheets of semiconductor material (e.g., Si) are used to create a transistor channel surrounded by a gate. Thus, the gate can surround each sheet on all four sides, thereby increasing the contact between the gate and the channel. Furthermore, the more nanosheets used by a transistor, the more surface area of ​​contact between the gate and the channel. This allows for better control of current leakage in the transistor. Nanosheet transistors may be vertically aligned, with the bottom source / drain disposed below the nanosheet (e.g., between the nanosheet and the substrate) and the top source / drain disposed on the top of the nanosheet (opposite the bottom source / drain), or horizontally aligned, with the current moving horizontally from source to drain (e.g., horizontal transfer GAAFET).

[0035] In some embodiments, nanosheets of opposite polarity are arranged horizontally side by side. For example, a GAA PFET may be arranged adjacent to a GAA NFET. Once arranged, the pair including a GAA PFET and a GAA NFET can be functionally interconnected and utilized as a complementary metal oxide semiconductor (CMOS) cell. In a CMOS cell, a complementary pair of a PFET and an NFET is used for logic functions.

[0036] Three approaches may be used to provide wiring front-end-of-line (FEOL) devices on the backside of the wafer to deliver power from a backside power distribution network (PDN): a first approach utilizes a front side VBPR, a front side buried power rail, and a backside PDN, a second approach utilizes a front side VBPR, a backside buried power rail (also referred to herein simply as a backside power rail (BPR)), and a backside PDN, and a third approach (also referred to herein as a direct backside contact approach), which embodiments of the present invention include, utilizes a backside VBPR, a backside BPR, and a backside PDN.

[0037] There are many drawbacks in the first and second approaches. For example, the first approach limits the size of the BPR, which can increase the resistance of the BPR. In addition, both the first and second approaches suffer from middle-of-line (MOL) congestion and routing limitations, resulting in extended source / drain (S / D), contact (CA) and VBPR. In addition, the first and second approaches only allow S / D epitaxy access to M1 (metal layer 1) signal lines through vias within the same CMOS cell.

[0038] Embodiments of the present invention may overcome these and other drawbacks of existing solutions. Embodiments of the present invention include a semiconductor device including a transistor (e.g., a complementary FET (CFET)), e.g., in a transistor region of the semiconductor device. A backside power rail is connected to the S / D epitaxy of the transistor through a backside contact. A backside interlayer dielectric (ILD) is formed beneath the transistor region of the semiconductor device and between shallow trench isolation (STI) regions beneath the channel of the transistor. In addition, a sacrificial contact placeholder is formed beneath the S / D epitaxy. A backside contact is formed to the S / D epitaxy through the backside ILD and the sacrificial contact placeholder.

[0039] In some embodiments, the semiconductor device may further include another device region for one or more other devices, referred to herein as a secondary device region. For example, the secondary device region may include electrostatic discharge (ESD) diodes, bipolar junction transistors (BJTs), or passive devices built on the bulk substrate. In an embodiment, in the secondary device region, a Si substrate may be below the front device (not the backside ILD). In some embodiments, there is an etch stop layer (e.g., SiGe or SiO2) below the Si substrate in the secondary device region.

[0040] In some embodiments, a bottom dielectric isolation (BDI) layer is present between the backside ILD and the gate stack of the transistor. The BDI may be any suitable dielectric material, including, for example, SiO2, SiOCN, SiOC, or SiBCN. The BDI can help protect against damage to the gate metal during backside Si removal.

[0041] In some embodiments, the back contact has a two-step shape. The back contact may have a large top critical dimension (CD) and a small bottom CD. In some embodiments, creating a back contact with a two-step shape allows for more flexibility in routing devices on different M1 tracks to avoid local congestion. Also, forming a two-step back contact allows for self-alignment of the contact since a large portion of the top can be offset, but the back contact is still effective since the bottom portion is fabricated in a self-aligned process.

[0042] An embodiment of the present invention further includes a method of manufacturing a semiconductor device. The method includes forming an etch stop layer on the substrate and a Si epitaxy layer on the etch stop layer. The method further includes forming both a transistor region and a secondary device region on the Si epitaxy layer. The method further includes forming a backside contact placeholder under the S / D region of the transistor. The method further includes forming the MOL, BEOL, and carrier-wafer bond. The method further includes flipping the wafer and removing the substrate to stop on the etch stop layer. The method further includes removing the etch stop layer and the remaining Si epitaxy layer between the contact placeholder and the STI. The method further includes forming a backside ILD. The method further includes forming a backside self-aligned contact, a BPR, and a backside power distribution network (BSPDN).

[0043] Turning now to the figures, FIG. 1 illustrates a plan view of an exemplary semiconductor device 100 showing cross-sectional portions Y1, Y2, and X of the following figure, in accordance with an embodiment of the present invention. The semiconductor device 100 includes an NFET region disposed adjacent to a PFET region. A metal gate 108 may intersect the NFET region and the PET region. The NFET region includes two NFET nanosheet transistors 106 and a BPR 104. Similarly, the PFET region includes two PFET nanosheet transistors 102 and a backside power rail (BPR) 104. Thus, FIG. 1 may show four nanosheet transistors (two PFET transistors and two NFET transistors).

[0044] Additionally, complementary pairs of PFET and NFET nanosheet transistors may be combined to create one or more CMOS cells, for example, an NFET transistor at the bottom of an NFET region may be paired with a PFET transistor at the top of a PFET region to create a CMOS cell.

[0045] The BPR 104 may be located at a different level of the semiconductor device 100 and may substantially overlap the NFET nanosheet transistor 106 and the PFET nanosheet transistor 102. In other words, the BPR 104 may be underneath the NFET and PFET (for example), as shown by the dashed dotted lines representing the edges of the BPR 104 that substantially overlap the nanosheet transistors 102, 106.

[0046] Figure 1 also illustrates the cross-sectional cuts shown in Figures 2-20D. Cut line Y1 crosses the nanosheet transistor in the source / drain epitaxy region, cut line Y2 crosses the nanosheet transistor in the gate region, and cut line X extends along the length of a single nanosheet 102 and crosses the three gates 108. Subsequent figures show cross-sectional views along these cut lines Y1, Y2, and X after specific fabrication operations.

[0047] Figures 2-20D illustrate a fabrication process for fabricating a semiconductor device 200 having self-aligned back contact integration. In particular, Figures 2-20D illustrate the semiconductor device 200 at various stages in the process, with each figure building on the previous figure. For example, Figure 3 illustrates the semiconductor device 200 of Figure 2 after subsequent fabrication operations have been performed, Figures 4A-4C illustrate the semiconductor device 200 of Figure 3 after subsequent fabrication operations have been performed, and so on.

[0048] Additionally, figures sharing the same numerals (e.g., Figures 4A, 4B, and 4C) depict the semiconductor device at the same point in time, in other words, each figure sharing a numeral depicts various views of the semiconductor device after the same set of fabrication operations have been performed.

[0049] Additionally, figures with the same letter followed by a number show the same cross-sectional cut at different stages. In particular, Figures 2, 3, and subsequent figures ending with "A" (e.g., Figures 4A, 5A, 6A, etc.) show cross-sectional views along the Y1 cut line (i.e., the inter-gate region or active region) as the fabrication process progresses. Similarly, figures ending with "B" (e.g., Figures 4B, 5B, 6B, etc.) show cross-sectional views along the Y2 cut line (i.e., the gate region), and figures ending with "C" (e.g., Figures 4C, 5C, 6C, etc.) show cross-sectional views along the X cut line at various stages. Figures ending with "D" (e.g., Figures 14D, 15D, 16D, etc.) show cross-sectional views of different areas of the semiconductor device 100 (secondary device regions) not seen in Figure 1, focusing on the transistor region of the semiconductor device 100.

[0050] Referring now to FIG. 2, a cross-sectional view of an exemplary semiconductor device 200 at an intermediate stage of a fabrication process is shown, in accordance with an embodiment of the present invention. In particular, FIG. 2 shows the semiconductor device 200 after the formation of an initial, or starting, semiconductor stack on a wafer. The semiconductor stack includes a first sacrificial layer 204 deposited on a substrate 202. The first sacrificial layer 204 may be, for example, SiGe with a sacrificial low Ge %, such as SiGe30%. The first sacrificial layer 204 acts as an etch stop when removing the substrate 202 in a subsequent fabrication operation. Thus, in some embodiments, the first sacrificial layer 204 may be a BOX SiO2 when the starting wafer is a SOI wafer.

[0051] A semiconductor (e.g., Si) layer 206 (e.g., a Si epitaxy layer) is deposited on the first sacrificial layer 204. A second sacrificial layer 208 is then deposited on the semiconductor layer 206. The second sacrificial layer 208 may be, for example, a sacrificial high Ge % SiGe layer, such as SiGe55%.

[0052] Alternating layers of a third sacrificial material 210 and a semiconductor (e.g., Si) 212 may then be deposited on the second sacrificial material layer. The third sacrificial material 210 may be, for example, SiGe with a sacrificial low Ge % such as SiGe30%. The semiconductor 212 layer ends up as a nanosheet layer that constitutes the semiconductor channel for the semiconductor device 200.

[0053] After creating the nanosheet stack, a hard mask 214 may be deposited on portions of the stack. After depositing the hard mask 214 on the semiconductor device 200, the nanosheet stack may be patterned. This is shown in Figure 3. Patterning the nanosheet stack may include, for example, performing extreme ultraviolet lithography (EUV) and / or RIE operations to create a plurality of nanosheet structures (referred to herein as fins 218) separated by grooves 220.

[0054] In addition, a shallow trench isolation (STI) layer 216 is formed in portions of the substrate semiconductor layer 206 that are laterally aligned with the patterned stack. The STI 216 can prevent current leakage between adjacent semiconductor components (e.g., between adjacent nanosheet FETs). In some embodiments, the STI 216 can be an oxide.

[0055] After forming the fins 218 and the STIs 216, a dummy gate 222 may be formed in the semiconductor device 200. This is shown in Figures 4A-4C. In particular, the dummy gate 222 may be formed in the gate region along cut line Y2, as shown in Figure 4B. The dummy gate 222 may be made of any suitable material, as will be recognized by those skilled in the art. In some embodiments, the dummy gate 222 is a thin layer of SiO2, followed by bulk amorphous silicon (a-Si). A hard mask 224 may also be formed on the dummy gate 222.

[0056] After forming the dummy gate 222 and the hard mask 224, the second sacrificial layer 208 may be selectively removed. This is shown in Figures 5A-5C. In particular, the second sacrificial layer 208 may be selectively removed without removing the first sacrificial layer 204 or the third sacrificial material 210. As shown in Figures 5A-5C, the second sacrificial layer 208 may be removed from the entire semiconductor device 200, including the inter-gate region (shown in Figure 5A), the gate region (shown in Figure 5B), and the nanosheet region (shown in Figure 5C).

[0057] After removing the second sacrificial layer 208, one or more spacer layers 226 may be formed in the semiconductor device 200. This is shown in Figures 6A-6C. The one or more spacer layers 226 may include a bottom dielectric insulation (BDI) layer and one or more sidewall spacers. The BDI layer may be that portion of the spacer layer 226 located between the semiconductor layer 206 and the fin 218. The BDI layer may be deposited where the second sacrificial layer 208 was previously found, as shown in Figures 6A and 6B. In addition, spacer sidewalls may be deposited along the walls of the exposed fin 218, as shown in Figure 6A, and along the sidewalls of the dummy gate 222 and hard mask 224, as shown in Figure 6C.

[0058] The spacer layer 226 may be made of, for example, SiO2, SiOCN, SiOC, SiBCN. The spacer layer 226 may be deposited on the semiconductor device 200 after removal of the second sacrificial layer 208. In some embodiments, a spacer RIE operation may be performed to remove the spacer layer 414 from over the STIs 216 and fins 218.

[0059] After forming one or more spacer layers 226, a nanosheet recess operation may be performed. This is shown in Figures 7A-7C. The nanosheet recess operation may include performing a selective etching operation to remove the fin 218 and a portion of the semiconductor layer 206 below the fin, resulting in the formation of a plurality of grooves 228, as shown in Figures 7A and 7C. However, the spacer sidewalls 226 and the STIs 216 are largely unaffected by the selective etching operation, although as seen in Figure 7C, the spacer material may be etched to be slightly shorter or thinner, or shorter and thinner, than it was before the etch (e.g., the tops of the spacers 226 are no longer flush with the tops of the hard mask 224). As a result of the selective etching, the sidewalls of the STIs 216 and the tops of the semiconductor layer 206 between the STI layers 216 are exposed.

[0060] 7C, the hard mask 224 and the spacer layer 226 serve to largely protect the semiconductor stack below the hard mask 224 and the spacer layer 226, while the portion of the semiconductor stack between the spacer layer 226 is etched down to the semiconductor layer 206. However, as a result of the recess operation (or a subsequent SiGe recess operation), the exposed portion of the third sacrificial layer 210 in the trench 228 is partially etched back. An inner spacer 230 is then formed where the third sacrificial layer 210 was etched back. The inner spacer 230 may be made of, for example, SiO2, SiOCN, SiOC, SiBCN.

[0061] Next, top-down epitaxy growth of a sacrificial placeholder 232 (e.g., SiGe) is performed. This is shown in Figures 8A-8C. The epitaxy sacrificial placeholder 232 may be grown in the grooves 228 between the spacer sidewalls 226 in the inter-gate region (shown in Figure 8A) as well as in the grooves 228 between the remaining semiconductor stack in the nanosheet region (shown in Figure 8C) by an epitaxy process that grows faster in the 100 direction than in the 110 direction. A cyclic epitaxy etch-back process may be used to ensure that epi growth from the exposed sidewalls of the nanosheets is suppressed.

[0062] A Si buffer epitaxy 234 can then be grown on the sacrificial placeholder 232. This is shown in Figures 9A-9C. A source / drain epitaxy 236 is then grown on the Si buffer epitaxy 234. This is shown in Figures 10A-10. As shown in Figure 10A, the source / drain epitaxy 236 covers the top of the sidewall spacer 226 in the inter-gate region. As further shown in Figure 10C, the source / drain epitaxy 236 extends above the top of the nanosheet stack. In other words, the top surface of the source / drain epitaxy 236 is above the top of the top Si layer 212.

[0063] After growing the source / drain epitaxy 236, an ILD fill operation may be performed to create an ILD layer 238, which may then be planarized using a CMP process. In addition, the dummy gate 222 may be removed, the remaining third sacrificial material 210 may be released, a gate cut may be performed, and a high-k metal gate (HKMG) 240 may be formed, as shown in Figures 11A-11C.

[0064] The ILD 238 may surround and cover the source / drain epitaxy 236, the STI 216, and the spacer sidewall 226 in the inter-gate region, as shown in Figure 11A. Similarly, the ILD 238 may fill the remainder of the trench 228 (shown in Figures 10A-10C), as shown in Figure 11C. A planarization process may expose the ILD 238, the sidewall spacer 226, and a top portion of the metal gate 240, as shown in Figure 11C.

[0065] The ILDs 238 may comprise any suitable material known in the art, such as, for example, porous silica, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric material. The ILDs 238 may be formed using any method known in the art, such as, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0066] After releasing the third sacrificial layer 210, an HKMG layer 240 is formed on and around the remaining semiconductor material 212 in the gate region, as shown in FIG. 11B. In other words, during this step, a replacement high-k metal gate is formed in place of each dummy gate 222 and the SiGe layer 210. The HKMG layer 240 may be any of a variety of materials, including HfO2, ZrO, HfLaO, etc. x , HfAlO x and workfunction metals (WFM) such as TiN, TiC, TiAlC, TiAl, etc., and may further include optional low resistivity conductive metals such as W, Co, and Ru.

[0067] Those skilled in the art will recognize that a "replacement metal gate" refers to a gate that replaces a previously formed dummy gate (also referred to herein as a sacrificial gate, inactive gate, or non-gate) and becomes an active component of the semiconductor structure being formed. The work function metal may include a metal selected to have a specific work function appropriate for a given type of FET (e.g., N-type FET or P-type FET). For example, for a silicon-based N-type FET, the work function metal may include hafnium, zirconium, titanium, tantalum, aluminum or alloys thereof, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide, such that the work function metal has a similar work function to the N-doped polysilicon. For silicon-based P-type FETs, the work function metal may include, for example, ruthenium, palladium, platinum, cobalt, or nickel, or a metal oxide (e.g., aluminum carbon oxide or aluminum titanium carbon oxide), or a metal nitride (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, or tantalum aluminum nitride), such that the work function metal has a similar work function as the P-doped polysilicon.

[0068] Additionally, a gate cut region 242 may be formed in the metal gate 240 to electrically isolate the various FETs. The gate cut region 242 may be formed of any suitable material to prevent shorts across the nanosheet transistors. The gate cut region 242 may extend from the STI 216 to the top of the semiconductor device 200 (i.e., be flush with the top of the metal gate 240).

[0069] Next, middle-of-line (MOL) and back-end-of-line (BEOL) 246 structures may be formed. The semiconductor device 200 may then be bonded to a carrier wafer 248, as shown in Figures 12A-12C. The MOL structure may include one or more epitaxy and / or gate contacts 244, as well as another ILD layer 238 deposited on the semiconductor device 200 (e.g., as shown in Figure 12B, where the ILD layer 238 is on a metal gate 240). The epitaxy contacts 244 may be made of any suitable material, including, for example, a silicide liner at the bottom of the contact, such as Ti, Ni, NiTi, NiPt, and a conductive metal, such as Ru, W, or Co, with a thin deposited metal liner, such as TiN. The BEOL 246 may include multiple interconnects or other structures.

[0070] It will be appreciated that the dimensions of the MOL and BEOL 246 structures and carrier wafer 248 are not necessarily drawn to scale. The MOL and BEOL 246 structures and carrier wafer 248 may be formed using any suitable process, as will be appreciated by those skilled in the art. In some embodiments, the BEOL 246 and carrier wafer 248 may be prefabricated and then bonded to the semiconductor device 200.

[0071] Next, the wafer is flipped. This is shown in Figures 13A-13C. After flipping the wafer, the substrate 202 is removed. This is shown in Figures 14A-14D. The substrate 202 may be removed by a selective etching process that stops at the first sacrificial layer 204, which acts as an etch stop. As shown in Figure 14D, the substrate 202 is also removed from the secondary device region of the semiconductor device 200. After removal of the substrate 202, the secondary device region includes the first sacrificial layer 204, the semiconductor layer 206, the one or more other devices 250, the BEOL 246, and the carrier wafer 248. The one or more other devices include other devices formed in the same wafer as the transistors. The other devices may include, for example, an ESD diode, a BJT, or another device (e.g., a passive device) built in the bulk substrate.

[0072] The secondary device region may then have a hard mask 252 deposited thereon, and a patterning process may be performed to remove the etch stop (i.e., first sacrificial layer 204) from the transistor region. This is shown in Figures 15A-15D. The semiconductor layer 206 is then selectively removed relative to the SiGe. This is shown in Figures 16A-16D. Selective removal of the semiconductor layer 206 exposes the STI 216 and the sacrificial epitaxy placeholder 232, as shown in Figures 16A-16C. In areas where the sacrificial epitaxy placeholder 232 does not abut the STI 216, the selective etching process may change the profile of the sacrificial epitaxy placeholder 232, as shown in Figure 16C.

[0073] Next, a backside ILD fill process and a CMP process may be performed, which is shown in Figures 17A-17D. As shown in Figures 17A-17C, an ILD 254 fill may be deposited over and around the STI 216, the epitaxy placeholder 232, and the BDI 226 (in the gate region shown in Figure 18B). A CMP process may then planarize the top of the semiconductor device 200 such that the top of the ILD 254 is flush with the top of the hard mask 252 in the secondary device region.

[0074] Patterning of the back contact may then be performed, as shown in Figures 18A-18D. In particular, in the areas where the back contact will be formed, trenches 256 may be patterned through the ILD 254 and into the epitaxy placeholder 232. Portions of the STI 216 may be removed by this process. This process allows for much better tolerances in critical dimensions (CD) and coverage compared to conventional processes.

[0075] Next, a pre-contact cleaning is performed to remove the exposed epitaxy placeholder 232 and smooth the corners 257, as shown in Figures 19A-19D. In addition, the Si buffer epitaxy 234 is removed from the contact area. The trench 256 is formed by patterning on the sacrificial epitaxy placeholder 232 and then removing the placeholder 232, so that the resulting trench 256 is a two-tiered trench, with the top portion of the trench 256 being larger than the bottom portion.

[0076] Following pre-contact cleaning, a backside contact 258 is formed in the trench 256. This is shown in Figures 20A-20D. The backside contact 258 may be formed from any suitable conductive material, such as, for example, a silicide liner at the bottom of the contact, such as Ti, Ni, NiTi, NiPt, and a conductive metal, such as Ru, W, or Co, and may have a thin deposited metal liner, such as TiN. In addition, an ILD 260 layer may be formed over the ILD 254 and contact 258 in the inter-gate region, as shown in Figure 20A. A BPR 262 may then be formed on the ILD 260. The BPR 262 may include a Vss and Vdd BPR 262. The Vdd BPR 262 may be formed at least partially on the backside contact 258, as shown in Figures 20A and 20C. A BSPDN 264 is then formed on the BPR 262.

[0077] 21, a flow chart of an exemplary method 2100 for forming a semiconductor device is shown, in accordance with an embodiment of the present invention. Method 2100 may be performed, for example, by hardware, software, firmware, or any combination thereof. For example, method 2100 may be performed by a computer system in a semiconductor fabrication factory that controls fabrication equipment.

[0078] The method may begin in operation 2102, where an etch stop layer (e.g., SiGe30% or BOX SiO2) is formed on a substrate. A Si epitaxy layer (e.g., Si layer 206 shown in FIG. 2) is then formed on the etch stop layer.

[0079] In operation 2104, one or more transistor regions and one or more secondary device regions are then formed on the Si epitaxy layer. Each of the one or more transistor regions may further include an inter-gate region, a gate region, and a nanosheet region as discussed herein. The one or more transistor regions may be regions in which transistors with self-aligned back contacts (e.g., CFETs) are formed as discussed herein. The one or more secondary device regions may be regions in which other devices (e.g., ESD diodes, BJTs, other passive devices) are formed in the bulk substrate. The one or more secondary device regions and the one or more transistor regions may be at the same level as each other (e.g., in a PCB stackup).

[0080] A back contact placeholder is formed under the source / drain regions of the transistor in operation 2106. The back contact placeholder may be formed from a sacrificial material, such as a SiGe material.

[0081] In operation 2108, the MOL and BEOL are formed and the semiconductor devices are bonded to the carrier wafer, after which the wafer is flipped and the substrate is removed stopping on the etch stop layer, as shown in operation 2110.

[0082] Next, in operation 2112, the etch stop layer and remaining Si epitaxy layer are removed between the contact placeholder and the STI. This can be done only in the transistor region. To selectively perform these steps, operation 2112 may further include providing a hard mask in the secondary device region.

[0083] Thereafter, in operation 2114, a backside ILD is formed. After forming the backside ILD, in operation 2116, a backside self-aligned contact, a BPR, and a BSPDN are formed. The BPR can be connected to the transistor through the backside self-aligned contact. After forming the backside contact, the BPR, and the BSPDN, the method 2100 may end.

[0084] Of course, the above advantages are exemplary advantages and are not intended to be limiting, and embodiments of the invention may include none, all, or some of the above advantages while remaining within the scope of the invention.

[0085] Detailed embodiments of the structure of the present invention are described herein. However, it should be understood that the embodiments described herein are merely examples of structures that can be embodied in various forms. In addition, each of the examples shown in relation to the various embodiments of the present invention is intended to be illustrative and not limiting. Furthermore, the figures are not necessarily to scale, and some features may be exaggerated to show the details of certain components. Therefore, the specific structural and functional details described herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art how to employ the methods and structures described in various ways.

[0086] It should also be understood that material compounds are described in terms of the listed elements, e.g., SiN, SiCN, SiCO, or SiGe. These compounds may contain different percentages of the elements within the compound, e.g., SiGe is SiN, SiCN, SiCO, or SiGe, where x is 1 or less. x Ge (1-x) etc. Additionally, other elements may be included in the compound and still function according to the present principles. Compounds with additional elements are referred to herein as alloys.

[0087] It should be noted that not all masking, patterning, and lithography processes are shown, as one of ordinary skill in the art will recognize where masking and patterning processes are utilized to form the identified layers and openings, and to perform the identified selective etching processes, as described herein.

[0088] As discussed herein, embodiments of the invention include methods. The methods may be performed, for example, by a computer system controlling semiconductor fabrication machinery. As such, the methods may be embodied as a computer program product having software instructions on a storage medium. The computer program product may include one or more computer readable storage media having computer readable program instructions for causing a processor to perform aspects of the invention.

[0089] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved structures having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transitory signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0090] The computer readable program instructions described herein may be downloaded from a computer readable storage medium into each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage.

[0091] The computer readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer as a standalone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the invention.

[0092] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0093] These computer readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute on the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored on a computer readable storage medium having instructions stored thereon to instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer readable storage medium having the instructions stored thereon comprises an article of manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0094] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operable steps to create a computer-implemented process such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0095] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may actually be performed as one step, or may be performed simultaneously, substantially simultaneously, partially or fully in a time-overlapping manner, or the blocks may sometimes be performed in reverse order depending on the functionality involved. It should be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a special purpose hardware-based system that performs the specified functions or operations or performs a combination of special purpose hardware and computer instructions.

[0096] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the various embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, it is to be understood that the terms "comprise" and / or "comprising", when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof. In the preceding detailed description of exemplary embodiments of the various embodiments, reference has been made to the accompanying drawings, in which like numbers represent like elements, which form a part of the specification, and in which are shown by way of illustration specific example embodiments in which the various embodiments may be practiced. These embodiments have been described in sufficient detail to enable one skilled in the art to practice the embodiments, but other embodiments may be utilized and logical, mechanical, electrical, and other changes may be made without departing from the scope of the various embodiments. In the above description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail so as not to obscure the embodiments.

[0097] As used herein, "plurality," when used in reference to an item, means one or more of the item. For example, "plurality of different types of networks" is one or more different types of networks.

[0098] When different reference numbers use a common number followed by different letters (e.g., 100a, 100b, 100c), or punctuation followed by different numbers (e.g., 100-1, 100-2, or 100.1, 100.2), using only the reference letter without the letter or following number (e.g., 100) may refer to an entire group of elements, any subset of the group, or exemplary samples of the group.

[0099] Additionally, the phrase "at least one," when used in conjunction with a list of items, means that different combinations of one or more of the listed items may be used, and only one of each item in the list may be required. In other words, "at least one" means any combination of items, and while multiple items may be used from the list, not all of the items in the list are required. An item may be a particular object, thing, or category.

[0100] For example, without limitation, "at least one of item A, item B, or item C" may include item A, item A and item B, or item B. This example may also include item A, item B, and item C, or item B and item C. Of course, any combination of these items may be present. In some illustrative examples, "at least one" may be, for example, without limitation, two of element A, one of element B, and ten of element C, or four of element B and seven of element C, or other suitable combinations.

[0101] As used herein, different instances of the phrase "embodiment" do not necessarily refer to the same embodiment, although they may. Any data and data structures shown or described herein are merely examples, and other embodiments may use different amounts of data, types of data, fields, numbers and types of fields, field names, numbers and types of rows, records, entries, or organizations of data. In addition, any data may be combined with logic, so a separate data structure may not be necessary. Thus, the foregoing detailed description should not be taken in a limiting sense.

[0102] Although the description of various embodiments of the present invention has been presented for illustrative purposes, the description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0103] While the present invention has been described with reference to specific embodiments, it is anticipated that variations and modifications thereof will become apparent to those skilled in the art, and it is therefore intended that the following claims be interpreted as covering all such variations and modifications that are within the scope of the present invention.

[0104] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive and is not limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments described in this specification.

[0105] Below, a non-limiting list of exemplary embodiments is provided to illustrate certain aspects of the present invention.

[0106] Exemplary embodiment 1 is a semiconductor device. The device includes a transistor including a plurality of source / drain epitaxies. The device further includes at least one backside power rail below the transistor. The device further includes a backside interlayer dielectric (ILD) located between the plurality of source / drain epitaxies and the at least one power rail. The device further includes a first backside contact connecting the first source / drain epitaxy to the at least one backside power rail. The device further includes one or more contact placeholders formed below other source / drain epitaxies.

[0107] Exemplary embodiment 2 includes the device of exemplary embodiment 1 with or without optional features. In this exemplary embodiment, the semiconductor device includes a transistor region and a secondary device region, the transistor region includes a transistor. Optionally, the secondary device region includes one or more other devices selected from the group consisting of an ESD diode, a BJT, and a passive device. Optionally, the device includes a Si substrate below the one or more other devices in the secondary device region. Optionally, the device includes an etch stop layer below the Si substrate in the secondary device region. Optionally, the transistor region further includes one or more additional transistors. Optionally, a pair of transistors in the transistor region are connected to create a complementary metal oxide semiconductor (CMOS) cell, the pair of transistors including an n-type transistor and a p-type transistor. Optionally, the pair of transistors forms a complementary field effect transistor (CFET).

[0108] Exemplary embodiment 3 includes the device of any one of exemplary embodiments 1-2, with or without optional features. In this exemplary embodiment, the first back contact has a two-step shape, where the first back contact has a large top critical dimension (CD) and a small bottom CD.

[0109] Exemplary embodiment 4 includes the device of any one of exemplary embodiments 1 to 3, with or without optional features. In this exemplary embodiment, each source / drain epitaxy of the multiple sources / drains is either connected to a backside power rail through a backside contact or connected to a contact placeholder.

[0110] Exemplary embodiment 5 includes the device of any one of exemplary embodiments 1 to 4, with or without optional features. In this exemplary embodiment, the device includes a bottom dielectric insulating layer between the backside ILD and the gate stack of the transistor.

[0111] Exemplary embodiment 6 includes the device of any one of exemplary embodiments 1-5, with or without optional features. In this exemplary embodiment, the device includes a shallow trench isolation (STI) layer under the channel of the transistor, the STI layer being surrounded by a backside ILD at the gate region. Optionally, the STI layer separates the one or more contact placeholders and the first contact from each other.

[0112] Exemplary embodiment 7 includes the device of any one of exemplary embodiments 1 to 6, with or without optional features. In this exemplary embodiment, the device includes a backside power distribution network (BSPDN) connected to at least one backside power rail on the opposite side of the transistor.

[0113] Exemplary embodiment 8 includes the device of any one of exemplary embodiments 1 to 7, with or without the optional features. In this exemplary embodiment, the transistor is a nanosheet transistor.

[0114] Exemplary embodiment 9 is a nanosheet transistor. The nanosheet transistor includes a plurality of source / drain epitaxies. The nanosheet transistor further includes a backside ILD below the plurality of source / drain epitaxies. The nanosheet transistor further includes a first contact connecting the first source / drain epitaxy to a backside power rail, the first contact extending through the backside ILD. The nanosheet transistor further includes a contact placeholder in contact with the second source / drain epitaxy. The contact placeholder is disposed between the second source / drain epitaxy and the backside ILD.

[0115] Exemplary embodiment 10 includes the nanosheet transistor of exemplary embodiment 9, with or without optional features. In this exemplary embodiment, the nanosheet transistor further includes a front ILD above the plurality of source / drain epitaxies. The front ILD is disposed between the plurality of source / drain epitaxies and a back-end-of-line (BEOL) portion of the semiconductor device. Optionally, the nanosheet transistor includes one or more BEOL contacts, each of the one or more BEOL contacts connecting one source / drain epitaxy of the plurality of source / drain epitaxies to the BEOL. Optionally, the one or more BEOL contacts include a first BEOL contact connecting a second source / drain epitaxy to the BEOL.

[0116] Exemplary embodiment 11 is a semiconductor device. The device includes a backside power distribution network (BSPDN) and one or more backside power rails connected to the BSPDN. The device further includes an ILD opposite the BSPDN and above the one or more backside power rails. The device further includes one or more nanosheet transistors. Each nanosheet transistor includes at least one backside contact connecting a first source / drain epitaxy of the respective nanosheet transistor to the backside power rail. The backside contact extends from the source / drain epitaxy through the backside ILD. Each nanosheet transistor further includes at least one placeholder contact connected to a second source / drain epitaxy.

[0117] Exemplary embodiment 12 includes the device of exemplary embodiment 11 with or without optional features. In this exemplary embodiment, the device includes a BEOL portion connected to one or more nanosheet transistors opposite the backside ILD. Each nanosheet transistor further includes one or more BEOL contacts, each of the BEOL contacts connecting a source / drain epitaxy of a respective transistor to the BEOL portion.

[0118] Exemplary embodiment 13 is a method of fabricating a semiconductor device. The method includes forming an etch stop layer on a substrate. The method further includes forming a Si epitaxy layer on the etch stop layer. The method further includes forming one or more transistor regions and one or more secondary device regions on the Si epitaxy layer. The method further includes forming a backside contact placeholder under a source / drain region of the one or more transistors. The method further includes forming a middle-of-line (MOL) section and a BEOL section. The method further includes removing the substrate selectively to the etch stop layer. The method further includes removing the etch stop layer and the Si epitaxy layer from the one or more transistor regions. The method further includes forming a backside ILD. The method further includes forming one or more backside contacts through the backside ILD. The method further includes forming one or more backside power rails and a backside power distribution network on the one or more backside contacts.

[0119] Exemplary embodiment 14 includes the method of exemplary embodiment 13, with or without the optional features. In this exemplary embodiment, forming the one or more transistor regions includes forming one or more nanosheet transistors. Additionally, in this exemplary embodiment, forming the one or more secondary device regions includes forming one or more devices selected from the group consisting of an ESD diode and a BJT.

[0120] Exemplary embodiment 15 includes the method of any one of exemplary embodiments 13-14, with or without optional features. In this exemplary embodiment, removing the etch stop layer and the Si epitaxy layer from the one or more transistor regions includes providing a hard mask over the one or more secondary device regions, removing the etch stop layer in a first etching operation, and removing the Si epitaxy layer in a second etching operation.

[0121] Exemplary embodiment 16 is a computer program product for forming a semiconductor device using one or more fabrication manufacturing components. The computer program product includes instructions directing a processor to perform a method. The method includes forming an etch stop layer in a substrate. The method further includes forming a Si epitaxy layer on the etch stop layer. The method further includes forming one or more transistor regions and one or more secondary device regions on the Si epitaxy layer. The method further includes forming a backside contact placeholder under a source / drain region of the one or more transistors. The method further includes forming a middle-of-line (MOL) section and a BEOL section. The method further includes removing the substrate selectively to the etch stop layer. The method further includes removing the etch stop layer and the Si epitaxy layer from the one or more transistor regions. The method further includes forming a backside ILD. The method further includes forming one or more backside contacts through the backside ILD. The method further includes forming one or more backside power rails and a backside power distribution network on the one or more backside contacts.

[0122] In a preferred embodiment of the invention described herein, a nanosheet transistor is provided that includes a plurality of source / drain epitaxies, a backside ILD below the plurality of source / drain epitaxies, a first contact connecting a first source / drain epitaxy to a backside power rail, the first contact extending through the backside ILD, and a contact placeholder in contact with a second source / drain epitaxy, the contact placeholder being disposed between the second source / drain epitaxy and the backside ILD. The transistor further includes a frontside ILD above the plurality of source / drain epitaxies, the frontside ILD being disposed between the plurality of source / drain epitaxies and a back-end-of-line (BEOL) portion of the semiconductor device. The transistor may further include one or more BEOL contacts, each connecting one of the plurality of source / drain epitaxies to the BEOL. The one or more BEOL contacts may include a first BEOL contact connecting the second source / drain epitaxy to the BEOL.

[0123] In a preferred embodiment of the invention described herein above, a semiconductor device is provided comprising a backside power distribution network (BSPDN), one or more backside power rails connected to the BSPDN, an ILD above the one or more backside power rails and opposite the BSPDN, and one or more nanosheet transistors, each nanosheet transistor including at least one backside contact connecting a first source / drain epitaxy of the respective nanosheet transistor to the backside power rail, the at least one backside contact extending from the source / drain epitaxy through the backside ILD, and at least one placeholder contact connected to a second source / drain epitaxy. The device further comprises a BEOL portion connected to the one or more nanosheet transistors opposite the backside ILD, each nanosheet transistor including one or more BEOL contacts, each BEOL contact connecting a source / drain epitaxy of the respective transistor to the BEOL portion.

Claims

1. a transistor including a plurality of source / drain epitaxies; at least one backside power rail beneath said transistor; a backside interlayer dielectric (ILD) located between the plurality of source / drain epitaxies and the at least one power rail; a first backside contact connecting a first source / drain epitaxy to the at least one backside power rail; one or more contact placeholders formed under the other source / drain epitaxy; A semiconductor device comprising:

2. The device of claim 1 comprising a transistor region and a secondary device region, said transistor region containing said transistor.

3. The device of claim 2 , wherein the secondary device region includes one or more other devices selected from the group consisting of ESD diodes, BJTs, and passive devices.

4. The device of claim 2 further comprising a Si substrate beneath the one or more other devices in the secondary device region.

5. The device of claim 4 further comprising an etch stop layer beneath said Si substrate in said secondary device region.

6. The device of claim 2 , wherein the transistor region further comprises one or more additional transistors.

7. 7. The device of claim 6, wherein a pair of transistors in the transistor region are connected to create a complementary metal-oxide-semiconductor (CMOS) cell, the pair of transistors including an n-type transistor and a p-type transistor.

8. The device of claim 7 , wherein the pair of transistors forms a complementary field effect transistor (CFET).

9. 10. The device of claim 1, wherein the first back contact has a two-step shape, the first back contact having a large top critical dimension (CD) and a small bottom CD.

10. 10. The device of claim 1, wherein each source / drain epitaxy of the plurality of sources / drains is connected to a backside power rail either through a backside contact or to a contact placeholder.

11. The device of claim 1 , further comprising a bottom dielectric isolation layer between the backside ILD and a gate stack of the transistor.

12. 10. The device of claim 1, further comprising a shallow trench isolation (STI) layer below a channel of the transistor, the STI layer being surrounded by the backside ILD in a gate region.

13. The device of claim 12 , wherein the STI layer separates the one or more contact placeholders and the first contact from each other.

14. 10. The device of claim 1, further comprising a backside power distribution network (BSPDN) connected to the at least one backside power rail opposite the transistor.

15. The device of claim 1 , wherein the transistor is a nanosheet transistor.

16. forming an etch stop layer on a substrate; forming a Si epitaxy layer on the etch stop layer; forming one or more transistor regions and one or more secondary device regions on the Si epitaxy layer; forming a back contact placeholder under a source / drain region of the one or more transistors; forming a middle-of-line (MOL) section and a BEOL section; removing the substrate selectively to the etch stop layer; removing the etch stop layer and the Si epitaxy layer from the one or more transistor regions; forming a backside ILD; forming one or more back contacts through the back ILD; forming one or more backside power rails and backside power distribution network over the one or more backside contacts; 1. A method for fabricating a semiconductor device, comprising:

17. 17. The method of claim 16, wherein said forming the one or more transistor regions comprises forming one or more nanosheet transistors, and said forming the one or more secondary device regions comprises forming one or more devices selected from the group consisting of: an ESD diode and a BJT.

18. The removing of the etch stop layer and the Si epitaxy layer from the one or more transistor regions comprises: providing a hard mask over the one or more secondary device regions; removing the etch stop layer in a first etching operation; removing said Si epitaxy layer in a second etching operation; 17. The method of claim 16, comprising:

19. 1. A computer program product for forming a semiconductor device using one or more fabrication manufacturing components, comprising: A computer readable storage medium having embodied program instructions executable by a computer to perform the method of any one of claims 16 to 18. Computer program products.

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