STEP-FREE MEMORY DEVICE AND METHOD FOR FORMING SAME - Patent application

Abstract

An embodiment of the present disclosure includes an apparatus and method for forming a non-volatile memory device, comprising: positioning a substrate on a surface of a substrate support disposed in a processing region of a processing chamber; delivering a processing gas composition to the processing region; and etching a plurality of alternating layers formed on a surface of the substrate. The substrate includes a hard mask layer disposed on the plurality of alternating layers including vertically stacked first and second layers. The hard mask layer includes an array of mask openings formed therein, the mask openings being aligned in a first pitch direction and having a pitch length in the first pitch direction between adjacent mask openings in the array of mask openings. The substrate further includes a first photoresist layer disposed on the hard mask layer and on the two or more mask openings, the first photoresist layer including an opening having an exposed surface. The process for etching multiple alternating layers includes forming a plasma in a processing region of a processing chamber, the plasma comprising a processing gas composition, and the process for etching multiple alternating layers etches a first photoresist layer such that during the etching process, an opening surface of the first photoresist layer sequentially exposes each mask opening in the array of mask openings, forming patterned openings, each having a different depth within the alternating layer, in portions of the alternating layer located beneath the sequentially exposed mask openings.

Description

[Technical field]

[0001] The present disclosure relates generally to memory devices and methods for their manufacture, and more particularly to device structures and methods for forming three-dimensional (3D) NAND memory devices. [Background technology]

[0002]

[0002] Memory devices are essential components in currently developed digital electronic devices. As the processing speed of electronic devices increases, the memory capacity of the memory devices used in combination with the processors of the electronic devices must also increase, and at the same time, there is a need to miniaturize the memory devices to meet market demands for smaller electronic devices in which the memory devices are positioned.

[0003]

[0003] A three-dimensional (3D) NAND memory has been proposed, which is a transition from a two-dimensional NAND memory structure to a three-dimensional NAND memory structure. FIG. 1 is a simplified schematic example of a conventional 3D NAND memory structure 100. The 3D NAND memory structure includes a vertically oriented channel structure 117, which is oriented perpendicular (e.g., in the -Z direction) to a major surface of a substrate 101 including an etch stop layer 102 and a common source line layer (CSL) 103 disposed thereon. The upper portion of the vertical channel layer structure 117 includes a number of bit lines 118. The stacked layers are arranged into stacked layer pairs 120, each including a dielectric layer 116 and a word line layer 115. In this configuration, the word line layers 115 (e.g., the four layers shown in FIG. 1) are stacked in a direction perpendicular to the major surface of the substrate to form a series of transistors, each including a portion of one of the channel layer structures 117. At the end of each word line layer 115, there is a staircase structure 110. In the stepped structure 110, one or more conductive columns 114 are used to connect the word line layer 115 to external control circuitry using connecting element lines 113. Thus, in a 3D NAND memory structure, the transistors can be fabricated vertically, making it easy to increase memory capacity by stacking additional layers.

[0004]

[0004] However, the staircase structures 110 formed on two opposing edges of the 3D NAND memory structure 100 required a large two-dimensional area (i.e., in the XZ plane) to connect all of the wordline layers 115 to external elements outside the 3D NAND device. The large two-dimensional area has a lateral width 112 and a height 125, which limits the number of NAND devices that can be formed laterally (i.e., in the X direction) for a desired lateral 3D NAND size. The lateral width 112 of the staircase structures 110 is limited by a minimum pitch 111 that is required to be used between the conductive columns 114 to ensure that the patterning process used to define the vertically etched openings that define the locations of the conductive columns 114 reliably lands on the exposed portions of the wordline layers 115 within each step of the staircase structures 110. Furthermore, the manufacturing process used to form the staircase structures 110 is overly complex, which reduces device yields and significantly increases memory costs. The fabrication process used to form a typical staircase structure 110 requires the completion of a repeating sequence of steps requiring at least a first lithography (litho) step followed by a second plasma etching step (etch) for each step of the staircase structure 110. In one example, as shown in Figure 1, a staircase structure 110 including four staircase steps would require a litho-etch-litho-etch-litho-etch-litho-etch processing sequence to form the four staircase steps in each of the two staircase structures 110 shown in Figure 1.

[0005]

[0005] Furthermore, the plasma etching processes involved in the fabrication of 3D NAND devices are becoming increasingly challenging. Specifically, etching of stepped contacts used to form 3D NAND devices, which are used to provide access to portions of the cells at the bottom of the NAND stack, is becoming increasingly challenging due to the need to form high aspect ratio features having aspect ratios of 20:1 to 40:1. Etching high aspect ratio conductive layers places increasing demands on the etch process, which must be able to form openings in layers that are free of striations, distortion, line bending, faceting, and clogging of features. Another challenge in performing the desired stepped contact etch is to ensure simultaneous multi-level etching of features with aspect ratios ranging from 20:1 to over 40:1 with high selectivity and negligible loss of the underlying conductive contact material.

[0006] Therefore, there is a need for an improved memory device structure and method of forming the same which overcomes the above-mentioned problems. Summary of the Invention

[0007]

[0007] An embodiment of the present disclosure may provide a method of forming a non-volatile memory device that includes etching a plurality of alternating layers formed on a surface of a substrate, the alternating layers including vertically stacked first and second layers. The method of etching the plurality of layers includes delivering a process gas composition to a processing region of a process chamber, forming a plasma in the processing region of the process chamber, the plasma including the process gas composition, and establishing a voltage waveform at an electrode positioned a distance from a substrate support surface of a substrate support disposed in the processing region of the process chamber while the plasma is formed on a substrate positioned on the substrate support surface. The substrate includes a hardmask layer disposed over a first layer and a second layer of the plurality of alternating layers, the first layer comprising a first material and the second layer comprising a second material different from the first material, an array of mask openings formed in the hardmask layer and aligned in a first pitch direction and having a pitch length in the first pitch direction between adjacent mask openings in the array of mask openings, and a first photoresist layer disposed over the hardmask layer and over two or more mask openings in the array of openings, the first photoresist layer being exposed to a plasma formed through an opening formed in the first photoresist layer. The process gas composition is selected such that the formed plasma increases a size of the opening formed in the first photoresist layer in the first pitch direction by a length equal to the pitch length during a first time interval and simultaneously etches a thickness of the first layer and the second layer during the first time interval.

[0008]

[0008] An embodiment of the present disclosure may also provide a method of forming a non-volatile memory device, comprising: positioning a substrate on a surface of a substrate support disposed in a processing region of a processing chamber; delivering a processing gas composition to the processing region of the process chamber; and etching a plurality of alternating layers formed on the surface of the substrate. The substrate includes a hardmask layer disposed on the plurality of alternating layers formed on the surface of the substrate, the alternating layers including a first layer and a second layer stacked in a vertical direction; an array of mask openings formed in the hardmask layer and aligned in a first pitch direction, the array of mask openings having a pitch length in the first pitch direction between adjacent mask openings in the array of openings; and a first photoresist layer disposed on the hardmask layer and on two or more mask openings in the array of mask openings, the first photoresist layer including an opening in the first photoresist layer having an exposed surface, the opening positioned to expose a first mask opening in the array of mask openings or positioned to expose a portion of the hardmask layer adjacent to the first mask opening in the array of mask openings. The process for etching the multiple layers includes forming a plasma in a processing region of a process chamber, the plasma including a process gas composition, the plasma being formed over the first photoresist layer and the openings formed therein. The process for etching the multiple alternating layers etches the first photoresist layer such that each mask opening in the array of mask openings is sequentially exposed to the formed plasma during the process for etching the multiple alternating layers to form patterned openings, each having a different depth within the alternating layers, in portions of the alternating layers disposed beneath the sequentially exposed mask openings.

[0009]

[0009] The embodiments of the present disclosure may also provide a non-volatile memory device including a plurality of alternating layers, each of which includes a plurality of stacked layer pairs including a first layer including a first material and a second layer including a second material different from the first material, the plurality of stacked layer pairs being stacked in a first direction, and including N stacked layer pairs, N being greater than 10. The non-volatile memory device also includes a plurality of conductive columns, each of which is aligned in a first pitch direction and spaced apart by a pitch length in the first pitch direction, the N-1 conductive columns extending through one or more stacked layer pairs, each of which includes a dielectric layer disposed between a conductive material disposed within the conductive column and a layer of the one or more stacked layer pairs through which the conductive column extends, and a voltage is applied to the conductive material of the conductive columns during operation of the non-volatile memory device. In some embodiments, the first material and the conductive material each include essentially the same material.

[0010]

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments, and therefore should not be considered as limiting the scope thereof, as other equally effective embodiments may be permitted. [Brief description of the drawings]

[0011] [Figure 1] 1 is a simplified schematic example of a conventional 3D NAND memory structure 100. [Figure 2A] 1 is a schematic cross-sectional view of a processing chamber configured to perform one or more of the methods described herein, according to one embodiment. [Figure 2B] FIG. 2 illustrates a pulsed voltage (PV) waveform established at a substrate during processing, according to one embodiment. [Diagram 3] 1 is a simplified schematic example of an improved 3D NAND memory structure according to one or more embodiments described herein. [Figure 4A]FIG. 2 illustrates a simplified schematic portion of a memory structure that may be used to form at least a portion of a 3D NAND memory structure in accordance with one or more embodiments described herein. [Figure 4B-4D] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Fig. 4E-4G] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Fig. 4H-4J] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Figure 4K] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Figure 4L] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Figure 4M] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Figure 4N] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Figure 4O] 6A-6C show simplified schematic portions of the memory structure shown in FIG. 4A during different portions of the method shown in FIG. 5 according to one or more embodiments described herein. [Diagram 5] FIG. 1 is a flow diagram illustrating processes that may be performed to form at least a portion of a 3D NAND memory structure in accordance with one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0018] To facilitate understanding, wherever possible, the same reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0013]

[0019] In the following description, details are illustratively set forth to facilitate understanding of the disclosed subject matter. However, it will be apparent to those skilled in the art that the disclosed embodiments are illustrative and do not cover all possible embodiments. Therefore, it should be understood that reference to the described embodiments is not intended to limit the scope of the present disclosure. Any changes and further modifications to the described devices, instruments, methods, and any further application of the principles of the present disclosure are fully anticipated by those skilled in the art to which the present disclosure pertains. In particular, it is fully anticipated that features, components, and / or steps described with respect to one embodiment may be combined with features, components, and / or steps described with respect to other embodiments of the present disclosure. As used herein, the term "about" may refer to a ±10% variation from the nominal value. It is understood that such variations may be included in any value provided herein.

[0014]

[0020] The embodiments of the present disclosure provided herein include apparatus and methods for forming improved three-dimensional (3D) NAND memory structures by using less complex processing sequences over conventional 3D NAND processing techniques currently known. As devices shrink, efficient structures for fabricating multiple memory cells are needed to maximize the density of memory cells in memory devices. Three-dimensional (3D) NAND technology addresses the challenges of two-dimensional (2D) NAND technology and the technology of stacking memory cells in vertical layers.

[0015]

[0021] The embodiments of the present disclosure provided herein include process sequences that include the use of a selectivity-enhancing etch process configured to selectively etch one or more dielectric layers relative to one or more masking layers using a reactive ion etch process. The reactive ion etch process may include a pulsed plasma ion etch process that includes delivering a radio frequency (RF) generated RF waveform from an RF generator to one or more electrodes in a process chamber and delivering a pulsed voltage (PV) waveform from one or more pulsed voltage (PV) generators to one or more electrodes disposed in a substrate support positioned in the process chamber. Thus, the pulsed voltage technique may enable a method of precisely controlling plasma ion density and ion energy during plasma processing. It is believed that precise control of plasma ion density and ion energy, in combination with the use of desirable dry etch chemistries, may be used to enhance etch selectivity and improve the process of forming the novel 3D NAND memory structures disclosed herein. Furthermore, by using one or more methods described herein, etch selectivity and improved etch process results may be further achieved by controlled formation of a fluorocarbon-based polymer layer on the conductive material surfaces exposed during the etch process.

[0016] Plasma Processing Chamber

[0022] 2A is a schematic cross-sectional view of a processing chamber 200 configured to perform one or more of the methods of forming a 3D NAND memory structure described herein. In one embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some embodiments, a plasma is formed in the processing chamber 200 by using a capacitively coupled plasma (CCP) source including an upper electrode assembly 227 disposed in a processing region 229 and including an upper electrode 223 facing a substrate support assembly 236. However, in some embodiments, the processing chamber 200 may alternatively or additionally include an inductively coupled plasma (ICP) source configured to form a plasma in the processing region 229.

[0017]

[0023] The processing chamber 200 also includes a chamber body 213 including one or more sidewalls 222, and a chamber base 224. The upper electrode 223, the one or more sidewalls 222, and the chamber base 224 together collectively define a processing region 229. The one or more sidewalls 222 and the chamber base 224 generally comprise a material sized and shaped to provide structural support for the elements of the processing chamber 200 and are configured to withstand pressure and additional energy applied thereto while a plasma 201 is generated within a vacuum environment maintained within the processing region 229 of the processing chamber 200 during processing. In one embodiment, the one or more sidewalls 222 and the chamber base 224 are formed from a metal, such as aluminum, an aluminum alloy, or stainless steel. A plurality of holes 223A formed in the upper electrode 223 are used to supply one or more process gases to the processing region 229 from a process gas source 219 in fluid communication therewith. The substrate 203 is loaded into and removed from the processing region 229 through an opening (not shown) in one of the sidewalls 222, which opening is sealed with a slit valve (not shown) during plasma processing of the substrate 203. Here, the substrate 203 is transferred to and from the substrate receiving surface 205A of the substrate support 205 using a lift pin system (not shown).

[0018]

[0024] During plasma processing by the process chamber 200, ions are purposefully accelerated towards the substrate 203 by a voltage drop in an electron repulsive sheath formed above a substrate placed on top of the substrate support assembly 236. Without intending to be limiting as to the scope of the invention provided herein, the substrate support assembly 236 is sometimes referred to herein as a "cathode assembly" or "cathode." In some embodiments, the substrate support assembly 236 includes a substrate support 205 and a support base 207. The substrate support 205 may include an electrostatic chuck (ESC) assembly configured to chuck (e.g., hold) the substrate 203 on the substrate receiving surface 205A.

[0019]

[0025] In some embodiments, the plasma processing chamber 200 is configured to form the plasma by using an RF generator assembly 263 that includes an RF generator 218 coupled to an RF electrode through a transmission line 267 and an RF matching network 261 ("RF match"). The RF matching network 261 is configured to tune the apparent load to 50 Ohms to minimize reflected power during plasma processing and maximize power delivery efficiency to a composite load 230 formed in the processing region 229. In some embodiments, the RF electrode includes a metal plate positioned parallel to a plasma-facing surface of a substrate 203, such as a support base 207.

[0020]

[0026] 2A, the upper electrode assembly 231 includes an upper electrode 223 and a lid plate 239 configured to form a showerhead configured to evenly distribute one or more gases provided from a process gas source 219 to the processing region 229 through a plurality of holes 223A formed in the upper electrode 223. The upper electrode assembly 231 is also positioned on and electrically isolated from the grounded sidewall 222 of the processing chamber 200 by a lid insulator 237. In some embodiments, the upper electrode 223 is electrically coupled to a plasma generator assembly 263 configured to ignite and sustain a plasma 201 in the processing region 229 by using an RF generator 218 coupled to the upper electrode 223 through an RF matching network 261. However, in some embodiments, the plasma generator assembly 263 is not coupled to the upper electrode 223, in which case the upper electrode 223 may be grounded, and the RF power used to form the plasma 201 in the processing region 229 is supplied to the bias electrode 204 and the support base 207.

[0021]

[0027] In general, the generated RF waveform (e.g., a sinusoidal waveform) provided by the RF generator 218 is configured to establish and maintain a plasma in the processing chamber. The RF waveform can be delivered during portions of the plasma process while a pulse voltage (PV) waveform is delivered from the pulse voltage (PV) generator 250, thus resulting in a desired ion energy distribution function (IEDF) at the surface of the substrate 203 during one or more plasma processing steps performed in the processing chamber. The pulse voltage (PV) waveform provided from the pulse voltage (PV) generator 250 is configured to control a sheath voltage across the surface of the substrate 203 positioned on the substrate support 205 of the substrate support assembly 236. In some embodiments, the one or more pulse voltage (PV) generators 250 are configured to establish a pulse voltage waveform at one or more bias electrodes 204 disposed in the substrate support assembly 236. In some embodiments, the one or more bias electrodes 204 include a chucking electrode separated from the substrate 203 by a thin layer (e.g., 0.1 mm to 0.7 mm) of dielectric material formed in the substrate support assembly 236, and optionally an edge control electrode 215 disposed in or below an edge ring 214 that surrounds the substrate 203 when the substrate 203 is disposed on the substrate support surface 205A of the substrate support assembly 236. In one embodiment, the first PV generator 250 is electrically coupled to the bias electrode 204 through an RF filter 251 and a transmission line 257, and the second PV generator 250 is electrically coupled to the edge control electrode 215 through an RF filter 251 and a transmission line 258. As described further below, the PV waveform can be configured to create a substantially constant sheath voltage (e.g., the difference between the plasma potential and the substrate potential) during a significant portion of the PV waveform's pulse period, which corresponds to a single (narrow) peak that comprises the ion energy distribution function (IEDF) of the ions arriving at the substrate during that portion of the pulse period, also referred to herein as the "ion current phase." The plasma processes disclosed herein can be used to control the interaction of the plasma with the substrate surface during processing.In some configurations, the plasma processes disclosed herein are used to control the profile of features formed on a surface of a substrate 203 during processing. In some embodiments, a pulsed voltage waveform is established by a PV generator 250 electrically coupled to a bias electrode 204 disposed in a substrate support assembly 236 disposed in the plasma processing chamber 200.

[0022]

[0028] In some embodiments, the RF generator assembly 260 is configured to deliver RF power to a support base 207 disposed within the substrate support assembly 236 proximate to the ESC substrate support 205. The RF power provided to the support base 207 is configured to ignite and maintain a processing plasma 201 formed using a processing gas disposed within the processing region 229. In some embodiments, the support base 207 is an RF electrode electrically coupled to the RF generator 218 via an RF matching circuit 261 and a first filter assembly 262, both disposed within the RF generator assembly 260. In some embodiments, the plasma generator assembly 260 and the RF generator 218 are used to ignite and maintain the processing plasma 201 using a field generated by the processing gas disposed within the processing region 229 and the RF power provided by the RF generator 218 to the support base 207. The processing region 229 is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet 220 to maintain the processing region 229 at sub-atmospheric pressure conditions and to evacuate processing and / or other gases therefrom. A substrate support assembly 236 disposed in the processing region 229 is disposed on a support shaft 238 that is grounded and extends through the chamber base 224. However, in some embodiments, an RF generator assembly 260 is configured to deliver RF power to a bias electrode 204 disposed on the substrate support 205 relative to the support base 207. The RF generator 218 may be configured to supply an RF signal to the electrode at an RF frequency greater than about 300 kHz, such as a frequency in a range of about 300 kHz to 60 MHz, or alternatively, about 2 MHz to about 40 MHz.

[0023]

[0029] The substrate support assembly 236 generally includes a substrate support 205 (e.g., an ESC substrate support) and a support base 207, as briefly described above. In some embodiments, the substrate support assembly 236 may further include an insulator plate 211 and a ground plate 212, as further described below. The substrate support 205 is thermally coupled to and disposed on the support base 207. In some embodiments, the support base 207 is configured to regulate a temperature of the substrate support 205 and a substrate 203 disposed on the substrate support 205 during substrate processing. In some embodiments, the support base 207 is fluidly coupled to a coolant source (not shown), such as a refrigerant source or a water source having a relatively high electrical resistance, and includes one or more cooling channels (not shown) disposed therein that are in fluid communication with the coolant source. In some embodiments, the substrate support 205 includes a heater (not shown), such as a resistive heating element embedded in its dielectric material. Here, the support base 207 is formed from a corrosion-resistant, heat-conductive material, for example a corrosion-resistant metal such as aluminum, an aluminum alloy, stainless steel, etc., and is bonded to the substrate support by adhesive or mechanical means.

[0024]

[0030] The support base 207 is electrically insulated from the chamber base 224 by an insulator plate 211, and a ground plate 212 is interposed between the insulator plate 211 and the chamber base 224. In some embodiments, the process chamber 200 further includes a quartz pipe 210 or collar that at least partially surrounds portions of the substrate support assembly 236 to prevent corrosion of the ESC substrate support 205 and / or the support base 207 from contact with corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz pipe 210, the insulator plate 211, and the ground plate 212 are surrounded by a liner 208, where a plasma screen 209, approximately coplanar with the substrate receiving surface of the ESC substrate support 205, prevents plasma from forming in the region between the liner 208 and one or more sidewalls 222.

[0025]

[0031] The substrate support 205 is typically formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In an embodiment herein, the substrate support 205 further includes a bias electrode 204 embedded in the dielectric material. In one configuration, the bias electrode 204 is a chucking pole used to chuck the substrate 203 to the substrate receiving surface 205A of the substrate support 205, also referred to herein as an ESC substrate support, and bias the substrate 203 against the processing plasma 201 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 204 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof, spaced from the substrate receiving surface 205A of the substrate support 205 by a layer of dielectric material of the substrate support 205. In some embodiments, the bias electrode 204 is electrically coupled to a bias compensation module 216, which supplies it with a chucking voltage, such as a static DC voltage of about −5000 V to about 5000 V, using an electrical conductor, such as a coaxial transmission line 206 (e.g., a coaxial cable). The high voltage module 216 includes a bias compensation circuit element 216A, a DC power supply 255, and a blocking capacitor C5 disposed between the output of a pulsed voltage waveform generator (PVWG) 250 and the bias electrode 204.

[0026]

[0032] The processing chamber 200 further includes a controller 226, also referred to herein as a processing chamber controller. The controller 226 herein includes a central processing unit (CPU) 233, a memory 234, and support circuits 235. The controller 226 is used to control the process sequence used to process the substrate 203, including the substrate bias method described herein. The CPU 233 is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated sub-processors. The memory 234 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage, local or remote. The support circuits 235 are conventionally coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 234 to instruct the processor in the CPU 233. The software programs (or computer instructions) readable by the CPU 233 of the controller 226 determine tasks that can be performed by the components in the processing chamber 200. Preferably, a program readable by the CPU 233 in the controller 226 includes code that, when executed by the processor (CPU 233), performs tasks related to monitoring and executing the electrode biasing schemes described herein. The program includes instructions used to control various hardware and electrical components within the processing chamber 200 to perform various process tasks and various process sequences used to implement the electrode biasing schemes described herein.

[0027]

[0033] During processing, one or more PV generators in the PV waveform generator 250 of the first PV source assembly 296 and the second PV source assembly 297 establish a pulsed voltage waveform across a load disposed with the processing chamber 200. Overall control of the delivery of the PV waveform from each PV waveform generator 250 is controlled using signals provided from the controller 226. In one embodiment, the PV waveform generator 250 is configured to maintain a predetermined substantially constant positive voltage across its output (i.e., relative to ground) for a regularly repeated time interval of a predetermined length by repeatedly closing and opening its internal switches at a predetermined rate. Alternatively, in one embodiment, the PV waveform generator 250 maintains a predetermined substantially constant negative voltage across its output (i.e., relative to ground) for a regularly repeated time interval of a predetermined length by repeatedly closing and opening its internal switches at a predetermined rate. Each PV waveform generator 250 includes a PV generator (e.g., a DC power supply) and one or more electrical components configured to provide a PV waveform to an output port, such as a high repetition rate switch, a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown). PV waveform generator 250 may in some cases be used primarily as a charge injector (current source) rather than as a constant voltage source. Thus, there are no stringent requirements on the stability of the output voltage, in that it may vary over time even when the switch remains in the closed (on) position.

[0028]

[0034] 2B illustrates an example of a voltage waveform, such as a series of asymmetric PV waveforms (e.g., non-sinusoidal waveforms) pulsed voltage (PV) waveform 281, established at the substrate 203 by an established PV waveform formed at the bias electrode 204 or edge control electrode 215 by the PV waveform generator 250. The substrate PV waveform 281 is established at the substrate surface during processing and includes a sheath collapse and ESC recharge phase 282 (or, for ease of explanation, a sheath collapse phase 282) extending between points 270 and 271 of the exemplary substrate PV waveform 281, a sheath formation phase 283 extending between points 271 and 272, and an ion current phase 284 extending between point 272 and back to the starting point at point 270 of the next sequentially established pulsed voltage waveform. In some embodiments, the sheath collapse phase 282 and the sheath formation phase 283 last for a first time interval and the ion current phase 284 lasts for a second time interval, the first time interval being from about 100 nanoseconds (ns) to about 500 ns, e.g., 200 ns to 400 ns, and the second time interval being at least 80% of each cycle of the series of PV waveforms, e.g., 85% to 90% of each cycle. The plasma potential curve 286 shows the local plasma potential during delivery of a negative pulse waveform established at the bias electrode 204 and / or the edge control electrode 215 by use of one or more PV waveform generators 250, thus establishing the pulse voltage (PV) waveform 281 at the substrate 203. By delivering and controlling the PV waveforms supplied to the bias electrode 204 during plasma processing, a desired ion energy distribution function (IEDF), such as a nearly monoenergetic IEDF, can be created. The generation and control of the PV waveform characteristics (e.g., peak-to-peak voltage, duty cycle, frequency, etc.) allows for precise control of plasma ion density and generated ion energy, and also results in more controllable deposition of fluorinated carbon (C) on the surface of conductive materials (e.g., W) often found at the bottom of etched features. x F y)-based polymers are deposited. The formation of polymer deposits on the conductive material surface improves the etch selectivity of dry etch chemistries for the conductive material versus the intervening etched dielectric material. Process gases that may be suitable for the plasma etching processes disclosed herein generally include fluorides (C4F6, C3F6, CF4, NF3, C3F8, C4F8, CHF4, CH3F, CH2F2, SF6, SiF4, and WF6), chlorides (HCl, C2, BCl3), bromides (Br2, HBr), or oxygen-containing gases (e.g., O3, O2, CO2, CO, H2O, NO, NO2, N2O, CO, etc.), and may optionally include inert gases such as argon (Ar), xenon (Xe), nitrogen (N2), krypton (Kr), or helium (He).

[0029]

[0035] In some embodiments, the process chamber 200 includes one or more sensor assemblies 290 including a sensor 291 and a probe 292 positioned and configured to view a portion of the substrate surface 203A during plasma processing. In one configuration, the probe 292 (e.g., an optical fiber) and the sensor 291 are positioned to detect a property of the portion of the substrate surface 203A through a portion of the upper electrode assembly 231 by using an optical emission spectroscopy (OES) technique, such as an interferometer technique. In some embodiments, one or more of the sensor assemblies 290 are configured to detect a property of the portion of the substrate surface or a material disposed thereon, and then provide a signal to the controller 226 such that the information regarding the state of the substrate surface or the material thereon can be used to determine whether one or more characteristics of a plasma process running in the process chamber need to be adjusted by the controller 226. The sensor assembly 290 can be configured to detect a state (e.g., a relative percentage of completion) or an endpoint of the etch process by detecting the amount of interference and / or light transmitted to and reflected from the surface of the substrate by the probe 292. In one example, the sensor assembly 290 performs in situ measurements of the thickness of nitride material formed in a 3D NAND structure and / or determines the relative depth of etched features formed on a substrate during processing.

[0030] 3D NAND Device and Processing Sequence

[0036] FIG. 3 is a simplified schematic example of an improved 3D NAND memory structure 300. Similar to the portion of the 3D NAND memory structure 100 illustrated in FIG. 1, the 3D NAND memory structure 300 includes a channel structure 117 oriented perpendicular (e.g., in the −Z direction) to a major surface of a substrate 401, the channel structure 117 including an etch stop layer 402 and a common source line layer (CSL) 403 disposed thereon. An upper portion of the vertical channel layer structure 117 of the 3D NAND memory structure 300 includes a plurality of bit lines 118. The 3D NAND memory structure 300 includes a plurality of stacked layers arranged into stacked layer pairs 320, each including alternating layers of a dielectric layer 416 and a conductive material 465. The alternating layers of conductive material 465 form a word line layer 415. The stacked layer pairs 320 are alternately stacked in a direction perpendicular to the major surface of the substrate 401 to form portions of a series of transistors, each including a portion of one of the channel structures 117. Stacked layer pair 320 may also be referred to herein as the "stacked layer pair of the device."

[0031]

[0037] The 3D NAND memory structure 300 desirably does not include the complex and costly staircase structure 110 found in the conventional 3D NAND memory structure illustrated in Figure 1. The 3D NAND memory structure 300 instead includes interconnect regions 310 formed above the memory layer stack at opposing edges of the 3D NAND memory structure 300. Each of the interconnect regions 310 includes a plurality of conductive columns 314 formed to a desired depth within the memory layer stack, eliminating the need for the formation of staircases as required in conventional 3D NAND memory structures.

[0032]

[0038] As described below in connection with Figures 4A-4O and 5, the method of forming the 3D NAND memory structure 300 is significantly simplified relative to conventional processes involving the formation of stair-like structures. Furthermore, the lateral width 312 of the interconnect region 310 of the 3D NAND memory structure 300 relative to the lateral width 112 of the stair-like region 110 of the 3D NAND memory structure 100 can be approximately 4-5 times smaller than conventional stair-like designs, so that the required overall lateral dimension 205 of the 3D NAND memory structure 300 is significantly reduced relative to the stair-like structures that comprise the 3D NAND memory structure. The reduced lateral width reduction is due in large part to the reduced required pitch 311 between the conductive columns 314 relative to the pitch 111 between the conductive columns 114 of conventional 3D NAND designs due to the reduced need to include large exposed lateral areas of the stair-steps to ensure that the etched openings used to form the conductive columns 114 land reliably on the stair-like features after processing. The configurations disclosed herein also significantly relax requirements regarding the need to align the openings used to form the conductive columns 314 to the wordline layer 415 of the designs disclosed herein relative to the wordline layer 115 found in conventional 3D NAND designs. Additionally, the manufacturing process used to form the interconnect regions 310 is much less complex, improving device yields and significantly reducing the cost of forming 3D NAND memory.

[0033]

[0039] Figure 5 illustrates a method 500 for use in the manufacture of semiconductor devices, such as forming at least a portion of a 3D NAND memory structure 300. Figures 4A-4O are schematic cross-sectional side views of a portion of a 3D NAND memory structure during one or more of the steps illustrated in Figure 5, according to one or more embodiments described herein. Figures 4B-4K are enlarged schematic cross-sectional side views of a portion of the memory structure 400 illustrated in Figure 4A during one or more steps illustrated in Figure 5.

[0034]

[0040] The method 500 begins at step 502 with forming the basic building blocks of a 3D NAND memory structure on a surface of a substrate 401, as shown in FIG. 4A. For ease of explanation, the starting basic building blocks of a 3D NAND memory structure is referred to herein as memory structure 400, which essentially includes an etch stop layer 402, a common source line layer (CSL) 403, and a plurality of alternating layers 425 disposed on a surface of the substrate 401. The plurality of alternating layers 425 includes a series of alternating layers of a first dielectric material 413 and a second dielectric material 416. In some embodiments, the plurality of alternating layers 425 includes a first dielectric material 413 that is a nitride material (e.g., silicon nitride (SiN x )) and the second dielectric material 416 is an oxide material (e.g., SiO X In some embodiments, the plurality of alternating layers 425 includes a stack of ON layers where the first dielectric material 413 is a silicon material (e.g., polysilicon) and the second dielectric material 416 is an oxide material (e.g., SiO2). The substrate 401 may be any suitable starting material for forming integrated circuits, such as a silicon (Si) wafer or a germanium (Ge) wafer. The semiconductor substrate 401 may be crystalline silicon (e.g., Si <100> or Si <111> ), Si3N4, strained silicon, silicon germanium, doped or undoped polysilicon (poly-Si), doped or undoped silicon, patterned or unpatterned wafer, silicon on insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, etc. The substrate 401 may be a circular wafer, such as a 200 mm, 300 mm, 450 mm diameter wafer, or may be a rectangular or square panel. The common source line layer (CSL) 403 and / or etch stop layer 402 may be made of materials such as tungsten (W), silicon nitride (SiN), poly-Si, or combinations thereof.

[0035]

[0041] During step 504, a hard mask layer 406 and a first photoresist (PR) layer 407 are formed and patterned over the plurality of alternating layers 425 to form a series of patterned openings 414 therein. In one embodiment, as shown in FIGS. 4A and 4B, the first photoresist layer 407 includes an array of openings (e.g., four openings 414) positioned at opposing edges of the memory structure 400 and spaced apart in a first direction (e.g., the X-direction) by a pitch distance 414A. Each of the openings 414 is positioned and sized such that a subsequent etching step using the first photoresist layer 407 can be used to enable the formation of one or more conductive columns 314 (FIG. 3). The openings 414 in the array of openings can be formed, for example, in a rectangular or hexagonal array distributed across a lateral plane (i.e., the XY plane).

[0036]

[0042] In some embodiments, the hard mask layer 406 and the first photoresist (PR) layer 407 are formed on a layer of a second dielectric material 416 disposed on a plurality of stacked layer pairs 420, each including a first dielectric material 413 and a second dielectric material 416. The stacked layer pairs 420 are also referred to herein as "temporary stacked layer pairs" because each stacked pair includes one or more layers, or a significant portion of one or more layers, that may not result in the final 3D NAND device. The hard mask layer 406 may be formed of any suitable material, such as titanium nitride (TiN), silicon nitride, aluminum oxide (AlO X ), or other suitable materials. The first photoresist (PR) layer 407 can be a conventional photoresist material.

[0037]

[0043] 4C, an etching process is then performed on the memory structure 400 to form a pattern of openings 417 in the hardmask layer 406 based on the pattern formed in the photoresist layer 407 during step 504. The etching process may be performed in the processing chamber 200 using a plasma etching process that selectively etches the hardmask material 406 but stops on an underlying layer, such as the second dielectric material 416 disposed on the multiple stacked layer pairs 420.

[0038]

[0044] In step 508, as shown in FIG. 4D, the first photoresist layer 407 is removed from the surface 417A of the hard mask layer 406, and a second photoresist layer 418 is deposited over the surface 417A of the hard mask layer 406 and the openings 417 formed in the hard mask layer 406. The second photoresist layer 418 may be deposited over the surface 417A of the hard mask layer 406 and the openings 417 by a spin-on process, a chemical vapor deposition (CVD) process, or other similar process. The second photoresist layer 418 is formed to have a first thickness 421, or original thickness 421, in a second direction (i.e., the Z direction). In some embodiments, the second photoresist layer 418 comprises a material different from the material used to form the first photoresist layer 407. In general, the second photoresist layer 418 comprises a material that is etched at a known or desired rate by the chemistry of the plasma formed during the subsequent etching process performed during step 512, and need not be a photosensitive material. Without intending to limit the disclosure provided herein, in some embodiments, the second photoresist layer 418 comprises an organic material, such as a polymeric material. In some embodiments, the second photoresist layer 418 includes, but is not limited to, a positive photoresist, a DNQ-novolac photoresist, a negative photoresist, an epoxy-based polymer, an off-stoichiometric trithiol-ene (OSTE) polymer, a polymer doped with metal particles, a polymer doped with light enhancing particles, or an EUV photoresist. However, in some embodiments, the second photoresist layer 418 may include an inorganic material, such as a metal oxide, such as a tin-containing oxide.

[0039]

[0045] In step 510, the second photoresist layer 418 is patterned to form one or more patterned openings 419 therein. The openings 419 are formed to expose the surface 417A of the hardmask 406 and to provide an exposed surface 418A of the second photoresist layer 418. In one configuration, as shown in FIG. 4D, the patterned opening 419 is positioned to expose a portion of the hardmask layer 406 adjacent a first opening (i.e., the right-most opening 417) of the array of openings formed in the hardmask layer 406. In another configuration, the patterned opening 419 may be formed to expose a first opening of the array of openings 417 formed in the hardmask layer 406. In either configuration, at least a portion of the second photoresist layer 418 remains disposed over the surface 417A of the hardmask layer 406 and at least one or more of the openings 417 formed in the hardmask layer 406, as shown in FIG. 4D. In some embodiments, a first patterned opening 419 is formed at a first edge of memory structure 400 and a second patterned opening 419 is formed at a second edge of memory structure 400. In some configurations, the first edge and the second edge are at opposing edges of memory structure 400. If memory structure 400 is rectangular, one or more patterned openings 419 may be formed at desired locations relative to the array of openings on each of the four sides of memory structure 400 when viewed from the top (i.e., in the -Z direction).

[0040]

[0046] Next, during step 512, a plasma etching process is performed on the memory structure 400, which ultimately forms a series of patterned openings in the alternating layers 425, such as patterned openings 419A-419D, each having a depth that varies within the alternating layers 425, as shown in Figures 4H and 4I. At the end of step 512, the formed patterned openings 419A-419D have depths in the alternating layers 425 such that a bottom region of each of the patterned openings contacts at least a portion of the first dielectric layer material 413 in the stacked layer pair 420 positioned at a desired depth within the alternating layers 425. The bottom region of the patterned openings may include a bottom surface and a portion of a side surface of the patterned opening. In one embodiment, as shown generally in Figures 4H and 4I, upon completion of step 512, the bottom surface of patterned opening 419A is in contact with the first dielectric layer material 413 in the fourth stacked layer pair 420 of alternating layers 425, patterned opening 419B is in contact with the first dielectric layer material 413 in the third stacked layer pair 420 of alternating layers 425, patterned opening 419C is in contact with the first dielectric layer material 413 in the second stacked layer pair 420 of alternating layers 425, and patterned opening 419D is in contact with the first dielectric layer material 413 in the first stacked layer pair 420 of alternating layers 425. At the end of step 512, at least N minus one (i.e., N-1) patterned openings (e.g., patterned openings 419A-419C) extend through at least one of the stacked layer pairs 420, where N is equal to the total number of stacked layer pairs 420 in the stack of alternating layers 425. In typical 3D NAND devices today, N is greater than 10, or greater than 64, or greater than 85, or greater than 100, or greater than 150.

[0041]

[0047] 4B-4H, the plasma etch process performed during step 512 is configured to form patterned openings 419A-419D in the interconnect region 310 formed on the memory structure 400 by performing the plasma etch process for a first period of time. In some embodiments, one or more process variables of the plasma etch process (e.g., process time, RF power, process gas composition, PV waveform characteristics, pressure, etc.) are adjusted during the first period of time using commands sent from the controller 226 via signals received from one or more sensors coupled to the process chamber 200, such as the sensor assembly 290, further described below. As shown in FIGS. 4E-4H, the plasma etch process performed during step 512 sequentially exposes each of the mask openings 417 in the array of mask openings formed in the hard mask 406 due to the position of the exposed surface 418A changing throughout the plasma etch process. Because alternating layer 425 is exposed to plasma for different lengths of time through each of mask openings 417 sequentially exposed during the plasma etching process, each of the patterned openings 419A-D formed has a different depth within alternating layer 425.

[0042]

[0048] 4E illustrates a portion of the memory structure 400 after a first time interval within a first time period has elapsed. As shown in FIG. 4E, the plasma etching process etches a first portion of the second photoresist layer 418, thereby exposing a first opening 417 in the array of openings, thus allowing the chemistry of the plasma processing gas to etch a portion of the alternating layer 425 (e.g., the second dielectric layer 416) to a desired depth 441. The thickness and / or composition of the "first" second dielectric layer 416, which is the topmost second dielectric layer 416 positioned over the multiple stacked layer pairs 420 shown in FIGS. 4E-4H, may be adjusted so that the etch rate and / or time it takes to etch the "first" second dielectric layer 416 is similar to the average etch rate and / or etch time it takes the plasma etching process to etch the stacked layer pairs 420. However, in some embodiments, the "first" second dielectric layer 416 shown in Figures 4E-4H may be removed or replaced with a third dielectric layer having a different material composition than the first and second dielectric layers 413 and 416, respectively. During the first time interval, the exposed surface 418A of the second photoresist layer 418 is laterally etched to a point near the second opening 417 in the array of openings. The chemistry of the plasma processing gas formed during the first time interval is selected such that the amount 451 of the second photoresist layer 418 etched laterally (i.e., in the -X direction) is proportional to the desired amount (i.e., depth 441) that the alternating layers 425 are etched vertically (i.e., in the -Z direction). As shown in Figure 4E, the plasma etching process also removes a portion of the top surface of the second photoresist layer 418 during the first time interval, and thus the thickness of the second photoresist layer 418 is reduced from its original thickness 421.

[0043]

[0049] In general, during a portion of the plasma etching process, the amount that the second photoresist layer 418 is etched during a time interval versus the depth to which the alternating layers 425 are etched during the same time interval is set by the etch selectivity of the chemistry of the plasma processing gas for the material in the alternating layers 425 relative to the material(s) in the second photoresist layer 418. In some embodiments, the selectivity of the chemistry of the plasma processing gas is adjusted during the plasma etching process such that the lateral etch rate (i.e., etch rate in the X and / or Y directions) of the second photoresist layer 418 and the vertical etch rate (i.e., etch rate in the Z direction) of the alternating layers 425 are proportional to each other such that the time it takes to etch the second photoresist layer 418 a distance of one pitch length 414A is equal to the time it takes to etch one stacked layer pair 420 vertically. For ease of explanation, the plasma processing gas chemistries and process variable settings used to achieve this desired selectivity are referred to herein as having the desired "lateral-to-vertical etch selectivity" or as being capable of achieving the desired "lateral-to-vertical etch selectivity."

[0044]

[0050] 4F illustrates a portion of the memory structure after a second time interval within the first period of time has elapsed. As shown in FIG. 4F, the plasma etching process exposes a second opening 417 in the array of openings, thus allowing the chemicals of the plasma processing gas to etch a portion of the alternating layers 425 below the second opening to a desired depth 441, and also etches the alternating layers 425 below the first opening 417 to an additional depth 442. During the second time interval, the exposed surface 418A of the second photoresist layer 418 has also been etched to a point near the third opening 417 in the array of openings. The chemistry of the plasma processing gas formed during the second time interval is selected such that the amount 452 of the second photoresist layer 418 etched laterally (i.e., in the -X direction) is proportional to the desired amount (i.e., depths 441 and 442) of the alternating layers 425 etched vertically (i.e., in the -Z direction), and thus has a desired lateral to vertical etch selectivity during the second time interval. As shown in FIG. 4F, the plasma etching process also removes a portion of the top surface of the second photoresist layer 418 during the second time interval, and thus the thickness of the second photoresist layer 418 is reduced from its thickness 422 formed during the first time interval to a new thickness 423.

[0045]

[0051] FIG. 4G illustrates a portion of the memory structure after a third time interval within the first period has elapsed. As shown in FIG. 4G, the plasma etching process exposes a third opening 417 in the array of openings, thus allowing the plasma processing gas chemistry to etch a portion of the alternating layers 425 below the third opening to a desired depth 441, and also etches the alternating layers 425 below the first and second openings 417 to additional depths 442 and 443, respectively. During the third time interval, the exposed surface 418A of the second photoresist layer 418 has also been etched to a point near the fourth opening 417 in the array of openings. The plasma processing gas chemistry formed during the third time interval is selected such that the amount 453 of the second photoresist layer 418 etched laterally is proportional to the desired amount of the alternating layers 425 etched vertically (i.e., depths 441, 442, and 443), thus providing a desired lateral-to-vertical etch selectivity during the third time interval. As shown in FIG. 4G, the plasma etching process also removes a portion of the top surface of the second photoresist layer 418 during the third time interval, such that the thickness of the second photoresist layer 418 is reduced from its thickness 423 formed during the second time interval to a new thickness 424.

[0046]

[0052] FIG 4H illustrates a portion of the memory structure after a fourth time interval within the first time period has elapsed. As shown in FIG 4H, the plasma etching process exposes a fourth opening 417 in the array of openings, thereby allowing the plasma processing gas chemistry to etch a portion of the alternating layers 425 below the fourth opening to a desired depth 441, and the alternating layers 425 below the first, second, and third openings 417 to additional depths 442, 443, and 444, respectively. The plasma processing gas chemistry formed during the fourth time interval is selected such that the amount 454 of the second photoresist layer 418 etched laterally is proportional to the desired amount of the alternating layers 425 etched vertically (i.e., depths 441, 442, 443, and 444), and thus has a desired lateral-to-vertical etch selectivity during the fourth time interval.

[0047]

[0053] In some embodiments, because at least a portion of the second photoresist layer 418 remains on the hard mask layer after forming the patterned openings 419A-419D at the end of step 512 (see FIG. 4H ), the original thickness 421 of the second photoresist layer 418 can be selected such that a desired amount of the second resist layer 418 remains on the surface of the hard mask layer 406 at the end of the plasma etching process. If the original thickness 421 of the second photoresist layer 418 is selected too thin, the openings 417 in the hard mask layer may be exposed too early in the plasma etching process that enables the sequential formation of the patterned openings 419 in the alternating layers 425, as described herein. Also, if the original thickness 421 of the second photoresist layer 418 is selected too thick, it may be more difficult to remove the second photoresist layer 418 from the hard mask layer 406 before subsequent steps can be performed on the substrate 401.

[0048]

[0054] The plasma etch process performed during operation 512, such as during the first, second, third and fourth time intervals, includes forming a plasma process gas chemistry by delivering a process gas composition to a processing region of the plasma processing chamber to form a chamber pressure of 1 mT to 500 mT, where delivering the process gas composition includes delivering a first process gas at a first flow rate and delivering a second process gas at a second flow rate. The first process gas may include a first fluorocarbon-containing gas, such as at least one of C4F6, C3F6, CF4, NF3, C3F8, C4F8, CH3F, CH2F2, SF6, SiF4, and WF6, and the second process gas may include at least one of HBr, He, Ar, Xe, N2, Kr, and O2. The chemistry of the plasma processing gas may include ions, radicals and neutrals of the different gases found in the processing gas composition, and the amount of ions, radicals or neutrals generated for a given processing gas composition can be adjusted by controlling the amount of RF power, the amount of PV applied, and the chamber pressure maintained during processing.

[0049]

[0055] The plasma etching process also includes generating and maintaining a plasma in the processing chamber by delivering an RF signal to an electrode in the processing chamber. In one embodiment, the electrode is a support base 207 disposed in the substrate support assembly 236. The RF signal may include a signal provided from an RF generator 218 configured to establish and maintain a plasma in the processing chamber 200. The RF signal may be delivered to the electrode at an RF frequency greater than about 300 kHz, such as from about 300 kHz to 60 MHz, or even at a frequency in the range of about 2 MHz to about 40 MHz, such as 13.56 MHz or 40 MHz.

[0050]

[0056] The plasma etching process also includes delivering a pulsed voltage (PV) waveform established at an electrode disposed in the processing region 229 of the processing chamber 200, such as a bias electrode 204 disposed in a substrate support 205 of the substrate support assembly 236. The substrate support 205 may be maintained at a temperature of −80° C. to 500° C. The process of delivering the PV waveform may include providing an asymmetric PV pulse at a frequency greater than 100 kHz, such as 200 kHz to 800 kHz, or about 400 kHz to about 500 kHz. As described above, the asymmetric PV pulse may include a sheath collapse phase 282 and a sheath formation phase 283 that last for a first time interval, and an ion current phase 284 that lasts for a second time interval. The first time interval may be about 100 nanoseconds (ns) to about 500 ns, e.g., 200 ns to 400 ns, and the second time interval occupies at least 80% of each cycle of the series of PV waveforms, e.g., 85% to 90% of each cycle. The delivery of the PV waveform may have a burst duty cycle of 1% to 99%, for example, about 50% to about 95%, and a burst delivery length (T ON The PV waveform may also include delivering a burst of asymmetric nanosecond PV pulses with a peak-to-peak voltage of about 2 kilovolts (kV) to about 20 kV.

[0051]

[0057] In some embodiments, one or more process variables are adjusted to control the depth 441-444 of the patterned openings 419A-419D and the amount the second photoresist layer 418 is laterally etched during one or more portions of the first, second, third, and fourth time intervals of the plasma etch process. Due to the presence and need for etching of the first dielectric layer material 413 and the second dielectric layer 416 during the first, second, third, and / or fourth time intervals, it may be desirable to adjust one or more of the process variables to reduce the total etch time and / or etch rate during one or more portions of each of the first, second, third, and fourth time intervals. In one example, one or more process variables can be adjusted during a first portion of each time interval to adjust the etch process to etch a silicon nitride-containing material, and then one or more process variables can be adjusted during a second portion of each time interval to adjust the etch process to etch a silicon oxide-containing material. In one embodiment, the one or more process variables that are adjusted may include the chemical composition of the plasma processing gas, the length of the time interval, the chamber pressure, the RF power, and / or the PV voltage waveform characteristics.

[0052]

[0058] In some embodiments, one or more sensor assemblies 290 are used to detect a characteristic of a portion of the substrate surface, such as a portion of the second photoresist layer 418, a portion of the hard mask layer 406, or a combination thereof, to determine a state of the plasma etch process during one or more portions of the first, second, third, and fourth time intervals, and then adjust and / or control one or more aspects of the plasma etch process based on the detected characteristic. During step 512, a signal including information regarding the detected characteristic of the substrate surface is provided to the controller 226, which can then be used by a software algorithm executing within the controller 226 to determine whether one or more characteristics of the plasma etch process need to be adjusted. In one example, the detected characteristic of the portion of the substrate surface may include detecting a state (e.g., a relative percentage of completion) or an end point of a portion of the plasma etch process during the first, second, third, and fourth time intervals by detecting an amount of interference and / or light transmitted and received by the second photoresist layer 418, a portion of the hard mask layer 406, or a combination thereof, through the use of the probes 292 and sensors 291 of the sensor assemblies 290. In another embodiment, the sensor assembly 290 is configured to perform in-situ measurements to determine the relative depths of the patterned openings 419A-419D, the thicknesses (e.g., thicknesses 421, 422, 423, 424 and / or 425) of the second photoresist layer 418 during the first, second, third and fourth time intervals, and / or the position of the exposed surface 418A during the first, second, third and fourth time intervals relative to the original position of the exposed surface 418A formed during step 510. The in-situ measurements may include the use of interferometric techniques performed at wavelengths in a spectral range of 200 nanometers (nm) to 1700 nm, e.g., 200 nm to 800 nm. Thus, during the plasma etching process, the controller 226 may receive a signal from the sensor 291 positioned to detect a property of the surface of the substrate, the signal including information regarding the detected property of the substrate surface.Software executing on the controller 226 can then determine that one or more characteristics of the plasma etch process need to be adjusted based on the information received in the signal. The controller 226 can then send commands to one or more of the process chamber components to adjust one or more process variables, such as process time, RF power level, process gas composition (e.g., relative amounts of a first process gas or a second process gas), PV waveform characteristics, chamber pressure, or other desired process variables, based on the determined characteristics of the plasma etch process that need to be adjusted.

[0053]

[0059] Next, during step 514, as shown in FIG. 4I, the second photoresist layer 418 and remaining portions of the hard mask layer 406 are removed, and the substrate is cleaned using a conventional process. Also during step 514, as shown in FIG. 4J, a dielectric layer is deposited on the memory structure 400 to form a dielectric layer 461 over the memory structure 400 and within the patterned openings 419A-419D. The dielectric layer 461 is used in the resulting 3D NAND device to separate the conductive portions (e.g., W material) of each conductive column 314 (FIG. 3) from the conductive material 465 used to form the wordline layer 415, allowing each conductive column 314 to penetrate the wordline layer 415 without making an electrical connection. In one embodiment, the conductive columns 314 formed in the openings 419A are prevented from electrically contacting the wordline layers 415 of the first, second, and third stacked layer pairs 320 (FIGS. 3 and 4O), counting from top to bottom, due to the presence of a dielectric layer 461 lining the vertical sides of the patterned openings 419A. The dielectric layer 461 is a silicon oxide (SiO XThe first dielectric material 413 may be formed using atomic layer deposition (ALD), a plasma enhanced ALD process (PEALD), a chemical vapor deposition (CVD) process, a plasma enhanced CVD process (PECVD), or other conformal deposition process to form a dielectric layer that may include silicon (Si), silicon, or other dielectric material that is not substantially etched during the process used to etch the first dielectric material 413. The dielectric layer 461 may have a thickness of 10 angstroms (Å) to 5000 Å, for example 10 Å to 1000 Å.

[0054]

[0060] During step 516, the dielectric layer 461 is removed from the field regions (top surface) of the memory structure 400 and from the bottoms of the patterned openings 419A-419D. The process of removing the dielectric layer 461 from the field regions and the bottoms of the patterned openings 419A-419D can be performed by using a sputter etch process, a dry etch process, or other similar process. In some embodiments, the sputter etch process is performed in an ALD, PEALD, CVD, or PECVD process chamber after the dielectric layer 461 is deposited therein on the memory structure 400 by generating a plasma and biasing the substrate 101 such that ions formed in the plasma tend to selectively etch the field regions and the bottoms of the patterned openings 419A-419D.

[0055]

[0061] Next, as shown in FIG. 4L, during step 518, the patterned openings 419A-419D formed in the memory structure 400 are filled with a fill material 463 that is at least similar and / or essentially the same as the material found in the first dielectric material layer 413. In one embodiment, the fill material is silicon nitride (SiN ) formed using a conventional ALD, PEALD, CVD, PECVD, or physical vapor deposition (PVD) process. X After filling the patterned openings 419A-419D, an overburden layer 464 containing the fill material 463 is formed in the field region of the memory structure 400.

[0056]

[0062] Next, as also shown in Figure 4L, during step 520, gate line slits 119 are formed through the memory structure 400. The process of forming the gate line slits 119 includes depositing a third photoresist layer 467, patterning the third photoresist layer 467 to form openings in the third photoresist layer 467, and then performing one or more conventional dry etching processes to etch through the overburden layer 464, the alternating layer 425, and the common source line layer (CSL) 103 to form separations between regions of the memory structure 425.

[0057]

[0063] 4M, during operation 522, the third photoresist layer 467 and the overburden layer 464 are removed, and the substrate is optionally cleaned using one or more conventional processes to expose the top surface 468 of the memory structure 400. In some embodiments, the overburden layer 464 is removed using a conventional chemical mechanical polishing (CMP) process or other similar process.

[0058]

[0064] Next, during operation 524, a selective etching process is performed on the memory structure 400 to remove the material(s) formed in the patterned openings 419A-419D and the first dielectric layer 413. The process of removing the material in these features can be performed using one or more conventional etching processes used in the formation of 3D NAND structures today. In one embodiment, an isotropic etching process is performed to selectively remove the material(s) formed in the patterned openings 419A-419D and the first dielectric layer 413 relative to the second dielectric layer 416 and the third dielectric layer 461. In some embodiments, the selective etching process includes delivering nitrogen trifluoride (NF3), a mixture of nitrogen trifluoride and helium (He), or a similar process chemistry to the memory structure 400 to remove the desired material.

[0059]

[0065] Next, as shown in FIG. 4N, during step 526, a conductive material 465 is formed in the spaces formed during steps 520 and 522. The conductive material 465 used to form the conductive columns 314 (FIG. 3) is electrically insulated from the one or more stacked layer pairs 320 through which the formed conductive columns 314 extend by the presence of the dielectric layer 461. In some embodiments, the conductive material 465 includes at least one of tungsten (W), platinum (Pt), titanium (Ti), ruthenium (Ru), cobalt (Co), and silicon (Si) formed using a conventional ALD, PEALD, CVD, or PECVD process. In one example, the conductive material 465 includes tungsten (W) formed using a conventional ALD process. During the process of filling the patterned openings 419A-419D, an overburden layer 466 is formed in the field region of the memory structure 400.

[0060]

[0066] The overburden layer 466 is then removed and the substrate is optionally cleaned using one or more conventional processes during operation 528. In some embodiments, the overburden layer 466 is removed using a conventional chemical mechanical polishing (CMP) process or other similar process.

[0061]

[0067] Next, as also shown in Figure 4O, during step 530, the gate line slits 119 are reformed through the memory structure 400. The process of reforming the gate line slits 119 includes depositing a fourth photoresist layer 469, patterning the fourth photoresist layer 469 to form openings in the fourth photoresist layer 469, and then performing one or more conventional dry etching processes to etch the conductive material 465 formed in the gate line slit spaces initially formed during step 526 to form separations between regions of the memory structure 425.

[0062]

[0068] After performing the operations of method 500 on memory structure 400, additional conventional processing steps are performed on memory structure 400 to complete the formation of a functioning 3D NAND device.

[0063]

[0069] The methods, apparatus, and portions of the 3D NAND device structure(s) described herein can be used to form 3D NAND memory structures with reduced size, lower manufacturing costs, and improved reliability over conventional 3D NAND processing techniques currently known. The embodiments of the disclosure provided herein include apparatus and methods for forming improved three-dimensional (3D) NAND memory structures by using less complicated processing sequences over conventional 3D NAND processing techniques currently known. It is believed that precise control of plasma ion density, plasma sheath characteristics, and ion energy, in combination with the use of desirable dry etch chemistries described herein, can be beneficially used to enhance the etch selectivity and improve etch process results used to form the novel 3D NAND memory structures disclosed herein. Furthermore, etch selectivity and improved etch process results can be further achieved by monitoring and controlling various aspects of the plasma etch process as described herein through the use of one or more methods described herein.

[0064]

[0070] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, as determined by the following claims.

Claims

1. 1. A method of forming a non-volatile memory device, comprising:

2. The method of claim 1, further comprising: etching a plurality of alternating layers formed over a surface of a substrate, the alternating layers including vertically stacked first and second layers, the etching of the plurality of layers comprising: (a) delivering a process gas composition to a processing region of a process chamber; (b) forming a plasma in the processing region of the process chamber, the plasma comprising the process gas composition; and (c) while the plasma is formed on a substrate positioned on a substrate support surface of a substrate support disposed within a processing region of a processing chamber, establishing a voltage waveform at an electrode positioned at a distance from the substrate support surface; Including, The substrate is a hardmask layer disposed on the first and second layers of the plurality of alternating layers, the first layer comprising a first material and the second layer comprising a second material different from the first material; an array of mask openings formed in the hard mask layer, the array of mask openings aligned in a first pitch direction and having a pitch length in the first pitch direction between adjacent mask openings in the array of mask openings; a first photoresist layer disposed over the hard mask layer and over two or more mask openings in the array of openings, at least one of the mask openings in the array of openings being exposed to the plasma formed through an opening formed in the first photoresist layer; Including, The process gas composition is further treated by the formed plasma. a size of an opening formed in the first photoresist layer increases in the first pitch direction by a length equal to the pitch length during a first time interval; During the first time interval, thicknesses of the first layer and the second layer are simultaneously etched. The method is selected as follows.

2. The method of claim 1 , wherein the first material comprises silicon and nitrogen and the second material comprises silicon and oxygen.

3. The method of claim 1 , wherein the first material comprises silicon and nitrogen and the second material comprises polysilicon.

4. 2. The method of claim 1, wherein the first photoresist layer comprises a DNQ-novolac photoresist, an epoxy-based polymer, or an off-stoichiometric trithiol-ene (OSTE) polymer.

5. The voltage waveform is a series of pulses, each pulse having a first time interval ranging from 200 nanoseconds to 400 nanoseconds, and a second time interval occupying at least 80% of each pulse period of the series of pulses; Including, 10. The method of claim 1, wherein each pulse in the series of pulses has a peak-to-peak voltage of about 2 kV to 20 kV.

6. The process gas composition is ４ F ６ , C ３ F ６ , C.F. ４ , N.F. ３ , C ３ F ８ , C ４ F ８ , C.H. ３ F, C.H. ２ F ２ , S.F. ６ , SiF ４ , and W.F. ６ At least one of HBr, He, Ar, Xe, and N ２ , Kr, and O ２ and at least one of:

7. The alternating layers include a plurality of first and second layers stacked in an alternating vertical direction, the method further comprising: the first photoresist layer positioned over the two or more mask openings in the array of mask openings is removed; A patterned opening formed through each of the mask openings in the alternating layers has a bottom surface having a different depth within the alternating layers, the bottom surface of each of the patterned openings having a first end in contact with a portion of a first layer of the plurality of second layers.

2. The method of claim 1, comprising performing (a), (b) and (c) until:

8. depositing a dielectric layer over surfaces of the patterned openings formed in the alternating layers; removing at least a portion of the deposited dielectric layer from the bottom surface of each of the patterned openings formed in the alternating layers; The method of claim 7 further comprising:

9. 9. The method of claim 8, further comprising filling the patterned openings formed in the alternating layers with the first material after removing at least a portion of the deposited dielectric layer from the bottom surface of each of the patterned openings formed in the alternating layers.

10. etching each of the filled patterned openings and the first layer to remove the first material from each of the filled patterned openings and the first layer to form openings extending through the patterned openings and extending through at least a portion of the first layer; filling the etched patterned openings and the etched first layer with a conductive material, the conductive material comprising at least one of tungsten, platinum, titanium, ruthenium, and silicon; and The method of claim 9 further comprising:

11. receiving, by a controller, a signal from a sensor positioned to detect a characteristic of a surface of the substrate while etching a plurality of layers, the signal including information regarding the detected characteristic of the surface of the substrate; determining, by the controller, that one or more characteristics of the plasma etch process need to be adjusted based on the received signal; The method of claim 1 further comprising:

12. 1. A method of forming a non-volatile memory device, comprising: Positioning a substrate on a surface of a substrate support disposed within a processing region of a processing chamber, the substrate comprising: a hardmask layer disposed on a plurality of alternating layers formed on a surface of the substrate, the alternating layers including vertically stacked first and second layers; an array of mask openings formed in the hard mask layer, the array of mask openings being aligned in a first pitch direction and having a pitch length in the first pitch direction between adjacent mask openings in the array of openings; a first photoresist layer disposed over the hard mask layer and over two or more mask openings in the array of mask openings, the first photoresist layer including an opening in the first photoresist layer having an exposed surface, the opening positioned to expose a first mask opening of the array of mask openings or positioned to expose a portion of the hard mask layer adjacent to the first mask opening of the array of mask openings; positioning the substrate on a surface of a substrate support disposed within a processing region of a processing chamber; delivering a process gas composition to the processing region of the process chamber; Etching a plurality of alternating layers formed on a surface of the substrate; Etching the plurality of layers includes: forming a plasma in the processing region of the process chamber, the plasma comprising the process gas composition, the plasma being formed over the first photoresist layer and the opening formed therein; Including, the first photoresist layer is etched by etching the plurality of alternating layers, whereby each mask opening in the array of mask openings is sequentially exposed to the plasma formed during the process of etching the plurality of alternating layers, forming patterned openings in the alternating layers, each having a different depth, in the portions of the alternating layers located beneath the sequentially exposed mask openings.

13. 13. The method of claim 12, wherein a bottom surface of each of the patterned openings has a first end in contact with a portion of a first layer of the plurality of second layers.

14. 13. The method of claim 12, further comprising establishing a voltage waveform at an electrode positioned a distance from a surface of the substrate support while the plasma is formed over the first photoresist layer and the opening formed therein.

15. 1. A non-volatile memory device, comprising: A plurality of alternating layers, a plurality of alternating layers, each of which includes a first layer including a first material and a second layer including a second material different from the first material, the alternating layers being stacked in a first direction, the alternating layers including a plurality of stacked layer pairs including N stacked layer pairs, N being greater than 10; A plurality of conductive columns, each of the conductive columns is aligned in a first pitch direction and spaced apart a pitch length in the first pitch direction; N-1 of the conductive columns extend through one or more stacked layer pairs; a plurality of conductive columns, each of the conductive columns including a dielectric layer disposed between a conductive material disposed within the conductive column and one or more of the layers of the stacked layer pair through which the conductive column extends, and a voltage is applied to the conductive material of the conductive columns during operation of the non-volatile memory device; Equipped with The first material and the conductive material each comprise essentially the same material.

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