Methods for forming memory cells, high voltage devices, and logic devices in a semiconductor substrate - Patents.com

Abstract

The method includes recessing a top surface of the substrate in the first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area while maintaining the second conductive layer in the second and third areas, leaving a pair of stack structures in the first area each having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing a top surface of the third conductive layer below a top of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming a block of metal material in the second and third areas.

Description

[Technical field]

[0001] (Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 318,657, filed March 10, 2022, and U.S. Patent Application No. 17 / 834,746, filed June 7, 2022.

[0002] FIELD OF THEINVENTION The present disclosure relates to semiconductor devices having non-volatile memory cells embedded in the same substrate as logic devices and high voltage devices. [Background technology]

[0003] Non-volatile memory semiconductor devices formed in silicon semiconductor substrates are known. For example, U.S. Patent Nos. 6,747,310, 7,868,375, and 7,927,994 disclose memory cells having four gates (floating gate, control gate, select gate, and erase gate) formed in a semiconductor substrate, which are incorporated herein by reference for all purposes. The source and drain regions are formed as diffusion embedded regions in the substrate and define a channel region therebetween in the substrate. The floating gate is disposed above a first portion of the channel region and controls the conductivity of the first portion, the select gate is disposed above a second portion of the channel region and controls the conductivity of the second portion, the control gate is disposed above the floating gate (to capacitively couple with the floating gate), and the erase gate is disposed above the source region and laterally adjacent to the floating gate.

[0004] It is also known to form low-voltage and high-voltage logic devices in the same substrate as non-volatile memory cells. See, for example, U.S. Patent No. 9,276,005, which is incorporated herein by reference for all purposes. New gate materials, such as high-K dielectrics and metal gates, are also used to improve performance. However, processing operations in forming memory cells may adversely affect simultaneously fabricated logic devices, and vice versa.

[0005] What is needed is an improved method for fabricating devices that include memory cells, low voltage logic devices, and high voltage devices on the same substrate. Summary of the Invention

[0006] The problems and needs noted above are addressed by a method of forming a semiconductor device, the method comprising: providing a substrate of a semiconductor material including a first area, a second area, and a third area; recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in a third area; forming a first conductive layer disposed over the top surface in the first area, the second area, and the third area and insulated from the top surface in the first area, the second area, and the third area; removing the first conductive layer from the second area and the third area; forming an insulating layer on the first conductive layer in the first area and over the top surface in the second area and the third area; forming a second conductive layer on the insulating layer in the first area, the second area, and the third area; performing one or more etches to selectively remove portions of the first and second conductive layers in the first area while maintaining the second conductive layer in the second and third areas, the one or more etches resulting in a plurality of pairs of stack structures in the first area, each stack structure including a control gate of the second conductive layer disposed above a floating gate of the first conductive layer and insulated from the floating gate of the first conductive layer; forming a plurality of first source regions in the substrate in a first area, each of the first source regions being disposed between a respective pair of the stack structures; forming a third conductive layer disposed above and between the stack structure in the first area and disposed in the second area and the third area; performing chemical mechanical polishing or etch back to planarize an upper surface of the third conductive layer; performing an etch to recess a top surface of the third conductive layer below a top of the stack structure in the first area and remove the third conductive layer from the second area and the third area, leaving each of a plurality of erase gates of the third conductive layer disposed above and insulated from one of the plurality of first source regions in the first area; removing the second conductive layer from the second area and the third area; forming a plurality of blocks of dummy conductive material disposed above and insulated from the top surface in the second area and the third area after the step of removing the second conductive layer from the second area and the third area; After forming the plurality of blocks of dummy conductive material in the second area and the third area, etching portions of the third conductive layer in the first area to form a plurality of select gates of the third conductive layer each disposed adjacent one of the stack structures; forming a plurality of first drain regions in the substrate in a first area, each of the plurality of first drain regions adjacent one of the plurality of select gates; forming second source regions in the substrate, each second source region adjacent to one of the blocks of dummy conductive material in the second area; forming second drain regions in the substrate, each second drain region adjacent to one of the blocks of dummy conductive material in the second area; forming third source regions in the substrate, each of the third source regions adjacent to one of the blocks of dummy conductive material in the third area; forming third drain regions in the substrate, each of the third drain regions adjacent to one of the blocks of dummy conductive material in the third area; and replacing the blocks of dummy conductive material in the second area and in the third area with blocks of metallic material.

[0007] Other objects and features of the present disclosure will become apparent from a review of the specification, claims, and accompanying drawings.

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[0013] [Brief description of the drawings]

[0014] [Figure 1A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 1B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 1C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 2A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 2B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 2C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 3A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 3B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 3C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 4A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 4B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 4C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 5A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 5B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 5C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 6A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 6B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 6C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 7A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 7B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 7C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 8A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 8B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 8C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 9A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 9B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 9C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 10A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 10B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 10C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 11A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 11B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 11C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 12A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 12B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 12C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 13A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 13B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 13C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 14A] 1 is a cross-sectional view of a memory cell area illustrating the formation of a memory cell. [Figure 14B] 1 is a cross-sectional view of an HV area showing the formation of an HV device. [Figure 14C] 1 is a cross-sectional view of a logic area illustrating the formation of a logic device. [Figure 15] FIG. 2 is a cross-sectional view of a memory cell area showing a completed memory cell. [Figure 16] FIG. 13 is a cross-sectional view of the HV area showing the completed HV device. [Figure 17] 1 is a cross-sectional view of a logic area showing a completed logic device. [Figure 18] FIG. 11 is a cross-sectional view of a memory cell area illustrating an alternative embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] A process for forming a semiconductor device by simultaneously forming memory cells, low voltage logic devices, and high voltage logic devices in the same semiconductor substrate is disclosed. The process described below includes forming memory cells in one or more memory cell areas 2 (also referred to as first area 2 or MC area 2) of the substrate 10, high voltage logic devices (also referred to herein as HV devices) in one or more high voltage logic device areas 4 (also referred to as second area 4 or HV area 4) of the substrate 10, and low voltage logic devices (also referred to herein as LV devices) in one or more low voltage logic device areas 6 (also referred to as third area 6 or logic area 6) of the substrate 10. The process is described with respect to simultaneously forming pairs of memory cells in the MC area 2, high voltage logic devices in the HV area 4, and low voltage logic devices in the logic area 6. However, multiple such devices in each area may be formed simultaneously. The substrate 10 is a substrate of semiconductor material (e.g., silicon). For purposes of this disclosure, a high voltage logic device (HV device) is one that has a higher operating voltage than that of a low voltage logic device (LV device).

[0016] 1A-14A for the MC area 2, 1B-14B for the HV area 4, and 1C-14C for the logic area 6, cross-sectional views of operations in a process for fabricating a semiconductor device are shown. The process begins by recessing a top surface 10a of a silicon substrate 10 in the MC area 2 and the HV area 4 by a recess amount R relative to the logic area 6. The step of recessing the substrate top surface 10a may be performed by forming a silicon dioxide (also referred to herein as "oxide") layer on the substrate top surface 10a, and forming a silicon nitride (also referred to herein as "nitride") layer on the oxide layer. A photolithographic masking operation is performed to cover logic area 6 with photoresist but not MC and HV areas 2 / 4 (i.e., form photoresist over all three areas, selectively expose portions of the photoresist, and selectively remove portions of the photoresist, leaving portions of the underlying structure exposed (in this case, the nitride layer in MC and HV areas 2 / 4) while leaving other portions of the underlying structure covered by photoresist (in this case, the nitride layer in logic area 6)). A nitride and oxide etch is performed to remove these layers from MC and HV areas 2 / 4, leaving top surface 10a in these areas exposed. After removing the photoresist, a silicon etch is performed to substantially lower top surface 10a in MC and HV areas 2 / 4 by a recess amount R. A nitride and oxide etch is then used to remove all oxide and nitride layers from logic area 6, resulting in the structure shown in Figures 1A, 1B, and 1C. The top surface 10a in the MC and HV areas 2 / 4 is recessed by a recess amount R (e.g., ∼300A) relative to the top surface 10a in the logic area 6. Alternatively or additionally, the surface 10a in the MC and HV areas 2 / 4 can be recessed by thermal oxidation, which consumes a portion of the top surface 10a.

[0017] Next, an oxide layer 12 is formed (e.g., by deposition or thermal growth) on the top surface 10a. Thereafter, a conductive layer 14 (also referred to herein as a first conductive layer) is formed on the oxide layer 12. The conductive layer 14 can be polysilicon or amorphous silicon, either in-situ doped or undoped. A photolithographic masking operation is then performed to cover the MC area 2 with photoresist, but leave the HV and logic areas 4 / 6 exposed (i.e., the photoresist is removed from the HV and logic areas 4 / 6 as part of the masking operation). An etch is used to remove the conductive layer 14 from the HV and logic areas 4 / 6. The resulting structure is shown in Figures 2A, 2B, and 2C (after photoresist removal).

[0018] An oxide layer 18 is formed on the conductive layer 14 in the MC area 2 and on the oxide layer 12 in the HV and logic areas 4 / 6. An insulating layer 20, such as nitride (also referred to herein as hard mask insulating layer 20), is formed on the oxide layer 18. A photolithographic masking operation is used to selectively cover portions of each area with photoresist, leaving portions of the nitride layer exposed in each area. An etch, such as nitride, oxide, polysilicon, and silicon etch, is used to form a trench through the hard mask insulating layer 20, the oxide layer 18, the conductive layer 14 (in the MC area 2), the oxide layer 12, and into the silicon substrate 10. The trench is then filled with oxide 22 by oxide deposition and chemical mechanical polishing (CMP). The oxide 22 is an insulating material that may also be referred to as shallow trench isolation (STI) oxide 22. The STI oxide 22 may include a liner oxide formed by thermal oxidation prior to oxide deposition. The resulting structure is shown in Figures 3A, 3B, and 3C (after photoresist removal). The trenches filled with oxide 22 run parallel to the active areas in the MC area 2, but because Figure 3A is a cross-sectional view of one of the active areas, the trenches filled with oxide 22 are not shown in Figure 3A.

[0019] The hard mask insulating layer 20 is removed by a nitride etch. A series of implants can be performed (after respective photolithographic masking operations to selectively cover one or more other areas with photoresist during each implant) to create the desired wells in the substrate 10 in each of the areas 2 / 4 / 6. After removal of the photoresist from the implant stage and respective photolithographic masking operations to cover the HV and logic areas 4 / 6 with photoresist and leave the MC area 2 exposed, an oxide etch recesses the STI oxide 22 and removes the oxide layer 18 from the MC area 2. After removal of the photoresist, an insulating layer 24 is formed above the structure. The insulating layer 24 can be an ONO composite layer with oxide / nitride / oxide sublayers (formed by oxide, nitride, oxide deposition, and anneal). However, the insulating layer 24 can instead be formed of a composite of other dielectric layers, or a single dielectric material without sublayers. A conductive layer 26 (also referred to herein as a second conductive layer) is then formed in the structure, in one example by deposition. Conductive layer 26 may be polysilicon or may be amorphous silicon, either in-situ doped or undoped. If polysilicon or undoped amorphous silicon is used for conductive layer 26, implantation and annealing are performed. One or more hard mask layers are then formed on conductive layer 26. Specifically, in one example, oxide layer 27 is formed on conductive layer 26, and nitride layer 28 is formed on oxide layer 27. The resulting structure is shown in Figures 4A, 4B, and 4C.

[0020] Using respective photolithographic masking operations, photoresist is formed on the structure, and the photoresist is selectively removed from the MC area 2 to expose portions of the nitride layer 28 in the MC area 2. Using a series of etches, the exposed portions of the nitride layer 28, the oxide layer 27, the conductive layer 26, and the insulating layer 24 are removed, resulting in a pair of spaced apart stack structures S1 and S2 of the nitride layer 28, the oxide layer 27, the conductive layer 26, and the insulating layer 24 remaining in the MC area 2. The resulting structures are shown in Figures 5A, 5B, and 5C (after photoresist removal).

[0021] Oxide spacers 32, nitride spacers 34, and oxide spacers 36 are formed on the sides of stacks S1 and S2 in MC area 2. Spacer formation is well known in the art and involves depositing material above the contours of the structure followed by an anisotropic etching process, whereby material is removed from the horizontal surfaces of the structure while material remains largely intact on the vertically oriented surfaces of the structure (which often have rounded top surfaces). In this case, oxide spacers 32 and nitride spacers 34 are formed by oxide deposition, nitride deposition, followed by one or more anisotropic etches. Oxide spacers 36 are then formed by oxide deposition and etching. The planar nitride layer 28 in HV and logic areas 4 / 6 is largely unaffected by this spacer formation. Using a photolithographic masking operation, the MC area 2 is covered with photoresist 38, including the area between stacks S1 and S2 (referred to herein as the inner stack area) and in the area on the opposite side of stack structures S1 and S2 from the inner stack area (referred to herein as the outer stack area). The photoresist 38 is removed from the outer stack area. An oxide etch is used to remove the oxide spacers 36 facing the outer stack area. The resulting structure is shown in Figures 6A, 6B, and 6C.

[0022] After the photoresist 38 is removed, an etch such as a polysilicon or silicon etch is performed depending on the material of the conductive layer 14 to remove the exposed portions of the conductive layer 14 (in the inner and outer stack areas) and the oxide layer 12, which etch does not remove the nitride layer 28 in the HV / LV areas 4, 6, so that each spaced stack structure S1 / S2 includes a block of conductive material 14a from the remainder of the conductive layer 14 that is maintained under the stacks S1 and S2 and the spacers 32, 34, 36 in the MC area 2, and this block of conductive material 14a is separated from the substrate 10 by the remaining portion of the oxide layer 12. The block of conductive material 14a constitutes the floating gate, also referred to herein as the floating gate 14a. Oxide spacers 40 are formed along the exposed ends of the block of conductive material 14a by oxide deposition and oxide anisotropic etching. Photoresist is formed on the structure and removed from the area between the stacks S1 and S2 in the MC area 2 (inner stack area). A fill process is performed to form source region 42 (also referred to herein as first source region) in the substrate between stack S1 and stack S2. An oxide etch is then used to remove oxide spacers 40 in the inter-stack area down to the exposed ends of the blocks of conductive material 14a. The resulting structure is shown in Figures 7A, 7B, and 7C (after photoresist removal).

[0023] A tunnel oxide layer 44 is formed on the structure, including directly on the exposed ends of the blocks of conductive material 14a in the interior stack areas. The tunnel oxide 44 can be an oxide, oxynitride, or both formed by deposition, thermal growth, or both. Due to the catalytic effect of the higher dopant levels in the source regions 42, the tunnel oxide 44 can have a thicker portion in the source regions 42. Using a photolithographic masking operation, the HV and logic areas 4 / 6 and the interior stack areas in the MC area 2 are covered with photoresist. The exterior stack areas remain exposed. A fill can be performed at this point on the portions of the substrate 10 in the exterior stack areas (i.e., those substrate portions that underlie the select gates that will be formed later). An oxide etch can be used to remove any remaining portions of the oxide layer 12 and the tunnel oxide layer 44 in the exterior stack areas and the HV and logic areas 4, 6. After removal of the photoresist, an insulating layer 46 is formed on the structure. Insulating layer 46 may be an oxide, oxynitride, or any other suitable dielectric material formed by deposition, thermal growth, or both. The formation of insulating layer 46 is not shown separately since it thickens tunnel oxide 44 or becomes part of tunnel oxide 44 in the inner stack area. The resulting structure is shown in Figures 8A, 8B, and 8C.

[0024] A conductive layer 48 (also referred to herein as a third conductive layer) is formed on the structure. The conductive layer 48 can be either in-situ doped or undoped polysilicon, or alternatively amorphous silicon. If undoped polysilicon or amorphous silicon is used for the conductive layer 48, doping and annealing are performed. A chemical mechanical polishing (CMP) or etchback is performed to planarize the top surface of the conductive layer 48. A further etchback process is used to recess the top surface of the conductive layer 48 below the tops of the stacks S1 and S2, and remove the conductive layer 48 from the HV and logic area 4 / 6. An oxide layer 50 is formed above the structure and planarized to be flush with the tops of the stacks S1 and S2 in the MC area 2, and is completely removed from the HV and logic area 4 / 6. The resulting structure is shown in Figures 9A, 9B, and 9C.

[0025] At this point, most of the memory cell formation is complete. Oxide 50 protects MC area 2 from subsequent processing in HV and logic area 4 / 6. A photolithographic masking operation is used to cover MC area 2 with photoresist while leaving HV and logic area 4 / 6 exposed. One or more etches are used to remove nitride layer 28, oxide layer 27, conductive layer 26, and insulating layer 24 in HV and logic area 4 / 6 as shown in Figures 10A, 10B, and 10C (after photoresist removal).

[0026] An implant can now be performed to form doped P and N wells in the substrate 10 in the HV and logic areas 4 / 6. The MC and logic areas 2 / 6 are covered with photoresist and an oxide etch is used to remove the oxide layer 12 / 18 from the HV area 4, leaving the substrate 10 exposed. An oxide layer 52 is formed on the substrate 10 in the HV area 4. After photoresist removal, a layer 54 of high K insulating material is formed on the oxide layer 50 in the MC area 2, the oxide layer 52 in the HV area 4, and the oxide layer 12 / 18 in the logic area 6. A high K insulating material is an insulating material that has a dielectric constant K greater than the dielectric constant of silicon dioxide. An example of a high K insulating material is HfO 2 , ZrO2 , TiO 2 , Ta 2 O 5 , and combinations thereof. A titanium nitride (TiN) layer 56 is formed on the high-K insulating layer 54. The resulting structure is shown in Figures 11A, 11B, and 11C.

[0027] A layer of dummy conductive material is then formed above the structure, which may be formed of polysilicon. An insulating layer 59, such as nitride (also referred to herein as logic insulating layer 59), and a hard mask layer 60, such as oxide, are then formed over the layer of dummy conductive material, respectively. Using a photolithographic masking operation, selected portions of the HV and logic areas 4 / 6 are covered with photoresist, leaving the entire MC area 2 exposed. One or more etches are then used to remove the exposed areas of the hard mask layer 60, insulating layer 59, layer of dummy conductive material, and high-K layer 54 in the MC, HV, and logic areas 2 / 4 / 6, leaving blocks 58 of dummy conductive material covered by the insulating layer 59 and hard mask layer 60 in the HV and logic areas 4 / 6. After photoresist removal, oxide spacers 61 are formed by oxide deposition and etching. At this point, embedding can be performed on the substrate 10 in the logic areas 6. The resulting structure is shown in Figures 12A, 12B, and 12C.

[0028] Using photolithographic masking operations, the HV and logic areas 4 / 6 and portions of the MC area 2 are covered with photoresist (i.e., covering the inner stack area, the stack structures S1 and S2, and those portions of the outer stack area directly adjacent to the stack structures S1 and S2). Using etching, the exposed portions of the oxide layer 50 and the conductive layer 48 are removed. After photoresist removal, additional selective implants and etches can be performed (i.e., by additional photolithographic mask operations and implants such as LDD implants) in different exposed portions of the substrate 10. Oxide spacers 66 are formed by oxide deposition and etching, nitride spacers 68 are formed by nitride deposition and etching, and oxide spacers 70 are formed by oxide deposition and etching. One or more implants are performed to form drain region 74 (also referred to herein as a first drain region) in the substrate adjacent to oxide spacer 70 in MC area 2, source and drain regions 76 / 78 (also referred to herein as a second source region and a second drain region) adjacent to oxide spacer 70 in HV area 4, and source and drain regions 80 / 82 (also referred to herein as a third source region and a third drain region) adjacent to oxide spacer 70 in logic area 6. After further oxide etching, silicide 84 (also referred to as salicide, which is a self-aligned silicide) is formed in source region 76 / 80 and drain region 74 / 78 / 82 by metal deposition (e.g., NiPt) and annealing. The resulting structure is shown in Figures 13A, 13B, and 13C.

[0029] An insulating layer 86 (e.g., nitride) is formed over the structure. A relatively thick layer 88 of interlevel dielectric (ILD) insulating material (e.g., oxide) is then formed over layer 86. CMP is performed to planarize and recess layer 88 of ILD insulating material and remove nitride layer 59 to expose dummy conductive layer 58 in HV and logic area 4 / 6. An etch such as a polysilicon etch is then used to remove the remaining blocks of dummy conductive material from layer 58 in HV and logic area 4 / 6. A layer such as, but not limited to, Al, Ti, TiAlN, TaSiN, TaN, TiN, or other suitable metal material, or a composite thereof, is formed over the structure. CMP is then performed to remove portions of the metal material layer leaving blocks 92 of metal material in HV and logic area 4 / 6 (i.e., replacing blocks 58 of dummy conductive material with blocks 92 of metal material). A nitride layer 94 is formed over the structure. A relatively thick layer of oxide 96 is formed over the structure, followed by planarization of the top surface of the structure by chemical mechanical polishing (CMP) or etchback. Contact holes are then formed through oxide layer 96, nitride layer 94, oxide layer 88, and nitride layer 86 to expose the silicide 84 in source regions 76 / 80 and drain regions 74 / 78 / 82. The contact holes are filled with a TiN liner layer 98 and a metal material 100 (e.g., tungsten). The final structure is shown in Figures 14A, 14B, and 14C.

[0030] Figure 15 shows the final memory cell structure in MC area 2, which includes multiple pairs of memory cells, each sharing a source region 42 spaced from two drain regions 74 and having a channel region 102 in silicon 10 extending between the two drain regions 74. Each memory cell includes a floating gate 14a (i.e., a block of remaining conductive material from the conductive layer 14) disposed above and insulated from a first portion of the channel region 102 to control the conductivity of the first portion of the channel region 102, a select gate 48a (i.e., which may also be referred to as a word line gate and is a block of remaining conductive material from the conductive layer 48) disposed above and insulated from a second portion of the channel region 102 to control the conductivity of the second portion of the channel region 102, a control gate 26a (i.e., a block of remaining conductive material from the conductive layer 26) disposed above and insulated from the floating gate 14a, and an erase gate 48b (i.e., a block of remaining conductive material from the conductive layer 48) disposed above and insulated from a source region 42 (shared by a pair of memory cells). The pairs of memory cells can be arranged in an array of memory cells arranged in rows and columns. The pairs of memory cells may run end-to-end in a column direction (i.e., in the bit line direction) with STI oxide 22 disposed between adjacent columns. The row of control gates 26a may be formed as a continuous control gate line that interconnects the control gates 26a across the rows of memory cells. The row of select gates 48a is formed as a continuous select gate line (also known as a word gate line) that interconnects the select gates 48a across the rows of memory cells. The row of erase gates 48b is formed as a continuous erase gate line that interconnects the erase gates 48b across the rows of memory cell pairs.

[0031] The final HV devices are shown in Figure 16. Each HV device includes spaced apart source and drain regions 76 and 78 with a channel region 104 of the silicon substrate 10 extending therebetween. An HV gate 92a (i.e., a block of remaining metal material from the layer of metal material) is disposed above and insulated from the channel region 104 to control the conductivity of the channel region 104.

[0032] The final logic devices are shown in Figure 17. Each logic device includes spaced apart source and drain regions 80 and 82 with a channel region 106 of the silicon substrate 10 extending therebetween. A logic gate 92b (i.e., a block of remaining metal material from the layer of metal material) is disposed above and insulated from the channel region 106 to control the conductivity of the channel region 106.

[0033] The above method of forming memory cells, HV devices, and logic devices on the same substrate has many advantages. Memory cell formation is substantially completed before metal HV and logic gates 92a and 92b are formed in HV and logic area 4 / 6, so that metal HV and logic gates 92a / 92b are not adversely affected by memory cell formation. Process operations for forming gates in MC area 2 are separate and independent of (and can be customized to) process operations for forming gates in HV and logic area 4 / 6. MC area 2 is covered after the majority of memory cell formation is completed and before processing in HV and logic area 4 / 6 (i.e., before removal of layers in HV and logic area 4 / 6 resulting from memory cell formation, and before deposition and removal of layers used in HV and logic device formation, including but not limited to removal of dummy polysilicon). The top surface 10a of the substrate 10 is recessed in the MC and HV areas 2 / 4 relative to the top surface 10a in the logic area 6 to accommodate the taller structures in the MC / HV area 2 / 4 (i.e., so that the tops of the lower logic devices in the logic area 6 are approximately flush with the tops of the taller memory cells and HV devices in the MC / HV area 2 / 4, and so that CMP across all three areas can be used for processing). The silicide 84 enhances the conductivity of the drain region 74, and the source / drain regions 76 / 78, 80 / 82. The memory cell select gate 48a and the memory cell erase gate 48b are formed using a single conductive material deposition (i.e., a single polysilicon layer formed by a single polysilicon deposition can be used to form both the select gate 48a and the erase gate 48b). The thicknesses of the various layers 46, 12, 18, 52, and 54 (which are used as gate insulators) are independent of each other and each is sized for its respective gate operation. For example, the insulating layer 46 under the select gate 48a may be thinner than the oxide layer 12 under the floating gate 14a.

[0034] The CMP used to planarize the conductive layer 48 with the tops of the stack structures S1 and S2, followed by etching to recess the conductive layer 48 below the tops of the stack structures S1 and S2 (see Figures 9A-9C and related description) provides reliable control of the height of the conductive layer 48 in the MC area 2 (e.g., using APC (automatic process control) to measure the thickness of the conductive layer 48 before the etching process and then derive the etching time based on the etch rate of the etch), thus avoiding additional masking operations.

[0035] 18 shows an alternative embodiment in which silicide 84 is also formed on the top surfaces of select gate 48a and erase gate 48b to increase the conductivity of these gates and gate lines. Silicide 84 can be formed on the top surfaces of select gate 48a and erase gate 48b by exposing these gates (i.e., using an oxide etch to remove the oxide on the top surfaces of select / erase gates 48a / 48b) before silicide 84 is formed on the source and drain regions (see FIGS. 13A-13B).

[0036] It will be understood that the present disclosure is not limited to the above-described examples illustrated herein, but encompasses any and all variations falling within the scope of any claims. For example, any reference herein to the present disclosure or invention or examples is not intended to limit the scope of any claims or claim terms, but instead merely refers to one or more features that may be covered by one or more claims. The material, process, and numerical examples described above are merely illustrative and should not be considered as limiting the scope of the claims. Furthermore, as will be apparent from the claims and the specification, all method operations need not be performed in the exact order illustrated or claimed, but rather in any order that allows for the proper formation of the memory cell areas, HV areas, and logic areas described herein (unless there is an expressly recited limitation in any order). A single material layer can be formed as multiple layers composed of such or similar materials, and vice versa. Finally, as used herein, the terms "formation" and "formed" are intended to include material deposition, material formation, or any other technique in providing the disclosed or claimed materials.

[0037] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate materials, elements, or spaces disposed therebetween) and "indirectly" (with intermediate materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (with intermediate materials, elements, or spaces disposed therebetween). For example, forming an element "over a substrate" can include forming the element directly on the substrate without any intermediate materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A method of forming a semiconductor device, the method comprising: providing a substrate of a semiconductor material including a first area, a second area, and a third area; recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area; forming a first conductive layer disposed over the top surface in the first area, the second area, and the third area and insulated from the top surface in the first area, the second area, and the third area; removing the first conductive layer from the second area and the third area; forming an insulating layer on the first conductive layer in the first area and over the top surface in the second area and the third area; forming a second conductive layer on the insulating layer in the first area, the second area, and the third area; performing one or more etches to selectively remove portions of the first and second conductive layers in the first area while maintaining the second conductive layer in the second and third areas, the one or more etches resulting in a plurality of pairs of stack structures in the first area, each stack structure including a control gate of the second conductive layer disposed above and insulated from a floating gate of the first conductive layer; forming a plurality of first source regions in the substrate in the first area, each first source region being disposed between a respective pair of stack structures; forming a third conductive layer disposed above and between the stack structures in the first area and disposed in the second area and the third area; performing chemical mechanical polishing or etch back to planarize an upper surface of the third conductive layer; performing an etch to recess the top surface of the third conductive layer below a top of the stack structure in the first area and remove the third conductive layer from the second area and the third area, leaving a plurality of erase gates of the third conductive layer each disposed above one of the plurality of first source regions in the first area and insulated from the one of the plurality of first source regions in the first area; removing the second conductive layer from the second area and the third area; forming a plurality of blocks of dummy conductive material disposed above and insulated from the top surface in the second and third areas after the removing of the second conductive layer from the second and third areas; after the forming of the blocks of dummy conductive material in the second and third areas, etching portions of the third conductive layer in the first area to form a plurality of select gates of the third conductive layer each disposed adjacent one of the plurality of stack structures; forming a plurality of first drain regions in the substrate in the first area, each of the first drain regions adjacent one of the plurality of select gates; forming a plurality of second source regions in the substrate, each of the second source regions adjacent one of the plurality of blocks of the dummy conductive material in the second area; forming a plurality of second drain regions in the substrate, each of the plurality of second drain regions adjacent one of the plurality of blocks of the dummy conductive material in the second area; forming a plurality of third source regions in the substrate, each of the plurality of third source regions adjacent one of the plurality of blocks of the dummy conductive material in the third area; forming a plurality of third drain regions in the substrate, each of the plurality of third drain regions adjacent one of the plurality of blocks of the dummy conductive material in the third area; and replacing the blocks of dummy conductive material in the second area and in the third area with blocks of metallic material.

2. forming a hard mask insulating layer on the first conductive layer in the first area and over the top surface in the second and third areas; forming a plurality of trenches through the hard mask insulating layer into the substrate in the second and third areas and through the hard mask insulating layer and the first conductive layer into the substrate in the first area; filling the plurality of trenches with an insulating material; 2. The method of claim 1, further comprising the step of: removing said hard mask insulating layer from said first area, said second area, and said third area after said filling of said plurality of trenches.

3. 2. The method of claim 1 , comprising forming a layer of high-K insulating material above the top surface in the second area and the third area, wherein the plurality of blocks of dummy conductive material are formed in the layer of high-K insulating material in the second area and the third area.

4. The method of claim 1 , wherein the first conductive layer, the second conductive layer, and the third conductive layer are each formed of polysilicon or amorphous silicon.

5. 2. The method of claim 1, further comprising forming a silicide on said first, second and third drain regions and on said second and third source regions.

6. The method of claim 4 including forming a silicide on said plurality of select gates and said plurality of erase gates.

7. 2. The method of claim 1, wherein the insulating layer includes an oxide sublayer, a nitride sublayer, and an oxide sublayer, such that, for each of the plurality of stack structures, the control gate is insulated from the floating gate by the oxide sublayer, the nitride sublayer, and the oxide sublayer.

8. 2. The method of claim 1, wherein the forming step of the plurality of blocks of dummy conductive material comprises forming a logic insulation layer on the plurality of blocks of dummy conductive material and forming a hard mask layer on the logic insulation layer.

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