Method and system for writing states into superconducting circuits with integrated semiconductor-based circuits

Abstract

A write circuit for writing a state to a plurality of superconducting memory cells includes a control circuit, a plurality of write lines, each of the write lines associated with a corresponding column of the superconducting memory cells and configured to deliver a write column current, and a first plurality of non-superconducting switch devices, each of the non-superconducting switch devices associated with a corresponding one of the write lines and configured to receive a first control signal provided by the control circuit to enable the write column current to flow through the corresponding one of the write lines and write a state to a selected one of the superconducting memory cells associated with the corresponding one of the write lines.

Description

[Technical field]

[0001] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 425,160, entitled "Superconducting Memory, Programmable Logic Arrays, and Fungible Arrays," filed on November 14, 2022, and U.S. Provisional Patent Application No. 63 / 322,694, entitled "Control Logic, Buses, Memory and Support Circuitry for Reading and Writing Large Capacity Memories Within Superconducting Systems," filed on March 23, 2022, the disclosures of which are incorporated by reference in their entireties herein for all purposes.

[0002] The present invention relates generally to quantum and classical digital superconducting circuits and systems, and more particularly to circuits for writing to superconducting memory circuits. [Background technology]

[0003] Superconducting digital technology has enabled computing and / or communication resources that benefit from high speed and low power consumption. For decades, superconducting digital technology has lacked random-access memory (RAM) with sufficient capacity and speed compared to logic circuits. This is a major obstacle to the industrialization of current applications of superconducting technology in telecommunications and signal intelligence, and may be especially hindering for high-end and quantum computing.

[0004] Superconducting Josephson junctions with magnetic barriers, also called magnetic Josephson junctions (MJJs), can function as memory elements in MJJ-based RAMs, programmable logic arrays (PLAs), and various types of field programmable gate arrays (FPGAs). MJJs rely on oscillations of the relative Cooper pair phase as a function of the thickness of the magnetic layers, resulting in junctions that exhibit a Josephson phase of 0 or π depending on the relative magnetic layer orientations. This binary phase switching property of MJJs can be exploited to create superconducting memory elements that can store a first logic state or a second logic state, which are associated with the appropriate selection of a circulating current in a first or second direction, or lack of circulating current, that corresponds to a Josephson phase of zero and / or π for the MJJ. Memory unit elements can be arranged in an array with read and write lines to create an addressable memory, for example fabricated on an integrated circuit (IC) chip that can be cooled to cryogenic temperatures (e.g., about 4 Kelvin).

[0005] MJJ-based RAMs are being actively developed because they are believed to be one key approach to making cost-sensitive memories (i.e., high-density, large-capacity memories) for superconducting systems commercially viable. No functional demonstrations of an entire MJJ-based RAM have been reported to date. Instead, one-off demonstrations of the core circuitry have been gradually revealed. The currently reported highest level of technology integration of a demonstration of the core circuitry can be found in "Superconducting Memory: A Novel Approach to Memory Integration," vol. 1, no. 1, 2003, the disclosure of which is incorporated herein by reference in its entirety.

[0006] Another memory based exclusively on Josephson junctions is described in US Pat. No. 5,999,333. Many other forms of memory exist, all of which could benefit if their write operations were made more reliable or if the chip area allocated to their write circuitry was reduced. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Pat. No. 10,554,207 [Patent Document 2] U.S. Pat. No. 10,650,884 [Patent Document 3] U.S. Patent No. 9,595,970 [Patent Document 4] U.S. Pat. No. 11,120,869 [Patent Document 5] U.S. Patent Application Serial No. 17 / 993,586 [Patent Document 6] U.S. Pat. No. 10,622,977 [Patent Document 7] U.S. Patent Application Serial No. 17 / 976,179 [Patent Document 8] U.S. Patent No. 10,122,351 [Non-patent literature]

[0008] [Non-Patent Document 1] Ian Dayton et. al., “Experimental Demonstration of a Josephson Magnetic Memory Cell With a Programmable π-Junction”, IEEE Magnetics Letters, Vol. 9, February 8, 2018 Summary of the Invention [Means for solving the problem]

[0009] The present invention, as demonstrated in one or more embodiments, relates to exemplary systems, circuits, devices, and / or methods that enable reliable writing of superconducting memory circuits containing both magnetic Josephson junctions (MJJs) and Josephson junctions, or superconducting memory circuits containing only Josephson junctions that form an underlying hybrid circuit with a non-superconducting (e.g., bipolar and / or complementary metal-oxide semiconductor (Bi)CMOS) write circuit, methods of writing to random access memories (RAMs), and programming and / or enabling one or more functions of superconducting programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), and pi-junction circuits, among other applications.

[0010] According to one embodiment of the present invention, a write circuit for writing a state to a plurality of superconducting memory cells comprises a control circuit, a plurality of write lines, each of the write lines associated with a corresponding column of superconducting memory cells and configured to deliver a write column current, and a first plurality of non-superconducting switch devices, each of the non-superconducting switch devices being associated with a corresponding one of the write lines and configured to receive a first control signal provided by the control circuit to enable the write column current to flow through the corresponding one of the write lines and write a state to a selected one of the superconducting memory cells associated with the corresponding one of the write lines.

[0011] According to another embodiment of the present invention, a write circuit for writing a state to a superconducting memory cell comprises a first non-superconducting switch, a second non-superconducting switch, a first radio frequency (RF) superconducting quantum interference device (SQUID) connected in series with the first non-superconducting switch, and a second RF SQUID connected in series with the second non-superconducting switch, the write circuit further comprises a first Josephson transmission line (JTL) having an input connected to the first RF SQUID and an output connected to the superconducting memory cell, and a second JTL having an input connected to the second RF SQUID and an output connected to the superconducting memory cell. The first non-superconducting switch and the first RF SQUID are connected between the first and second terminals of the first write current source via a first interconnect and a second interconnect, respectively, and the second non-superconducting switch and the second RF SQUID are connected between the first and second terminals of the second write current source via a third interconnect and a fourth interconnect.

[0012] According to yet another embodiment of the present invention, a superconducting memory circuit for reading and writing a plurality of MJJ-based memory cells comprises at least one superconducting read circuit operably coupled to the plurality of MJJ-based memory cells. The superconducting read circuit comprises at least a first current source and at least a first non-superconducting switch circuit connected to one or more corresponding row lines and column lines associated with the memory cells. The read circuit is configured to selectively provide a read current generated by the first current source along at least one of the row lines and column lines via the first non-superconducting switch circuit to read a state of at least one of the MJJ-based memory cells during a read operation. The superconducting memory circuit further comprises a non-superconducting write circuit operably coupled to the plurality of MJJ-based memory cells, the non-superconducting write circuit comprising at least a second current source and at least a second non-superconducting switch circuit connected to one or more corresponding row lines and column lines associated with the memory cells. The write circuit is configured to selectively provide a write current generated by the second current source along at least one of the row lines and the column lines via the second non-superconducting switch circuit to write a state to at least one of the MJJ-based memory cells during a write operation.

[0013] According to yet another embodiment of the present invention, a write circuit for selectively writing states to a plurality of superconducting memory cells of a random access memory comprises at least one superconducting column write circuit, the superconducting column write circuit coupled to one or more write column lines, each of the write column lines configured to deliver a write column line current. The column write circuit comprises at least one superconducting switch circuit configured to selectively provide a write column current to at least a given one of the write column lines, the at least one superconducting switch circuit responsive to at least a first control signal to write a state to one or more corresponding memory cells of the plurality of superconducting memory cells associated with the given one of the write column lines. The write circuit further comprises at least one non-superconducting row write circuit, the non-superconducting row write circuit coupled to one or more write row lines, each of the write row lines configured to deliver a write row line current. The row write circuitry includes at least one non-superconducting switch circuit configured to selectively supply a write row current to at least a given one of the write row lines, the at least one non-superconducting switch circuit responsive to at least a second control signal to select one or more corresponding memory cells of the plurality of superconducting memory cells associated with the given one of the write row lines.

[0014] According to one embodiment of the present invention, a write circuit for selectively writing states to a plurality of superconducting memory cells of a random access memory comprises at least one non-superconducting column write circuit, the non-superconducting column write circuit coupled to one or more write column lines, each of the write column lines configured to deliver a write column line current. The column write circuit comprises at least a first non-superconducting switch circuit configured to selectively provide a write column current to at least a given one of the write column lines, the at least first non-superconducting switch circuit responsive to at least a first non-superconducting control signal to write a state to one or more corresponding memory cells of the plurality of superconducting memory cells associated with the given one of the write column lines. The write circuit further comprises at least one non-superconducting row write circuit, the non-superconducting row write circuit coupled to one or more write row lines, each of the write row lines configured to deliver a write row line current. The row write circuitry includes at least a second non-superconducting switch circuit configured to selectively supply a write row current to at least a given one of the write row lines, the at least second non-superconducting switch circuit responsive to at least a second non-superconducting control signal to select one or more corresponding memory cells of the plurality of superconducting memory cells associated with the given one of the write row lines.

[0015] First and second conversion circuits are further provided in the write circuit, the first conversion circuit configured to receive the superconducting encoded write address and generate a first non-superconducting control signal in response to the superconducting encoded write address, and the second conversion circuit configured to receive the superconducting data signal and generate a second non-superconducting control signal in response to the superconducting data signal.

[0016] The techniques of the present invention are capable of providing significant beneficial technical advantages. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0017] The following drawings are offered by way of illustration only and not by way of limitation: The same reference numbers (where used) refer to corresponding elements throughout the several views. [Brief description of the drawings]

[0018] [Figure 1] FIG. 2 is a schematic diagram conceptually illustrating at least a portion of an exemplary MJJ write circuit, in accordance with one or more embodiments of the present invention. [Diagram 2] FIG. 2 conceptually illustrates idealized Stoner-Wohlfarth switching astroids associated with each of at least a subset of the MJJs of the example MJJ writing circuit of FIG. [Diagram 3] FIG. 3 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based memory circuit 300 with an integrated write FET in accordance with one or more embodiments of the present invention. [Figure 4] 1 is a graph conceptually illustrating the distribution of hypothetical switching fields in the pinned and free layers of an MJJ in a number of MJJ-based circuits. [Diagram 5] FIG. 12 conceptually illustrates ideal Stoner-Wohlfarth switching astroids associated with each of at least a subset of MJJs, including field selection points enabled by an exemplary MJJ writing circuitry to be discussed in connection with FIG. 11 . [Figure 6] FIG. 2 conceptually illustrates ideal Stoner-Wohlfarth switching astroids associated with each of at least a subset of the MJJs in the exemplary MJJ write circuit of FIG. 1 that sets the MJJs to a π state using the indicated field points. [Figure 7] FIG. 2 is a schematic diagram illustrating at least a portion of an example MJJ-based memory circuit with an integrated write switch in accordance with one or more embodiments of the present invention. [Figure 8] FIG. 2 is a schematic diagram illustrating at least a portion of an example MJJ-based memory circuit with at least one integrated write switch in accordance with one or more embodiments of the present invention. [Figure 9] FIG. 2 is a schematic diagram illustrating at least a portion of an example MJJ-based memory circuit with at least one integrated write switch in accordance with one or more embodiments of the present invention. [Figure 10] FIG. 2 is a schematic diagram illustrating at least a portion of an exemplary MJJ write circuit, in accordance with one or more embodiments of the present invention. [Figure 11] FIG. 2 is a schematic diagram illustrating at least a portion of an example MJJ write circuit that individually controls both the hard axis and easy axis magnetic fields applied to each MJJ in accordance with one or more embodiments of the present invention. [Figure 12] FIG. 2 is a schematic diagram illustrating at least a portion of an example write current multiplexing circuit for reducing leakage current in accordance with one or more embodiments of the present invention. [Figure 13] FIG. 2 is a schematic diagram illustrating at least a portion of an example MJJ-based write circuit for writing to an MJJ in accordance with one or more embodiments of the present invention. [Figure 14] 4 is a timing diagram illustrating at least a portion of an example timing diagram of a writing method in accordance with one or more embodiments of the present invention. [Figure 15A] FIG. 14 is a schematic diagram illustrating an example shifting circuit suitable for use in combination with the example circuit of FIG. 13, in accordance with an embodiment of the present invention. [Figure 15B] FIG. 14 is a schematic diagram illustrating an example shifting circuit suitable for use in combination with the example circuit of FIG. 13, in accordance with an embodiment of the present invention. [Figure 16] FIG. 2 is a schematic diagram illustrating at least a portion of an example circuit for writing to an MJJ, in accordance with one or more alternative embodiments of the present invention. [Figure 17] FIG. 2 is a schematic diagram illustrating at least a portion of an example circuit for writing to an MJJ, in accordance with one or more alternative embodiments of the present invention. [Figure 18] FIG. 2 is a schematic diagram illustrating at least a portion of an example circuit for writing to an MJJ, in accordance with one or more alternative embodiments of the present invention. [Figure 19]FIG. 1 illustrates ideal and non-ideal Stoner-Wohlfarth switching of the MJJ. [Figure 20] FIG. 2 is a schematic diagram illustrating at least a portion of an example circuit for writing to an MJJ, in accordance with one or more alternative embodiments of the present invention. [Figure 21] 1 is a flow diagram illustrating at least a portion of an example method for writing to an MJJ in accordance with one or more embodiments of the present invention. [Figure 22] FIG. 1 is a block diagram illustrating at least a portion of a conventional MJJ-based memory circuit. [Figure 23A] FIG. 1 is a schematic diagram illustrating at least a portion of an exemplary write circuit for writing to a MJJ that may be incorporated into a superconducting memory cell and that uses a mixed superconducting write circuit and a (Bi)CMOS write circuit, in accordance with one or more embodiments of the present invention. [Figure 23B] FIG. 1 is a schematic diagram illustrating at least a portion of an exemplary write circuit for writing to a MJJ that may be incorporated into a superconducting memory cell and that uses a mixed superconducting write circuit and a (Bi)CMOS write circuit, in accordance with one or more embodiments of the present invention. [Figure 24] FIG. 1 is a schematic diagram illustrating at least a portion of an exemplary write circuit for writing to a MJJ that may be incorporated into a superconducting memory cell and that uses a mixed superconducting write circuit and a (Bi)CMOS write circuit, in accordance with one or more embodiments of the present invention. [Diagram 25] FIG. 2 is a schematic diagram illustrating at least a portion of an exemplary mixed superconducting and (Bi)CMOS write circuit, in accordance with one or more embodiments of the present invention. [Figure 26A] FIG. 2 is a schematic diagram illustrating at least a portion of an exemplary write circuit for writing states to a superconducting memory cell in accordance with one or more embodiments of the present invention. [Figure 26B] FIG. 2 is a schematic diagram illustrating at least a portion of an exemplary write circuit for writing states to a superconducting memory cell in accordance with one or more embodiments of the present invention. [Figure 27] 1 is a schematic diagram illustrating at least a portion of an exemplary read-only memory (ROM) circuit in accordance with one or more embodiments of the present invention. [Figure 28] FIG. 2 is a schematic diagram illustrating at least a portion of an exemplary write circuit for writing states to a superconducting memory cell in accordance with one or more embodiments of the present invention. [Figure 29] FIG. 29 is a schematic diagram illustrating a conventional core memory cell suitable for use in combination with the exemplary write circuit shown in FIG. 28. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] It should be understood that the elements in the figures are illustrated for simplicity and clarity, and that common and well-understood elements that may be useful or necessary in a commercially viable embodiment are not necessarily shown in order to provide a less intrusive view of the illustrated embodiment.

[0020] The principles of the present invention, as demonstrated in one or more embodiments, will be described herein in the context of exemplary systems, circuits, devices, and / or methods that enable reliable writing of superconducting memory circuits (i.e., memory cells) containing both magnetic Josephson junctions (MJJs) and Josephson junctions, or superconducting memory circuits containing only Josephson junctions that form an underlying hybrid circuit with complementary metal oxide semiconductor (Bi)CMOS writing circuitry, methods of writing to random access memories (RAMs), and programming and / or enabling one or more functions of superconducting programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), and pi-junction circuits, among other applications. It should be understood, however, that the present invention is not limited to the particular devices, circuits, and / or methods illustratively shown and described herein. Rather, given the teachings herein, it will be apparent to one of ordinary skill in the art that numerous modifications may be made to the illustrated embodiments that are within the scope and spirit of the present disclosure. Thus, no limitation is intended or should be inferred with respect to the embodiments shown and described herein.

[0021] In this detailed description, the term "MJJ" (magnetic Josephson junction) as used herein can refer to a programmable junction including a magnetic spin valve with a free magnetic layer and a fixed magnetic layer, while the term "π junction" as used herein can broadly refer to a junction containing only a single magnetic layer phase shifted by a fixed π. Furthermore, the terms "0 state", "positive π state", and "negative π state" as used herein are intended to broadly refer to the respective states of orientation of the MJJ layer and the cyclic or non-cyclic states of the circuit, which can be used to store first and second logic states in any combination suitable for the use and operation of a memory cell incorporating such MJJ devices, and any pair of states can be used to represent the first and second logic states, so long as such states are the intended / stable states of the circuit.

[0022] In general, microwave signals, such as single flux quantum (SFQ) pulses, can be used to control the states of memory cells in a memory array. Word lines and bit lines can be selectively activated during read / write operations by SFQ or reciprocal quantum logic (RQL) pulses arriving via the address bus and via separate read and write control signals. These pulses can further control word line and bit line driver circuits adapted to selectively direct respective word line and bit line currents to appropriate memory cells in the memory array.

[0023] Embodiments of the present invention relate to reliable write operations for (i) MJJ-based circuits that include both Josephson junctions (JJs) and magnetic Josephson junctions, and (ii) JJ-only circuits that include Josephson junctions but not magnetic Josephson junctions. The write circuitry for MJJ-based circuits will be discussed first and more extensively than the JJ-only circuits. The circuit topology underlying the write circuitry for MJJ-based circuits can also be applied to the write circuitry for JJ-only circuits with minimal modifications (e.g., one can consider a revised version of FIG. 20) to write to JJ-only memory cells, as described in more detail below.

[0024] As used herein, the terms "memory cell" and "memory circuit" are intended broadly to describe a partially or fully superconducting memory cell, and these terms are essentially synonymous with one another and may be used interchangeably herein. A "memory cell" may perform the function of a logic circuit or other circuit, or be an integral part of a logical operation, as known in the art.

[0025] A distinction can be made between memory elements and memory circuits, where a memory element (e.g. MJJ) only records a state, whereas a memory circuit always comprises additional elements (e.g. field-effect transistors (FETs), inductors, etc.).

[0026] Since the discovery of the MJJ, many alternative MJJs and corresponding write operations (including, for example, application of a magnetic field, π-current seeding, or spin injection) have been devised for the MJJ. Exemplary circuits according to one or more embodiments described herein deliver current in various ways to accommodate these write operations (but not single flux quantum). Thus, the write operations themselves are known in the art and are incorporated primarily by reference. Only the applicability of aspects of the present disclosure to reliably write MJJ-based superconducting circuits will be described with reference to exemplary embodiments.

[0027] It should be noted that the read operation of the exemplary memory cells discussed herein is generally known to those skilled in the art and will not be discussed in detail herein. It should be understood that memory cells suitable for use in the embodiments of the present disclosure have been evolved, at least in part, based on several references, some of which are identified and incorporated by reference herein, as well as other references not expressly mentioned.

[0028] While many diagrams may show regular arrays of memory cells, such arrangements of memory cells are not intended to be limiting. Other superconducting circuits may occupy areas within the regions (e.g., rows and columns) that contain memory cells, having locations where memory cells are excluded.

[0029] The term "bipolar CMOS ((Bi)CMOS)" is commonly used in the art to refer to the integration of two semiconductor technologies, namely, bipolar technology used to form bipolar junction transistors (BJTs) and CMOS technology used to form CMOS logic gates and the like. Thus, the use of (Bi)CMOS technology allows for the integration of BJT and CMOS logic gates into a single integrated circuit (IC) device. However, the term "(Bi)CMOS" as used herein throughout this disclosure is intended to refer not only to the integration technology of mixed CMOS and BJT circuits, but more broadly to the inclusion of any non-superconducting semiconductor device components, including, but not limited to, field effect transistors (FETs), BJTs, resistors, inductors, capacitors, diodes, and the like.

[0030] Generally, the ability to generate signals using room temperature electronics in superconducting circuits is known. Such room temperature electronics typically utilize CMOS circuits to generate and control signals flowing into the low temperature / superconducting environment. In some embodiments, the use of (Bi)CMOS circuits in the low temperature superconducting space will be described. A write circuit according to one or more embodiments of the present disclosure can comprise both room temperature electronics and (Bi)CMOS circuits located (integrated) with the superconducting circuits on a chip / die to write to a superconducting memory circuit or array of superconducting memory cells. This write circuit can be useful for read-only superconducting memory arrays (ROMs) that infrequently utilize the (Bi)CMOS write mechanism, followed by multiple reads performed in the superconducting domain.

[0031] A Josephson magnetic random-access memory (JMRAM) circuit can include an array of JMRAM memory cells, each of which includes a phase-hysteretic MJJ that can be configured to include a ferromagnetic material in an associated barrier. The MJJ can be configured, as an example, as a junction switchable between a zero-phase state and a π-phase state configured to generate a superconducting phase based on a digital state stored in the MJJ. Each of the JMRAM memory cells can also include at least one Josephson junction (e.g., a pair of Josephson junctions in parallel with the MJJ). The basic element of SFQ, RQL, and JMRAM circuits is the Josephson junction, which emits a voltage-time spike with an integrated amplitude equal to a flux quantum (Φ0) when the current through the Josephson junction exceeds a critical current, and the resulting voltage opposes the current flow.

[0032] Exemplary embodiments of the present invention are advantageously suitable for use with conventional MJJs (e.g., in conventional memory cells) that are switched / written by (i) a magnetic field alone, or (ii) a combination of magnetic field selection and phase-based torque.

[0033] The MJJ can be configured to store a digital state corresponding to one of a first logic state (e.g., logic 1) or a second logic state (e.g., logic 0) in response to a write word current and a write bit current associated with the MJJ. For example, the first logic state can correspond to a positive π state in which a superconducting phase is exhibited. As an example, the write word current and the write bit current can be provided to an associated (e.g., coupled to the MJJ) write word line (abbreviated WWL, synonyms include “write row line” or “write row line”) and associated write bit line (abbreviated WBL, synonyms include “write column line” or “write column line”), respectively, and together can set the logic state of the selected MJJ. As used herein, the term “selected” MJJ is intended to broadly refer to an MJJ selected from among a plurality of MJJs for writing by activating a current flow in an associated write bit line WBL of the MJJ. The digital state of the MJJ is written by the flow of positive or negative current in the associated write bit line of the MJJ (for all known / conceived MJJs except for "toggle" MJJs). The MJJ may further comprise a directional write element configured to generate a directional bias current through the MJJ during a data write operation to prevent the MJJ from being set to an undesired negative π state. Thus, the MJJ may be forced into a positive π state to achieve a superconducting phase in a predetermined direction.

[0034] Additionally, the MJJ of each of the JMRAM memory cells in the array can exhibit an indication of a stored digital state in response to a read word current and a read bit current. That is, the superconducting phase can cause a smaller critical current associated with at least one Josephson junction in each of the JMRAM memory cells in a row of the array. Thus, by providing a read bit current and a derivative of the read word current (induced by the read word current flowing through the transformer) in combination, the Josephson junction can be triggered to change the voltage of an associated read bit line if the MJJ stores a digital state corresponding to a first logic state, and (ii) not triggered if the MJJ stores a digital state corresponding to a second logic state. That is, the read bit line can have a voltage that exhibits a change in magnitude (e.g., between a non-zero amplitude and a zero amplitude) based on whether the digital state of the MJJ corresponds to a first logic state, a logic 1, or a second logic state, a logic 0. As used herein, the term "triggering" with respect to a Josephson junction is intended to refer broadly to the phenomenon whereby the Josephson junction produces a discrete voltage pulse in response to the current flowing through the Josephson junction exceeding a predetermined critical current level.

[0035] Write circuits for single cell to twin / few cells 1 is a schematic diagram conceptually illustrating at least a portion of an exemplary MJJ write circuit 100 in accordance with one or more embodiments of the present disclosure. The MJJ write circuit 100 is beneficial because it provides a reliable and process variation tolerant mechanism for programming (i.e., writing) the phase (e.g., state) of the MJJ in an MJJ-based circuit. Referring to FIG. 1, the MJJ write circuit 100 includes a plurality of MJJ cells 1020 to 1024. N-1 Each MJJ cell has its own corresponding write line segment (WLS) lines WLS0 to WLS N-1where N is an integer greater than 1. The WLS associated with a given MJJ is preferably oriented at an angle to the major axis of the MJJ, rather than being positioned perpendicular to the major axis, although the WLS passes over and adjacent to the free layer of the MJJ. MJJs, as known to those skilled in the art, are typically formed in the shape of an ellipse having major and minor axes, the major axis being longer than and perpendicular to the minor axis of the ellipse.

[0036] Each MJJ-based memory circuit 100 includes at least one MJJ, MJJ_0 through MJJ_N-1, and at least one WLS, WLS0 through WLS N-1 , and at least one transistor, each of which may be an n-channel FET (NFET) device (e.g., an n-channel metal-oxide semiconductor field-effect transistor (MOSFET)), NFETs 1040 to 104 N-1 , which are connected in series with a corresponding WLS and selectively connect the WLS to a current source 106. The current source 106, in one or more embodiments, supplies a wire to a bus or other interconnect (e.g., In_Out_1, In_Out_2) of a selected WLS and a corresponding selected FET 1040, 1042, N-1 A given amplitude I W A GND ground potential is an analog current source that can be programmed to generate either a positive or negative (i.e., bidirectional) current.

[0037] Current source 106 may, in one or more alternative embodiments, be configured to generate current in only one direction, and a control circuit, such as an H-bridge, may regulate the current I through the WLS, as will be apparent to one of ordinary skill in the art. WAn H-bridge circuit may be used in combination with current source 106 to selectively change the direction of the current. An H-bridge circuit may be incorporated into current source 106 in some embodiments to form a bidirectional current source. Additionally, transistors 1040 to 1044 are used to selectively connect the WLS lines to interconnects In_Out_1 and / or In_Out_2. N-1 103, each of which connects a first one of the interconnects In_Out_1 to a corresponding WLS. N-1 1030, a first subset of upper and lower transistors (e.g., 1040), each of which connects a second one of the interconnects In_Out_2 to a corresponding WLS. In other embodiments, a given WLS may include both upper and lower transistors. N-1 is provided to illustrate a generic current switch that may be implemented with (Bi)CMOS circuit elements such as BJTs or a combination of FETs and BJTs, and may include first and second subsets of transistors along with corresponding WLS lines of MJJ-based circuit 100. For clarity, only one MJJ write circuit is shown in FIG. 1, however, it should be understood that embodiments of the invention are not limited to the particular arrangement shown. When one of the transistors, such as transistor 1040, is active (i.e., on or enabled), transistors 1041 to 104 N-1 The remaining N-1 transistors, etc., are preferably inactive (ie, off or disabled).

[0038] The exemplary MJJ write circuit 100 conceptualizes for the experienced magnetic random-access memory (MRAM) researcher / designer a circuit and novel approach for writing one MJJ at a time with the aid of at least one magnetic field defined by a room temperature analog current source 106 according to one or more embodiments. The current source 106 can be programmed to provide a specific positive current or a specific negative current unique to a positive current that generates positive and negative fields, respectively, on the free layer of a selected MJJ to selectively write a “1” or “0” logic state (defined by the π-phase and zero-phase states of the MJJ, respectively) to the MJJ.

[0039] In the exemplary MJJ write circuit 100, by way of example only and not by way of limitation, a first end of the WLS0 is connected to a first interconnect In_Out_1, a second end of the WLS0 is connected to a first drain / source of a corresponding FET 1040, and a second source / drain of the FET 1040 is connected to a second interconnect In_Out_2. N-1 The first end of the corresponding FET 104 N-1 connected to the first source / drain of the WLS N-1 The second end of the FET 104 is connected to the second interconnect In_Out_2. N-1 The second source / drain of is connected to the first interconnect In_Out_1. It should be understood that embodiments of the present invention are not limited to the particular arrangement of WLS and MJJ connections shown in FIG. 1. For example, while MJJ write circuit 100 is illustrated with alternating top and bottom switches (e.g., FETs) to connect the first and second interconnects to corresponding WLS lines, other embodiments may use only bottom switches, only top switches, or both top and bottom switches to connect the WLS lines to the first and second interconnects.

[0040] In the exemplary MJJ write circuit 100, only one MJJ is selected at a given time for writing. That is, one FET is active (i.e., turned “on”), resulting in a current I W When this signal is sent, the remaining FETs in the MJJ write circuit 100 are inactive (i.e., turned off). N-1 Each of the control signals 1100 to 110 is applied to the gate of the corresponding FET. N-1 For example, during a write operation to MJJ 1020, applying an appropriate control signal to the gate of FET 1040 turns on the corresponding FET 1040, while the remaining FETs 1041 through 1044 are turned on. N-1 Therefore, assuming n-type FETs (NFETs) are used, the control signal 1100 provided to the gate of FET 1040 to write to MJJ0 may be VDD, while FETs 1041 through 1042 may be VDD. N-1 The control signals 1101 to 110 are respectively supplied to the gates of N-1 may be ground (GND). N-1 The control signals 1100 to 110 are used to drive the gates of N-1 can be generated using any known CMOS circuit (e.g. logic gates, shift registers, latches, etc.).

[0041] It should be understood that the location of a FET in series with a given WLS is not important; that is, the FET may be connected below (i.e., after) the corresponding MJJ, as in the case of FET 1040, or the FET may be connected in series with (i.e., after) the corresponding MJJ, as in the case of FET 1040. N-1In addition, although only one FET is shown connected in series with each WLS, multiple FETs (e.g., above and below each MJJ) may be used to selectively connect a given WLS line to the first and second interconnects, as will be apparent to one of ordinary skill in the art given the teachings herein.

[0042] FIG. 2 conceptually illustrates ideal Stoner-Wohlfarth switching assteroids associated with each of at least a subset of the MJJs of the exemplary MJJ write circuit 100 of FIG. 1. The Stoner-Wohlfarth model, as known in the art, is the simplest model that adequately describes magnetization reversal in nanoscale systems small enough to contain a single magnetic domain. In FIG. 2, the hard axis field is represented on the y-axis and the easy axis field is represented on the x-axis. The Stoner-Wohlfarth assteroid is essentially a plot of magnetic poles showing the reversal field assuming coherent reversal. With reference to FIG. 2, a smaller (normalized magnitude ±0.5) free layer switching assteroid is shown centered at the origin, and a larger (normalized magnitude ±1.0) fixed layer switching assteroid is shown centered at the origin and surrounding (i.e., concentric with) the free layer switching assteroid. The free-layer switching asteroids and pinned-layer switching asteroids shown in Figure 2 are simplified in that they neglect interactions between the free and pinned layers of the MJJ, which would otherwise cause the asteroids to deviate from their origin.

[0043] The boundary of the switching asteroid represents the point on the curve of the magnetic field beyond which the MJJ will switch the phase of the MJJ (and in some write techniques represents switching of state, as known in the art). Thus, in the free layer of the MJJ, magnetic fields having geometrically combined hard and easy axis amplitudes less than the free layer switching asteroid will not switch the state of the MJJ, and magnetic fields having geometrically combined magnitudes greater than the boundary of the free layer switching asteroid will switch the state of the MJJ (such as the write "1" and write "0" programming magnetic field points shown in FIG. 2). However, the write "1" and write "0" programming magnetic field points are within the boundary of the fixed layer switching asteroid and will not switch the fixed layer state. The write "1" and write "0" programming magnetic fields are generated by the MJJ write circuit 100 shown in FIG. 1 in one or more embodiments.

[0044] The write "1" and write "0" programming fields are located between the boundaries of the free layer switching asteroid and the fixed layer switching asteroid, respectively, in the example of FIG. 2. The distance D between the magnetic field point and the boundary of the free or fixed layer switching asteroid represents the design margin of the MJJ write circuit. The MJJ write circuit 100 therefore adjusts the write current I so that the magnetic field point is halfway between the boundary of the free layer switching asteroid and the boundary of the fixed layer switching asteroid to maximize the design margin (D). W Preferably, the signal processing unit 100 is configured to generate

[0045] 3 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based memory circuit 300 with an integrated write FET, according to one or more embodiments of the present disclosure. The exemplary MJJ-based memory circuit 300 includes at least one MJJ 310, a plurality of Josephson junctions 302 and 303, an inductor 312, and at least one transformer, shown here (in a preferred symmetrical arrangement) as a plurality of transformers 306 and 308. The read and write operations of a similar MJJ-based circuit are described in "A Novel MJJ-Based Memory Circuit," IEEE Transactions on Memory Electronics, vol. 13, no. 1, pp. 1111-1115, and will not be described in further detail herein. However, in contrast to the MJJ-based circuit described in "A Novel MJJ-Based Memory Circuit," IEEE Transactions on Memory Electronics, vol. 13, no. 1, pp. 1111-1115, the MJJ-based memory circuit 300 includes multiple switches and, in some embodiments, a FET 304. Easy_Axis , 304 Hard_Axis , or more broadly, non-superconducting (e.g., (Bi)CMOS) switches 304 Easy_Axis , 304 Hard_Axis The integrated write circuit portion of the MJJ-based memory circuit 300 can be implemented using an exemplary write circuit 1100 shown in FIG. 11, which will be described in further detail herein below.

[0046] With continued reference to FIG. 3, the integrated write circuit portion of the MJJ-based memory circuit 300 includes a FET 304 Easy_Axis Preferably, the easy axis write line passes adjacent to the MJJ 310 between the first terminal (e.g., drain) of the FET 304 and the first interconnect terminal In_Out_1_Easy_Axis. Easy_Axis A second terminal (e.g., a source) of the FET 304 may be connected to the second interconnect terminal In_Out_2_Easy_Axis. Easy_Axis The gate of is preferably adapted to receive a first control signal 320 capable of driving a CMOS.

[0047] The integrated write circuit portion of the MJJ-based memory circuit 300 preferably further comprises a hard axis write line that passes adjacent to the MJJ 310 and may be arranged orthogonal to the easy axis write line. Hard_Axis and the third interconnect terminal In_Out_1_Hard_Axis. Hard_Axis A second terminal (e.g., a source) of the FET 304 may be connected to the fourth interconnect terminal In_Out_2_Hard_Axis. Easy_Axis The gate is preferably adapted to receive a first control signal 320 .

[0048] Figure 4 is a graph conceptually illustrating the distribution of hypothetical switching fields for the pinned and free layers of MJJs in multiple MJJ-based circuits. When the distributions of MJJs in a row overlap, as is the case for the example distribution shown in Figure 4, a unique value of the switching field cannot be found that switches all of the free layers of the MJJs associated with that row without also switching the pinned layers of some of the MJJs in that row. A solution to this problem can be achieved by tailoring the switching field to each individual MJJ device.

[0049] FIG. 5 conceptually illustrates ideal Stoner-Wohlfarth switching asteroids associated with at least a subset of MJJs, including field selection points effected by an exemplary MJJ write circuit to be discussed with respect to FIG. 11. To accommodate the write "0" and write "1" field points superimposed on the asteroids of FIG. 5, a more expensive orthogonal write circuit, an example of which is shown in FIG. 11, may be required compared to the write "0" and write "1" field points superimposed on the asteroids of FIG. 2 (e.g., effected by the exemplary MJJ write circuit 100 shown in FIG. 1). Integration of FET switches with memory elements to form memory cells has already been described with respect to the exemplary MJJ-based memory circuit 300 of FIG. 3 (with associated FET switches, MJJs, and write line segments shown in FIG. 11). The novel write circuit of FIG. 11 can be configured to provide more degrees of freedom with respect to the magnitude and / or orientation of the applied magnetic field. As is known in the art, the MJJ 310 of the memory circuit 300 shown in Figure 3 may have many possible write "0" and write "1" field points, reflected respectively by the light gray and dark gray points on the asteroid in Figure 5. The main cost of this approach over the technique shown in Figure 1 is the provision of additional write lines located above or below the MJJ.

[0050] FIG. 6 conceptually illustrates an ideal Stoner-Wohlfarth switching astroid associated with each of at least a subset of the MJJs in the exemplary MJJ writing circuit 100 of FIG. 1, with the field points 604 and 606 marked to set the MJJs to π states 604 and 606. As long as no field is applied, the MJJs remain in π state 602. In the system mode, the MJJs spontaneously accommodate clockwise or counterclockwise currents in the superconducting loop that contains the MJJ. The two distinct π states 604 and 606 differ in that the magnetic layers of the MJJ point in opposite directions, and the orientation of the layers of the MJJ (i.e., free and fixed magnets pointing left or right) accommodate circulating currents. Both can accommodate either type of persistent circulating current to change the dynamics (operating point) of the superconducting circuit. Note that the π-state itself depends on the properties of the spin-valve MJJ (e.g., the thicknesses of the magnetic layers), as is known in the art.

[0051] FIG. 7 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based memory circuit 700 with an integrated write switch, according to one or more embodiments of the present disclosure, for purposes of illustration only and not limitation. The MJJ-based memory circuit 700 specifically includes at least one MJJ 710, one or more Josephson junctions 702 and 704, and a number of transformers 706 and 708. A memory circuit topology and exemplary read and write operations that may be similar to the exemplary MJJ-based memory circuit 700 of FIG. 7 are described in U.S. Pat. No. 6,399,343, the disclosure of which is incorporated herein by reference in its entirety. However, the memory circuit taught by U.S. Pat. No. 6,399,343 does not use a non-superconducting (e.g., FET) switch to route current through the memory circuit, which will be described in more detail herein below with reference to FIG. 7.

[0052] The integrated write circuit of the MJJ-based memory circuit 700 may include one or more write switches, which in this illustrative example may be implemented using FETs 712 and 714 (e.g., n-channel field-effect transistors (NFETs) or p-channel field-effect transistors (PFETs)), or other non-superconducting elements / devices. The integrated write circuit of the MJJ-based memory circuit 700 may further include, in one or more examples, hard and easy axis WLS lines between a first terminal (e.g., drain) of the first FET switch 712 and a first interconnect terminal In_Out_1_Hard_And_Easy_Axis, a second terminal (e.g., source) of the FET switch 712 that may be connected to a second interconnect terminal In_Out_2_Hard_And_Easy_Axis, and a gate of the FET switch 712 adapted to receive a control signal 720 that may drive a CMOS.

[0053] A second FET switch 714 of the integrated write circuit of the MJJ-based memory circuit 700 may have a first terminal (e.g., drain) connected to a first transformer 706 connected in series with a third interconnect terminal In_Out_1_Spin_Torque_&_π-Phase_Setting, which has a primary winding L1. The transformer 706 functions, at least in part, to (i) set the π-phase (positive or negative) and / or (ii) write (or assist in writing) the MJJ. A second terminal (e.g., source) of the FET switch 714 may be connected to a fourth interconnect terminal In_Out_2_Spin_Torque_&_π-Phase_Setting, and a gate of the FET switch 714 may be adapted to receive a control signal 720. The integrated write circuit portion of the MJJ-based memory circuit 700 may, in some embodiments, be operated in a manner consistent with the operation of the example write circuit 100 shown in FIG. 1.

[0054] A second transformer 708 is provided in the memory circuit 700, with a primary winding L3 in series with the read line (RL) and is used primarily during read operations. Since aspects of the present disclosure focus primarily on write operations of the memory circuit, the transformer 708 will not be described in further detail herein.

[0055] The memory circuit writing technique taught by US Pat. No. 6,399,663, or portions thereof, may also be incorporated (with or without modifications) into the exemplary memory circuit 700 shown in FIG. 7. The technique of US Pat. No. 6,399,663 will not be described in further detail herein. However, the use of the memory circuit 700 has the beneficial ability to enable a reliable and functional version of the writing technique of US Pat. No. 6,399,663, thereby enhancing the writing technique of US Pat. No. 6,399,663 by providing external control (i.e., non-superconducting based control) over (i) the easy and hard axis field generating currents, (ii) the spin torque current, and / or (iii) the π-phase setting current, which is not possible with the technique of US Pat. No. 6,399,663. The first transformer 706, particularly for the spin torque current and the π-phase setting current, is beneficially placed in series with the second FET switch 714 and the third interconnect terminal In_Out_1_Spin_Torque_&_π-Phase_Setting in one or more embodiments such that a regulated programming current, e.g., governed by a room temperature current source, can generate (by induction) a current through the secondary winding L2 of the transformer 706. At least a portion of the induced current flows through at least one MJJ 710. The secondary current generated in the transformer 706 that flows through the MJJ 710 can be scaled as the ratio of the number of turns in the secondary winding to the number of turns in the primary winding (or the equivalent mutual inductance between the two conductive wires).

[0056] 8 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based memory circuit 800 with at least one integrated write switch according to one or more embodiments of the present disclosure, by way of example only and not by way of limitation. The exemplary MJJ-based memory circuit 800 shown in FIG. 8 includes at least one MJJ 810, one or more JJs 802 and 804, and multiple transformers 806 and 808, similar to the exemplary memory circuit 700 of FIG. 7. The transformer 808 is primarily used for read operations and will not be discussed in further detail herein.

[0057] The integrated write circuit of the exemplary MJJ-based memory circuit 800 includes a write switch that may be implemented with a FET switch 812. A first terminal (e.g., drain) of the FET switch 812 may be connected to a first interconnect terminal In_Out_1_Hard_And_Easy_Axis via a WLS line passing adjacent to the MJJ 810 to write the state of the MJJ. A second terminal (e.g., source) of the FET switch 812 may be connected to a second interconnect terminal In_Out_2_Hard_And_Easy_Axis, and a gate of the FET switch 812 is adapted to receive a control signal 820 capable of driving a CMOS. The integrated write circuit portion of the MJJ-based memory circuit 800 may, in some embodiments, be operated in a manner consistent with the operation of the write circuit 100 illustrated in FIG. 1.

[0058] The exemplary memory circuit 800 shown in Figure 8, like the exemplary MJJ-based memory circuit 700 of Figure 7, has the ability to provide external control over the currents generating the easy and hard axis fields, which may provide a significant advantage over the approach used in US Pat. No. 6,399,366. However, in contrast to the memory circuit 700 of Figure 7, the memory circuit 800 of Figure 8 eliminates the second FET switch (714 of Figure 7) and instead has a first transformer 806 connected in series directly between the third and fourth interconnect terminals, In_Out_1_Spin_Torque_&_πPhase_Setting and In_Out_2_Spin_Torque_&_πPhase_Setting, respectively. The write circuit (proportional to the size of the FET) can drive a current through a primary winding L1 of a transformer 806 (of multiple series-connected memory circuits 800, as discussed in more detail below with reference to FIG. 20), which can then simultaneously generate a corresponding current through a secondary winding L2 of the transformer 806 that induces a current (in secondary winding L2) to flow through the MJJ 810, generating at least one of (i) a spin torque current and (ii) a π-phase set current. The secondary current generated in the transformer 806 flows through the MJJ 810 and can be scaled as the ratio of the number of turns in the secondary winding to the number of turns in the primary winding (or the equivalent mutual inductance between the two conductive wires). This primary current of the write circuit can be used to drive multiple series-connected MJJ-based memory circuits 800.

[0059] 9 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based memory circuit 900 with at least one integrated write switch according to one or more embodiments of the present disclosure, by way of example only and not by way of limitation. The exemplary MJJ-based memory circuit 900, which is consistent with the exemplary memory circuit 800 of FIG. 8, includes at least one MJJ 910, one or more JJs 902 and 904, and multiple transformers, 906 and 908. The first transformer 906 includes a primary winding L1 connected at a first end to a first interconnect terminal In_Out_1_Spin_Torque_&_π-Phase_Setting_&_Hard_&_Easy_Axis, and includes a secondary winding L2 connected to the MJJ 910 and conducting the write current through the MJJ. The second transformer 908 with secondary winding L4 is primarily used for read operations and will not be discussed in further detail herein.

[0060] The integrated write circuit of the exemplary MJJ-based memory circuit 900 includes a write switch that can be implemented with a FET switch 912 (e.g., an NFET or a PFET). A first terminal (e.g., a drain) of the FET switch 912 can be connected to a second end of the primary winding L1 of the first transformer 906 via a WLS line passing adjacent to the MJJ 910 to write a state to the MJJ. A second terminal (e.g., a source) of the FET switch 912 can be connected to a second interconnect terminal In_Out_2_Spin_Torque_&_π-Phase_Setting_&_Hard_&_Easy_Axis, and a gate of the FET switch 912 is adapted to receive a control signal 920 capable of driving a CMOS. The integrated write circuit portion of the MJJ-based memory circuit 900 can, in some embodiments, be operated in a manner consistent with the operation of the exemplary write circuit 100 shown in FIG. 1.

[0061] In the MJJ-based memory circuit 900, an external current source can generate a current through a primary winding L1 of a transformer 906 and can also generate a current through a secondary winding L2 to flow through at least one MJJ 910. This generated current can function as at least one of (i) a spin torque current and (ii) a π-phase setting current. The first transformer 906 is advantageously placed in series with the WLS line and a FET switch 912 such that a "regulated" programming current, for example, managed by a room temperature current source, can generate a magnetic field in the WLS line coupled to at least one adjacent MJJ 910 and also generate a current in the secondary winding L2 of the transformer 906 that flows through the MJJ 910. The secondary current generated in the transformer 906 and flowing through the MJJ 910 can be scaled as the mutual inductance of the secondary inductor L2 and the primary inductor L1.

[0062] Although several exemplary embodiments of a write circuit suitable for use in an MJJ-based memory circuit have been described in conjunction with Figures 3, 7, 8, and 9, it should be understood that aspects according to the present disclosure are not limited to these embodiments. Rather, it will be apparent to one skilled in the relevant art that modifications may be made to the write circuit shown and described herein within the scope of the embodiments of the present invention. Thus, according to embodiments of the present disclosure, a write circuit for an MJJ-based memory circuit is contemplated that incorporates (i) an at least partially field-switched MJJ comprising a FET switch in combination with at least one WLS line, and (ii) an apparatus for assisting in writing the MJJ comprising a FET switch in combination with a transformer.

[0063] 10 is a schematic diagram illustrating at least a portion of an example MJJ write circuit 1000 in accordance with one or more embodiments of the present disclosure. The MJJ write circuit 1000 includes a WLS including one FET switch and MJJ pair, i.e., a true (T) MJJ, a MJJ T_0 and complement (C) MJJ, MJJ C_01. A true MJJ, MJJ T_0 and its complement MJJ, MJJ C_0 is the corresponding true write line segment WLS T_0 Line and complement write line segment WLS C_0 Together with the lines, they form a dual MJJ based circuit 10100 of the write circuit 1000. Although only one representative MJJ based circuit 10100 is shown in FIG. 10, it should be understood that the MJJ write circuit 1000 may comprise (N-1) MJJ based circuits (collectively referred to as 1010), where N is an integer greater than 1. The MJJ based circuit 108 of the write circuit 100 is replaced with the dual MJJ based circuit 1010. True MJJ, MJJ T_0 and its complement MJJ, MJJ C_0 Each MJJ of a given pair with preferably has its own corresponding WLS line associated with it. The MJJ write circuit 1000 is beneficially suitable for use with a number of superconducting circuits that require true (e.g., 0 state) and complementary (e.g., π state, 0 state) states to be held in the true and complementary MJJs, respectively, in order to operate.

[0064] For example, referring to FIG. 10, a given WLS line may be a true MJJ, a MJJ T_0 Above (or below) MJJ T_0 The first WLS segment passing close to WLS T_0 (true WLS segment) and its complement MJJ, MJJ C_0 Above (or below) MJJ C_0 A second WLS segment passes close to WLS C_0 (complementary WLS segment) and true WLS segment WLS T_0 and the complement WLS segment WLS C_0 are electrically connected together by at least one conductive segment and connected to a first interconnect (In_Out_1 or In_Out_2). T_0 and WLS C_0In one or more embodiments, the axial ends of the MJJ are oriented at an angle relative to the longitudinal axis of the corresponding MJJ.

[0065] WLS segment WLS for a given WLS line T_0 and WLS C_0 Each of the selection switches, FETs 10040 to 10044, in one or more embodiments, is connected together in series with a corresponding selection switch, which may be implemented with a FET 10040 (e.g., an NFET or a PFET). Specifically, a first terminal (e.g., drain) of the selection switch associated with each WLS line is connected to the end of the corresponding WLS segment (either the true WLS segment or the complement WLS segment), and a second terminal (e.g., source) of the selection switch is connected to the second interconnect (In_Out_2 or In_Out_1). The selection switches, FETs 10040 to 10044, N-1 Each of the FETs (only FET 10040 is explicitly shown) couples a corresponding control signal 10080 to 10088, respectively, to the control terminal (e.g., gate) of the corresponding select switch. N-1 10080 are selectively activated by providing a control signal 10081 (only control signal 10080 is explicitly shown).

[0066] In the exemplary embodiment shown in FIG. 10, the complementary WLS segment WLS C_0 The first end of the WLS is connected to a first interconnect In_Out_1, which is connected to a first terminal of the current source 106, C_0 The second end of the WLS segment is a true WLS T_0 connected to the first end of the WLS T_0 A second end of the selected WLS line is connected to a first source / drain of the FET 10040, and a second source / drain of the FET 10040 is connected to a second interconnect In_Out_2 that is connected to a second terminal of the current source 106. The WLS segment controls the current I flowing through the selected WLS line. W_0 But the corresponding true MJJ, MJJ T_0 in the first direction and the corresponding complement MJJ, MJJ C_0 in a second direction opposite to the first direction.

[0067] The exemplary MJJ write circuit 1000 illustrates one embodiment that may be advantageous in some applications using superconducting circuits that require true and complement phases for operation, but the write circuit is less tolerant to process variations compared to the exemplary MJJ write circuit 100 shown in Figure 1. The addition of a second MJJ to the MJJ write circuit 1000 shown in Figure 10 affects the ability of the circuit to generate individualized (i.e., tailored) MJJ programming magnetic fields for the π and 0 states used to program the MJJ.

[0068] 11 is a schematic diagram illustrating at least a portion of an example MJJ write circuit 1100 that individually controls both the hard axis magnetic field and the easy axis magnetic field applied to each MJJ, in accordance with one or more embodiments of the present disclosure. To assist in illustrating this example embodiment, example conductor currents and NFET gate voltages associated with an active mode of the MJJ write circuit 1100 are illustrated in FIG. 11. The MJJ write circuit 1100 includes MJJs 11020 to 1102. N-1 1, except that each of at least a subset of the MJJs (only one MJJ11020 is explicitly shown) has a hard axis WLS segment and an easy axis WLS segment associated with the subset of MJJs, and each WLS segment is separately controlled by a corresponding FET switch, where N is an integer greater than 1.

[0069] 11, the exemplary MJJ write circuit 1100 includes a plurality of MJJs, of which only one (MJJ 11020) is shown for purposes of clarity. Each MJJ includes a hard axis WLS segment (WLS11020) that passes under (or over) the corresponding MJJ 11020, proximate to the pinned layer of the MJJ, using MJJ 11020 as a representative example. 0_Hard_Axis and the corresponding WLS segment WLS of the easy axis passing above (or below) MJJ11020 close to the free layer of the MJJ. 0_Easy_AxisIn this exemplary embodiment, WLS 0_Hard_Axis is oriented parallel to the long axis of MJJ11020 and the WLS 0_Easy_Axis is oriented parallel to the minor axis of the MJJ and the WLS 0_Hard_Axis However, it should be understood that embodiments of the present invention are not limited to any particular orientation of the hard axis WLS segment and the easy axis WLS segment associated with each MJJ.

[0070] The memory circuit 1100 is provided with an easy axis write current I W_0_Easy_Axis A first FET, FET1104, which is used to generate the easy axis magnetic field by controlling 0_Easy_Axis and the hard axis write current I W_0_Hard_Axis Control the first MJJ, MJJ _0 A second FET, 1104, which is used to generate the hard axis magnetic field associated with 0_Hard_Axis There are two FET switches: FET1104 and FET1104. 0_Easy_Axis The first source / drain of WLS 0_Easy_Axis Connected to the first end of the segment, WLS 0_Easy_Axis A second end of the segment is connected to the first interconnect In_Out_1_Easy_Axis to deliver the easy axis write current and FET 1104 0_Easy_Axis The second source / drain of FET 1104 is connected to the second interconnect In_Out_2_Easy_Axis. 0_Easy_Axis The gate of the FET 1104 is adapted to receive a first control signal 11080 to select (write to) the corresponding MJJ 11020. 0_Hard_Axis The first source / drain of WLS 0_Hard_Axis Connected to the first end of the segment, WLS 0_Hard_Axis A second end of the segment is connected to a third interconnect In_Out_1_Hard_Axis to deliver the hard axis write current and FET 1104 0_Hard_Axis The second source / drain of FET 1104 is connected to the fourth interconnect In_Out_2_Hard_Axis. 0_Hard_AxisThe gate of is adapted to receive a first control signal 11080. In FIG. 11, for the sake of clarity, only one MJJ is shown, but it should be understood that the same circuit configuration and description are applicable to the other MJJs of the write circuit 1100.

[0071] Although not explicitly shown (but implied) in FIG. 11, the current I W_Hard_Axis A first programmable current source configured to supply a current I may be connected between the In_Out_1_Hard_Axis interconnect and the In_Out_2_Hard_Axis interconnect to generate an easy axis magnetic field. W_Easy_Axis A second programmable current source configured to provide a current source current I / O 2 may be connected between the In_Out_1_Easy_Axis interconnect and the In_Out_2_Easy_Axis interconnect. The second programmable current source is also not explicitly shown, but is implied.

[0072] During a write operation to a selected MJJ, such as MJJ11020, the corresponding FET 1104 0_Easy_Axis and 1104 0_Hard_Axis Both of the selected MJJs and the selected FETs are turned on by applying an appropriate control signal 11080 (e.g., VDD, assuming NFET switches are used) to the gates of the corresponding FETs, and the remaining FETs associated with the unselected MJJs of the write circuit 1100 are turned on by applying appropriate control signals 11081 to 1108 N-1 (e.g., ground, assuming an NFET switch is used) to a corresponding FET (not explicitly shown, e.g., 1104 1_Easy_Axis and 1104 1_Hard_Axis From 1104 N-1_Easy_Axis and 1104 N-1_Hard_Axis ) to the gates of the selected MJJ, where N is an integer greater than 1. The write circuit 1100 may, for example, provide orthogonal write line segments WLS 0_Hard_Axis and WLS 0_Easy_Axis , and their associated respective FET switches 1104 0_Hard_Axis and 11040_Easy_Axis Since any two-dimensional magnetic field can be applied, which is effective in the above-described manner, the present invention has the advantage of being highly versatile.

[0073] 12 is a schematic diagram illustrating at least a portion of an example write current multiplexing circuit 1200 for reducing leakage current in accordance with one or more embodiments of the present invention. N-1 (collectively 102) and a plurality of transistors 1205 A , 1205 B And, 12040 to 1204 N-1 Each of the MJJs 102 may be associated with a corresponding write-column line of one of a plurality of subsets A and B of write-column lines. In the example multiplexing circuit 1200, half of the MJJs 102 (MJJs 1020 through 1022) are (N / 2)-1 ) is associated with the write-column lines of subset A, and the other half of the MJJ (MJJ102 (N / 2) From 102 N-1 ) are associated with the write-column lines of subset B. It should be understood that embodiments of the present invention are not limited to a particular number of subsets of write-column lines or to any other distribution of MJJs 102 among multiple subsets of write-column lines.

[0074] For example, in a large circuit with hundreds of millions of MJs, a series of “off” transistors 1205 A , 1205 B , and 12040 to 1204 N-1 The parallel leakage current through the 1205 A , 1205 B One of the following and 12040 to 1204 N-1 Two series “on” transistors, one of which is a MJJ, and a magnetic field is applied to a specific MJJ (i.e., MJJ1020 to 102 N-1 This can significantly affect the write current supplied through the WLS line coupled to the MOSFET (one of the MOSFETs) for each programming operation (which may occur once a day).

[0075] However, a read-modify-write scheme could mitigate the effects of such leakage currents, given that the write current could be tuned each time the MJJ is written. Read-modify-write schemes suitable for use in embodiments of the present disclosure are known to those skilled in the relevant art and will not be discussed in further detail herein.

[0076] It is important to note that, as is known in the art, the π state (or 0 state) can be associated with either a parallel or antiparallel orientation, and the π state can be a function of the thickness of the ferromagnetic layers in the MJJ.

[0077] Shift register drive array write circuit FIG. 13 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based write circuit 1300 for writing to an MJJ in accordance with one or more embodiments of the present disclosure. As described in more detail below, the write circuit 1300 beneficially allows for the application of bidirectional easy axis fields in the plane of the MJJ, or alternatively, for the provision of bidirectional spin torque currents (or π-state currents) through the MJJ stack of material via inductors associated with memory circuits (not explicitly shown in FIG. 13). The write circuit 1300 can be used to “program” the MJJ, which can function as a memory element, acting as a programmable switch in a Josephson magnetic programmable logic array (JMPLA), as described in U.S. Pat. No. 6,399,323, the disclosure of which is incorporated herein by reference in its entirety, among other applications, and for other programmable circuit functions in a superconducting field programmable gate array (FPGA). It should be noted that FIG. 13 primarily shows only the MJJ and not the superconducting array cells (programmable switches, PS) or FPGA circuits comprising superconducting array cells, since this apparatus / circuitry allows one to write to the MJJ of all known superconducting array cells and FPGA circuits disclosed in the art.

[0078] 13 includes a plurality of magnetic Josephson junctions 1302 and a control circuit 1303 that controls the current used to write the MJJ. The control circuit 1303, in one or more embodiments, can be implemented as a shift register that includes a plurality of shift circuits 1330, each of which includes one or more master-slave latches (M / S_+) 1304. The write circuit 1300 drives a write row line current I through a selected one of the write row lines. WRL A plurality of write row lines WRL1 to WRLN (where N is an integer) (In FIG. 13, WRL1 is the write row line current I WRL , thus indicating a “selected” write row line), and a write column line current I WCL_1 From I WCL_M A plurality of write-column lines WCL1 to WCL M (where M is an integer) (e.g., the exemplary selected write-column lines WCL1 to WCL M It should be understood that the term “write line” as used herein is intended to broadly refer to one or more conductive elements of a write column path, including write column lines, write line segments, bonded wires forming a primary coil / winding of at least one inductor, and a series of JJ pass-throughs, and / or one or more conductive elements of a write row path, including write line segments, write row lines, and bonded wires forming a primary coil / winding of at least one inductor.

[0079] A write column current input circuit provided in write circuit 1300 can control the input (i.e., current supply) of a write column line (WCL) current. In one or more embodiments, the write column current input circuit can comprise a number of NFET switches 1306, 1308, 1310, 1312 (which advantageously provides a simple and effective implementation) adapted to receive corresponding control signals generated by control circuit 1303 at control inputs of the write column current input circuit, which in this embodiment are the gates of respective NFETs 1306, 1308, 1310, 1312. Each of NFET switches 1306, 1308, 1310, 1312 forming the write column current input circuit supplies a write column line current I WCL_1 From I WCL_M a first source / drain coupled to a first terminal In_C of a first current source 1328 that may be the overall write-column line current source generating M, and a gate for receiving one of the control signals generated at corresponding output nodes (i.e., taps) 1307, 1309, 1311, 1313 of the control circuit 1303. The first current source 1328 may comprise a single current source or multiple current sources and includes at least one control signal En_I for enabling and / or controlling the amplitude of the current generated by the first current source. WCL The write column current input circuit is preferably adapted to receive the corresponding write column lines WCL1 to WCL M The write column current I WCL_1 From I WCL_M Control the supply of.

[0080] Similarly, a write column current outlet circuit provided in write circuit 1300 is configured to control the write column line current outlet (i.e., current sink) for writing to MJJ 1302. The write column current outlet circuit, which may comprise NFET switches 1314, 1316, 1318, 1320 (which is advantageous as it provides a simple and effective implementation), is adapted to receive corresponding control signals generated by control circuit 1303 at control inputs of the write column current outlet circuit, which in this embodiment are the gates of NFETs 1314, 1316, 1318, 1320, respectively. Each of NFET switches 1314, 1316, 1318, 1320 forming the write column current outlet circuit is connected to write column lines WCL1 to WCL2. M , a second source / drain coupled to a second terminal Out_C of the first current source 1328, and a gate for receiving one of the control signals generated at the corresponding outputs 1315, 1317, 1319, 1321 of the control circuit 1303. The write column current outlet circuit comprises a first source / drain coupled to a corresponding one of the write column lines WCL1 to WCL M The write column current I WCL_1 From I WCL_M Controls the intake of.

[0081] Although referred to herein as current inlet or current outlet circuits, it should be understood that each of these circuits can be placed in either position as an inlet or outlet circuit due to the zero voltage on the superconducting wire for DC-like currents. The primary function of the write column current inlet and write column current outlet circuits is to selectively control the direction of current flow through the write column lines as a whole.

[0082] The write circuit 1300, in one or more embodiments, connects corresponding write row lines WRL1 through WRL N (where N is an integer greater than 1) WRL In particular, the write row line current I WRL A first terminal of a second current source (i.e., write row line current source) 1326 configured to generate N The second current source 1326 may comprise a single current source or multiple current sources, and the current I generated by the second current source is connected to a first end of the second current source 1326. WRL and / or current I WRL At least one control signal En_I is used to control the amplitude of WRL Each of the NFET switches 1322, 1324 comprises a first source / drain connected to a second end of a corresponding one of the write row lines, a second source / drain connected to a second terminal Out_R of a second current source 1326, and a gate adapted to receive one of the control signals generated at corresponding outputs 1323-1325 of the control circuit 1303.

[0083] A second (write row line) current source 1326 supplies a current (e.g., control signal En_I WRL When enabled (by setting t to the “1” (i.e., active) state), a write row line current I WRLis enabled by activating a corresponding one of the write row current circuits, e.g., by turning on a corresponding NFET switch 1322, 1324, which may be an entry transistor or an exit transistor. N 13. Activation of the selected NFET switch 1322, 1324 is coordinated by a control circuit 1303 configured to manage the current written to the MJJ 1302. The control circuit 1303 provides row input control signals 1323, 1325 to the write row current circuitry shown as NFET switches 1322, 1324 as previously described.

[0084] A first (global write-column) current source 1328 supplies a current (e.g., control signal En_I WCL When the first current source 1328 is enabled (by setting WCL_T is divided into a current of zero magnitude (i.e., no current flows), a substantially equal positive current, and a substantially equal negative current. In this regard, it is important to note that the positive and negative currents may be of different magnitudes, which is beneficial for reliable writing of the MJJ 1302, given the practical non-ideal magnetic switching characteristics of the MJJ 1302. When the first source 1328 is enabled, the current I WCL_1 From I WCL_M is adjusted by the control circuit 1303 that manages the current written to the MJJ 1302, and the current I WCL_1 From I WCL_M The associated write-column lines WCL1 through WCL M The control circuit 1303 also provides column input control signals 1307, 1309, 1311, 1313, 1315, 1317, 1319, 1321 which are supplied to corresponding write column current input circuits 1306, 1308, 1310, 1312 and write column current output circuits 1314, 1316, 1318, 1320.

[0085] Total write column line current I WCL_T can be determined using the following formula: I WCL_T =WCLN P ×I WCL_P +WCLN N ×I WCL_N Here, I WCL_P represents the positive current component of the write column current, and WCLN P is the positive write column line current I WCL_P The number of I WCL_N represents the negative current component of the write column current, and WCLN N is the negative write column line current I WCL_N is the number of.

[0086] Although the illustrative embodiment (and other illustrative embodiments to be discussed herein) has been generally described, the schematic of the write circuitry 1300 for writing to the MJJ 1302 illustrates symbols for "NFETs" and "shift registers," terms that are most often used to describe the operation of this embodiment, rather than the terms "circuitry" (e.g., the write column current in circuit, write column current out circuit, write row current out circuit, and write column current circuit shown in FIG. 16) or "transistor-based circuitry that manages the current written to the MJJ."

[0087] The control circuitry 1303 managing the write column line currents and the write row line currents comprises, in one or more embodiments, a shift register that can be formed using CMOS technology consistent with known shift register configurations, as would be apparent to one of ordinary skill in the art. The input-limited shift register of the control circuitry 1303 is advantageous because, in one or more embodiments, it can reduce or minimize heat input (i.e., cooling loss) into a refrigerator below 4.2 Kelvin, as compared to other viable alternatives involving limited input signal wires that may connect (provide a path for thermal conduction between) the room temperature and cold regions through an insulating layer. This exemplary embodiment enables bidirectional field application along the easy axis of the MJJ 1302, as well as bidirectional spin torque current supply through the MJJ stack of materials (implied, but not explicitly shown in FIG. 13), and other unique embodied / claimed capabilities, some of which are discussed in more detail below.

[0088] For the purposes of this disclosure, current flowing in a first direction is defined as positive and current flowing in a second direction opposite the first direction is defined as negative, although it should be understood that embodiments of the invention are not limited to any particular assignment of current direction and polarity.

[0089] The column lines (or row lines) can be arranged in a "wrap-around" fashion, and aspects of the present disclosure are well suited for use as shift registers. Given such a "wrap-around" configuration, one skilled in the relevant art will appreciate that the inlet and outlet terminals can be arranged close to one another, and the inlet and outlet transistors can be enabled and disabled in pairs, thereby allowing the transistors associated with the inlet and outlet terminals to be driven with fewer common input control signals (e.g., write column current inlet control input signals 1307, 1309 and write column current outlet control input signals 1319, 1321).

[0090] 14 is a timing diagram illustrating at least a portion of an example timing diagram 1400 of a write method in accordance with one or more embodiments of the present invention. Before discussing the example write method, it is important to note that row input control signals (RICS) and column input control signals (CICS) are abbreviated in the diagram as "RICSes" to indicate multiple RICS signals, "CICS" to indicate a single CICS signal, and "CICSes" to indicate multiple CICS signals. The example write method illustrated in timing diagram 1400 includes the following steps, applied in order, in one or more embodiments: [1] Shifting the RICS and CICS into place for a write operation (step 1402), during which the current sources are disabled (the current sources can be disabled using a switch or other mechanism located anywhere in the conductor path including either the write row line or the write column line), and [2] providing a write current to write to the MJJ (step 1404), during which shift clocks "A" and "B" are disabled (e.g., set to "0"), thereby causing the shifted input control signals to remain constant at a specified voltage or state. As will be apparent to one skilled in the art, the write current can be used to generate a magnetic field or spin torque current for writing to the MJJ.

[0091] The shifting step 1402 may more specifically include providing the input data through the "Shift_In" input (see, for example, FIG. 13) and, on the other hand, providing a pair of "A" and "B" clocks, where each data of the sequence of data used goes through one master-slave latch 1304 (M / S_+) of the shift register 1303 each time the pair of "A" and "B" clocks is provided. Here, the "A" and "B" clocks may be non-overlapping clocks that can be generated from a single clock signal that is sent to the refrigerated domain (e.g., low temperature domain, 4.2 Kelvin) via a single clock wire / source. The non-overlapping clock pulses can be generated from one clock input using delay lines and / or clock choppers, etc., while managing the duration of the input signal pulses overall, as known in the art.

[0092] 13 and 14, with proper timing synchronization of the desired data supply to the shift register of the control circuit 1303 at the "Shift_In" inputs, the row and column input control signals (e.g., write column current in control input signals 1307, 1309 and write column current out control input signals 1319, 1321) are shifted into place within the shift register 1303 by pairs of "A" and "B" clock pulses that correspond in number to the total number of master-slave latches 1304 that collectively form the shift register 1303. It is important to note that, as labeled in timing diagram 1400, the first and last data inputs in time sequence supplied to the shift register 1303 (which has the basic structure shown in FIG. 13) set the input control signals 1307, 1319 that enable or disable the NFET switches 1306, 1318, respectively. In general, all desired input control signals to enable or disable the write row line current circuits 1322, 1324 (e.g., NFETs), the write column current input circuits 1306, 1308, 1310, 1312 (e.g., NFETs), and the write column current output circuits 1314, 1316, 1318, 1320 (e.g., NFETs) can be brought into place by the control circuit 1303.

[0093] In a write operation, the input control signals control the appropriate write currents I, provided by the write row line current source 1326 and the global write column line current source 1328, respectively. WRL and I WCL_1 From I WCL_M Write row lines WRL1 to WRL N and at least one of the write column lines WCL1 to WCL M In a typical write scheme, a current generates a magnetic field that is collectively written to the selected MJJ. In contrast, a π-current-based or spin torque JMRAM cell (spin transfer torque (STT)-based JMRAM cell) uses a write column current to couple a supercurrent to the JMRAM cell itself, for example via a transformer. The JMRAM internal current then couples at least one of a π-phase setting seed current and a spin torque (write row current I) through the selected MJJ as the JMRAM internal current passes through the selected MJJ, as known in the art. WRL This is supplied in combination with the hard axis field (generated by

[0094] For a row, it is preferable to write to a row of superconducting array cells by selecting (i.e., enabling) only one row NFET switch of the row NFET switches (write row current circuit) associated with the row. As an example, in FIG. 13, NFET switch 1322 is enabled (i.e., made conductive) under the following conditions: the source and drain of NFET switch 1322 (connected to the “Out_R” terminal of write row line current source 1326) are held substantially near ground (GND) by write row line current source 1326, and the gate of NFET switch 1322 (connected to output node / tap 1323 of shift register of control circuit 1303) is driven to VDD by control circuit 1303. More specifically, for the entire row circuit, by supplying VDD (where VDD equals logic "1" in CMOS technologies) to the gate of row NFET switch 1322 and GND (where GND equals logic "0" in CMOS technologies) to the gates of other row NFET switches, such as NFET switch 1324, the selected row NFET switch 1322 can be made conductive while all other unselected row NFET switches (e.g., NFET switch 1324) can be made non-conductive, provided that the sources and drains of all NFET switches are held substantially near GND. The write row line current I WRL This causes current to flow through the selected write row line WRL1.

[0095] With respect to the columns, the following discussion assumes that the global write-column line current source 1328 drives the sources and drains of the write column current in NFET switches 1306, 1308, 1310, 1312 and the write column current out NFET switches 1314, 1316, 1318, 1320 to GND (the NFETs are assumed to be highly conductive). Any column input control signal can be provided to the column NFET switches (write column current in and write column current out circuits) associated with the write-column line WCL, although in one or more embodiments, seven switch setting options per write-column line are deemed most desirable.

[0096] By way of example only and not by way of limitation, the seven switch setting options that may be desirable for each write column are as follows for an exemplary write column line 1, WCL1 (for the purposes of broadest generalization here, this example also assumes that WRL1 is set to I WRL (It is assumed that ideal simultaneous magnetic field writing is feasible based on the Stoner-Wohlfarth switching asteroids provided and known in the art). [i] To prepare to write a “1 state” to MJJ_1_1 by supplying positive current 1406 in FIG. 14, (a) set input voltage 1307 of NFET 1306 to VDD, (b) set input voltage 1319 of NFET 1318 to VDD, (c) set input voltage 1315 of NFET 1314 to GND, and (d) set input voltage 1311 of NFET 1310 to GND. [ii] To prepare to supply zero magnitude current 1408 of FIG. 14 to WCL1, (a) set input voltage 1307 of NFET 1306 to VDD, (b) set input voltage 1319 of NFET 1318 to GND, (c) set input voltage 1315 of NFET 1314 to GND, and (d) set input voltage 1311 of NFET 1310 to GND. [iii] To prepare to source zero magnitude current 1408 in FIG. 14 to WCL1, (a) input voltage 1307 of NFET 1306 is set to GND, (b) input voltage 1319 of NFET 1318 is set to VDD, (c) input voltage 1315 of NFET 1314 is set to GND, and (d) input voltage 1311 of NFET 1310 is set to GND. [iv] To prepare to source zero magnitude current 1408 in FIG. 14 to WCL1, (a) set input voltage 1307 of NFET 1306 to GND, (b) set input voltage 1319 of NFET 1318 to GND, (c) set input voltage 1315 of NFET 1314 to VDD, and (d) set input voltage 1311 of NFET 1310 to GND. [v] To prepare to supply zero magnitude current 1408 of FIG. 14 to WCL1, (a) set input voltage 1307 of NFET 1306 to GND, (b) set input voltage 1319 of NFET 1318 to GND, (c) set input voltage 1315 of NFET 1314 to GND, and (d) set input voltage 1311 of NFET 1310 to VDD. [vi] To prepare to supply negative current 1410 to write a "0 state" to MJJ_1_1, (a) set input voltage 1307 of NFET 1306 to GND, (b) set input voltage 1319 of NFET 1318 to GND, (c) set input voltage 1315 of NFET 1314 to VDD, and (d) set input voltage 1311 of NFET 1310 to VDD; and [vii] To completely isolate WCL1 from the “In_C” and “Out_C” nodes and ensure that no transient currents flow (zero magnitude current 1408), (a) set input voltage 1307 of NFET 1306 to GND, (b) set input voltage 1319 of NFET 1318 to GND, (c) set input voltage 1315 of NFET 1314 to GND, and (d) set input voltage 1311 of NFET 1310 to GND.

[0097] While other combinations may occur while shifting data in place through the shift register of control circuit 1303, primarily other combinations may create various current loops, for example through NFET switches 1306, 1314, or NFET switches 1306, 1314, 1318, which do not pass through or only partially pass through WCL1, respectively, so only the previously described settings need be used during step 1404.

[0098] Before turning to a discussion of the write step, it is important to note that in one or more embodiments, the total write column current I provided by the global write column line current source 1328 is WCL_T must be calculated for each write cycle. The total write column current I WCL_T [i] The number of positive write column line currents WCLN, as shown in FIG. P (integer) and the desired positive write column current IWCL_P and [ii] the number of negative write column line currents WCLN N (integer) and the desired negative write column current I WCL_N As will be discussed in more detail herein below, to define the target positive and negative write column currents, first an electrical simulation is performed, then I WCL_T , VDD P , and VDD N It should be understood that experimentation with the particular chip with NFET switches for the write column currents may be required. The write currents can ultimately be tailored to each particular chip.

[0099] In particular, step 1404 of FIG. 14 may include enabling as a function of time (i) the global write-column current source 1328 and (ii) the write-row current source 1326, with the current sources 1328 and 1326 being disabled at all other times, and the enabling and disabling of the current sources 1328 and 1326 being controlled by the inputs En_I WCL and En_I WRL As shown in FIG. 14, the enable signals must overlap for a given period of time, and for high hard axis writing, the write row line current I WRL is the write column line current I that generates the easy axis field. WCL_1 From I WCL_M The write column current I WCL_1 From I WCL_M It is important to note that in one or more embodiments, the current level 1406 may have at least three distinct levels: a positive current level 1406, a zero magnitude current level 1408, and a negative current level 1410.

[0100] The exemplary writing method illustrated in timing diagram 1400 can be used not only in test modes of operation (e.g., during wafer test) and initial program load (IPL) modes of operation, but also in system modes of operation (all modes known to those skilled in the art), such as to redefine Boolean logic functions on the fly for a particular algorithm of interest in a superconducting array circuit (e.g., MJJ-based writing circuit 1300 of FIG. 13, RAM, FPGA, PLA, etc.) and then run on a quantum computing system.

[0101] Fig. 15A is a schematic diagram illustrating an example shift circuit 1500 suitable for use in combination with the example circuit of Fig. 13, in accordance with an embodiment of the present invention. The shift circuit 1500 can be used to implement the example shift circuit 1330 shown in Fig. 13 and includes a master / slave latch (M / S_+) 1304. However, rather than using two series master-slave latches 1304 to form the shift circuit 1330, the example shift circuit 1500 shown in Fig. 15A retains one master-slave latch 1304 but replaces the second master-slave latch with two series-connected inverters 1502 and 1504.

[0102] More specifically, a first input of the master-slave latch 1304 is adapted to receive an input signal Shift_In provided to the shift circuit 1500, and an output of the master-slave latch 1304 is connected to an input of a first inverter 1502. The master-slave latch 1304 further comprises a first clock input configured to receive a first clock signal A and a second clock input configured to receive a second clock signal B. The clock signals A and B may be non-overlapping clock signals, as known in the art, in one or more embodiments. An output of the first inverter 1502 is connected to an input of a second inverter 1504, and an output of the second inverter 1504 generates an output signal Shift_Out of the shift circuit 1500. The first inverter 1502 generates a complementary input control signal, and the second inverter 1504 returns the signal to its original level for the next (i.e., subsequent) shift circuit of the shift register 1303 (see FIG. 13). The inversion between the pair of inlet and outlet NFET switches connected to the ends of a given write-column line ensures that one NFET switch is enabled while the other is disabled. In this manner, a push-pull current operation can be advantageously performed by the NFET switches at both ends of a given write-column line. It is important to understand that the overall current source, in one or more embodiments, does not provide current during a shift operation and is always disabled.

[0103] The output of the master-slave latch 1304 of each of the shift circuits 1330 can generate a first subset of control signals for the control circuit 1303 that are supplied to the corresponding gates of the write column current exit NFET switches (e.g., NFET switches 1314, 1316, 1318, 1320 of FIG. 13). The output of the first inverter 1502 of each of the shift circuits 1330 can generate a second subset of control signals for the control circuit 1303 that are supplied to the gates of the write column current entry NFET switches (e.g., NFET switches 1306, 1308, 1310, 1312 of FIG. 13), and the output Shift_Out of the second inverter 1502 of each of the shift circuits 1330 is connected to the Shift_In input of the subsequent shift circuit 1330 of the control circuit 1303.

[0104] 15B is a schematic diagram illustrating at least a portion of an exemplary shift circuit 1550 suitable for use in combination with the exemplary circuit of FIG. 13, in accordance with an embodiment of the present invention. The shift circuit 1550 includes a first master / slave latch (M / S_+) 1552, a second master / slave latch 1554 connected in series with the first master / slave latch 1552, and at least two master latches (M_+) 1556 and 1558. Specifically, an input of the first master / slave latch 1552 is configured to receive an input signal Shift_In provided to the shift circuit 1550, an output of the first master / slave latch 1552 is connected to an input of the second master / slave latch 1554, and an output of the second master / slave latch generates an output signal Shift_Out of the shift circuit 1550. Each of the first and second master / slave latches 1552 and 1554 includes a first clock input configured to receive a first clock signal A and a second clock input configured to receive a second clock signal B. Clock signals A, B, and C, in one or more embodiments, may be non-overlapping clock signals, as known in the art.

[0105] The first master latch 1556 has a first clock input connected to the output of the first master / slave latch 1552, and the second master latch 1558 has a first clock input connected to the output of the second master / slave latch 1554. Each of the two master latches 1556, 1558 further comprises a second clock input configured to receive a third clock signal D. The output signal generated by the first master latch 1556 of each of the plurality of shift circuits 1550 (1330 of the control circuit 1303 of FIG. 13) is provided to the gate of a corresponding one of the write column current outlet NFET switches (e.g., NFETs 1314, 1316, 1318, 1320 of FIG. 13). Similarly, the output signal generated by the second master latch 1558 of each of the plurality of shift circuits 1550 (1330 of the control circuit 1303 of FIG. 13) is provided to the gate of a corresponding one of the write column current entry NFET switches (e.g., NFETs 1314, 1308, 1310, 1312 of FIG. 13). With the addition of non-overlapping "D" clocks, which may be pulsed only when the correct data pattern has been fully shifted into place, the master latches 1556, 1558 may decouple the shifting function of the shift register 1303 from the driving function of the shift register 1303 (see FIG. 13). The exemplary shift circuit 1550 may thus be configured to reduce the switching power consumption (e.g., switching FET power consumption CV) associated with the potentially large write row current NFETs, write column current entry NFETs, and write column current exit NFETs in accordance with one or more embodiments of the present disclosure. 2 / 2)

[0106] 16 is a schematic diagram illustrating at least a portion of an example write circuit 1600 for a write MJJ (e.g., for a "toggle" MJJ proposed in the art) that allows for application of a field in one selected direction, in accordance with one or more embodiments of the present disclosure. For a toggle MJJ, the total write column current I WCL_TThe magnitude of the write column current I can be adjusted for each write operation since it depends on the existing stored data pattern, which is determined by a read operation issued prior to the write operation. Every superconducting array cell requiring a state change is subjected to a write column current I, as is known to those skilled in the relevant art. WCL The total write column line current I WCL_T can be determined using the following formula: I WCL_T =T×I WCL_P where T is an integer corresponding to the number of superconducting array cells that need to be toggled (i.e., flipped) in a particular write operation, and I WCL_P is previously defined.

[0107] The write circuit 1600 includes a plurality of MJJs 1302, a control circuit 1603 that may include a shift register, and a write row line current I through a selected one of the write row lines. WRL A plurality of write row lines WRL1 to WRL N (where N is an integer greater than 1), a write-column current I WCL_1 From I WCL_M , configured to deliver M (where M is an integer greater than 1), a write row current circuit that may comprise NFET switches 1322 to 1324, and a write column current circuit that may comprise NFET switches 1618 to 1620. Each of NFET switches 1622 to 1624 in the write row current circuit is coupled to write row lines WRL1 to WRL N , and a second end of each of the write row lines is connected to a write row line current source 1626 configured to provide a write row line current to select a given row of MJJs 1302 of the write circuit 1600. Similarly, each of the NFET switches 1618 to 1620 of the write column current circuit is connected to a first end of a corresponding one of the write column lines WCL1 to WCL M, and a second end of each of the write-column lines is connected to a global write-column line current source 1628 configured to provide a write-column line current for writing to a selected MJJ 1302 of the write circuit 1600.

[0108] The example write circuit 1600 of FIG. M 13, which includes both write column current input circuits (e.g., NFETs 1306, 1308, 1310, 1312) and write column current output circuits (e.g., NFETs 1314, 1316, 1318, 1320). Write circuit 1600, in the example shown in FIG. 16, includes write column current output circuits. Specifically, at least a subset of the write column current output circuits each connect to write column lines WCL1 through WCL M 16, each of the write-column lines WCL1 through WCL20 includes an NFET switch, which is one of NFET switches 1618 through 1620, each of which has a first source / drain connected to a first end of a corresponding one of the write-column lines WCL1 through WCL20. M A second end of each of the NFET switches 1618 to 1620 is connected, such as via a first interconnect or bus, to a first terminal of a write-column line current source 1628. A second source / drain of each of the NFET switches 1618 to 1620 is connected, such as via a first interconnect Out_C, to a second terminal of the write-column line current source 1628, which may be ground or another column voltage return, via a second interconnect Out_C. In one or more alternative embodiments, a write column current outlet circuit is provided for the write-column lines WCL1 to WCL M , and a first terminal of the write-column line current source 1628. M It should be understood that the first end of each of the write-column-line current sources 1628 may be directly connected to the second terminal of the write-column-line current source 1628 via the second interconnect Out_C.

[0109] Write circuit 1600 connects write row lines WRL1 to WRL N 16, write row current input circuits or write row current output circuits. Write circuit 1600, in the example shown in FIG. 16, includes write row current output circuits. Specifically, at least a subset of the write row current output circuits each include an NFET switch, which is one of NFET switches 1322 through 1324. Each of NFET switches 1322 through 1324 is coupled to write row lines WRL1 through WCL1. N , and a first source / drain connected to a first end of a corresponding one of the write row lines WRL1 to WRL N A second end of each of the NFET switches 1322 through 1324 is connected via a third interconnect, bus, or the like to a first terminal of a write row line current source 1626. A second source / drain of each of the NFET switches 1322 through 1324 is connected via a fourth interconnect Out_R to a second terminal of the write row line current source 1626, which may be ground or another row voltage return. In one or more alternative embodiments, a write row current outlet circuit is provided for the write row lines WRL1 through WRL N 16, may be replaced by a write row current input circuit connected in series between the second end of each of the write row lines WRL1 through WRL N It should be understood that the first end of each of the write row line current sources 1626 may be directly connected to the second terminal of the write row line current source 1626 via the fourth interconnect Out_R.

[0110] With continued reference to FIG. 16, control signals activating each of the write column current outlet circuits (e.g., NFET switches 1618 to 1620) and the write row current outlet circuits (e.g., NFET switches 1322 to 1324) may be provided by a shift register 1603. The shift register 1603, in this exemplary embodiment, comprises a plurality of master-slave latches (M / S_+) 1304 connected in series between an input of the shift register configured to receive an input signal Shift_In provided to the shift register, and an output of the shift register 1603 configured to provide an output signal Shift_Out. Each of at least a subset of the master-slave latches 1304 may be operated consistent with the description previously presented (e.g., in connection with FIGS. 15A-15B). The gates of each of the NFET switches 1618 to 1620 of the write column current outlet circuits are connected to corresponding outputs 1619 to 1621, respectively, of the master-slave latches 1304 of the shift register 1603. Similarly, the gates of each of the NFET switches 1322 to 1324 in the write row current outlet circuit are connected to corresponding outputs 1323 to 1325, respectively, of the master-slave latch 1304 in the shift register 1603.

[0111] When NFET switches (e.g., 1618 to 1620 and 1322 to 1324) are used in the write column current outlet circuits and the write row current outlet circuits, shift register 1603 is configured to generate a high voltage (e.g., VDD) to activate (i.e., enable or turn on) the switches and a low voltage (e.g., ground or zero) to deactivate (i.e., disable or turn off) the switches. In other embodiments where PFET switches are used, the control signals provided by shift register 1603 may be inverted.

[0112] For a write operation, global write-column line current source 1628 is enabled, which is enabled at least partially simultaneously with the activation of write-row line current source 1626, to generate a total (global) write-column line current IWCL_T represents a current of zero magnitude (i.e., no current flows), and / or I WCL_1 From I WCL_M These currents are regulated by a control circuit (which may comprise a shift register 1603) that provides column input control signals 1619, 1621 that are fed to write column current outlet circuits 1618, 1620 to manage the current written to the MJJ 1302, thereby directing the current to each of the write column lines WCL1 to WCL M The device is configured to flow through

[0113] An embodiment of adjusting at least two magnetic fields according to aspects of the present disclosure is configured to allow application of hard axis and easy axis fields of different magnitudes to an array of MJJs, such that each MJJ in the array can reliably write a first or second logic state, although each MJJ may exhibit non-ideal switching characteristics. The hard axis field is sourced by write row line current source 1626, which provides a current (write row line current I WRL While the easy axis field can be easily tuned directly by adjusting the magnitude of the easy axis field, the easy axis field cannot be tuned directly because both positive and negative easy axis fields of different magnitudes would likely be required to reliably write each MJJ to its first or second logic state. Thus, a key component of a magnetic field tuning embodiment is to achieve positive and negative easy axis fields of different magnitudes while limiting the number of signal or power lines running, for example, from "room temperature" electronics to "cold" electronics.

[0114] FIG. 17 illustrates, by way of example only and not by way of limitation or loss of generality, an example MJJ-based write circuit 1700 (which may be derived from the example write circuit 1300, but may be powered by a separate VDD rail, VDD P , and VDD N17 is a schematic diagram illustrating at least a portion of a write circuit 1300 that includes a hard axis magnetic field and a write column line WCL that are configured to have adjustable magnitudes, as indicated by the size of the currents in the write row line WRL and the write column line WCL.

[0115] In this exemplary embodiment, there are two distinct voltages associated with the write column current NFET switches (i.e., the write column current input circuit and the write column current output circuit), namely, the high voltage VDD P and VDD N where the subscript "P" refers to positive (higher VDD) and "N" refers to negative (lower VDD), although embodiments of the present disclosure are not limited to two particular voltages. When these two voltages are appropriately supplied to the gates of the NFET switches (e.g., NFET switches 1306, 1308, 1310, 1312, 1314, 1316, 1318, 1320) that form the write column current input and output circuits, the gate-to-source and gate-to-drain voltages (V GS and V DS ) can be used, without loss of generality, to adjust the relative magnitudes of the positive column current associated with writing a first logic state (a π state) and the negative column current associated with writing a second logic state (a 0 state) of the MJJ. P is supplied to the NFET switches in the positive column current path (e.g., NFETs 1306 and 1318), and VDD N is supplied to the NFET switches in the negative column current path (e.g., NFETs 1312 and 1316). Other NFET switches associated with the write-column lines can be disabled, such as by setting the appropriate control signal (e.g., 1309, 1311, 1315, 1321) to a zero voltage (ground or GND) supplied to the gates of the corresponding NFETs (e.g., 1308, 1310, 1314, 1320).

[0116] Global write-column line current source 1328 Pand 1328 N The total current I supplied from each of WCL_TP and I WCL_TN can be determined by the following formula: I WCL_TP =WCLN P ×I WCL_P I WCL_TN =WCLN N ×I WCL_N Here at WCLN P , W.C.L.N. N , I WCL_P and I WCL_N is defined previously. As previously stated, the total write column current I WCL_T is shown in FIG. 17. (i) The number of positive write column line currents WCLN P (integer) and the desired positive write column current I WCL_TP and (ii) the number of negative write column line currents WCLN N (integer) and the desired negative write column current I WCL_TN The sum of the products of the magnitudes of

[0117] High voltage supply VDD P and VDD N can be configured to adjust the gate voltage relative to the source and drain voltages of the write column current inlet (or outlet) NFET switches, and can be maintained substantially near ground (GND). As shown in FIG. 17, the voltage VDD P VDD N , the higher the positive write-column line current I 1 (which serves to write the first logic state (π state) to MJJ_1_1) flows through the corresponding write-column line WCL1. WCL_1 is the corresponding write column line WCL M The negative write column line current I flows through WCL_MIt is important to note that the positive and negative write-column line currents are larger as indicated by the larger and smaller arrows for the NFET switches (responsible for writing the second logic state (0 state) to MJJ_1_M), respectively. At steady state, the more conductive positive current path NFET switches (e.g., NFETs 1306, 1318) exhibit less resistance compared to the more resistive negative current path NFET switches (e.g., NFETs 1316, 1312). Thus, the positive and negative write-column line currents will be divided based on the respective conductance of the NFET switches associated with the write-column lines. That is, more current will flow through the write-column line with the least resistive (i.e., highest conductance) NFET switch and less current will flow through the write-column line with the most resistive (i.e., lowest conductance) NFET switch.

[0118] As known to those skilled in the relevant art, differentiating voltages can be incorporated into a circuit by including level shifters.

[0119] With respect to the write row current outlet circuitry configured to select a given row of MJJs to be written to, in this example, an appropriate master-slave latch 1304 in the control circuitry 1303 drives a corresponding control signal 1323 to a high voltage VDD (e.g., VDD P or VDD N ), an NFET switch 1322 associated with write row line WRL1 is selected. N ) is disabled, such as by control circuit 1303 setting the appropriate control signal (eg, 1325) to a low voltage of zero or ground (GND).

[0120] 18 is a schematic diagram illustrating at least a portion of an example MJJ-based write circuit 1800 having example voltages supplied to control inputs of a write column current in circuit, a write column current out circuit, and a write row current out circuit during a write operation, in accordance with one or more alternative embodiments of the present disclosure. More specifically, in FIG. 18, the example write circuit 1800 is configured such that the write column line current source shown in FIG. 18 supplies a positive write column line current I WCL_P A first write column line current source 1828 configured to generate P , and the negative write column line current I WCL_N A second write-column line current source 1828 configured to generate N 13 and 17. The write row line current sources 1326 may be the same as those used in the write circuit 1300 shown in FIG. 13 and 17.

[0121] 18, an exemplary write circuit 1800 is beneficially configured to write selected MJJs 1302 (MJJ_1_1 and MJJ_1_M) to a first logic state (π state) and a second logic state (0 state), respectively, using an alternative arrangement with adjustable hard and easy axis magnetic field magnitudes, as shown. As noted above, modifications from the original write circuit 1300 shown in FIG. 13 for writing MJJs 1302 include splitting the global write-column current source 1328 (FIG. 13) into two current sources (or sets of two current sources), splitting the first global write-column current source 1828 P to source positive current through a selected write-column line (as directed by the shift register of control circuitry 1303) and a corresponding selected NFET switch (e.g., 1306, 1318, 1308, 1320), and a second global write-column current source 1328 Nto source a negative current through a selected write-column line (as directed by control circuit 1303) and a corresponding selected NFET switch (eg, 1314, 1310, 1316, 1312).

[0122] In Figure 18, the total write column positive current I WCL_TP is the number of positive write column line currents WCLN P (integer) and the desired positive write column current I WCL_P and the total negative write column current I WCL_TN Similarly, WCLN is the number of negative write column line currents. P (integer) and the desired negative write column current I WCL_N can be determined as the product of the magnitude of

[0123] It is important to emphasize again that controlling the magnitude of the "1" and "0" write currents can be advantageous in dealing with non-ideal switching asteroids, such as those required in MJJs that do not currently have a synthetic antiferromagnetic layer (SAF) associated with the MJJ's pinned magnet. Within much of the current superconductivity research, such a synthetic antiferromagnetic layer is believed to be unable to be feasibly incorporated into MJJ stacks because it would block supercurrents. The field lines from the pinned domains affect the free domains as demagnetizing or magnetizing forces, causing, for example, a horizontal shift from an "ideal" asteroid 1902 to a "deviated" asteroid 1904, as conceptually illustrated in the exemplary Stoner-Wohlfarth switching asteroid plot shown in FIG. 19.

[0124] Thus, while shown in FIG. 19 as a thin, uniform boundary line conforming to the shape of the asteroid, it is important to understand that the actual shape of the asteroid may vary significantly and / or may be misaligned (relative to the origin of the axes shown in FIG. 19). This variation in the shape and / or misalignment of the asteroid may be due, for example, to environmental conditions (e.g., temperature) (rather than the properties of the underlying pinned layer), variations in the MJJ crystal, and / or variations in processing, among other factors. Variations between individual JMRAM superconducting array cells (and more specifically, the corresponding MJJs of the array cells) in a memory array significantly reduce the write select margin within the entire memory array. For example, non-ideal physical artifacts may obscure the distinction between half-selected and selected MJJ cells, and half-selected MJJ cells may be written to by write operations intended for only selected MJJ cells. FIG. 19 conceptually illustrates and explains how hard axis field and easy axis field points for writing to MJJ_1_1 and MJJ_1_M can be positioned around a displaced asteroid 1904 using circuitry for writing to MJJs 1300, 1800, with example currents shown in FIGS. 17 and 18, respectively.

[0125] Because of the very significant differences between CMOS circuitry and superconducting electronic circuitry, with CMOS being over 1000 times denser, it is believed that all of the hard and easy axis field information needed to write (i.e., program) the MJJs in a particular chip from a particular wafer could be stored in "room temperature" electronic circuitry such as flash technology. Assuming that environmental factors such as temperature do not change, a write circuit according to an embodiment of the present disclosure can reliably write the MJJs accurately.

[0126] FIG. 20 is a schematic diagram illustrating at least a portion of an exemplary MJJ-based write circuit 2000 for writing to an MJJ in accordance with one or more embodiments of the present invention. The write circuit 2000 is beneficial because it provides a clockwise or counterclockwise π-phase setting seed current (or alternatively allows for application of a bidirectional easy axis field in the plane of the MJJ, or a bidirectional spin torque current) to a superconducting loop of the memory circuit through the MJJ stack of material via an inductor associated with the memory cell, as described in more detail below (details of the memory cell are not explicitly shown in FIG. 20). The write circuit 2000 can be used to “program” the MJJ, which can function as a memory element acting as a programmable switch in a Josephson Magnetic Programmable Logic Array (JMPLA), as described, for example, in U.S. Pat. No. 6,399,323, the disclosure of which is incorporated herein by reference in its entirety, and for other programmable circuit functions in a superconducting field programmable gate array (FPGA), among other applications.

[0127] Write circuit 2000 comprises a plurality of memory circuits 2002 arranged in a plurality of write columns A through Z, although embodiments of the present invention are not limited to a particular number of write columns. Memory circuits 2002 in each of write columns A through Z may be further divided into one or more write-column lines 1 through M, where M is an integer greater than 1, and each write-column line comprises a plurality of memory circuits 1 through N, where N is an integer greater than 1. Each of memory circuits 2002 may be labeled according to the unique row and write-column line with which it is associated. Thus, for example, memory circuit 2002 in write column A, row 1, write-column line 1 may be labeled as memory circuit A. <1> <1> The memory circuit of write column A, row N, and write column line M can be expressed as follows: <n> <m>Similarly, the memory circuit 2002 in write column Z, row 1, and write column line 1 can be expressed as memory circuit Z <1> <1> The memory circuit of write column Z, row N, and write column line M can be expressed as memory circuit Z <n> <m>It can be expressed as:

[0128] The write circuit 2000 further comprises a plurality of (Bi)CMOS switches, which in one or more embodiments may include NFETs 2014 and 2016. A From 2014 Z Each NFET 2014 is connected to a corresponding one of write columns A to Z. A From 2014 Z More specifically, the NFET 2016 includes a first source / drain connected to a first terminal of a write current source 2020 via a first interconnect In_Out1, a second source / drain connected to first ends of a plurality of column lines 1 to M associated with a corresponding one of the write columns, and a plurality of control signals 2016 provided to the NFET. A From 2016 Z , respectively. A second end of each of the write-column lines for each of the write columns A through Z is connected through a series-connected resistor 2018 or other resistive element (e.g., a wire) to a second terminal of a write current source 2020 via a second interconnect In_Out2. The write current source 2020, in one or more embodiments, provides a bidirectional write current I Column_Source The device is configured to supply

[0129] The write circuit 2000 is configured to write only one memory circuit 2002 at a time in this exemplary array-like embodiment shown in FIG. 20. For illustration only and without loss of generality, a selected memory circuit A is written to illustrate the operation of the write circuit 2000. <1> <1> A write operation to the memory circuit is illustrated using a dashed box that surrounds the memory circuit. Within the dashed box is the write line segment current I WLS , and the magnetic field H of the write line segment generated by the current in the write line segment. WLS Also shown is a write line segment current passing through write line segment WLS 2024 and acting on MJJ 2022 of the "selected" memory cell (specifically, generating a hard axis field in the preferred embodiment). <1> <1> To select NFET2014 A A high voltage (e.g., VDD) control signal 2016 is supplied to the gate of A NFET2014 A Activate (i.e., turn on) the memory circuit A <1> <1> Write line segment current I WLS preferably generates a hard axis magnetic field that can select memory cells for a write operation, which is consistent with (i) the relative orientation of the WLS 2024 and MJJ 2022, (ii) FIG. 8 (incorporation of FET 812 as disclosed herein to selectively write to memory cells), and (iii) U.S. Pat. No. 6,399,633.

[0130] Each of the write-column lines 1 through M in each of the write columns A through Z is preferably configured to deliver a write current to write a state to the memory circuit 2002, which in some embodiments may be arranged to pass through a transformer in each of at least a subset of the memory cells 2002. Recall from discussion of the exemplary memory circuit 800 shown in FIG. 8 that the transformer 806 of the exemplary memory circuit 800 may receive a clockwise or counterclockwise π-phase setting seed current and induce a proportional secondary current to set a clockwise or counterclockwise π-phase current in the superconducting loop of the memory circuit 800. Each of at least a subset of the memory circuits 2002 may comprise the example memory circuits 800 of FIG. 8 connected in series along the write column lines of the write circuit 2000 by connecting each second terminal “In_Out_2_Spin_Torque_&_π-phase” of the memory circuits 800 to each first terminal “In_Out_1_Spin_Torque_&_π-phase” in the example write circuit 2000 of FIG. 20 , except at both ends of the write column lines, where the columns of memory circuits 2002 are connected to FETs 2014 at the first ends of the write column lines WCL and resistors 2018 at the second ends of the write column lines WCL to set a clockwise or counterclockwise π-phase current in the superconducting loop of each memory circuit 2002, and in particular a “selected” one of the memory circuits 2002.

[0131] The memory circuit 800 may require modification for use with the write circuit 2000 in some embodiments. For example, to accommodate the write operation described in U.S. Pat. No. 6,399,633, the orientation of the write line segment (WLS) relative to the long axis of the elliptical MJJ may be modified such that the write line segment 2024 is parallel (i.e., 0 degrees) to the long axis of each MJJ 2022 of the memory circuit 2002, as shown in FIG. 20. With this modification, a current delivered by the write line segment WLS can apply a hard axis field to a selected MJJ to place the MJJ in a 0 state, which for the particular design of this particular MJJ can be achieved when the magnetic layers of the MJJ are aligned parallel (note that in previous examples, the 0 state of the MJJ of the previous example had an antiparallel magnetic layer orientation and thus the MJJ of the previous example had a different design known in the art). This approach of US Pat. No. 6,299,336 relies on the properties of superconducting circuits and is significantly different from the MTJ MRAM-like schemes first proposed for MJJ-based MRAMs, where the state is encoded in the magnetic orientation of the MJJ. The MJJs must be in an antiparallel orientation, which is the π state of the MJJ, in the ground state of this system. Advantageously, the write circuit 2000 provides better read and write margins than conventional MJJ write schemes.

[0132] It should be understood that memory circuits 2002 need not be located at every intersection of a unique row and column pair in this, and other exemplary embodiments. Furthermore, the terms "row" and "column" lines are used to imply at least intersecting lines, regardless of whether they may be orthogonal at any location. It should also be understood that the terms "row" and "column" are intended merely to convey relative location. For example, by rotating the circuit by 90 degrees, a "row" can become a "column."

[0133] 20, at least a subset of the memory circuits 2002 of the write circuit 2000 may, in one or more embodiments, each control a write line segment current I delivered on a corresponding write line segment WLS 2024 to write (or, more specifically, to select to write, in a preferred embodiment) at least one corresponding MJJ 2022 (e.g., MJJ 810 of FIG. 8) per memory circuit (e.g., arranged to correspond to NFET 812 shown in FIG. 8, as previously described). WLS Specifically, the write line segment current I WLS A first terminal of a second current source (not explicitly shown in either FIG. 8 or FIG. 20, but rather shown as current source 106 in FIG. 1) configured to generate <1> <1> Memory Circuit Z from 2002 <n> <m>2002 to a first end of each write line segment (e.g., WLS 2024) associated with the WLS 2002. The second current source (e.g., current source 106 in FIG. 1) may comprise a single current source or multiple current sources, and the current I generated by the second current source W and / or current I W At least one control signal, En_I in FIG. W Each of the NFET switches associated with the write line segments of a respective memory circuit 2002 comprises a first source / drain connected to the second end of a corresponding one of the write line segments, a second source / drain connected to a second terminal of the second current source (e.g., terminal In_Out_2 of FIG. 1 ), and a gate adapted to receive one or more control signals.

[0134] A second (write line segment) current source (e.g., current source 106 in FIG. 1 and therefore not shown) is supplied with a write operation (e.g., control signal En_I W When the write segment line circuit is enabled (by setting the write segment line circuit to a “1” (i.e., active) state), the write segment line circuit is enabled by activating a corresponding one of the write segment line circuits, for example by turning on a corresponding NFET switch (812 in FIG. 8) of memory circuit 2002. <1> <1> Memory Circuit Z from WLS 2002 <n> <m>A write line segment current I of a predetermined amplitude is applied through a selected one of the write line segments to the WLS of 2002. WLS flows.

[0135] A current source 2020 (for the global write-column line) is asserted for a write operation (e.g., control signal En_I Column_Source ) and current source 2020 generates the write line segment current I WLS ) becomes effective simultaneously (or nearly simultaneously) with the activation of the second current source (which supplies WCL_T is the effective (Bi)CMOS switch / NFET circuit (e.g., NFET2014 in Figure 20). A ) are split into substantially equal positive currents (or substantially equal negative currents) in each write column line associated with the first and second current sources. In this regard, it is important to note that the positive and negative currents may be of different magnitudes (since each memory circuit 2002 may be written with different currents provided by the first and second current sources), which may be beneficial for reliably writing the MJJ in the memory cell 202, given the actual non-ideal magnetic switching characteristics of the MJJ. When the first source 2020 is enabled, the current I Column<1> From I Column <m>< / m> For a write operation, a selected single memory circuit 2002 (i.e., memory circuit <1> <1> 2002)) in the selected MJJ, one magnetic field (H WLS ) to manage the current written in,(Bi)CMOS switch / NFET circuit 2014 A From 2014 Z Control Signals 2016 A From 2016 Z The currents are adjusted by the associated multiple column lines, <1> From column line <m>It will flow through.

[0136] Total column current I Column_Line_T can be determined using the following formula: I Column_Line_T =WCLN×I Column where WCLN is the positive (or negative) flowing write column line current I associated with each write column (e.g., A to Z). WCL is the number of I Column represents the positive (or negative) current component of the write column line current. Column_Line_T are divided into substantially equal column currents I by the presence of resistors 2018 (which serve to "split" the current equally, as is known in the art of superconducting electronic circuits). Column (i.e., I Column<1> From I Column <m>< / m> These column currents in turn induce a π-phase setting current by the action (induction) of the transformer in each memory circuit 2002.

[0137] As described with respect to Figure 1, the MJJs associated with a corresponding memory circuit 2002 (e.g., memory circuit 800) can be selected one at a time from the entire set of MJJs for a write operation. In the write circuit 2000 shown in Figure 20, the gate voltages of each NFET 812 of each memory circuit 800 of Figure 8 and each NFET 2014 of Figure 20 are A From 2014 Z The gate voltages of the MOS transistors can be controlled by a shift register. These gate voltages are respectively (I WLS ) to select the memory cell, and (I Column The memory cell then receives a current (by applying a voltage across it) that goes where it needs to go to transfer the state of the memory cell.

[0138] Memory Circuit A <0> <0> 8) by driving the gate of the NFET high while holding all other gates of memory circuit 2002 low, this embodiment of memory circuit 800 of FIG. 8, in combination with write circuit 100 of FIG. 1, sends a hard axis write line segment current IWLS (which generates a hard axis field HWLS) to power the entire array of memory circuit 2002 (here memory circuit A <1> <1> From memory circuit Z <n> <m>2002 (here, memory circuit A <1> <1> Column current IColumn is supplied to a selected memory circuit 2002 (e.g., memory circuit A <1> <1> ) to set the state of the memory circuit. <1> <1> From memory circuit A <n> <m>) without affecting the state of other memory circuits.

[0139] 21 is a flow diagram illustrating at least a portion of an exemplary method 2100 for writing to a memory circuit, in accordance with one or more embodiments of the present invention. It should be noted at the outset that the arrows illustrated in FIG. 21 are intended to define the flow between steps of the exemplary method 2100, and may include continuous / stream flows 2120, 2122, 2124, 2126, and branches 2128, 2130, 2132. The exemplary method 2100 includes the following steps:

[0140] Step 2101: Select at least one memory circuit from a set of memory circuits for which initialization can be performed and for subsequent writing.

[0141] STEP 2102: For a write operation, move (Bi)CMOS control signals into place to select at least one memory circuit.

[0142] STEP 2104: Provide at least one current (eg, by providing write current 1404 of FIG. 14) to write at least one state to the selected at least one memory circuit.

[0143] Step 2106: Reading the at least one memory circuit using a superconducting circuit of the memory circuit and transferring the at least one read result to another thermal layer (eg, room temperature).

[0144] Step 2108: Verify that the stored state of the at least one memory cell is the at least one state in question. If so (pass), proceed to final step 2110 if the at least one memory cell was the last memory cell intended for the write operation, otherwise return to step 2102 to select the next at least one memory cell for writing. If not so (fail), proceed to step 2110.

[0145] Step 2110: Failure option, and

[0146] Step 2112: One or more entities are ready for operation.

[0147] Depending on the number of failures recorded for this particular entity, or entities, the failure options, which are effectively step 2110, can be: [i] performing a retry; [ii] completely disabling the entity's functionality; and / or [iii] performing other retries with various adjustments to the hard and easy axis fields.

[0148] Upon reaching step 2112, one or more entities, for example a JMPLA or Josephson Magnetic FPGA, both with MJJs, are ready for operation and can therefore perform their newly defined functions in a broader system environment, such as those defined for a controller of a quantum computer system.

[0149] It is contemplated that built-in self-test (BIST) may also be used as an alternative to at least some of steps 2106 through 2112.

[0150] High performance single row parallel write operations (preferred embodiment for use in e.g. RAM or content-addressable memory (CAM)) Write operations to memory arrays often require parallel use of data over a single write cycle. The data for each cycle is not shifted in place; the data is generated elsewhere and sent to the memory array at nearly the same time.

[0151] A read operation of a MJJ memory circuit / cell may require only the JJ, MJJ, transformer, and superconducting wires. For example, a current-hungry write operation of a superconducting MJJ-based RAM or MJJ-based CAM can benefit from the incorporation / addition of selected (Bi)CMOS circuits arranged as follows:

[0152] i) A first preferred write circuit approach may implement (a) row (word line) write circuits in (Bi)CMOS circuits and (b) column (bit line) write circuits in superconducting circuits. This preferred approach, among other things, utilizes current generated by the (Bi)CMOS write circuits to select a row (word line) of memory cells for a write operation. This approach is preferred over alternative (ii) discussed below because only one row line (word line) delivers the selection current per write operation. The significant power consumed by the entire row circuit, primarily the power consumed in the row lines, is the product of the row current (e.g., 2mA to 20mA) required to achieve / realize / deliver a particular magnetic field strength on each MJJ, the voltage (e.g., 200mV to 2V) applied across the row circuit, the duration of the current supplied (e.g., 5ns to 40ns), and the frequency (average utilization) of write operations to the RAM (e.g., 1MHz, by design to keep the write workload low). It is known that generating enough magnetic flux to drive the word lines (magnetic fields) is a major challenge for superconducting circuits, both in terms of (a) the circuit area consumed to store the magnetic flux in a large inductor, and (b) the recovery time (e.g., tens of microseconds) of the flux pump for a subsequent RAM write operation. The column line write circuitry, as known in the art, can remain a superconducting circuit, since significantly fewer flux quanta are required for each write operation (e.g., the write operation of U.S. Pat. No. 6,399,433 needs to supply column currents, which range from 10 microamps to 200 microamps).

[0153] ii) A second write circuit approach can be implemented using both row (word line) and column (bit line) write circuits that are (Bi)CMOS circuits in order to reduce the superconducting circuit area and to provide finer control over the amplitude of the write current through the (Bi)CMOS circuits.

[0154] In one or more preferred embodiments of the present invention, the first write technique (i) can be accommodated by a superconducting column write circuit of the memory array that can provide the bidirectional current necessary to accommodate a write operation of the memory array. Alternative superconducting column write circuits include (i) US Pat. No. 6,399,633, the disclosure of which is incorporated herein by reference in its entirety, and (ii) a combination of US Pat. No. 6,399,633, the disclosure of which is incorporated herein by reference in its entirety, and US Pat. No. 6,399,633, the disclosure of which is incorporated herein by reference in its entirety. The former (i), as employed in FIG. 23A among others, can distribute bus signals to multiple instances of superconducting circuits (adapted to sink and / or source current during operation), whereas the latter (ii), as employed in FIG. 23B, requires wraparound bit lines and may require modifications to the read path circuitry to ensure Boolean consistency between stored and retrieved data, as described by Reohr.

[0155] Figure 22 is an exemplary prior art memory circuit, which is preferred as it can be utilized and incorporated into subsequent Figures 23A, 23B, 24, and 25. The read and write operations of this memory circuit are described in U.S. Patent Nos. 5,993,333 and 5,943,223, respectively, the disclosures of which are incorporated herein by reference in their entireties.

[0156] The integrated write circuit of the exemplary MJJ based memory cell / circuit 2200 includes a transformer 2206, a MJJ 2210, and first and second write lines that can be oriented toward write row and write column lines, respectively, for purposes of subsequent Figures 23A, 23B, 24, and 25. A first terminal of the first write line can be connected to a first interconnect terminal In_Out_2_Magnetic_Field, and a second terminal of the first write line can be connected to a second interconnect terminal In_Out_1_Magnetic_Field through a write row line that passes near the MJJ 2210 to write the state of the MJJ. A first terminal of the second write line can be connected to the first interconnect terminal In_Out_1_πPhase_Setting, and through a write row line that passes through transformer 2206 to write the state of the MJJ and is connected to a second terminal of the first write line, and the second terminal of the first write line can be connected to the second interconnect terminal In_Out_2_πPhase_Setting.

[0157] Hereinafter, the relative orientation of the write row line and each MJJ in the preferred embodiment is defined by the following icons: WRL 2 324 and MJJ 2 322 (in FIG. 23A), WRL 2 374 and MJJ 2 372 (in FIG. 23B), WRL 2 424 and MJJ 2 422 (in FIG. 24), and WRL 2 524 and MJJ 2 522 (in FIG. 25). Similarly, WLS 2 024 and MJJ 2 022 (in FIG. 20) are illustrated. The write row line WRL generates a hard axis field for the selected row of MJJs through the write row line current I WRL Deliver these icons.

[0158] FIG. 23A is a schematic diagram illustrating at least a portion of an exemplary write circuit 2300 for writing to a MJJ that may be embedded in a superconducting memory cell and that uses a mixed superconducting and (Bi)CMOS write circuit, according to one or more embodiments of the present disclosure. To aid in understanding this exemplary embodiment, by way of illustration only and not by way of limitation or loss of generality, the conductor currents and exemplary NFET gate voltages associated with an active mode of the write circuit 2300 are illustrated in FIG. 23A. Unlike the exemplary write circuit 2000 illustrated in FIG. 20, if the column currents were ideally identical in sign and magnitude, the column write line currents generated by the write circuit 2300 of FIG. 23A, as well as the exemplary write circuits illustrated in FIGS. 23B, 24, and 25, according to one or more embodiments, may be positive (i.e., a first direction) or negative (i.e., a second direction) depending on the state being written to each memory cell of a series of selected memory cells. However, it should be understood that embodiments of the present invention are not limited to any particular assignment of current direction and polarity.

[0159] The write circuit 2300 is advantageous because it allows for the application of a clockwise or counterclockwise π-phase setting seed current (or alternatively allows for the application of a bidirectional easy axis field in the plane of the MJJ, or alternatively allows for the application of a bidirectional spin torque current) to the superconducting loop of the memory circuit through the MJJ stack of material via a transformer (e.g., transformer 2206, the column line connections being formed accordingly) or other coupling elements associated with the memory circuit, as described in further detail below. The write circuit 2300 can be used to "write" or "program" the MJJ, which can function as a memory element in JMRAM and JMPLA, for example, as described in U.S. Patent No. 6,399,992, the disclosure of which is incorporated herein by reference in its entirety, among other applications, and can also function as a memory cell for other programmable circuit functions in a superconducting FPGA.

[0160] Continuing to refer to FIG. 23A, the write circuit 2300 includes a plurality of memory cells 2302, <1> <1> From memory cells <n> <m>a plurality of memory cells, where N and M are integers; at least one (Bi)CMOS row write circuit 2304; a superconducting column write circuit 2306 comprising first and second elements; and a plurality of write row lines, WRL1 to WRL2, connected to the row write circuit 2304 and arranged in a row (i.e., horizontal) direction, WRL1 to WRL3, M and a plurality of write-column lines, WCL1 to WCL2, connected to the column write circuit 2306 and arranged in the column (i.e., vertical) direction. M In this configuration, each memory cell 2302 to be written to can have at least one MJJ, and the (Bi)CMOS row write circuit 2304 connects write row lines WRL1 to WRL N The write row line current I delivered by a selected one of WRL The write-column lines WCL1 through WCL M A first element of a superconducting column write circuit 2306 that can be connected to a bottom end of each of the write-column lines, and a second element of a superconducting column write circuit 2306 that can be connected to an upper end of each of the write-column lines, are generally designated by write-column lines WCL1 through WCL M Multiple write-line supercurrents I delivered by WCL_1 From I WCL_M . It is contemplated that multiple write column lines may be associated with each column of memory cells 2302, i.e., memory cells 2302 may require multiple column inputs to complete a write operation for selection or state determination. Similarly, multiple write row lines may be associated with each row of memory cells 2302, i.e., memory cells 2302 may require multiple row inputs to complete a write operation for selection or state determination.

[0161] Write-column lines 1 to M (WCL1 to WCL M ) is supplied with a write column line current I WCL_1 From I WCL_M 22. In some embodiments, the transformer 2206 of the exemplary memory circuit 2200 can be configured to deliver a clockwise or counterclockwise π-phase setting seed current and induce a proportional secondary current to set a clockwise or counterclockwise π-phase current in the superconducting loop of the memory circuit 2200. In the example write circuit 2300 of FIG. 23A, each of at least a subset of the memory cells 2302 may comprise the example memory circuits 2200 of FIG. 22 connected in series along a given write column line of the write circuit 2300, for example, by connecting the second terminals “In_Out_2_π-Phase_Setting” of the memory cells 2200 (FIG. 22) to the first terminals “In_Out_1_π-Phase_Setting” of the memory cells 2200, except at both ends of the write column line, where the column line of the memory 2302 thus formed is connected at a first end to a second element of the superconducting column write circuit 2306 and at a second end to a first element of the superconducting column write circuit 2306 along the given write column line WCL, in order to specifically set a clockwise or counterclockwise π-phase current in the respective superconducting loop of a “selected” one of the memory cells 2302.

[0162] The first and second elements of the superconducting column write circuit 2306 are connected to a write column line current I WCL_1 From I WCL_M and collectively act to classify each of the column line currents as negative or positive, which patent application is incorporated herein by reference in its entirety. Each of the data preferably defines the sign (i.e., direction) of current flow in the corresponding column. The data is provided to both the first and second elements of the superconducting column write circuit 2306, where the data triggers portions of the superconducting circuit into voltage states, as known in the art, that drive each of the write column lines WCL1 to WCL M Note that each of the electrodes diverts and directs the current along a specific path that defines the sign of the current delivered.

[0163] The column current, in one or more embodiments, can induce a clockwise or counterclockwise π-phase setting seed current in the superconducting loop of the memory cell 2302. The superconducting bidirectional driver described in US Pat. No. 6,399,633 is not identical in its internal function to a (Bi)CMOS push-pull circuit, but performs a similar overall function as a push-pull circuit: it drives a positive or negative current (i.e., in a first or second direction) based on the input data signal.

[0164] A (Bi)CMOS row write circuit 2304, in one or more embodiments, writes the memory cells 2302 for a write operation. <1> <1> from <n> <m>To select a row, write row lines WRL1 through WRL N Which of the write row line currents I WRL The present invention may include multiple NFET switches 2312 or alternative switch elements configured to selectively control which NFET current switch 2312 delivers the write row line current I through the selected write row line. In one or more embodiments, only one NFET current switch 2312 is enabled during a given write cycle to deliver the write row line current I through the selected write row line. WRL Send.

[0165] A voltage source V that can be a regulated voltage source Regulated 2305 is connected to each of the write row lines WRL1 to WRL N , while a (Bi)CMOS row write circuit 2304 comprising an NFET 2312 can be connected to the first end of each of the write row lines WRL1 to WRL N is connected to the second end of the voltage source V Regulated 2305 represents, in one or more embodiments, the write row line current I delivered to the write row line. WRL Each of the NFETs 2312 can be configured to control the amplitude of the write row lines WRL1 to WRL N a first source / drain connected to a second end of a corresponding one of the inputs, a second source / drain connected to a voltage source which may be ground (GND), and a gate adapted to receive a corresponding one of a plurality of control signals generated by the (Bi)CMOS write address decoder 2308.

[0166] The write circuit 2300 may further include a conversion circuit 2310 configured to convert the superconducting signal to a (Bi)CMOS signal suitable for use in the (Bi)CMOS write address decoder 2308. In one or more embodiments, a Suzuki stack in the conversion circuit 2310 may be used to convert the superconducting signal to a (Bi)CMOS signal. Suzuki stacks are known in the art and will not be described in detail herein. Such a converted (Bi)CMOS signal (labeled "encoded write address" in FIG. 23A ) that interfaces directly with the (Bi)CMOS write address decoder 2308 (and / or the (Bi)CMOS row write circuit 2304, which is implied but not explicitly shown) may include, for example, (i) a write row line current I WRL (ii) a write timing trigger to shape the write column line current I WCL_1 and I WCL_M The write row line current I WRL Included may be (iii) a write timing trigger for enabling the write operation of the superconducting to (Bi)CMOS conversion circuit 2310, as well as (iv) an address signal for selecting a particular row, which is preferably "encoded" to reduce the size of the superconducting to (Bi)CMOS conversion circuit 2310, as described above.

[0167] A (Bi)CMOS write address decoder 2308, as known in the art, couples write row lines WRL1 through WRL N Write row line current I WRL A "hot" signal, which is set to a high voltage such as VDD (described above), and a "cold" signal, which is set to a low voltage such as GND (described above), can be generated to respectively enable and disable the corresponding NFET 2312 to deliver a write row line current I WRL The remaining write row lines WRL2 through WRL N 2312 corresponding to these unselected write row lines are disabled by application of a gate voltage GND, so that they do not deliver any write row line current.

[0168] Addresses and time triggers (clock signals) associated with a write operation can be passed through conversion circuitry 2310, which can provide bit conversion ranging from substantially serial to substantially parallel. Substantially serial bit conversion can significantly reduce the area of ​​the superconducting die associated with a Suzuki stack.

[0169] It should be appreciated that the row and write-column line currents can be used to induce a superconducting current in the memory cell 2302, such as through a transformer (e.g., transformers 806 and / or 808 in FIG. 8), or can directly couple a magnetic field to the MJJ of the memory cell 2302. While not intended to be limiting, the write-row line current I delivered along the write row line WRL1 shown in FIG. WRL The magnetic field H generated by WRL is the magnetic field H WRL This is useful to illustrate one embodiment in which the MJJ is directly coupled to the MJJ.

[0170] The (Bi)CMOS write address decoder 2308 and row write circuit 2304 can provide a significant reduction in chip area in a mixed (Bi)CMOS and superconducting chip / die implementation compared to an implementation using only superconducting circuitry in a superconducting chip / die, primarily due to (a) the significantly better scaling of (Bi)CMOS circuit area compared to superconducting circuitry (e.g., greater than 500 times area reduction) and (b) the ability to place the (Bi)CMOS circuitry underneath the superconducting circuitry on the chip / die.

[0171] 23B is a schematic diagram illustrating at least a portion of an example write circuit 2350 for writing to a MJJ that may be embedded within a superconducting memory cell and that uses a mixed superconducting and (Bi)CMOS write circuit in accordance with one or more embodiments of the present disclosure. The write circuit 2350 includes a plurality of memory cells 2352, <1> <1> from <n> <m>23A, except that it uses wrap-around write column and write row lines that pass above and below each of the memory cells, and each of the memory cells includes at least one MJJ.

[0172] Specifically, a superconducting column write circuit 2356 provided in the write circuit 2350 supplies a write column line current I WCL_1 From I WCL_M , and classifies each of the write column line currents as negative or positive, indicating the assigned direction of the write column line current flow for the corresponding write column line, as described, for example, in U.S. Pat. No. 6,353,993. Each of the data provided to the superconducting column write circuit 2356 can define the sign of the current for a particular write column line. Each write column line current I WCL 23A , can be fed from and returned to the same superconducting column write circuit 2356. This functionality is achieved through the use of write-column line wraparound connections 2364, each configured to connect an adjacent pair of even and odd write-column lines.

[0173] The write column line current, in one or more embodiments, can induce a clockwise or counterclockwise π-phase setting seed current in the superconducting loop of memory cell 2352. A superconducting bidirectional driver is not identical in its internal function to a (Bi)CMOS push-pull circuit, but performs a similar overall function of being able to drive a negative or positive current (in a first or second direction) depending on the input data signal.

[0174] A given write row line, such as WRL1, in the example write circuit 2350 of FIG. 23B, has a write row line current I WRL_Over_MJJs and I WRL_Under_MJJs , and these write row line currents are in fact the same currents seen at different locations along a given write row line, and the memory cells associated with write row line WRL1 <1> <1> from <1> <m>2352, etc. Using this wrap-around topology for the write-column lines increases the magnetic field coupled into the MJJs (e.g., effectively doubles the magnetic field coupled into each memory cell). Write circuit 2350 includes a modified (Bi)CMOS row write circuit 2354 to achieve this topology.

[0175] The modified (Bi)CMOS row write circuit 2354, similar to the row write circuit 2304 shown in FIG. 23A, preferably includes a plurality of NFET switches 2362 or alternative switch elements, which are coupled to write row lines WRL1 through WRL2, respectively, which are “upper and lower” write row lines. N Which of the write row line currents I WRL_Over_MJJs and I WRL_Under_MJJs In one or more embodiments, only one NFET current switch 2362 is enabled during a given write cycle to deliver a write row line current I through a selected write row line. WRL_Over_MJJs and I WRL_Under_MJJs However, unlike the row write circuit 2304, the regulated voltage source V Regulated is integrated into the row write circuit 2354. Therefore, in the (Bi)CMOS row write circuit 2354, the write row line current I WRL_Over_MJJs and I WRL_Under_MJJs is supplied by a regulated power supply and returned to ground GND.

[0176] 24 is a schematic diagram illustrating at least a portion of an exemplary mixed superconducting and (Bi)CMOS write circuit 2400 in accordance with another embodiment of the present disclosure. The write circuit 2400 includes a plurality of memory cells 2402, memory cells 2403, and the like, similar to the exemplary write circuit 2300 illustrated in FIG. <1> <1> From memory cells <n> <m>a plurality of memory cells, where N and M are integers; at least two (Bi)CMOS row write circuits 2404 and 2405; a superconducting column write circuit 2406 comprising first and second elements; and a plurality of write row lines, WRL1 to WRL2, connected to the (Bi)CMOS row write circuit 2404 and arranged in a row (i.e., horizontal) direction, WRL1 to WRL3, M and a plurality of write-column lines, WCL1 to WCL2, connected to the column write circuit 2406 and arranged in the column (i.e., vertical) direction. M In this configuration, each memory cell 2402 to be written to can have at least one MJJ, and the (Bi)CMOS row write circuits 2404, 2405 collectively connect the write row lines WRL1 to WRL N The write row line current I delivered by a selected one of WRL Having row write circuits 2404, 2405 connected to both ends of the write row lines provides the ability to disconnect the unselected write row lines, which advantageously reduces current surges on the unselected write row lines of write circuit 2400.

[0177] The first and second elements of the superconducting column write circuit 2406 collectively connect the write column lines WCL1 to WCL M The multiple write-column supercurrents I WCL_1 From I WCL_M . It is contemplated that multiple write column lines may be associated with each column of memory cells 2402. That is, memory cells 2402 may require multiple column inputs to complete a write operation to select or establish a state. It is understood that the first and second elements of the superconducting column write circuit 2406 may be configured consistent with the superconducting column write circuit 2306 shown in FIG. 23A.

[0178] Each of the (Bi)CMOS row write circuits 2404, 2405 may include multiple NFET switches 2412 or alternative switch elements. N Each of the row write circuits 2404, 2405 is preferably connected at a first end to a first one of the row write circuits (e.g., 2404) and at a second end to a second one of the row write circuits (e.g., 2405). A pair of corresponding NFETs 2412 in the first and second (Bi)CMOS row write circuits 2404, 2405 function together to provide a single NFET 2412 for the write row lines WRL1 to WRL N Which of the write row line currents I WRL , and is configured to control the direction of the write row line current.

[0179] More specifically, each of the NFETs 2412 in the first and second (Bi)CMOS row write circuits 2404, 2405 is coupled to write row lines WRL1 to WRL N , a second source / drain connected to a voltage source, which may be programmable, and a gate adapted to receive a corresponding one of a plurality of control signals generated by a corresponding (Bi)CMOS write address decoder 2408, where the first ("left") (Bi)CMOS write address decoder is configured to generate a first subset of control signals provided to the first row write circuit 2404 and the second ("right") (Bi)CMOS write address decoder is configured to generate a second subset of control signals provided to the second row write circuit 2405. The first and second subsets of control signals work in conjunction with each other to enable or disable pairs of NFETs in the first and second row write circuits 2404, 2405 associated with the same write row line. The voltage provided to the second source / drain of each of the NFETs 2412, in one or more embodiments, controls the write row line current I WRL 24. The amplitude and direction of the MJJs can be controlled separately so that they can be optimized according to the characteristics of the individual MJJs of each memory cell 2402 being written to.

[0180] By way of example only and not by way of limitation, for a corresponding pair of NFETs 2412 connected to the same write row line, such as WRL1, if the source / drain of NFET 2412 in the second row write circuit 2405 is connected to VDD and the source / drain of NFET 2412 in the first row write circuit 2404 is configured to be connected to ground, then providing an appropriate control signal to the gate of the corresponding NFET (driven to VDD) will result in a write row line current I WRL will flow from the second row write circuit 2405 to the first row write circuit 2404. Similarly, if the source / drain of NFET 2412 in the second row write circuit 2405 is configured to be connected to ground and the source / drain of NFET 2412 in the first row write circuit 2404 is configured to be connected to VDD, then the write row line current I WRL will flow in the opposite direction (i.e., from the first row write circuit 2404 to the second row write circuit 2405). In one or more embodiments, only one pair of NFET switches 2412 is enabled during a given write cycle to direct the write row line current I through the selected write row line. WRL To control the write row line current in this circuit, a regulated voltage can be introduced at the point labeled "VDD."

[0181] The write circuit 2400 may further include two conversion circuits 2410, each configured to convert the superconducting signal to a (Bi)CMOS signal suitable for use in the (Bi)CMOS write address decoder 2408. Similar to the conversion circuit 2310 previously described in connection with FIG. 23A, in one or more embodiments, a Suzuki stack may be used in the conversion circuit 2410 to convert the superconducting signal to a (Bi)CMOS signal. Such a converted (Bi)CMOS signal (labeled "encoded write address" in FIG. 24) that interfaces directly with the (Bi)CMOS write address decoder 2408 (and / or the (Bi)CMOS row write circuits 2404, 2405, which are implied but not explicitly shown) may include, for example, (i) a write row line current I WRL (ii) a write timing trigger to shape the write column line current I WCL_1 and I WCL_M The write row line current I WRL Included may be (iii) a write timing trigger for enabling the write operation of the superconducting to (Bi)CMOS conversion circuit 2410, as well as (iv) an address signal for selecting a particular row, which is preferably "encoded" to reduce the size of the superconducting to (Bi)CMOS conversion circuit 2410, as described above.

[0182] 25 is a schematic diagram illustrating at least a portion of an exemplary mixed superconducting and (Bi)CMOS write circuit 2500 in accordance with another embodiment of the present disclosure. The write circuit 2500 includes (Bi)CMOS column write circuits, each of which includes a true (Bi)CMOS column write circuit 2506 and a complementary (Bi)CMOS column write circuit 2507, and corresponding write column lines WCL1 to WCL2. M and write row lines WRL1 to WRL N 23A, but uses at least one (Bi)CMOS row write circuit 2504 that controls the current in the row and column write circuits. The (Bi)CMOS row and column circuits can be configured to function similarly to the row and column write circuits shown in FIG. 23A.

[0183] The write circuit 2500 further comprises a multiplexer 2514 operatively connected to the (Bi)CMOS column write circuits 2506, 2507 and the (Bi)CMOS address decoder 2508, which controls the write row line current I WRL , which transmits write row lines WRL1 to WRL N 23A , and configured to generate a plurality of control signals to control NFETs 2512 or other switching elements of the (Bi)CMOS row write circuit 2504 to select a corresponding one of the write row lines. A first one of the (Bi)CMOS multiplexers 2514 has a first input port configured to receive a (Bi)CMOS encoded write address and a second input port configured to receive a superconducting encoded write address generated by the first superconducting to (Bi)CMOS conversion circuit 2510. The first conversion circuit 2510 can be configured to correspond to the conversion circuit 2310 shown in FIG. 23A . An output port of the first (Bi)CMOS multiplexer 2514 can be configured to generate an address signal provided to the write address decoder 2508 to select a given one of the write row lines.

[0184] A second one of the (Bi)CMOS multiplexers 2514 similarly comprises a first input port configured to receive a (Bi)CMOS data signal provided to the second multiplexer and a second input port configured to receive a superconducting data signal that may be generated by a second superconducting to (Bi)CMOS conversion circuit 2510. The second conversion circuit 2510 may be configured to correspond to the conversion circuit 2310 shown in FIG. 23A. An output port of the second (Bi)CMOS multiplexer 2514 may be configured to generate a data signal that is provided to a (Bi)CMOS column write circuit 2507 to write a state to a selected one or more memory cells 2502.

[0185] 26A is a schematic diagram illustrating at least a portion of an example write circuit 2600 for writing states to superconducting memory cells, which may comprise JJ-based and FET-based superconducting memory cells, in accordance with one or more embodiments of the present invention. The write circuit 2600 includes one or more write column switches 2602, each of which may comprise an NFET or other (Bi)CMOS device in one or more embodiments, and corresponding write lines 26140 to 26141. N-1 , where N is an integer, and one or more superconducting memory cells (or elements) 26080 through 2608 (e.g., JJ-based, but not MJJ-based, and FET-based) that hold the written state. N-1 (collectively 2608) and memory cells 26080 to 2608 N-1 To write the state of W Preferably, the current source 2610 includes at least one control signal, Control_I, provided to the current source (e.g., a programmable current source), in one or more embodiments. W A bidirectional write current I with a controllable current level and direction (positive or negative) depending on W It should be appreciated that the current source 2610, in one or more embodiments, may reside in a thermal environment at room temperature (i.e., a room temperature layer) or may reside in another environment external to the remainder of the write circuit 2600.

[0186] Write lines 26140 through 2614 passing through memory cells N-1 Each of at least a subset of the superconducting memory cells 26080-2608 is integrated with a corresponding write line switch 2602 and transformer 2604 to hold a write state. N-1 Specifically, assuming an NFET implementation of the write line switches, write lines 26140 to 2614 N-1 Each of at least a subset of the inputs has a first source / drain connected to a first terminal of a write current source 2610 via a first interconnect In_Out_1, a second source / drain connected to a first terminal of a primary winding (i.e., an inductor or coil) L1 of a transformer 2604, and a plurality of control signals (CTL0 through CTL N-1 ) 26060 to 2606 N-1 26140 to 26140. N-1 A second terminal of the primary inductor L1 of the transformer 2604 in each of at least a subset of the first and second inductors can be connected to a second terminal of the current source 2610 via a second interconnect In_Out_2.

[0187] The write current I flows through a given one of the primary inductors L1 of the transformer 2604. W Induces a proportional write current in the secondary winding (i.e., inductor or coil) L2 of transformer 2604 according to the principle of mutual inductance. This proportional write current has an amplitude and direction that depends on the amplitude and direction of the write current flowing in the corresponding write column line and the ratio of the number of turns in the secondary winding to the number of turns in the primary winding (flux ratio, or equivalently, the mutual inductance of the wires). N-1 Each of the write-column lines is connected to a secondary inductor L2 of a transformer 2604 on a corresponding one of the write-column lines, and a proportional write current provided by the transformer secondary inductor L2 is used to write a state to the memory cell.

[0188] A current source 2610 provides a write current I W from the first interconnect In_Out_1 to the write column lines WCL0 to WCL N-1 2 through an NFET 2602 (configured as a write column switch) and a transformer 2604 on at least one selected one of the interconnects In_Out_1 and In_Out_2 and back to the current source 2610 via the second interconnect In_Out_2, or vice versa (depending on the direction of the write current). The current source 2610 can provide a temporary DC current or can provide a more complex current signal that includes AC and DC components. Thus, the write lines 26140 to 2614 connected between the two interconnects In_Out_1 and In_Out_2 N-1 Each of at least a subset of the 16A-16B includes a series-connected (Bi)CMOS switch (i.e., gate element) 2602 and a transformer 2604 integrated therein, the primary inductor L1 of the transformer may be a normal conductor or a superconductor, while the secondary inductor L2 of the transformer is a superconducting inductor.

[0189] Each write-column line may comprise, in broader terms, a (Bi)CMOS gate circuit (2602) that includes a transformer (2604) that is also an integral part of a superconducting memory cell (2608). A write current I is provided by a current source 2610. W In the basic operation of write circuit 2600, a current is selectively gated by transistor 2602 (in response to a control signal 2606 provided) to flow through a primary inductor L1 of a transformer 2604 on a selected write-column line. This current flowing through the primary inductor L1 of transformer 2604 induces a time-varying voltage and / or a constant phase difference across secondary inductor L2 of transformer 2604 that is then applied to the remainder of superconducting memory cell 2608.

[0190] 26B is a schematic diagram illustrating at least a portion of an example write circuit 2650 for writing states to a superconducting memory cell, in accordance with one or more alternative embodiments of the present invention. The example write circuit 2650 of FIG. 26B, like the example write circuit 2600 shown in FIG. 26A, includes corresponding write lines 26140 to 2614, each of which may, in one or more embodiments, comprise an NFET or other (Bi)CMOS device. N-1 , where N is an integer, and one or more superconducting memory cells 26580 through 26581 that hold the written state (e.g., JJ-based and FET-based, but not MJJ-based). N-1 (collectively 2658) and memory cells 26580 to 2658 N-1 To write each state of W Preferably, the current source 2610 comprises at least one control signal, Control_I, provided to the current source, as previously described. W A bidirectional write current I with a controllable current level and direction (positive or negative) depending on W It should be appreciated that the current source 2610, in one or more embodiments, may be in a room temperature thermal environment (i.e., a room temperature layer) or may be in another environment external to the remainder of the write circuitry 2650.

[0191] Write lines 26140 to 2614 of an exemplary write circuit 2650 N-1 Each of at least a subset of the write circuits 2650-2658 includes a Josephson junction 2654 and a superconducting memory cell 26580-2658, rather than including a transformer as in the exemplary write circuit 2600 of FIG. 26A. N-1 2658 to couple a single flux voltage pulse resulting from current source 2610 (collectively producing a current pulse in superconducting inductor 2656) to an associated superconducting memory cell 26580 to 2658. N-1 and a superconducting inductor 2656 configured to selectively transmit

[0192] Specifically, the write column lines WCL0 to WCL N-1 Each of at least a subset of the write column switches 2602 includes a write column switch 2602 integrated with a write column line, the write column switch having a first source / drain connected to a first terminal of a current source 2610 via a first interconnect In_Out_1, a second source / drain connected to a first terminal of a superconducting inductor 2656 and a first terminal of a Josephson junction 2654, and a plurality of control signals (CTL0 through CTL N-1 ) 26060 to 2606 N-1 and a gate adapted to receive a corresponding one of the inputs of the superconducting memory cells 26580 to 2658, where N is an integer. N-1 2658 through 2659, and the second terminal of Josephson junction 2654 is connected to a first terminal of a corresponding one of memory cells 26580 through 2658. N-1 The second terminal of the current source 2610 is connected to a second terminal of a corresponding one of the plurality of superconducting memory cells 26580 to 2658 through a second interconnect In_Out_2. N-1 and a second terminal of each of at least a subset of the write lines 26140 to 2614. N-1 and a second terminal of each of at least a subset of the plurality of Josephson junctions 2654 located at

[0193] The example write circuit 2650 of FIG. 26B connects write lines 26140 to 2614 of the write circuit 2600. N-1 26A, except that the transformers 2605 in each of at least a subset of the write circuits 2600 are replaced with Josephson junctions 2654 and superconducting inductors 2656 as previously described. Here, the write current signal provided by the current source 2610 passes directly through the Josephson junctions 2654. As known to those skilled in the art, a carefully selected current signal through Josephson junctions 2654 of appropriate critical current can generate discrete single flux quantum pulses at desired intervals. These quantized pulses are provided to the superconducting memory cells 2658 via the superconducting inductors 2656, which may be significantly different in design and / or construction (e.g., optimized for a galvanically coupled input rather than an inductively coupled input as in the write circuit 2600). As known in the art, multiple single flux quantum pulses can be stored in a superconducting inductor and released onto a transmission line by a control signal. The superconducting inductor 2656 itself can be designed to be a storage inductor for these stored pulses. This exemplary embodiment of write circuit 2650 may provide benefits in terms of speed and / or precision of generating such stored single flux quantum pulses.

[0194] 27 is a schematic diagram illustrating at least a portion of an exemplary read only memory (ROM) circuit 2700, in accordance with one or more embodiments of the present invention. The ROM circuit 2700 can be programmed only once per cool down, in one or more embodiments, and is suitable for use in the exemplary write system 2600 of FIG. 26A. The ROM circuit 2700 can more specifically comprise a read port (i.e., input) R, a write port W, and an output port Q. A write signal provided to the write port W of the ROM circuit 2700 passes through a first Josephson transmission line (JTL) 2702 and preferably flows into one of the inputs of a logical OR gate 2704. The output of the OR gate 2704 flows into a second JTL 2706 configured to amplify the signal. The amplified output signal from the second JTL 2706 is split along two signal paths, with a first portion of the split signal being fed to a JTL-based delay line 2708 and a second portion of the split signal being fed to a third JTL 2710.

[0195] The JTL-based delay line 2708, in one or more embodiments, is configured to delay a second portion of the output signal from the second JTL 2706 by one clock cycle before providing it to a second input of the OR gate 2704. So configured, the output from the third JTL 2710 provided to a first input of the logical AND gate 2714 is always a logical 1 when a logical 1 is provided to the write port W.

[0196] The read signal provided to read port R of ROM circuit 2700 preferably passes through a fourth JTL 2712 and then is provided to a second input of AND gate 2714. AND gate 2714 outputs a logic 1 signal to output port Q of ROM circuit 2700 only if a read signal (logic 1) is received from read port R and a logic 1 signal appears at write port W during that clock cycle.

[0197] A logic zero is otherwise established as the initial state of the ROM circuit 2700 upon cooldown. In the exemplary ROM circuit 2700, as in many superconducting logic circuits, the circuit is in a logic zero state upon cooldown. In ROMs as well as other superconducting memory circuits, such as but not limited to field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs), if the (Bi)CMOS inputs write to the memory circuit (e.g., the ROM circuit 2700) only once at the beginning of operation, no mechanism is needed to rewrite the memory cells of the ROM circuit 2700 to a zero state during system operation, with or without the application of flux quanta. Temperature cycling the system to a temperature not compatible with superconductivity (i.e., above the critical temperature) can reset all memory cells of the superconducting memory circuit to a logic zero state.

[0198] 28 is a schematic diagram illustrating at least a portion of an example write circuit 2800 for writing states to a superconducting memory cell in accordance with one or more embodiments of the present invention. Although the write circuit 2800 illustrates only one memory cell for clarity of illustration, it should be understood that the write circuit 2800 can be configured for use with multiple memory cells, as will be apparent to those of ordinary skill in the art given the teachings herein.

[0199] An exemplary write circuit 2800 includes, with reference to FIG. 28, at least a first (Bi)CMOS switch 2802, which may comprise a first NFET. A and a second (Bi)CMOS switch 2802, which may comprise a second NFET. B It is preferable to have a first and second (Bi)CMOS switch 2802. A and 2802 B 28, each of which provides a corresponding control signal 2814 for selectively activating the switch. A and 2814 B Preferably, the control signal 2814 is adapted to receive A and 2814 B In some embodiments, the write circuit 2800 includes at least a first transformer 2808. A and the second transformer 2808 B , each of which corresponds to a transformer 2808 A , 2808 B At least a first Josephson junction 2806 that may be integrated with A and the second Josephson junction 2806 B , at least the first JTL2810 A and the second JTL2810 B , and at least one superconducting memory cell 2812 (e.g., JJ-based and FET-based, rather than MJJ-based). Each superconducting memory cell 2812 that retains a written state is connected to a corresponding write circuit element of the superconducting memory cell (e.g., first and second NFET switches 2802, A , 2802 B , the first and second transformers 2808 A , 2808 B , first and second Josephson junctions 2806 A , 2806 B , and the first and second JTL2810 A , 2810 B ) may be integrated.

[0200] More specifically, the first NFET switch 2802 A 28 includes a first source / drain connected to a first interconnect (i.e., bus) In_Out_1_A and a corresponding first transformer 2808 A a second source / drain connected to a first terminal of the primary winding (i.e., an inductor or coil) of the A and a gate adapted to receive the first transformer 2808. A The second terminal of the primary inductor of the second NFET switch 2802 may be connected to the second interconnect In_Out_2_A. B Similarly, the first source / drain is connected to a third interconnect (i.e., bus) In_Out_1_B, and the corresponding second transformer 2808 B a second source / drain connected to a first terminal of the primary winding (i.e., an inductor or coil) of the B and a gate adapted to receive the second transformer 2808. B The second terminal of the primary inductor may be connected to the fourth interconnect In_Out_2_B.

[0201] In one or more embodiments, the two pairs of interconnects, preferably In_Out_1_A and In_Out_1_B, and / or In_Out_2_A and In_Out_2_B, may be connected in common (and to ground). The interconnects In_Out_1_A, In_Out_2_A, In_Out_2_A, In_Out_2_B may be formed of normal conductors and need not be formed of superconductors, although embodiments of the present invention contemplate that one or more of the interconnects may be comprised of a superconductor.

[0202] At least the first and second current sources, not explicitly shown in FIG. 28, may be implemented as bidirectional programmable current sources consistent with current source 2610 shown in FIG. 26 and may be connected to the exemplary write circuit 2800 and configured to provide a write current for writing a state to memory cell 2812. It should be appreciated that the first and second current sources need not be bidirectional, but the exemplary arrangement shown in FIG. 28 may benefit from having bidirectional current sources. The first current source may be connected between the first interconnect In_Out_1_A to the second interconnect In_Out_2_A, and the second current source may be connected between the third interconnect In_Out_1_B to the fourth interconnect In_Out_2_B. The first and second current sources may preferentially reside in a room temperature thermal environment (i.e., a room temperature layer).

[0203] First transformer 2808 A The secondary winding (i.e., inductor or coil) of the first transformer 2808 A The first terminal of the secondary inductor is connected to the first Josephson junction 2806. A 2808 is connected to the first terminal of the first transformer 2808. A The second terminal of the secondary inductor is connected to the first Josephson junction 2806 A a first Josephson junction 2806 connected to the second terminal of the A The first transformer 2808 may be connected across the A and the first Josephson junction 2806 A The two were integrated to produce the first radio frequency (RF) superconducting quantum interference detector (SQUID) 2804. A Similarly, the second transformer 2808 can be formed. B The secondary winding (i.e., inductor or coil) of the second transformer 2808 B The first terminal of the secondary inductor of the second Josephson junction 2806 B 2808 is connected to the first terminal of the second transformer 2808. B The second terminal of the secondary inductor is connected to the second Josephson junction 2806 B a second Josephson junction 2806 connected to the second terminal of the B A second transformer 2808 may be connected across the B and the second Josephson junction 2806 B The second RF SQUID2804 is integrated into the B can be formed.

[0204] The first JTL2810 A The first RF SQUID2804 A and an output connected to a corresponding superconducting memory cell 2812. B Similarly, the second RF SQUID2804 B and an output connected to the memory cell 2812. A , 2810 B The magnetic flux generated by the first and second current sources is expressed as (for example, JTL2810 A , 2810 B , preferably configured to selectively transmit a current pulse through the associated memory cells 2812 (by collectively generating a current pulse through the

[0205] The exemplary write circuit 2800 shown in FIG. 28 includes two (Bi)CMOS switches (e.g., NFET 2802 A and 2802 B It should be appreciated that FIG. 28 illustrates an arrangement in which a first RF SQUID 2804 is used to provide data and write enable signals to write a state to each superconducting memory cell 2812. In one or more embodiments, a first write current source (not explicitly shown in FIG. 28 but implied) connected between the first interconnect In_Out_1_A and the second interconnect In_Out_2_A may be used to write a state to the first RF SQUID 2804. A 28, a second write current source (not explicitly shown in FIG. 28 but implied) connected between the third interconnect In_Out_1_B and the fourth interconnect In_Out_2_B is connected to the second RF SQUID 2804. B By connecting to the control signal 2814 A , 2812 B selects the memory cell 2812 corresponding to the write operation (each of the SQUIDs comprises a transformer (2808) and a Josephson junction (2806)).

[0206] FIG. 29 is a schematic diagram of a conventional core memory cell 2900 suitable for use in combination with the exemplary write circuit 2800 shown in FIG. 28. Details of the memory cell 2900 are provided in U.S. Pat. No. 6,399,343, the disclosure of which is incorporated herein by reference in its entirety for all purposes. The memory cell 2900 comprises a "body" portion 2902 and a "tail" portion 2904 and utilizes two write signals received at a data input port DI and a clock input port LCLK, respectively. A read input port NDRO and a data output port QO are not shown in the exemplary write circuit 2800 of FIG. 28 since they are fully superconducting in the ROM array. As will be appreciated by those skilled in the art, certain inputs and / or outputs that may otherwise be present in an actual implementation of one or more exemplary circuits according to embodiments of the invention described herein may be omitted for brevity and clarity.

[0207] An exemplary write cycle operation for writing a state to memory cell 2900 of FIG. 29 (which is memory cell 2812) using the exemplary write circuit 2800 shown in FIG. 28 in accordance with one or more embodiments of the present invention will now be described. With reference to FIGS. 28 and 29, in an exemplary write cycle, the data input port DI and the clock input port LCLK of memory cell 2900 are asserted, respectively, to write a logic "high" value as the state to be stored in the body and enable this state to be read out at data output port QO. With respect to the write circuit 2800, these signals are asserted by providing appropriate write currents through interconnects In_Out_1_A and In_Out_1_B, respectively, while simultaneously enabling control signals 2814A and 2814B, respectively. RF SQUID 2804 A and 2804 B The write current supplied to each is JTL2810 A and 2810 B The SFQ pulses are then supplied to the data input port DI and the clock input port LCLK of the memory cell 2900, respectively.

[0208] The superconducting phase of Josephson junction J2 of memory cell 2900 transitions to high (e.g., logic “1”) (e.g., to 2π radians) in response to a write enable signal provided to logic clock input port LCLK going high. The superconducting phase of Josephson junction J2 remains high after an assertion SFQ pulse provided to data input port DI triggers Josephson junction J4. When clock input port LCLK transitions low, the superconducting phase of state-storing Josephson junction J2 is maintained high. Rather than de-triggering Josephson junction J2, Josephson junction J3 (which may be an “escape” Josephson junction) is triggered. The combination of logic clock input LCLK going high and data input DI going high places memory cell 2900 in a “write 1” state, thus writing a logic “1” to the body-stored state by maintaining Josephson junction J2 at a superconducting phase of 2π radians. As long as Josephson junction J2 remains in the 2π radian high state, a pre-critical bias current is provided to Josephson junction J5 in tail 2904 of memory cell 2900, such that Josephson junction J5 is ready to propagate a pulse received at read input port NDRO to data output port QO. Writing memory cell 2900 to a “write 0” state is similarly described in the art.

[0209] In this example, the transistor / transformer line (e.g., NFET2802 in Figure 28) A / trans2808 A , or NFET2802 B / trans2808 B ) is fed to a corresponding RF SQUID (e.g., RF SQUID 2804 in FIG. 28). A , 2804 B ) to the secondary transformer coil 111. Such an arrangement can be used to generate SFQ pulses that are then fed to the remainder of the superconducting memory cell (e.g., 2812 in FIG. 28). Such an rf SQUID can be designed to allow encoding of selected desired data. That is, by carefully selecting the inductance value of the secondary transformer coil and the critical current of the Josephson junction, both of the following behaviors of interest may be possible: In one case, the rf SQUID can be designed such that a signal of sufficient strength will produce a single SFQ pulse and then no other SFQ pulses when the signal is removed. In another case, the onset of the signal may produce a positive SFQ pulse and, when removed, a negative SFQ pulse. Both of these, or any number of other pulse generation patterns (i.e., encoding), may be useful depending on the requirements of the associated memory cell. This arrangement is compatible with all components that transform the fed primary transformer current into a phase or voltage signal of a superconducting logic circuit.

[0210] As is known in the art, a similar arrangement of multiple transistors can be used to achieve a push / pull configuration (already shown in FIG. 13) to drive current through the primary transformer coil. Similarly, any number of transistor / transformer wire pairs can be used to drive signals to a single superconducting circuit. For superconducting memory cells that require distinct or separate signals to write first or second logic states, multiple transistor / transformer wire pairs can be assigned to a single superconducting memory cell.

[0211] The write circuit arrangement according to an embodiment of the present invention is advantageous because it provides a means, using CMOS or (Bi)CMOS circuitry, to provide a data pattern to be written to the entire superconducting memory array, write the data to the array elements (superconducting memory circuits), and then remove the CMOS transient data signal to turn off the CMOS circuitry. The superconducting memory array can then be read and written as needed. The power consumption of the CMOS operations is thereby limited to isolated periods of time. For arrays that only need to be written once, but read frequently, this arrangement allows for just one high power write followed by any number of low power reads. If no write operations are performed after the initial write, the size and complexity of the memory circuitry may be reduced over a typical read and write superconducting memory cell.

[0212] At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming an integrated circuit, identical dies are typically manufactured in a repeating pattern on the surface of a semiconductor wafer. Each die comprises the devices described herein and may comprise other structures and / or circuits. The individual dies are cut or diced from the wafer and then packaged as an integrated circuit. Those skilled in the art will know how to dices the wafer and package the dies to produce an integrated circuit. Any of the exemplary structures or devices shown in the accompanying figures, or portions of the structures or devices, may be part of an integrated circuit. Integrated circuits so manufactured are considered part of this invention.

[0213] Those skilled in the art will appreciate that the exemplary devices, structures, and circuits discussed above may be distributed in raw form as bare die (i.e., a single wafer comprising multiple unpackaged chips), in packaged form, or incorporated as part of an intermediate or final product that benefits from a formed memory device, such as, for example, a JMRAM, in accordance with one or more embodiments of the present invention.

[0214] Integrated circuits according to aspects of the present disclosure may be used in virtually any memory application and / or electronic system. Systems suitable for implementing embodiments of the present invention may include, but are not limited to, quantum computing systems and the like. Systems incorporating such integrated circuits are considered part of this invention. Those skilled in the art will be able to contemplate other implementations and applications of embodiments of the present invention given the teachings of the present disclosure presented herein.

[0215] The illustrations of the embodiments of the invention described herein are intended to provide a general understanding of the various embodiments, and are not intended to serve as a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art given the teachings herein. Other embodiments may be utilized and derived from the teachings herein, such that structural and logical substitutions and modifications may be made without departing from the scope of this disclosure. The figures are further merely representative and are not drawn to scale. Thus, the specification and drawings should be considered in an illustrative sense and not in a restrictive sense.

[0216] Embodiments of the present invention are referred to herein individually and / or collectively using the term "embodiment" merely for convenience and without any intention of limiting the scope of this application to a single embodiment or inventive concept even if a plurality is actually shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that arrangements which achieve the same purpose may be substituted for the specific embodiment shown. That is, this disclosure is intended to cover any and all adaptations or variations of the various embodiments. Given the teachings herein, combinations of the above embodiments with other embodiments not specifically described herein will be apparent to those of skill in the art.

[0217] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, as used in this specification, the terms "comprises" and / or "comprising" identify the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The term "and / or" is intended to include any of the associated items alone or any combination of one or more of the associated items. Thus, for example, the phrase "A, B, and / or C" as used herein is intended to mean A only, B only, C only, or any combination of A, B, and C. Terms such as "above" and "below," when used, are intended to indicate the relative placement of elements or structures with respect to one another, rather than absolute positions.

[0218] The equivalents of the corresponding structures, materials, acts, and all means or steps and functional elements in the following claims are intended to include structures, materials, or acts for performing functions in combination with other elements recited in the claims, as specifically recited in the claims. The description of the various embodiments has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The examples were selected and described in order to best explain the principles and practical applications of the invention and to enable others skilled in the art to understand the various embodiments with various modifications as appropriate for the specific use contemplated.

[0219] The Abstract is provided to comply with 37 CFR §1.72(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. The Abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it will be understood that various features have been grouped together in a single embodiment to streamline the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Inventive subject matter lies, rather, in all features of a single embodiment, as the appended claims reflect. Accordingly, the following claims are hereby incorporated into the Summary, with each claim standing on its own as separately claimed subject matter.

[0220] Those skilled in the art will be able to contemplate other implementations and applications of the techniques of the embodiments of the present invention given the teachings of the embodiments of the present invention provided herein. Although exemplary embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the embodiments of the present invention are not limited to those precise embodiments, and various other changes and modifications may be made thereto by those skilled in the art without departing from the scope of the appended claims.< / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n>

Claims

1. 1. A write circuit for writing states into a plurality of superconducting memory cells, the write circuit comprising: A control circuit; a first plurality of write lines, each of the first plurality of write lines associated with a corresponding column of the plurality of superconducting memory cells and configured to deliver a write column current; a first plurality of non-superconducting switch devices, each of the first plurality of non-superconducting switch devices being integrated with a corresponding one of the first plurality of write lines and configured to receive a first control signal provided from the control circuitry, such that the write column current flows through the corresponding one of the first plurality of write lines to write a state to a selected one of the superconducting memory cells associated with the corresponding one of the first plurality of write lines; A write circuit comprising:

2. a second plurality of write lines, each of the second plurality of write lines associated with a corresponding row of the plurality of superconducting memory cells and configured to deliver a write row current; a second plurality of non-superconducting switch devices, each of the second plurality of non-superconducting switch devices being associated with a corresponding one of the second plurality of write lines and configured to receive a second control signal provided from the control circuitry, enabling the write row current to flow through the corresponding one of the second plurality of write row lines to select one or more of the superconducting memory cells associated with the corresponding one of the second plurality of write lines; The write circuit of claim 1 further comprising:

3. 2. The write circuit of claim 1, further comprising at least a first interconnect and a second interconnect, a first end of each of the first plurality of write lines connected to the first interconnect, a second end of each of the first plurality of write lines connected to a first terminal of a corresponding one of the first plurality of non-superconducting switch devices, a second terminal of the corresponding one of the first plurality of non-superconducting switch devices connected to the second interconnect, and the first interconnect and the second interconnect connected to a first terminal and a second terminal, respectively, of at least a first current source configured to supply the write column current.

4. 4. The write circuit of claim 3, wherein each of at least a subset of the first plurality of non-superconducting switch devices comprises at least one field effect transistor connected in series between a corresponding one of the write-column lines and at least one of the first interconnect and the second interconnect.

5. 4. The write circuit of claim 3, wherein each of at least a subset of the first plurality of non-superconducting switch devices comprises at least a first field effect transistor (FET) and a second field effect transistor, the first FET connected in series between the first interconnect and a corresponding one of the write-column lines and the second FET connected in series between the corresponding one of the write-column lines and the second interconnect, the first FET and the second FET configured to receive first and second control signals, respectively, provided from the control circuit.

6. 4. The write circuit of claim 3, wherein each of at least a subset of the first plurality of non-superconducting switch devices comprises a first field effect transistor (FET) and a second field effect transistor, the first FET connected between the first interconnect and a first node, and the second FET connected between the first node and a corresponding one of the write lines.

7. 2. The write circuit of claim 1, wherein each of at least a subset of the first plurality of write lines is configured to pass above or below a respective one of the superconducting memory cells at an angle relative to a major axis of the memory cell.

8. 3. The write circuit of claim 2, wherein each of at least a subset of the plurality of superconducting memory cells comprises opposing first and second layers, and each of at least the subset of the plurality of superconducting memory cells is configured such that a corresponding one of the second plurality of write lines passes over the first layer of the memory cells and a corresponding one of the first plurality of write lines passes over the second layer of the memory cells and is orthogonal to the corresponding one of the second plurality of write lines.

9. A first interconnect portion, a second interconnect portion, a third interconnect portion, and a fourth interconnect portion. a first end of each of the first plurality of write lines connected to the first interconnect, a second end of each of the first plurality of write lines connected to a first terminal of a corresponding one of the first plurality of non-superconducting switch devices, a second terminal of the corresponding one of the first plurality of non-superconducting switch devices connected to the second interconnect, a first end of each of the second plurality of write lines connected to the third interconnect, a second end of each of the second plurality of write lines connected to a first terminal of a corresponding one of the second plurality of non-superconducting switch devices, and a second terminal of the corresponding one of the second plurality of non-superconducting switch devices connected to the fourth interconnect; 3. The write circuit of claim 2, wherein the first interconnect and the second interconnect are connected to first and second terminals, respectively, of at least a first current source configured to supply the write column current, and the third interconnect and the fourth interconnect are connected to first and second terminals, respectively, of at least a second current source configured to supply a write row current to select one or more corresponding memory cells of the plurality of superconducting memory cells.

10. 3. The write circuit of claim 2, wherein each of at least a subset of the second plurality of non-superconducting switch devices comprises at least one field effect transistor connected in series between a corresponding one of the write row lines and a current source configured to provide a write row current to select one or more of the superconducting memory cells.

11. 2. The write circuit of claim 1, wherein each of at least a subset of the first plurality of write lines comprises a wrap-around bit line configured to pass above and below each of a corresponding plurality of superconducting memory cells associated with the bit line.

12. 2. The write circuit of claim 1, further comprising a plurality of coupling elements, each of said coupling elements connected in series with a given one of said first plurality of non-superconducting switch devices in a corresponding one of said first plurality of write lines.

13. 13. The write circuit of claim 12, wherein each of at least a subset of the plurality of coupling elements comprises a transformer having a primary wire connected in series with the given one of the first plurality of non-superconducting switch devices and a secondary wire configured to pass through or in proximity to a corresponding one of the superconducting memory cells.

14. 14. The write circuit of claim 13, wherein the primary wire of each of the transformers is a non-superconducting wire and the secondary wire of each of the transformers is a superconducting wire.

15. 2. The write circuit of claim 1, wherein the control circuit comprises a shift register having an input port configured to receive an input data pattern to be provided to the shift register to control write operations of the superconducting memory cells, the shift register comprising one or more master-slave latches connected in series with each other such that an output of one master-slave latch is provided to an input of an adjacent master-slave latch, and control signals for activating the first plurality of non-superconducting switch devices are generated at outputs of each of the master-slave latches of the shift register.

16. 2. The write circuit of claim 1, wherein at least a subset of the plurality of superconducting memory cells each comprises a magnetic Josephson junction.

17. 2. The write circuit of claim 1, wherein at least a given one of the first plurality of write lines comprises a true magnetic Josephson junction (MJJ) memory cell and a complementary MJJ memory cell associated with the given one of the first plurality of write lines, the given one of the first plurality of write lines being configured to deliver a write column current across the true MJJ memory cell in a first direction and to deliver the write column current across the complementary MJJ memory cell in a second direction opposite the first direction.

18. the first plurality of write lines are arranged in at least a first subset and a second subset of the first plurality of write lines, the write circuit further comprising a write current multiplexing circuit, the write current multiplexing circuit comprising: a first non-superconducting switch device having a first terminal connected to a first interconnect and a second terminal connected to a second interconnect, the first non-superconducting switch device being configured to electrically connect the second interconnect to the first interconnect in response to a second control signal provided by the control circuit; a second non-superconducting switch device, the second non-superconducting switch device having a first terminal connected to the first interconnect and a second terminal connected to a third interconnect, the second non-superconducting switch device configured to electrically connect the third interconnect to the first interconnect in response to a third control signal provided from the control circuit; each of the first plurality of non-superconducting switch devices associated with the first subset of the first plurality of write lines comprises a first terminal connected to the second interconnect and a second terminal connected to a first end of a corresponding one of the first subset of the first plurality of write lines; each of the first plurality of non-superconducting switch devices associated with the second subset of write-column lines comprises a first terminal connected to the third interconnect and a second terminal connected to a first end of a corresponding one of the second subset of the first plurality of write lines; a second end of the first plurality of write lines is connected to a fourth interconnect; 2. The write circuit of claim 1, wherein a write column current source configured to generate the write column current is connected between the first interconnect and the fourth interconnect.

19. 2. The write circuit of claim 1, wherein the write circuit is configurable to write a state to only one of the superconducting memory cells at a given time.

20. 1. A write circuit for writing a state into a superconducting memory cell, the write circuit comprising: a first non-superconducting switch; a second non-superconducting switch; and a first radio frequency (RF) superconducting quantum interference device (SQUID) connected in series with the first non-superconducting switch; a second RF SQUID connected in series with the second non-superconducting switch; a first Josephson transmission line (JTL) having an input connected to the first RF SQUID and an output connected to the superconducting memory cell; a second JTL having an input connected to the second RF SQUID and an output connected to the superconducting memory cell; the first non-superconducting switch and the first RF SQUID are connected between a first terminal and a second terminal of a first write current source via a first interconnect and a second interconnect, respectively, and the second non-superconducting switch and the second RF SQUID are connected between a first terminal and a second terminal of a second write current source via a third interconnect and a fourth interconnect.

21. At least one of the first RF SQUID and the second RF SQUID is a transformer comprising a primary bond wire and a secondary bond wire connected in series with a corresponding one of the first non-superconducting switch and the second non-superconducting switch; a Josephson junction having a first terminal connected to a first terminal of the secondary bond wire of the transformer and a second terminal connected to a second terminal of the secondary bond wire of the transformer, the first terminal of the Josephson junction being connected to the input of a corresponding one of the first and second JTLs; 21. The write circuit of claim 20 comprising:

22. 22. The write circuit of claim 21, wherein the primary bond wires of the transformer are non-superconducting, and the secondary bond wires of the transformer and the Josephson junctions are superconducting elements.

23. 21. The write circuit of claim 20, wherein at least one of the first non-superconducting switch and the second non-superconducting switch comprises at least one field effect transistor.

24. 1. A superconducting memory circuit for reading and writing a plurality of magnetic Josephson junction (MJJ) based memory cells, the memory circuit comprising: at least one superconducting read circuit operably coupled to the plurality of MJJ-based memory cells, the superconducting read circuit comprising at least a first current source and at least a first non-superconducting switch circuit connected to one or more corresponding row lines and column lines associated with the memory cells, the read circuit being configured to selectively provide a read current generated by the first current source along at least one of the row lines and the column lines via the first non-superconducting switch circuit to read a state of at least one of the MJJ-based memory cells during a read operation; a non-superconducting write circuit operably coupled to the plurality of MJJ-based memory cells, the non-superconducting write circuit comprising at least a second current source and at least a second non-superconducting switch circuit connected to the one or more corresponding row lines and column lines associated with the memory cells, the write circuit being configured to selectively provide a write current generated by the second current source along at least one of the row lines and the column lines via the second non-superconducting switch circuit to write a state to at least one of the MJJ-based memory cells during a write operation; A superconducting memory circuit comprising:

25. 25. The superconducting memory circuit of claim 24, wherein the non-superconducting write circuit is configured to assist in writing a state to at least the corresponding one of the plurality of MJJ-based memory cells by enabling controlled delivery of at least one of a write field along an easy axis of a corresponding memory cell, a write field along a hard axis of the corresponding memory cell, a write field along a common angular axis of the corresponding memory cell, a spin torque current to select one of a first and a second circulating current state associated with the corresponding memory cell, and a magnetic flux applied to select one of the first and the second circulating current states.

26. 1. A write circuit for selectively writing states to a plurality of superconducting memory cells of a random access memory, the write circuit comprising: at least one superconducting column write circuit, said superconducting column write circuit connected to one or more write-column lines, each of said write-column lines configured to deliver a write-column line current, said column write circuit comprising at least one superconducting switch circuit configured to selectively supply said write column current to at least a given one of said write-column lines, said at least one superconducting switch circuit responsive to at least a first control signal to write a state to one or more corresponding memory cells of said plurality of superconducting memory cells associated with said given one of said write-column lines; at least one non-superconducting row write circuit, said non-superconducting row write circuit connected to one or more write row lines, each of said write row lines configured to deliver a write row line current, said row write circuit comprising at least one non-superconducting switch circuit configured to selectively supply said write row current to at least a given one of said write row lines, said at least one non-superconducting switch circuit responsive to at least a second control signal to select one or more corresponding memory cells of said plurality of superconducting memory cells associated with said given one of said write row lines; A write circuit comprising:

27. 27. The write circuit of claim 26, further comprising at least one non-superconducting decoder circuit configured to receive at least a portion of a non-superconducting write address signal and to generate the at least second control signal in response to the write address signal.

28. 28. The write circuit of claim 27, further comprising a conversion circuit configured to receive at least a portion of a superconducting encoded write address signal and generate at least a portion of the non-superconducting write address signal provided to the non-superconducting decoder circuit.

29. 27. The write circuit of claim 26, wherein the write-column lines comprise one or more wrap-around connections, each wrap-around connection configured to connect a pair of adjacent write-column lines such that the write column current is sourced from the at least one superconducting column write circuit and returned to the superconducting column write circuit.

30. 27. The write circuit of claim 26, wherein the at least one superconducting column write circuit comprises a first superconducting column write circuit element and a second superconducting column write circuit element, the first superconducting column write circuit element connected to a first end of each of the write column lines and the second superconducting column write circuit element connected to a second end of each of the write column lines, the first superconducting column write circuit element and the second superconducting column write circuit element connected in a push-pull configuration.

31. 27. The write circuit of claim 26, wherein the at least one non-superconducting row write circuit comprises a first non-superconducting row write circuit element and a second non-superconducting row write circuit element, the first non-superconducting row write circuit element connected to a first end of each of the write row lines and the second non-superconducting row write circuit element connected to a second end of each of the write row lines, the first non-superconducting row write circuit element and the second non-superconducting row write circuit element connected in a push-pull configuration.

32. 1. A write circuit for selectively writing states to a plurality of superconducting memory cells of a random access memory, the write circuit comprising: at least one non-superconducting column write circuit, said non-superconducting column write circuit connected to one or more write-column lines, each of said write-column lines configured to deliver a write-column line current, said column write circuit comprising at least a first non-superconducting switch circuit configured to selectively supply said write column current to at least a given one of said write-column lines, said at least first non-superconducting switch circuit responsive to at least a first non-superconducting control signal to write a state to one or more corresponding memory cells of said plurality of superconducting memory cells associated with said given one of said write-column lines; at least one non-superconducting row write circuit, said non-superconducting row write circuit connected to one or more write row lines, each of said write row lines configured to deliver a write row line current, said row write circuit comprising at least a second non-superconducting switch circuit configured to selectively supply said write row current to at least a given one of said write row lines, said at least second non-superconducting switch circuit responsive to at least a second non-superconducting control signal to select one or more corresponding memory cells of said plurality of superconducting memory cells associated with said given one of said write row lines; a first conversion circuit and a second conversion circuit, the first conversion circuit configured to receive a superconducting encoded write address and generate the at least first non-superconducting control signal in response to the superconducting encoded write address, and the second conversion circuit configured to receive a superconducting data signal and generate the at least second non-superconducting control signal in response to the superconducting data signal; A write circuit comprising:

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