Sidewall passivation using aldehyde or isocyanate chemistries for high aspect ratio etching

Abstract

Various embodiments herein relate to methods, apparatus, and systems for forming recessed features in a dielectric material on a semiconductor substrate. Separate etching and deposition operations are performed in a cyclical fashion. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etching of the dielectric material during the etching operation. The protective coating may be deposited using a method capable of forming a protective coating along the sidewalls. In some cases, the protective coating is deposited using a molecular layer deposition technique. The protective coating may be deposited using certain reactants that provide relatively complete sidewall coverage at relatively low temperatures. In some embodiments, one or more reactants include an aldehyde functional group. In some embodiments, one or more reactants include an isocyanate functional group.

Description

[Background technology]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] A PCT application is being filed contemporaneously herewith as a part of this application. Each application identified in the contemporaneously filed PCT application to which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes.

[0002] One process that is often employed during the manufacture of semiconductor devices is the formation of etched cylindrical holes in dielectric materials. An exemplary situation in which such a process may occur is in memory applications, such as, but not limited to, DRAM and 3D NAND structures. As the semiconductor industry advances and device dimensions shrink, it becomes increasingly difficult to uniformly etch such cylindrical holes, especially in the case of high aspect ratio cylindrical holes with narrow widths and / or large depths. Summary of the Invention

[0003] Certain embodiments herein relate to methods and apparatus for forming etched features in a stack including a dielectric material on a semiconductor substrate. The embodiments of the present disclosure may utilize certain techniques for depositing passivation material on the sidewalls of the etched features, thereby enabling high aspect ratio etching. In some embodiments, a specific reactant or reactants may be used to deposit the passivation material. In some cases, one or more reactants may include an aldehyde functional group. In other cases, one or more reactants may include an isocyanate functional group.

[0004] In one aspect of an embodiment of the present disclosure, a method for forming an etched feature in a layer stack including a dielectric material on a semiconductor substrate is provided. The method includes: (a) generating a first plasma comprising an etching reactant and exposing a substrate to the first plasma to partially etch a feature into a dielectric material; (b) after (a), depositing a protective film on sidewalls of the feature by: (i) exposing the substrate to a first reactant and causing the first reactant to adsorb onto the substrate, the first reactant comprising an aldehyde functional group; (ii) exposing the substrate to a second reactant, the first and second reactants reacting with each other to form the protective film; and (iii) cyclically repeating (i) and (ii) until the protective film reaches a target thickness, the protective film being an organic polymer film; and (c) repeating (a)-(b) until the feature is etched to a final depth, the protective film deposited in (b) substantially prevents lateral etching of the feature during (a), and the feature has an aspect ratio of about 5 or greater at the final depth.

[0005] In some embodiments, the first reactant comprises a dialdehyde or trialdehyde. In some embodiments, the first reactant comprises succinaldehyde (C4H6O2), glutaraldehyde (C5H8O2), adipaldehyde (C6H 10 O2), terephthalaldehyde (C8H6O2), 1,4-benzenedicarboxaldehyde (C6H4(CHO)2), orthophthalaldehyde (C8H6O2), 1,2-benzenedicarboxaldehyde (C6H4(CHO)2), and 2-methylglutaraldehyde (C6H 10In some embodiments, the second reactant comprises at least one of a diamine, a diol, a thiol, and a trifunctional compound. In some embodiments, the second reactant comprises a diamine. In some embodiments, the second reactant comprises 1,2-ethanediamine, 1,3-propanediamine, 1,4-butanediamine, ethylenediamine, m-xylylenediamine, isophoronediamine, 1,3-cyclohexanebis(methylamine), 1,4-bis(aminomethyl)cyclohexane, 4,4'-methylenebis(2-methylcyclohexylamine), 4,4'-methylene-bis(cyclohexylamine), m-phenylenediamine, p-phenylenediamine, 4-aminobenzylamine, 3-aminobenzylamine, The additives include at least one of 4-(2-aminoethyl)aniline, p-xylylenediamine, m-xylylenediamine, ethylene glycol, 1,3-propanediol, 1,4-butanediol, 1,2-ethanedithiol, 1,3-propanedithiol, 1,4-butanedithiol, (±)-3-amino-1,2-propanediol, glycerol, bis(hexamethylene)triamine, melamine, diethylenetriamine, (±)-1,2,4-butanetriol, cyanuric chloride, and trimethylaluminum.

[0006] In some embodiments, the deposition of the protective film in (b) occurs without exposing the substrate to plasma energy. In some embodiments, the protective coating comprises a polyazomethine or polythioacetal. In some embodiments, the etching of the feature into the stack in (a) occurs in a reaction chamber, and the deposition of the protective film on the sidewalls of the feature in (b) occurs in the same reaction chamber. In some embodiments, the etching reactants comprise one or more fluorocarbons or hydrofluorocarbons. In some embodiments, the deposition of the protective film in (b) occurs in a reaction chamber, and the deposition of the protective film in (b) further comprises purging the reaction chamber at least once between each repetition of operation (b). In some embodiments, the stack comprises alternating layers of (i) a silicon oxide material and (ii) a silicon nitride material or a polysilicon material. In some embodiments, the protective film is deposited along substantially the entire depth of the feature. In some embodiments, the feature has an aspect ratio of about 20 or greater at its final depth.

[0007] Another aspect of an embodiment of the present disclosure provides a method for forming an etched feature in a layer stack including a dielectric material on a semiconductor substrate. The method includes: (a) generating a first plasma comprising an etching reactant and exposing a substrate to the first plasma to partially etch a feature into a dielectric material; (b) after (a), depositing a protective film on sidewalls of the feature by: (i) exposing the substrate to a first reactant to adsorb the first reactant onto the substrate, the first reactant comprising an isocyanate functional group; (ii) exposing the substrate to a second reactant, the first and second reactants react with each other to form the protective film; and (iii) cyclically repeating (i) and (ii) until the protective film reaches a target thickness, the protective film being an organic polymer film; and (c) repeating (a)-(b) until the feature is etched to a final depth, the protective film deposited in (b) substantially prevents lateral etching of the feature during (a), and the feature has an aspect ratio of about 5 or greater at the final depth.

[0008] In some embodiments, the first reactant comprises a diisocyanate, optionally including at least one of tolylene 2,4-diisocyanate, 1,3-bis(isocyanatomethyl)cyclohexane, hexamethylene diisocyanate, m-xylylene diisocyanate, 1,3-bis(1-isocyanato-1-methylethyl)benzene, isophorone diisocyanate, diphenylmethane-4,4'-diisocyanate, 4,4'-methylene-bis(cyclohexylisocyanate), tolylene-2,6-diisocyanate, 1,4-phenylene diisocyanate, 1,3-phenylene diisocyanate, and 3,3'-dimethyl-4,4'-biphenylene diisocyanate.

[0009] In some embodiments, the second reactant comprises at least one of a diamine, a diol, a thiol, and a trifunctional compound. In some embodiments, the second reactant comprises a diamine. In some embodiments, the second reactant comprises 1,2-ethanediamine, 1,3-propanediamine, 1,4-butanediamine, ethylenediamine, m-xylylenediamine, isophoronediamine, 1,3-cyclohexanebis(methylamine), 1,4-bis(aminomethyl)cyclohexane, 4,4'-methylenebis(2-methylcyclohexylamine), 4,4'-methylene-bis(cyclohexylamine), m-phenylenediamine, p-phenylenediamine, 4-aminobenzylamine, 3-aminobenzylamine, The additives include at least one of 4-(2-aminoethyl)aniline, p-xylylenediamine, m-xylylenediamine, ethylene glycol, 1,3-propanediol, 1,4-butanediol, 1,2-ethanedithiol, 1,3-propanedithiol, 1,4-butanedithiol, (±)-3-amino-1,2-propanediol, glycerol, bis(hexamethylene)triamine, melamine, diethylenetriamine, (±)-1,2,4-butanetriol, cyanuric chloride, and trimethylaluminum.

[0010] In some embodiments, the deposition of the protective film in (b) is performed without exposing the substrate to plasma energy. In some embodiments, the protective coating comprises a polyurethane or a polyurea. In some embodiments, the etching of the feature into the stack in (a) is performed in a reaction chamber, and the deposition of the protective film on the sidewalls of the feature in (b) is performed in the same reaction chamber. In some embodiments, the etching reactants comprise one or more fluorocarbons or hydrofluorocarbons. In some embodiments, the deposition of the protective film in (b) is performed in a reaction chamber, and the deposition of the protective film in (b) further comprises purging the reaction chamber at least once between each repetition of operation (b). In some embodiments, the stack comprises alternating layers of (i) a silicon oxide material and (ii) a silicon nitride material or a polysilicon material. In some embodiments, the protective film is deposited along substantially the entire depth of the feature. In some embodiments, the feature has an aspect ratio of about 20 or greater at the final depth.

[0011] These and other features are described in detail below with reference to the associated drawings. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 shows an etched cylindrical hole having an undesirable curvature due to overetching of the sidewalls.

[0013] [Figure 2A] FIG. 2A presents a flow chart of a method for forming etched features on a semiconductor substrate according to various embodiments of the present disclosure.

[0014] [Figure 2B] FIG. 2B presents a flow chart of a method for depositing a protective film on the sidewalls of a partially etched feature in accordance with certain embodiments.

[0015] [Figure 2C] FIG. 2C shows a specific deposition reaction for forming a protective film where the reactants used include glutaraldehyde and ethylenediamine. [Figure 2D] FIG. 2D shows a specific deposition reaction for forming a protective film where the reactants used include glutaraldehyde and ethylenediamine.

[0016] [Figure 3A] FIG. 3A depicts a cylindrical hole etched in a semiconductor substrate as it is repeatedly etched and coated with a sidewall protective coating according to various embodiments. [Figure 3B] FIG. 3B depicts a cylindrical hole etched in a semiconductor substrate as it is repeatedly etched and coated with a sidewall protective coating according to various embodiments. [Figure 3C] FIG. 3C depicts a cylindrical hole etched in a semiconductor substrate as it is repeatedly etched and coated with a sidewall protective coating according to various embodiments. [Figure 3D] FIG. 3D depicts a cylindrical hole etched in a semiconductor substrate as it is repeatedly etched and coated with a sidewall protective coating according to various embodiments.

[0017] [Figure 4A] FIG. 4A illustrates a reaction chamber that can be used to carry out the etching processes described herein in accordance with certain embodiments. [Figure 4B] FIG. 4B illustrates a reaction chamber that can be used to carry out the etching processes described herein in accordance with certain embodiments. [Figure 4C] FIG. 4C illustrates a reaction chamber that can be used to carry out the etching processes described herein in accordance with certain embodiments.

[0018] [Diagram 5] FIG. 5 depicts a reaction chamber that can be used to carry out the deposition processes described herein in accordance with certain embodiments.

[0019] [Figure 6] FIG. 6 illustrates a multi-station apparatus that can be used to perform a deposition process in accordance with certain embodiments.

[0020] [Figure 7] FIG. 7 presents a cluster tool that can be used to perform both deposition and etching in accordance with certain embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of a number of stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the invention is implemented on a wafer. However, the invention is not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the invention include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0022] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The embodiments of the present disclosure may be practiced even if some or all of these specific details are absent. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Although the embodiments of the present disclosure will be described in conjunction with these specific embodiments, it will be understood that there is no intent to limit the embodiments of the present disclosure to these specific embodiments.

[0023] I. Technique for etching high aspect ratio features in dielectric materials - Patents.com The fabrication of certain semiconductor devices involves etching features into one or more dielectric materials. The dielectric material may be a single layer of material or a stack of materials. In some cases, the stack includes alternating layers of dielectric materials (e.g., silicon nitride and silicon oxide). One example of an etched feature is a cylindrical hole, which may have a high aspect ratio. As the aspect ratio of such features continues to increase, etching the features into the dielectric material becomes more difficult. One problem that arises during the etching of high aspect ratio features is a non-uniform etch profile. In other words, the feature is not etched downward in a straight line. Instead, the sidewalls of the feature are often curved such that the width of the middle of the etched feature is wider (i.e., etched further) than the top and / or bottom of the feature. Such overetching near the middle of the feature can compromise the structural and / or electrical integrity of the remaining material. The outwardly curved portion of the feature may occupy a relatively small or a relatively large portion of the overall depth of the feature. The outwardly curved portion of a feature is where the feature's critical dimension (CD) is maximum. The critical dimension corresponds to the diameter of the feature at a given location. In general, it is desirable for the maximum CD of a feature to be approximately the same as the CD in other parts of the feature, such as at or near the bottom of the feature.

[0024] Without being bound to a particular theory or mechanism of operation, it is believed that overetching in the middle of a cylindrical hole or other feature is caused, at least in part, by the sidewalls of the cylindrical hole being insufficiently protected from etching. Conventional etching chemistries use fluorocarbon etchants to form cylindrical holes in dielectric materials. The fluorocarbon etchants are excited by exposure to a plasma, which results in the formation of various fluorocarbon fragments, such as, for example, CF, CF2, and CF3. The reactive fluorocarbon fragments, with the assistance of ions, etch away the dielectric material at the bottom of the feature (e.g., cylindrical hole). Other fluorocarbon fragments are deposited on the sidewalls of the cylindrical hole being etched, thereby forming a polymer sidewall protective coating. This sidewall protective coating facilitates the selective etching of the bottom of the feature relative to the sidewalls of the feature. Without this sidewall protection, the feature would begin to have a non-uniform profile with wider etching / cylindrical holes in places where the sidewalls are insufficiently protected.

[0025] Sidewall protection is especially difficult to achieve in high aspect ratio features. One reason for the difficulty is the inability of existing fluorocarbon-based processes to form a polymer sidewall protective coating deep into the cylindrical hole being etched. FIG. 1 presents a diagram of a cylindrical hole 102 being etched into a dielectric material 103 that is covered with a patterned mask layer 106. While the following discussion may refer to a cylindrical hole, the concepts also apply to other feature shapes such as rectangles and other polygons. The polymer sidewall protective coating 104 is concentrated near the top of the cylindrical hole 102. Chemical C x F yprovides both the etching reactants for etching the cylindrical hole vertically and the reactants for forming the polymer sidewall protective coating 104. The polymer sidewall protective coating 104 does not extend deep into the cylindrical hole (i.e., there is insufficient sidewall deposition), so the middle of the cylindrical hole 102 is wider than the top of the cylindrical hole 102. The wider middle of the cylindrical hole 102 is referred to as the bow 105. The bow can be numerically described in terms of the critical dimension of the feature in the bowed region (the relatively wider region) compared to the critical dimension of the feature below the bowed region. The bow may be quantified and reported in terms of distance (e.g., the critical dimension at the widest part of the feature minus the critical dimension at the narrowest part of the feature below the bow) or in terms of ratio / percentage (the critical dimension at the widest part of the feature divided by the critical dimension at the narrowest part of the feature below the bow). This bow 105, and the associated non-uniform etch profile, is undesirable. Because of the high ion energies often used in this type of etching process, bowing is often produced when etching high aspect ratio cylindrical holes. In some applications, bowing is also produced at aspect ratios as small as 5. Thus, conventional fluorocarbon etch chemistries are typically limited to producing relatively small aspect ratio cylindrical holes in dielectric materials. Some advanced applications require cylindrical holes with higher aspect ratios than can be achieved with conventional etch chemistries.

[0026] II. Background and Application In various embodiments herein, features are etched into a substrate (typically a semiconductor wafer) having a dielectric material on its surface. The etching process is generally a plasma-based etching process. The overall feature formation process may be performed in stages. One stage is aimed at etching the dielectric material, and another stage is aimed at forming a sidewall protective coating without substantially etching the dielectric material. The sidewall protective coating passivates the sidewalls to prevent the feature from being over-etched (i.e., the sidewall coating prevents lateral etching of the feature). These two stages can be repeated until the feature is etched to its final depth. By repeating these two stages, the diameter of the feature can be controlled throughout the depth of the feature, thereby forming a feature with a more uniform diameter and improved profile.

[0027] A "feature" as used herein may refer to a non-planar structure of a substrate, typically a surface that is deformed in a manufacturing operation of a semiconductor device. Examples of features, also referred to as "negative features" and "recessed features", include trenches, holes, vias, gaps, recessed areas, and the like. These terms may be used interchangeably in this disclosure. An example of a feature is a recess in the surface of a substrate. Generally, a feature has an aspect ratio (ratio of depth to lateral dimension). A feature may be characterized by one or more of one or more narrow and / or recessed openings, constrictions within the feature, and high aspect ratios. A feature may have a wide variety of shapes, including, but not limited to, cylindrical, rectangular, square, or other polygonal recesses, trenches, and the like.

[0028] Aspect ratio is the comparison of the depth of a feature to the critical dimension of the feature (often its width / diameter). For example, a feature with a depth of 2 μm and a width of 50 nm has an aspect ratio of 40:1 (often more simply expressed as 40). A feature may have non-uniform critical dimensions across the depth of the feature, so the aspect ratio may vary depending on where it is measured. For example, an etched cylindrical hole may have a middle section that is wider than its top and bottom. This wider middle section may be referred to as a bend, as discussed above. An aspect ratio measured based on the critical dimension at the top (i.e., neck) of the cylindrical hole will be greater than an aspect ratio measured based on the critical dimension at the wider middle / bend of the cylindrical hole. As used herein, unless otherwise stated, aspect ratios are measured based on the critical dimension near the opening of the feature.

[0029] The features formed by the methods of the present disclosure can be high aspect ratio features. In some applications, high aspect ratio features are features having an aspect ratio of at least about 5, at least about 10, at least about 20, at least about 30, at least about 40, at least about 50, at least about 60, at least about 80, or at least about 100. The critical dimension of the features formed by the methods of the present disclosure can be about 200 nm or less, such as about 100 nm or less, about 50 nm or less, or about 20 nm or less.

[0030] In various cases, the material into which the features are etched may be a dielectric material. Exemplary materials include, but are not limited to, silicon oxide, silicon nitride, silicon carbide, oxynitride, oxycarbide, carbonitride, doped versions of these materials (e.g., doped with boron, phosphorus, etc.), and stacks of any combination of these materials. Specific examples of materials include stoichiometric and non-stoichiometric SiO2, SiN, SiON, SiOC, SiCN, etc. In various cases, the material or materials to be etched may also include other elements, such as hydrogen. In some embodiments, the nitride and / or oxide materials to be etched have a composition that includes hydrogen. As used herein, silicon oxide materials, silicon nitride materials, etc. include both stoichiometric and non-stoichiometric types, and it is understood that such materials may have other elements, as described above.

[0031] One application of the disclosed method relates to the formation of DRAM devices. In this case, the features may be etched primarily in silicon oxide. The substrate may further include, for example, one or more silicon nitride layers. In one example, the substrate includes a silicon oxide layer sandwiched between two silicon nitride layers, the silicon oxide having a thickness of about 800 nm to about 1200 nm, and the silicon nitride layer or layers having a thickness of about 300 nm to about 400 nm. The etched features may be cylindrical holes with a final depth of about 1 μm to about 3 μm, for example, about 1.5 μm to about 2 μm. The cylindrical holes may have a width of about 20 nm to about 50 nm, for example, about 25 nm to about 30 nm. After the cylindrical holes are etched, a capacitor memory cell can be formed therein.

[0032] Another application of the disclosed method relates to the formation of vertical NAND (VNAND, also called 3D NAND) devices. In this case, the materials into which features are etched may have a repeated stacked structure. For example, the materials may include alternating layers of oxide (e.g., SiO2) and nitride (e.g., SiN) or alternating layers of oxide (e.g., SiO2) and polysilicon. The alternating layers form pairs of materials. In some cases, the number of pairs may be at least 20, at least 30, at least 40, at least 60, or at least 70. The oxide layers may have a thickness of about 20 nm to about 50 nm, such as about 30 nm to about 40 nm. The nitride or polysilicon may have a thickness of about 20 nm to about 50 nm, such as about 30 nm to about 40 nm. The features etched into the alternating layers may have a depth of about 2 μm to about 6 μm, such as about 3 μm to about 5 μm. The features may be from about 50 nm to about 150 nm in width, for example from about 50 nm to about 100 nm.

[0033] III. Etch / Deposition Process FIG. 2A depicts a flow chart of a method for forming an etched feature in a semiconductor substrate. The operations depicted in FIG. 2A are described in conjunction with FIGS. 3A-3D, which show a partially fabricated semiconductor substrate as the feature is being etched. In operation 201, a feature 302 is etched to a first depth in a substrate having a dielectric material 303 and a patterned mask layer 306. This first depth is only a portion of the final desired depth of the feature. The chemistry used to etch the feature is a fluorocarbon-based chemistry (C x F y ) or hydrofluorocarbon-based chemicals (H x F y C z) may be used. Other etching chemistries may be used. As a result of this etching operation 201, a first sidewall coating 304 may be formed. The first sidewall coating 304 may be a polymer sidewall coating as described with respect to FIG. 1. The first sidewall coating 304 extends to the first depth, although in many cases the first sidewall coating 304 does not actually reach the bottom of the feature 302.

[0034] The first sidewall coating 304 is formed by the deposition of specific fluorocarbon species / fragments on the sidewall of the feature, which are then deposited on the sidewall of the feature. x F y It is formed indirectly from the etching chemistry (i.e., certain fluorocarbon species are precursors of the first sidewall coating 304). One reason why the first sidewall coating 304 does not reach the bottom of the feature 302 may be related to the sticking coefficient of the precursors that form the coating. In particular, it is believed that for certain etchants, the sticking coefficient of the precursors of the first sidewall coating is too high, so that most of the precursor molecules stick to the sidewalls immediately after entering the feature. Thus, few sidewall coating precursor molecules are able to penetrate deep into the feature to where sidewall protection would be beneficial. Thus, the first sidewall coating 304 provides only partial protection against over-etching the sidewalls of the feature 302. In some embodiments, the etching conditions provide little, if any, sidewall protection.

[0035] Next, in operation 203, the etching process is stopped. After etching is stopped, in operation 205, a second sidewall coating 310 is deposited. In some cases, the second sidewall coating 310 can be substantially the first sidewall coating. This deposition can be done by a variety of reaction mechanisms, such as chemical vapor deposition (CVD), atomic layer deposition (ALD) (either of which may or may not be plasma-assisted), and molecular layer deposition (MLD). MLD processes can deposit thin films of organic polymers using cycles similar to ALD involving two half-reactions. In some cases, MLD processes can be driven in a manner that is less adsorption limited than traditional ALD processes. For example, certain MLD processes may utilize undersaturation or supersaturation of reactants. ALD and MLD processes are particularly suited to forming conformal films that line the sidewalls of features in certain embodiments. For example, ALD and MLD processes are useful for delivering reactants deep into features due to the adsorption-related nature of such processes. Embodiments herein are not limited to methods in which the second sidewall coating 310 is deposited by layer-by-layer deposition methods such as ALD and MLD, but the method selected to deposit the second sidewall coating 310 should be capable of forming a protective layer deep into the etched feature 302. CVD and other deposition processes may be suitable for various embodiments.

[0036] FIG. 2B shows a flow chart of a method 250 of depositing a second organic polymer sidewall coating 310 by an MLD process. As mentioned above, ALD and CVD methods may also be used and are described in more detail below. The method 250 begins with operation 251, where a first reactant is flowed into a reaction chamber and adsorbed onto the substrate surface. The reactant may penetrate deep into the partially etched feature and adsorb onto the sidewalls of the feature. In some embodiments, the first reactant is a dialdehyde or trialdehyde. In a particular embodiment, the first reactant may be glutaraldehyde (C5H8O2). The first reactant forms an adsorbed layer, as shown in FIG. 3B as adsorbed precursor layer 312.

[0037] Next, in operation 253, the reaction chamber may be optionally purged to remove excess first reactant from the reaction chamber. Next, in operation 255, a second reactant is provided to the reaction chamber. In some embodiments, the second reactant may be a diamine, a diol, a thiol, or a trifunctional compound. In certain embodiments, the second reactant may be ethylenediamine (C2H8N2). The second reactant reacts with the first reactant to form a protective film on the substrate. The formed protective film may be a second sidewall coating 310, as shown in Figures 3C and 3D. The protective film may be formed by a thermal reaction without relying on a plasma.

[0038] The reaction chamber may then optionally be purged in operation 257. Purging in operations 253 and 257 may be performed by purging the reaction chamber with a non-reactive gas, by evacuating the reaction chamber, or by some combination of these. The purpose of purging is to remove unadsorbed reactants and by-products from the reaction chamber. Both purge operations 253 and 257 are optional; however, they may help prevent undesired gas-phase reactions, which may improve deposition results.

[0039] Next, in operation 259, it is determined whether the protective film is thick enough. Such a determination may be made based on the thickness deposited per cycle and the number of cycles performed. In various embodiments, a film of about 0.1 nm to about 1 nm is deposited in each cycle. The thickness is based on the length of time the reactants are flowed into the reaction chamber and the resulting level of saturation of the reactants. If the film is not thick enough, the method 250 repeats from operation 251 to add film thickness by depositing additional layers. Otherwise, the method 250 is complete. In subsequent iterations, operation 251 may include both adsorbing additional first reactants onto the substrate and reacting the first reactant with a second reactant that may be present from a previous iteration of operation 255. In other words, after the first cycle, both operations 251 and 255 may include a reaction between the first reactant and the second reactant. After the protective film is thick enough, the substrate may undergo another etching process, as shown in operation 211 of FIG. 2A.

[0040] In many cases, the deposition method 250 may be used to form a layer of an organic polymer film. FIG. 2C illustrates steps 251-257 of FIG. 2B in the particular situation where the first reactant is glutaraldehyde and the second reactant is ethylenediamine. In operation 251, the first reactant, glutaraldehyde, is flowed in a vapor phase into the reaction chamber and adsorbed onto the substrate 260. The portion of the substrate 260 shown in FIG. 2C is the sidewall of a partially etched cylindrical hole. In operation 253, the reaction chamber is optionally purged, for example, by flowing a non-reactive purge gas through the reaction chamber. In operation 255, the second reactant, ethylenediamine, is flowed in a vapor phase into the reaction chamber. The first and second reactants react to form a layer of an organic polymer film on the exposed surface of the substrate 260, for example along the sidewall of the partially etched feature. The reaction chamber may then optionally be purged, for example, by flowing another purge gas into the reaction chamber, in operation 257. These operations can be repeated until the organic polymer film is grown to a desired thickness.

[0041] 2D further illustrates the reaction that occurs in operation 255 when the first reactant is glutaraldehyde and the second reactant is ethylenediamine. Without being bound by any theory, the reaction shown in FIG. 2D may result in two types of reaction products. One reaction product may be shown in the first line and is a partial reaction product. The other reaction product may be shown in the second line and is a complete reaction product resulting in an imine product.

[0042] These reactants can be particularly useful in applications where it is desirable to form a protective film at a relatively low temperature. These reactants have been shown to react with each other effectively and efficiently at temperatures much lower than those typically used in similar MLD and ALD reactions. Many thermal ALD reactions (without plasma) are carried out at much higher temperatures, e.g., at least about 200° C. Deposition at low temperatures is particularly useful in certain situations. In some cases, the use of low temperature, non-plasma deposition may allow deposition in the same reaction chamber as the etching reaction, eliminating the need for transport between two different reaction chambers. The MLD process is further discussed in U.S. Patent Application Serial No. 14 / 446,427, entitled “METHOD OF CONDITIONING VACUUM CHAMBER OF SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS,” filed July 30, 2014, which is incorporated herein by reference in its entirety for all purposes.

[0043] The MLD method 250 of the present disclosure in FIG. 2B is well suited for forming conformal films that cover the entire sidewall of a feature. One reason why MLD methods can be particularly useful is that very high conformality can be achieved because the reaction is driven by thermal energy, not plasma energy. When plasma is used to generate one or more reactants in a plasma-assisted ALD approach, the resulting reactants may be radical species with high surface reactivity. Thus, this approach generates reactants with limited ability to penetrate into high aspect ratio features, resulting in less conformality and / or higher doses compared to thermal methods. Furthermore, because the plasmas used in semiconductor manufacturing are non-uniform in the reaction chamber, the non-uniformity of the plasma can result in non-uniform deposition results across the substrate. In contrast, it is easier to provide uniform thermal energy to the substrate, for example, by providing a uniform heat source on the substrate support. Plasma energy is often used to drive reactions at relatively low temperatures (e.g., less than about 200° C.). Often, semiconductor devices have a particular thermal history during fabrication, and care may be taken to process the substrate at low temperatures to reduce the thermal history and therefore avoid device damage. However, as previously mentioned, the use of plasma may also have a detrimental effect on conformality and / or uniformity. In various embodiments herein, certain reactants are used to deposit the protective layer at relatively low temperatures, thereby obtaining both the uniformity benefits associated with thermal processing and the low temperature / thermal history benefits often associated with plasma processing. One example of a set of reactants that can be used at relatively low temperatures to deposit the protective layer is glutaraldehyde and ethylenediamine, as discussed in connection with Figures 2C and 2D.

[0044] Returning to FIG. 2A, the method continues at operation 207 where the deposition process is stopped. The method then repeats the operations of partially etching the feature into the substrate (operation 211, similar to operation 201), stopping the etching (operation 213, similar to operation 203), depositing a protective coating on the sidewalls of the partially etched feature (operation 215, similar to operation 205), and stopping the deposition (operation 217, similar to operation 207). It is then determined in operation 219 whether the feature is fully etched. If the feature is not fully etched, the method repeats from operation 211 with additional etching and deposition of a protective coating. The etching operation 211 may alter the second sidewall coating 310 to form a film that is more etch resistant than the films deposited in operations 205 and 215. In one example, the deposition operation 205 is performed by method 250, which forms an organic polymer film layer that includes carbon, nitrogen, oxygen, and hydrogen. Once the feature is completely etched, the method is complete.

[0045] In various embodiments, the etching operation 201 and the sidewall protective coating deposition operation 205 are repeated many times in a cyclical manner. For example, these operations may each be performed at least twice (as shown in FIG. 2A), such as at least about three times, or at least about five times. In some cases, the number of cycles (each cycle includes the etching operation 201 and the sidewall protective coating deposition operation 205, with the etching operation 211 and the deposition operation 215 counting as a second cycle) is about 2-10 times, such as about 2-5 times. Each time an etching operation is performed, the etching depth increases. The distance etched may be uniform between cycles, or it may be non-uniform. In certain embodiments, the distance etched in each cycle is smaller with each additional etching (i.e., a later etching operation is less etched than an earlier etching operation). The thickness of the second sidewall coating 310 deposited in each deposition operation 205 may be uniform between cycles, or the thickness of such coating may vary. An example thickness of the second sidewall coating 310 during each cycle may range from about 1 nm to about 10 nm, such as from about 3 nm to about 5 nm. Furthermore, the type of coating formed may be uniform or may vary between cycles.

[0046] The etching operation 201 and the deposition operation 205 may occur in the same reaction chamber or in different reaction chambers. In one example, the first and second reaction chambers together form a multi-chamber processing apparatus, such as a cluster tool, with the etching operation 201 occurring in a first reaction chamber and the deposition operation 205 occurring in a second chamber. In certain cases, load locks and other suitable vacuum seals may be provided to transfer the substrate between the corresponding chambers. The substrate may be transferred by a robot arm or other mechanical structure. The reaction chamber used for etching (and possibly deposition) may be a FLEX. TM A reaction chamber, such as the 2300® FLEX available from Lam Research Corporation, Fremont, Calif. TMThe reaction chamber used for deposition may be a chamber from the Vector® product family or the Altus® product family, both available from Lam Research Corporation. Using a combined reactor for both etching and deposition may be beneficial in certain embodiments, as it avoids the need for substrate transfer. Using different reactors for etching and deposition may be beneficial in other embodiments, where it is preferred to specifically optimize the reactor for each operation. In certain embodiments, both the etching and deposition operations may be performed in the same reaction chamber (e.g., FLEX TM The deposition reaction is carried out in a reaction chamber (such as a MLD method, such as method 250 of FIG. 2B). Low temperature thermally driven deposition reactions are particularly well suited to be carried out in reaction chambers designed to perform etching. Related reaction chambers are described further below.

[0047] As described above, the deposition operation helps optimize the etching operation by forming a deep penetrating protective layer that minimizes or prevents lateral etching of the feature during the etching operation. This promotes the formation of etched features with very vertical sidewalls with very little or no curvature. In a particular embodiment, the final etched feature with an aspect ratio of at least about 80 has a curvature (measured as (widest critical dimension-narrowest critical dimension below)÷narrowest critical dimension above×100) of less than about 60%. For example, a feature with a widest CD of 50 nm and a narrowest CD of 40 nm (where the 40 nm CD is located below the 50 nm CD in the feature) has a curvature of 25% (100×(50 nm-40 nm)÷40 nm=25%). In another embodiment, the final etched feature with an aspect ratio of at least about 40 has a curvature of less than about 20%.

[0048] IV. Process operating materials and parameters A. Substrate The methods disclosed herein are particularly useful in etching semiconductor substrates having dielectric materials thereon. Examples of dielectric materials include silicon oxide, silicon nitride, silicon carbide, oxynitrides, oxycarbides, carbonitrides, doped materials of these materials (e.g., doped with boron, phosphorus, etc.), and stacks of any combination of these materials. Specific examples of materials include stoichiometric or non-stoichiometric SiO2, SiN, SiON, SiOC, SiCN, etc. As noted above, the dielectric material to be etched may include more than one type / layer of material. In certain cases, the dielectric material may be provided in alternating layers of SiN and SiO2 or alternating layers of polysilicon and SiO2. Further details are provided above. The substrate may have a mask layer covering the substrate that defines where the features are to be etched. In some cases, the mask layer is Si and may be about 500 nm to about 1500 nm thick.

[0049] B. Etching process In various embodiments, the etching process is a reactive ion etching process that includes flowing a chemical etchant into a reaction chamber (often through a showerhead), forming a plasma from the etchant, among other things, and exposing the substrate to the plasma. The plasma converts the etchant compound(s) into neutral and ionic species (e.g., CF, CF 2、 and CF3) (charged or neutral species). Often the plasma is a capacitively coupled plasma, but other types of plasma may be used as appropriate. Ions in the plasma are directed toward the wafer, where collisions etch the dielectric material.

[0050] An exemplary apparatus that can be used to perform the etching process is the 2300® FLEX™ available from Lam Research Corporation, Fremont, Calif. TMThis type of etch reactor is further described in U.S. Patent No. 8,552,334 and U.S. Patent No. 6,841,943, each of which is incorporated herein by reference in its entirety for all purposes.

[0051] A variety of reactant options are available for etching features in dielectric materials. In certain cases, the etching chemistry includes one or more fluorocarbons. In these and other cases, the etching chemistry may include other etchants, such as NF3. One or more co-reactants may also be provided. In some cases, oxygen (O2) is provided as a co-reactant. The oxygen may help to slow the formation of a sidewall protective polymer coating (e.g., first sidewall coating 304 in Figures 3A-3D).

[0052] In a particular embodiment, the etching chemistry includes a combination of fluorocarbons and oxygen. For example, in one example, the etching chemistry includes C4F6, C4F8, N2, CO, CF4, and O2. Other conventional etching chemistries may be used as well as non-conventional chemistries. The fluorocarbons may flow at a flow rate of about 0 sccm to about 500 sccm, for example, about 10 sccm to about 200 sccm. When C4F6 and C4F8 are used, the flow rate of C4F6 may range between about 10 sccm to about 200 sccm and the flow rate of C4F8 may range between about 10 sccm to about 200 sccm. The flow rate of oxygen may range between about 0 sccm to about 500 sccm, for example, between about 10 sccm to about 200 sccm. The flow rate of nitrogen may range between about 0 sccm to about 500 sccm, for example, between about 10 sccm to about 200 sccm. The flow rate of the tetrafluoromethane may range from about 0 sccm to about 500 sccm, for example, between about 10 sccm to about 200 sccm. The flow rate of the carbon monoxide may range from about 0 sccm to about 500 sccm, for example, between about 10 sccm to about 200 sccm. These flow rates are suitable for a reactor volume of about 50 liters.

[0053] In some embodiments, the substrate temperature during etching is between about 30° C. and about 200° C. In some embodiments, the pressure during etching is between about 5 mTorr and about 80 mTorr. The ion energy may be relatively high, for example, between about 1 kV and about 10 kV. The ion energy is determined by the applied RF power. In various cases, a dual frequency RF power is used to generate the plasma. Thus, the RF power may include a first frequency component (e.g., about 2 MHz) and a second frequency component (e.g., about 60 MHz). Different powers may be provided at each frequency component. For example, the first frequency component (e.g., about 2 MHz) may be provided at a power of about 3 kW to about 24 kW, for example, about 10 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a lower power of about 0.5 kW to about 10 kW, for example, about 2 kW. In some embodiments, three different frequencies of RF power are used to generate the plasma. For example, the combination may be 2 MHz, 27 MHz, and 60 MHz. The power level of the third frequency component (e.g., about 27 MHz) may be similar to the power level specified above for the second frequency component. These power levels assume that the RF power is delivered to a single 300 mm wafer. The power levels may be scaled proportionally based on the substrate area of ​​additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In some embodiments, the RF power applied during etching may be modulated between high and low power at a repetition frequency between about 100 Hz and about 40,000 Hz.

[0054] Each cycle of the etching process etches the dielectric material to some extent. The distance etched during each etching cycle may be from about 10 nm to about 500 nm, such as from about 50 nm to about 200 nm. The total etch depth depends on the particular application. In some cases (e.g., DRAM), the total etch depth may be from about 1.5 μm to about 2 μm. In other cases (e.g., VNAND), the total etch depth may be at least about 3 μm, such as at least about 4 μm. In these or other cases, the total etch depth may be about 5 μm or less.

[0055] As mentioned in the description of Figures 3A-3D, the etch process can produce a first sidewall coating (e.g., first sidewall coating 304, which may be a polymer). However, the depth of this sidewall coating may be limited to an area near the top of the feature and may not extend all the way into the feature where sidewall protection is also required. Therefore, as described herein, a separate deposition operation is performed to form a sidewall coating that covers the deeper portions of the etch feature.

[0056] C. Deposition Process The deposition process is primarily performed to deposit a protective layer on the sidewalls in the etched feature. This protective layer needs to extend deep into the feature, even for high aspect ratio features. Forming a protective layer deep into a high aspect ratio feature may be possible with reactants that have a relatively low sticking coefficient. In addition, reaction mechanisms that rely on adsorption of reactants (e.g., ALD and MLD reactions) may facilitate the formation of a protective layer deep into the etched feature. Deposition of the protective layer begins after the feature is partially etched. As mentioned in the description of FIG. 2A, the deposition operation may be repeated along with the etching operation to form additional sidewall protection as the feature is etched deeper into the dielectric material. In some cases, deposition of the protective layer begins at or after the feature is etched to at least about 1 / 3 of its final depth. In some embodiments, deposition of the protective layer begins when the feature reaches an aspect ratio of at least about 2, at least about 5, at least about 10, at least about 15, at least about 20, or at least about 30. In these or other cases, deposition may begin before the feature aspect ratio reaches at least about 4, about 10, about 15, about 20, about 30, about 40, or about 50. In some embodiments (e.g., in VNAND embodiments with a final feature depth of 3-4 μm), deposition begins after the feature is at least about 1 μm deep, or at least about 1.5 μm deep. In other embodiments (e.g., in DRAM embodiments with a final feature depth of 1.5-2 μm), deposition begins after the feature is at least about 600 nm deep, or at least about 800 nm deep. The optimal time to begin deposition of the protective layer is just before the point at which the sidewalls would otherwise be overetched and bowed. The exact time at which this occurs depends on the shape of the feature being etched, the material being etched, the chemistries used to etch and deposit the protective layer, and the process conditions used to etch and deposit the associated materials.

[0057] The protective layer that forms during the deposition process may have a variety of compositions. As mentioned above, the protective layer must penetrate deep into the etched features and must be relatively resistant to the etching chemicals used to etch the features. In some cases, the protective layer is a ceramic material or an organic polymer. In some cases, examples of organic materials may include polyolefins, such as polyfluoroolefins. One specific example is polytetrafluoroethylene. The precursor fragment used to form some polyfluoroolefins is CF2 (which may be derived from hexafluoropropylene oxide (HFPO) in certain cases). CF2 has a very low sticking coefficient and therefore is prone to penetrate deep into the etched features.

[0058] In certain embodiments, the protective layer formed during the deposition process is an organic polymer. In some cases, the organic polymer is a polyazomethine. In some cases, the polyazomethine protective layer is formed from a combination of an amine (e.g., a diamine) and an aldehyde (e.g., a dialdehyde). In some cases, the organic polymer is a polythioacetal. For example, the polythioacetal protective layer is formed from a combination of an aldehyde (e.g., a dialdehyde) and a thiol. In some cases, the organic polymer is a polyurea. For example, the polyurea protective layer is formed from a combination of an isocyanate (e.g., a diisocyanate) and an amine (e.g., a diamine). In some cases, the organic polymer is a polyurethane. Specifically, the polyurethane protective layer is formed from a combination of an isocyanate (e.g., a diisocyanate) and an alcohol (e.g., a diol). For example, as shown in Figures 2C and 2D, in various embodiments, such reactants may be used in the MLD process to form the protective layer.

[0059] If the protective film contains nitrogen (e.g., a nitrogen-containing polymer), a nitrogen-containing reactant may be used. The nitrogen-containing reactant contains at least one nitrogen, for example, at least one of nitrogen, ammonia, hydrazine, methylamine, dimethylamine, ethylamine, ethylenediamine, isopropylamine, t-butylamine, di-t-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isoamylamine, 2-methylbutan-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, and di-t-butylhydrazine (e.g., carbon-containing amines), and aromatic-containing amines, such as aniline, pyridine, and benzylamine. The amines may be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). The nitrogen-containing reactant may contain heteroatoms other than nitrogen. For example, hydroxylamine, t-butyloxycarbonylamine, and Nt-butylhydroxylamine are nitrogen-containing reactants. Another example is nitrous oxide.

[0060] If the protective coating contains oxygen (e.g., an oxygen-containing polymer), an oxygen-containing reactant may be used. Examples of oxygen-containing reactants include oxygen, ozone, nitrous oxide, nitric oxide, nitrogen dioxide, carbon monoxide, sulfur oxides, sulfur dioxide, oxygen-containing hydrocarbons (C x H y O z ), water, acyl halides, acid anhydrides, mixtures thereof, etc. The precursors of the present disclosure are not intended to be limiting.

[0061] In certain embodiments in which the protective coating comprises an organic polymer, the first reactant may be an acyl halide (e.g., a diacyl halide), such as an acyl chloride (e.g., a diacyl chloride) (although in some cases other acyl halides may be used). In various embodiments, the first reactant diacyl chloride may be ethanediyl dichloride (also called oxalyl dichloride, ClCOCOCl), malonyl dichloride (also called malonyl chloride, CH2(COCl)2), succinyl dichloride (also called succinyl chloride, ClCOCH2CH2COCl), pentanediyl dichloride (also called glutaryl chloride, ClCO(CH2)3COCl), or a combination thereof. In some other embodiments, the first reactant may be an acid anhydride, such as an anhydride of a dicarboxylic acid that produces any of the diacyl chlorides described above. One example of an acid anhydride that may be used is maleic anhydride. In yet other embodiments, the first reactant may be an organometallic precursor, one example of which is trimethylaluminum (TMA).

[0062] In certain embodiments in which the protective coating comprises an organic polymer, the first reactant may alternatively be an aldehyde (e.g., a dialdehyde or trialdehyde) or may at least include an aldehyde functional group. In various embodiments, the first reactant may be succinaldehyde (C4H6O2), glutaraldehyde (C5H8O2), adipaldehyde (C6H 10 O2), terephthalaldehyde (C8H6O2), 1,4-benzenedicarboxaldehyde (C6H4(CHO)2), orthophthalaldehyde (C8H6O2), 1,2-benzenedicarboxaldehyde (C6H4(CHO)2), 2-methylglutaraldehyde (C6H 10 O2), or a combination of these.

[0063] In some embodiments in which the protective coating comprises an organic polymer, the first reactant may alternatively be an isocyanate (e.g., a diisocyanate) or may include at least an isocyanate functional group. In some cases, the diisocyanate may be tolylene 2,4-diisocyanate, 1,3-bis(isocyanatomethyl)cyclohexane, hexamethylene diisocyanate, m-xylylene diisocyanate, 1,3-bis(1-isocyanato-1-methylethyl)benzene, isophorone diisocyanate, diphenylmethane-4,4'-diisocyanate, 4,4'-methylene-bis(cyclohexylisocyanate), tolylene-2,6-diisocyanate, 1,4-phenylene diisocyanate, 1,3-phenylene diisocyanate, 3,3'-dimethyl-4,4'-biphenylene diisocyanate, or a combination thereof.

[0064] In some embodiments, aldehydes or isocyanates may be used as alternatives to acyl chlorides, which may have a tendency to self-react, resulting in short shelf life even at low temperatures.

[0065] Dialdehydes are generally more stable than acyl chlorides, such as diacyl chlorides. Dialdehydes also tend to be more volatile than acyl chlorides, such as diacyl chlorides. Dialdehydes typically have a higher vapor pressure, making them more volatile and more accessible to the substrate. Higher dose pressures reduce dose times, which in turn reduces deposition process times, thus improving throughput. Thus, repeated deposition and etch processes can be performed without the formation of recessed features being significantly slowed by the deposition process.

[0066] The dialdehyde may have a tendency to adhere to surfaces that have been etched. Without being bound by any theory, the dialdehyde may have a tendency to adhere to surfaces that have been etched with fluorocarbon chemistries. One of the challenges with depositing a conformal liner by MLD is initiating deposition on the etched surface. The dialdehyde selectively adheres to surfaces that have been etched with fluorocarbon or hydrofluorocarbon chemistries to improve initiation of the formation of a protective film on the sidewalls in the etch feature.

[0067] When the protective coating comprises an organic polymer, the second reactant may comprise an amine or alcohol functional group. In these or other embodiments in which the protective coating comprises an organic polymer, the second reactant may be a diamine. In some cases, the diamine may be 1,2-ethanediamine (also called ethylenediamine, (NH2(CH2)2NH2)), 1,3-propanediamine (NH2(CH2)3NH2), 1,4-butanediamine (NH2(CH2)4NH2), or a combination thereof. In some cases, the diamine may be ethylenediamine, m-xylylenediamine, isophoronediamine, 1,3-cyclohexanebis(methylamine), 1,4-bis(aminomethyl)cyclohexane, 4,4'-methylenebis(2-methylcyclohexylamine), 4,4'-methylene-bis(cyclohexylamine), m-phenylenediamine, p-phenylenediamine, 4-aminobenzylamine, 3-aminobenzylamine, 4-(2-aminoethyl)aniline, p-xylylenediamine, m-xylylenediamine, or combinations thereof. In some cases, the second reactant may be a diol. Examples of diols include ethylene glycol, 1,3-propanediol, 1,4-butanediol, or combinations thereof. In some cases, the second reactant may be a thiol. Examples of thiols include 1,2-ethanedithiol, 1,3-propanedithiol, 1,4-butanedithiol, or combinations thereof. In certain embodiments, the second reactant may be a trifunctional compound such as (±)-3-amino-1,2-propanediol, glycerol, bis(hexamethylene)triamine, melamine, diethylenetriamine, (±)-1,2,4-butanetriol, cyanuric chloride, or combinations thereof.

[0068] In certain embodiments, a dialdehyde, such as glutaraldehyde, may be used in conjunction with ethylenediamine to form a polyamide protective coating. When the first reactant is a dialdehyde and the second reactant is a diamine, the deposited organic polymer protective coating may have greater etch resistance than when the first reactant is an acyl halide. In fact, the deposited organic polymer protective coating may be more resistant to plasma etching, thereby providing an effective sidewall protection against lateral etching of the dielectric material during subsequent etching operations.

[0069] In some embodiments, the organic polymer protective coating may be deposited as an in-situ process in an etching reactor. The dialdehyde may react with the diamine at a relatively low temperature (e.g., less than 100° C.) and a relatively low dose (e.g., less than 10 Torr sec). Thus, the organic polymer coating may be deposited in the reaction chamber between etching operations without the introduction of an air break. In some embodiments, the deposition of the organic polymer coating may occur in the same reaction chamber as the etching operation during the formation of recessed features in the substrate.

[0070] In another particular embodiment, a diisocyanate may be used in conjunction with ethylene diamine to form a polyurea protective coating.

[0071] Examples of purge gases are He, Ar, Ne, H2, N 2、 and combinations thereof, but are not limited to these.

[0072] Other reactants may be used as known to those skilled in the art, for example, if the protective coating comprises a metal, a metal-containing reactant may be used, if the protective coating comprises carbon, a carbon-containing reactant may be used, etc.

[0073] Some specific examples of reactant combinations are provided, but these examples are not intended to be limiting. In one example, a dialdehyde, such as glutaraldehyde, is adsorbed onto the surface of a substrate to form a precursor film. As shown in Figures 2C and 2D, the precursor film may be exposed to ethylenediamine, thereby forming an organic polymer protective film. This reaction may occur without exposure to a plasma, instead relying on thermal energy to drive the reaction. As noted above, these reactants have been shown to react at relatively low temperatures, even in the absence of plasma energy.

[0074] As noted above, the precursors used to form the protective layer may have a relatively low sticking coefficient, allowing the precursor to penetrate deep into the etched features. In some cases, the sticking coefficient of the precursor (at the relevant deposition conditions) may be about 0.05 or less, such as about 0.001 or less.

[0075] The reaction mechanism may be cyclic (e.g., ALD or MLD) or continuous (e.g., CVD). Any method capable of forming a sidewall protective film with a high aspect ratio may be used. As mentioned above, ALD and MLD reactions may be particularly suitable for this purpose due to their conformal and adsorption-based mechanism. However, other types of reactions may be used as long as the film can be formed with a high aspect ratio to protect sidewalls deep within the etched features.

[0076] Briefly, a plasma-assisted ALD reaction involves (a) supplying a first reactant to form an adsorbed precursor layer; (b) optionally purging to remove the first reactant from the reaction chamber; (c) supplying a second reactant (often supplied in the form of a plasma) and using plasma energy to drive a reaction between the first and second reactants; (d) optionally purging to remove excess reactant and by-products; and (e) cyclically repeating (a)-(d) until the film reaches a desired thickness.

[0077] Similarly, the MLD reaction includes cyclically (a) supplying a first reactant to form an adsorbed precursor layer, (b) optionally purging to remove unadsorbed first reactant from the reaction chamber, (c) supplying a second reactant and using thermal energy to drive a reaction between the first reactant and the second reactant to form a protective film, (d) optionally purging to remove unadsorbed reactant and by-products, and (e) repeating (a)-(d) until the protective film reaches a desired thickness. The first and second reactants may be supplied in the gas phase, and the reaction may occur without the use of a plasma.

[0078] In the case of ALD and MLD methods, reactants are delivered at separate times and the reactions are surface reactions, so the film may be adsorption limited to some extent. This adsorption-based format results in the formation of a very conformal film that can line substantially the entire depth of the feature. In various cases, the protective film may be deposited along a significant percentage of the length / depth of the partially etched feature. In some cases, the protective film may be deposited along at least about 80%, at least about 90%, or at least about 95% of the length / depth of the feature. In certain embodiments, the protective film is deposited along the entire length / depth of the feature. On the other hand, plasma-assisted CVD reactions involve the continuous delivery of reactant(s) to the substrate while the substrate is exposed to a plasma. The CVD reaction is a gas-phase reaction that deposits reaction products on the substrate surface.

[0079] The following reaction conditions may be used in certain embodiments where the deposition reaction occurs by the MLD method. The conditions are described in relation to method 250 shown in FIG. 2B. In operation 251, a first reactant may be flowed into the reaction chamber. In certain embodiments, the first reactant may flow at a flow rate of about 0.1 sccm to about 5000 sccm, e.g., about 500 sccm to about 2000 scc, for about 0.1 seconds to about 30 seconds, e.g., about 0.2 seconds to about 5 seconds. In operation 253, the reaction chamber may be optionally purged for about 0.05 seconds to about 10 seconds, e.g., about 0.2 seconds to about 3 seconds. Purging may be performed by evacuating the reaction chamber and / or flowing an inert gas through the reaction chamber. In some cases, if an inert gas is used, the inert gas may flow at a flow rate of about 20 sccm to about 5000 sccm. Then, in operation 255, a second reactant may be flowed into the reaction chamber. In certain embodiments, the second reactant may flow at a flow rate of about 10 sccm to about 5000 sccm, or about 500 sccm to about 2000 sccm, for about 0.1 seconds to about 30 seconds, for example, about 0.2 seconds to about 5 seconds.

[0080] Thermal energy may be provided to drive the reaction between the first reactant and the second reactant. Thermal energy is available in a range controlled primarily by the temperature of the substrate. In some cases, thermal energy may be controlled by adjusting the substrate temperature via the substrate support / pedestal. In these or other cases, thermal energy may be provided by supplying reactants at a particular temperature. In some cases, the substrate temperature may be maintained at about -10°C to about 350°C, such as about 0°C to about 200°C, about 10°C to about 100°C, or about 20°C to about 50°C. In certain embodiments, the substrate is maintained below about 200°C, below about 100°C, below about 50°C, or below about 30°C. In these or other embodiments, the temperature of one or both reactant gases (and / or the inert gas used for purging) supplied to the reaction chamber may correspond to the substrate temperature indicated in this paragraph. In operation 257, the reaction chamber may be optionally purged using the conditions described above with respect to operation 253. In operation 259, it is determined whether the protective film is thick enough. If not, the method repeats from operation 251. In some cases, the pressure in the reaction chamber may be from about 1 Torr to about 4 Torr. In various cases, the protective film in each iteration of operation 205 or 215 of FIG. 2A may be deposited for about 10 minutes or less.

[0081] In certain embodiments, the end of the molecule forming the organic polymer film may form a hydroxyl, an amine, or a thiol. For example, when a diamine is used as the second reactant, -NH2 may form the end of the molecule forming the organic polymer film. When a diol is used as the second reactant, -OH may form the end of the molecule forming the organic polymer film. Similarly, when a thiol is used as the second reactant, -SH may form the end of the molecule forming the organic polymer film.

[0082] In certain embodiments, the first reactant and the second reactant used to form the organic polymer film may be flowed into the vacuum chamber until reaching about 100% saturation on the surfaces exposed to the plasma or process gas of the vacuum chamber to maximize the layer thickness of the organic polymer film deposited on the surfaces exposed to the plasma or process gas of the vacuum chamber. In some embodiments, undersaturation and supersaturation may also be performed, for example to adjust the deposition rate as desired.

[0083] The reaction conditions herein are provided as a guide and are not intended to be limiting.

[0084] V. Device The methods described herein may be implemented by any suitable apparatus or combination of apparatus. Suitable apparatus includes hardware for performing process operations and a system controller having instructions for controlling the process operations in accordance with the present invention. For example, in some embodiments, the hardware may include one or more process stations included in a process tool. One process station may be an etch station and another process station may be a deposition station. In another embodiment, etching and deposition are performed in a single station / chamber.

[0085] 4A-4C show an embodiment of an adjustable gap capacitively coupled enclosed RF plasma reactor 400 that may be used to perform the etching operations described herein. As shown, a vacuum chamber 402 includes a chamber housing 404 that encloses an interior space that houses a lower electrode 406. At the top of the chamber 402, an upper electrode 408 is located vertically spaced apart from the lower electrode 406. The planes of the upper electrode 408 and the lower electrode 406 are substantially parallel and perpendicular to the vertical direction between the electrodes. The upper electrode 408 and the lower electrode 406 are preferably circular and concentric about a vertical axis. The lower surface of the upper electrode 408 faces the upper surface of the lower electrode 406. The spaced apart opposing electrode surfaces define an adjustable gap 410 therebetween. In operation, the lower electrode 406 is supplied with RF power by an RF power source (matcher) 420. RF power is supplied to the lower electrode 406 through RF supply line 422, RF straps 424, and RF power member 426. A ground shield 436 may surround the RF power member 426 to provide a more uniform RF electric field to the lower electrode 406. A wafer is inserted through a wafer port 482 and supported on the lower electrode 406 in the gap 410 for processing, and process gas is supplied to the gap 410 and excited into a plasma state by RF power, as described in commonly owned U.S. Pat. No. 7,732,728, the entire contents of which are incorporated herein by reference. The upper electrode 408 may be powered or grounded.

[0086] 4A-4C, the bottom electrode 406 is supported on a bottom electrode support plate 416. An insulator ring 414 sandwiched between the bottom electrode 406 and the bottom electrode support plate 416 insulates the bottom electrode 406 from the support plate 416.

[0087] An RF bias housing 430 supports the lower electrode 406 on an RF bias housing bowl 432. The bowl 432 is connected by an arm 434 of the RF bias housing 430 to a conduit support plate 438 through an opening in the chamber wall plate 418. In a preferred embodiment, the RF bias housing bowl 432 and the RF bias housing arm 434 are integrally molded as one component, however, the arm 434 and bowl 432 may be two separate components that are bolted or otherwise joined together.

[0088] The RF bias housing arm 434 includes one or more hollow passages in the space behind the lower electrode 406 for passing RF power and equipment such as cables for gas coolant, liquid coolant, RF energy, lift pin control, electrical monitoring, and operating signals from outside the vacuum chamber 402 to the interior of the vacuum chamber 402. RF supply conduit 422 is insulated from the RF bias housing arm 434 providing a return path for RF power to the RF power source 420. Equipment conduit 440 provides a passage for equipment components. Further details regarding equipment components are described in U.S. Pat. Nos. 5,948,704 and 7,732,728 and are not shown here for brevity. The gap 410 is preferably surrounded by a confinement ring assembly or shroud (not shown), details of which can be found in commonly owned published U.S. Pat. No. 7,740,736, which is incorporated herein by reference. The interior of the vacuum chamber 402 is maintained at low pressure by connection to a vacuum pump through a vacuum portal 480.

[0089] The conduit support plate 438 is attached to an actuation mechanism 442. Details of the actuation mechanism are described in commonly owned U.S. Patent No. 7,732,728, incorporated herein by reference above. The actuation mechanism 442, such as a servomechanism motor, stepper motor, or the like, is attached to a vertical linear bearing 444 by a screw gear 446, such as a ball screw and a motor that rotates the ball screw. During the operation of adjusting the size of the gap 410, the actuation mechanism 442 moves along the vertical linear bearing 444. FIG. 4A shows the arrangement when the actuation mechanism 442 is in a high position on the linear bearing 444, resulting in a small gap 410a. FIG. 4B shows the arrangement when the actuation mechanism 442 is in an intermediate position on the linear bearing 444. As shown, the lower electrode 406, the RF bias housing 430, the conduit support plate 438, and the RF power supply 420 have all moved below the chamber housing 404 and the upper electrode 408, resulting in a medium sized gap 410b.

[0090] 4C shows the large gap 410c when the actuation mechanism 442 is in the low position of the linear bearing. The upper electrode 408 and the lower electrode 406 are preferably kept coaxial during gap adjustment, and the facing surfaces of the upper and lower electrodes across the gap are preferably kept parallel.

[0091] This embodiment allows for an adjustable gap 410 between the bottom electrode 406 and the top electrode 408 in the CCP chamber 402 during a multi-step process recipe (such as BARC, HARC, and STRIP) to maintain uniform etching across a large diameter substrate, such as a 300 mm wafer or flat panel display. In particular, the chamber is suited for a mechanical arrangement that allows for the linear motion necessary to provide an adjustable gap between the bottom electrode 406 and the top electrode 408.

[0092] 4A shows a laterally biased bellows 450 sealed at its proximal end to a conduit support plate 438 and at its distal end to a stepped flange 428 of a chamber wall plate 418. The inner diameter of the stepped flange defines an opening 412 in the chamber wall plate 418 through which an RF bias housing arm 434 passes. The distal end of the bellows 450 is clamped by a clamp ring 452.

[0093] The laterally deflected bellows 450 provides a vacuum seal while allowing vertical movement of the RF bias housing 430, the conduit support plate 438, and the actuation mechanism 442. The RF bias housing 430, the conduit support plate 438, and the actuation mechanism 442 may be referred to as a cantilever assembly. The RF power supply 420 preferably moves with the cantilever assembly and is attachable to the conduit support plate 438. FIG. 4B shows the bellows 450 in a neutral position when the cantilever assembly is in an intermediate position. FIG. 4C shows the laterally deflected bellows 450 when the cantilever assembly is in a low position.

[0094] A labyrinth seal 448 provides a particle barrier between the bellows 450 and the interior of the plasma processing chamber housing 404. A fixed shield 456 is fixed inside the inner wall of the chamber housing 404 at the chamber wall plate 418 to provide a labyrinth groove 460 (slot) in which a movable shield plate 458 moves vertically to accommodate vertical movement of the cantilever assembly. An outer portion of the movable shield plate 458 remains within the slot at all vertical positions of the lower electrode 406.

[0095] In the illustrated embodiment, the labyrinth seal 448 includes a fixed shield 456 attached to the inner surface of the chamber wall plate 418 around an opening 412 in the chamber wall plate 418 that defines a labyrinth groove 460. A movable shield plate 458 is attached extending radially from the arm 434 as the RF bias housing arm 434 passes through the opening 412 and into the labyrinth groove 460. The movable shield plate 458 is spaced a first gap from the fixed shield 456 and a second gap from the inner surface of the chamber wall plate 418 to allow vertical movement of the cantilever assembly. The labyrinth seal 448 prevents migration of particles that are dislodged from the bellows 450 into the vacuum chamber interior 405 and prevents migration of radicals from the process gas plasma into the bellows 450 where the radicals may form deposits that subsequently dislodge.

[0096] FIG 4A shows the movable shield plate 458 in a high position in the labyrinth groove 460 above the RF bias housing arm 434 when the cantilever assembly is in a high position (small gap 410a). FIG 4C shows the movable shield plate 458 in a low position in the labyrinth groove 460 above the RF bias housing arm 434 when the cantilever assembly is in a low position (large gap 410c). FIG 4B shows the movable shield plate 458 in a neutral or intermediate position in the labyrinth groove 460 when the cantilever assembly is in an intermediate position (medium gap 410b). Although the labyrinth seal 448 is shown symmetric about the RF bias housing arm 434, in alternative embodiments the labyrinth seal 448 may be asymmetric about the RF bias arm 434.

[0097] FIG. 5 is a simplified block diagram depicting various reactor components arranged to carry out the deposition methods described herein. As shown, the reactor 500 includes a process chamber 524 that surrounds the other components of the reactor and functions to contain a plasma generated by a capacitive discharge system including a showerhead 514 in cooperation with a grounded heater block 520. A high frequency (HF) radio frequency (RF) generator 504 and a low frequency (LF) RF generator 502 may be connected to a matching network 506 and the showerhead 514. The power and frequency provided by the matching network 506 may be sufficient to generate a plasma from process gases provided to the process chamber 524. For example, the matching network 506 may provide 50W to 500W of HFRF power. In some examples, the matching network 506 may provide a total energy of 100W to 5000W of HFRF power and 100W to 5000W of LFRF power. In a typical process, the HF RF component may typically be between 5 MHz and 60 MHz, for example 13.56 MHz. In operations where an LF component is present, the LF component may be approximately 100 kHz to 2 MHz, for example 430 kHz.

[0098] A wafer pedestal 518 may support the substrate 516 within the reactor. The wafer pedestal 518 may include a chuck, forks, or lift pins (not shown) for holding and transporting the substrate during or between deposition and / or plasma processing reactions. The chuck may be an electrostatic chuck, a mechanical chuck, or other type of chuck available for use in industry and / or research.

[0099] Various process gases may be introduced through inlets 512. A number of source gas lines 510 are connected to a manifold 508. The gases may or may not be premixed. Appropriate valve and mass flow control mechanisms may be employed to ensure the correct process gases are supplied during the deposition and plasma treatment stages of the process. If the chemical precursor(s) are supplied in liquid form, liquid flow control mechanisms may be employed. Such liquids may then be vaporized during delivery and mixed with the process gases in a manifold heated to a temperature above the vaporization point of the chemical precursors supplied in liquid form before reaching the deposition chamber.

[0100] Process gases may exit the chamber 524 through an outlet 522. A closed-loop controlled flow restriction device, such as a throttle valve or pendulum valve, may be used to draw the process gases out of the process chamber 524, and a vacuum pump, such as a single- or two-stage dry mechanical pump and / or a turbomolecular pump 540, may be used to maintain a moderately low pressure within the process chamber 524.

[0101] As mentioned above, the techniques for deposition described herein may be implemented in a multi-station or single station tool. In a particular embodiment, a 300 mm Lam Vector 4-station deposition setup is used. TM Tool or Sequel for 200mm with 6-station deposition mechanism TM A tool may be used. In some embodiments, a tool for processing 450 mm wafers may be used. In various embodiments, the wafer may be indexed after every deposition and / or after a post-deposition plasma treatment. Alternatively, the wafer may be indexed after an etching operation if the etch chamber or etching station is also part of the same tool. Alternatively, processing may be performed at a single station before the wafer is indexed.

[0102] In some embodiments, an apparatus configured to perform the techniques described herein may be provided. A suitable apparatus may include hardware for performing various process operations and a system controller 530 having instructions for controlling the process operations according to embodiments of the present disclosure. The system controller 530 generally includes one or more memory devices and one or more processors communicatively coupled to various process control devices, e.g., valves, RF generators, wafer handling systems, etc., and configured to execute instructions such that the apparatus performs the techniques according to embodiments of the present disclosure. A machine-readable medium including instructions for controlling the process operations according to the present disclosure may be coupled to the system controller 530. The system controller 530 may be communicatively coupled to various hardware devices, e.g., mass flow controllers, valves, RF generators, vacuum pumps, etc., to facilitate control of various process parameters associated with the deposition operations described herein.

[0103] In some embodiments, the system controller 530 may control all operations of the reactor 500. The system controller 530 may execute system control software stored on a mass storage device, loaded into a memory device, and executed on a processor. The system control software may include instructions for controlling timing of gas flows, wafer movement, activation of RF generators, etc., as well as instructions for controlling the mixture of gases, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestal position, chuck position, and / or susceptor position, and other parameters of the particular process being performed by the reactor apparatus 500. The system control software may be configured in any suitable manner. For example, subroutines or control objects of the various process tool components may be written to control the operation of the process tool components necessary to perform the processes of the various process tools. The system control software may be coded in any suitable computer readable programming language.

[0104] The system controller 530 may typically include one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs techniques in accordance with the present disclosure. A machine-readable medium containing instructions for controlling process operations in accordance with embodiments of the present disclosure may be coupled to the system controller 530.

[0105] A multi-station processing tool may include one or more process stations. FIG. 6 shows a schematic diagram of an embodiment of a multi-station processing tool 600 comprising an input load lock 602 and an output load lock 604. Either or both of the input load lock 602 and the output load lock 604 may include a remote plasma source. A robot 606 is configured to move a wafer from a cassette loaded from a pod 608 into the input load lock 602 through an atmospheric vent 610 at atmospheric pressure. The wafer is placed on a pedestal 612 of the input load lock 602 by the robot 606, the atmospheric vent 610 is closed, and the load lock is pumped down. If the input load lock 602 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment in the load lock before being introduced into the processing chamber 614. Additionally, the wafer may be heated in the input load lock 602, for example to remove moisture and adsorbed gases. The chamber transfer port 616 to the processing chamber 614 is then opened and another robot (not shown) places the wafer on a pedestal in the first station shown in the reactor for processing. While the illustrated embodiment includes a load lock, it should be understood that in some embodiments direct loading of the wafer into the process station may be provided.

[0106] The illustrated processing chamber 614 includes four process stations, numbered 1 through 4 in the embodiment shown in FIG. 6. Each station has a heated pedestal (shown at 618 for station 1) and a gas line inlet. It should be understood that in some embodiments, each process station may have different or multiple purposes. For example, each of process stations 1-4 may be a chamber for performing one or more of ALD, CVD, CFD, or etching (any of which may be plasma assisted). In one embodiment, at least one process station is a deposition station having a reaction chamber, as shown in FIG. 5, and at least one other process station is an etching station having a reaction chamber, as shown in FIGS. 4A-4C. Although the illustrated processing chamber 614 includes four stations, it should be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments, a processing chamber may have three or fewer stations.

[0107] FIG. 6 also depicts an embodiment of a wafer handling system 609 for transporting wafers within the processing chamber 614. In some embodiments, the wafer handling system 609 may transport wafers between various process stations and / or between process stations and load locks. It will be understood that any suitable wafer handling system may be employed. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 6 also depicts an embodiment of a system controller 650 employed to control process conditions and hardware states of the process tool 600. The system controller 650 may include one or more memory devices 656, one or more mass storage devices 654, and one or more processors 652. The processor 652 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0108] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. This electronics may be referred to as a "controller," which may control various components or subcomponents of one or more systems. Depending on the processing requirements and / or type of system, the controller may be programmed to control any process, such as delivery of process gases disclosed herein, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid supply settings, position and motion settings, transport of wafers into and out of tools and other transport tools and / or load locks connected or interfaced to the particular system, etc.

[0109] Broadly speaking, a controller may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable end-point metrology, and the like. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various personalized settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing operations during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0110] The controller may be part of or coupled to a computer that is integrated, coupled, or otherwise networked to the system, or a combination thereof, in some embodiments. For example, the controller may be all or part of a host computer system in the "cloud" or at a fab that allows remote access to wafer processing. The computer may allow remote access to the system to monitor the current progress of a manufacturing operation, review the history of past manufacturing operations, review trends or performance metrics from multiple manufacturing operations, modify parameters of a current process, set processing operations following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing operation that is performed during one or more operations. It should be understood that the parameters may be specific to the type of process that is performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more separate controllers networked together and working toward a common purpose, such as the processes and controls described herein. An example of a controller distributed for such purposes would be one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) combined to control the process on the chamber.

[0111] Without limitation, exemplary systems may be a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, a molecular layer deposition (MLD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0112] As described above, depending on the process operation or operations being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, other controllers, or one or more of the tools used in material transport to transport containers of wafers to tool locations and / or load ports within a semiconductor manufacturing factory.

[0113] In certain embodiments, the controller has instructions to perform the operations shown and described with respect to FIG. 2A. For example, the controller may have instructions to periodically (a) perform an etching operation to partially etch a feature on the substrate, and (b) deposit a sidewall protective coating on the etched feature without substantially etching the substrate. Deposition of the sidewall protective coating may proceed by exposing the substrate to a first reactant, where the first reactant may include a dialdehyde or a trialdehyde, and exposing the substrate to a second reactant, where the first reactant and the second reactant react with each other to form the sidewall protective coating. The exposure to the first reactant and the second reactant may be repeated periodically until the protective coating reaches a target thickness. The instructions may relate to performing these processes using reaction conditions of the present disclosure. In some embodiments, the instructions may also relate to transporting the substrate between the etching chamber and the deposition chamber.

[0114] Returning to the embodiment of FIG. 6, in some embodiments, a system controller 650 controls all operations of the process tool 600. The system controller 650 executes system control software 658 stored on mass storage device 654, loaded into memory device 656, and executed by processor 652. Alternatively, the control logic may be hard-coded into the controller 650. For these purposes, application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used. In the following description, where "software" or "code" is used, functionally equivalent hard-coded logic may be used in that portion. The system control software 658 may include instructions for controlling the timing, mixture of gases, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, RF exposure times, substrate pedestal, chuck and / or susceptor positions, and other parameters of a particular process being performed in the process tool 600. The system control software 658 may be configured in any suitable manner. For example, subroutines or control objects of the various process tool components may be written to control the operation of the process tool components necessary to perform the processes of the various process tools. The system control software 658 may be coded in any suitable computer readable programming language.

[0115] In some embodiments, system control software 658 may include input / output control (IOC) array instructions for controlling the various parameters described above. For example, each stage of a CFD process may include one or more instructions for execution by system controller 650. Instructions for setting process conditions for an ALD process stage may be included in a corresponding ALD recipe stage. In some embodiments, the ALD recipe stages may be arranged in series such that all instructions for an ALD process stage are executed simultaneously with that process stage.

[0116] In some embodiments, other computer software and / or other programs stored on the mass storage device 654 and / or memory device 656 associated with the system controller 650 may be employed. Examples of programs or program sections for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0117] The substrate positioning program is used to load the substrate onto the pedestal 618 and may include program code for process tool components used to control the spacing between the substrate and other parts of the process tool 600.

[0118] The process gas control program may include code for controlling gas composition and flow rates to stabilize pressure in the process stations and for flowing gases into one or more process stations prior to deposition as necessary. In some embodiments, the controller may include instructions for depositing a nanolaminate protective layer on the core layer and depositing a conformal layer above the protective layer.

[0119] The pressure control program may include code for controlling the pressure in the process station, for example, by adjusting a throttle valve in the exhaust system of the process station, gas flow into the process station, etc. In some embodiments, the controller may include instructions for depositing a nanolaminate protective layer on the core layer and depositing a conformal layer over the protective layer.

[0120] The heater control program may include code for controlling current to a heating device used to heat the substrate. Alternatively, the heater control program may control a supply of a heat transfer gas (such as helium) to the substrate. In certain embodiments, the controller includes instructions for depositing a nanolaminate protective layer at a first temperature and depositing a conformal layer above the nanolaminate protective layer at a second temperature. The second temperature is greater than the first temperature.

[0121] The plasma control program may include code for setting RF power levels and exposure times of one or more process stations according to embodiments herein. In some embodiments, the controller may include instructions for depositing a nanolaminate protective layer at a first RF power level and RF duration and depositing a conformal layer at a second RF power level and RF duration. The second RF power level and / or the second RF duration may be higher / longer than the first RF power level / duration.

[0122] In some embodiments, there may be a user interface associated with the system controller 650. The user interface may include a display screen, graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0123] In some embodiments, the parameters adjusted by the system controller 650 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels and exposure times), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing a user interface.

[0124] Signals for monitoring the process may be provided from various process tool sensors by analog and / or digital input connections of the system controller 650. Signals for controlling the process may be output at analog and digital output connections of the process tool 600. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0125] The system controller 650 may provide program instructions for carrying out the deposition processes described above. The program instructions may control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. These instructions may control the parameters to operate the in-situ deposition of film stacks according to various embodiments described herein.

[0126] The system controller generally includes one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs methods according to embodiments of the present disclosure. A machine-readable, non-transitory medium including instructions for controlling process operations according to embodiments of the present disclosure may be coupled to the system controller.

[0127] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes for, for example, the fabrication or manufacture of semiconductor devices, display screens, LEDs, solar panels, etc. Typically, although not necessarily, such tools / processes will be used or performed together in a common fabrication facility.

[0128] FIG. 7 depicts a semiconductor process cluster architecture with various modules coupled to a vacuum transfer module (VTM) 738. The configuration of transfer modules for "transferring" substrates between multiple containment facilities and processing modules may be referred to as a "cluster tool architecture" system. An airlock 730, also known as a load lock or transfer module, is shown in the VTM 738 with four processing modules, processing modules 720a-720d, which may be individually optimized to perform various manufacturing processes. For example, processing modules 720a-720d may be implemented to perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and / or other semiconductor processes, as well as laser metrology and other defect detection and identification methods. One or more processing modules (any of 720a-720d) may be implemented as disclosed herein, i.e., etching recessed features into a substrate, depositing protective films on the sidewalls of the recessed features, and other suitable functions according to embodiments of the present disclosure. The airlock 730 and processing modules 720a-720d may be referred to as "stations." Each station has a facet 736 that couples the station with a VTM 738. Inside the facet, sensors 1-18 are used to detect the passage of the substrate 726 as it moves between the respective stations.

[0129] A robot 722 transfers substrates between stations. In one embodiment, the robot may have one arm, and in another embodiment, the robot may have two arms. Each arm has an end effector 724 that picks up the substrate for transfer. In the atmospheric transfer module (ATM) 740, a front-end robot 732 may be used to transfer substrates from a cassette or a full opening wafer pod (FOUP) 734 in a load port module (LPM) 742 to the airlock 730. The module center 728 inside the process modules 720a-720d may be one location for placing substrates. An aligner 744 in the ATM 740 may be used to align the substrate.

[0130] In an exemplary processing method, the substrate is placed in one of the FOUPs 734 of the LPM 742. The front-end robot 732 transfers the substrate from the FOUP 734 to an aligner 744 so that the substrate 726 can be properly centered before etching, deposition, or otherwise processing. After alignment, the substrate is moved into the airlock 730 by the front-end robot 732. The airlock module functions to match the environment between the ATM and the VTM so that the substrate can be moved between the two pressure environments without being damaged. From the airlock module 730, the substrate is moved by the robot 722 through the VTM 738 into one of the processing modules 720a-720d, for example, processing module 720a. To accomplish this substrate movement, the robot 722 uses an end effector 724 on each arm. In processing module 720a, the substrate is etched as described herein to form partially etched features. The robot 722 then moves the substrate from process module 720a into the VTM 738 and then into a different process module 720b. In process module 720b, a protective film is deposited on the sidewalls of the partially etched features. The robot 722 then moves the substrate from process module 720b into the VTM 738 and then into process module 720a, where the partially etched features are further etched. The etching / deposition can be repeated until the features are completely etched.

[0131] It should be noted that the computer controlling the movement of the substrate may be intrinsic to the cluster architecture, or may be located outside the cluster architecture at the manufacturing site, or may be connected to the cluster architecture over a network at a remote location.

[0132] Lithographic patterning of a film generally includes some or all of the following steps, each of which may be performed in a tool that may be used: (1) applying a photoresist to a workpiece, such as a substrate having a silicon nitride film thereon, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or UV or X-ray light using a tool such as a wafer stepper; (4) developing the resist and patterning the resist by selectively removing the resist using a tool such as a wet bench or spray developer; (5) transferring the resist pattern into the underlying film or workpiece using a dry etching tool or a plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF plasma resist stripper or a microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited before applying the photoresist.

[0133] It should be understood that the configurations and / or techniques described herein are exemplary in nature, as many variations are possible, and that these specific embodiments or examples should not be considered limiting. A particular routine or method described herein may represent any number of one or more process steps. As such, various operations described may be performed in the order described, in other orders, in parallel, or in some cases omitted. Similarly, the order of the processes described above may be altered.

[0134] The subject matter of the present disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, and all equivalents thereof.

Claims

1. A method for forming etched features in a laminate containing a dielectric material on a semiconductor substrate, wherein the method is: (a) A step of generating a first plasma containing etching reactants, exposing the substrate to the first plasma, and partially etching the features in the lamination, (b) After (a), a protective film is applied to the sidewall of the feature. (i) A step of exposing the substrate to a first reactant and adsorbing the first reactant onto the substrate, wherein the first reactant contains an aldehyde functional group, (ii) A step of exposing the substrate to a second reactant, wherein the first and second reactants react with each other to form the protective film, (iii) A step of periodically repeating (i) and (ii) until the protective film reaches a target thickness, wherein the protective film is an organic polymer film. The process of depositing by, (c) A step of repeating (a) and (b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etching of the feature during (a), and the feature has an aspect ratio of about 5 or more at its final depth. Methods that include...

2. The method according to claim 1, The method wherein the first reactant comprises a dialdehyde or trialaldehyde.

3. The method according to claim 2, The first reactant is succinaldehyde (C 4 H 6 O 2 ), glutaraldehyde (C 5 H 8 O 2 ), adipaldehyde (C 6 H 10 O 2 ), terephthalaldehyde (C 8 H 6 O 2 ), 1,4-benzenedicarboxaldehyde (C 6 H 4 (CHO) 2 ), orthophthalaldehyde (C 8 H 6 O 2 ), 1,2-benzenedicarboxaldehyde (C 6 H 4 (CHO) 2 ), and 2-methylglutaraldehyde (C 6 H 10 O 2 ) and includes at least one method.

4. The method according to claim 1, The method wherein the second reactant comprises at least one of a diamine, a diol, a thiol, and a trifunctional compound.

5. The method according to claim 4, The method wherein the second reactant comprises a diamine.

6. The method according to claim 4, The second reaction products are 1,2-ethanediamine, 1,3-propanediamine, 1,4-butanediamine, ethylenediamine, m-xylylenediamine, isophoronediamine, 1,3-cyclohexanebis(methylamine), 1,4-bis(aminomethyl)cyclohexane, 4,4'-methylenebis(2-methylcyclohexylamine), 4,4'-methylenebis(cyclohexylamine), m-phenylenediamine, p-phenylenediamine, 4-aminobenzylamine, 3-aminobenzylamine, 4-(2- A method comprising at least one of aminoethyl)aniline, p-xylylenediamine, m-xylylenediamine, ethylene glycol, 1,3-propanediol, 1,4-butanediol, 1,2-ethanedithiol, 1,3-propanedithiol, 1,4-butanedithiol, (±)-3-amino-1,2-propanediol, glycerol, bis(hexamethylene)triamine, melamine, diethylenetriamine, (±)-1,2,4-butanetriol, cyanuryl chloride, and trimethylaluminum.

7. The method according to claim 1, (b) A method wherein the deposition of the protective film is carried out without exposing the substrate to plasma energy.

8. The method according to claim 1, The method wherein the protective film comprises a polythioacetal or polyazomethine.

9. The method according to claim 1, A method wherein the etching of the features into the stack in (a) is carried out in a reaction chamber, and the deposition of the protective film onto the sidewalls of the features in (b) is carried out in the same reaction chamber.

10. The method according to claim 1, The etching reaction product comprises one or more fluorocarbons or hydrofluorocarbons, and the method is described above.

11. The method according to claim 1, A method wherein the deposition of the protective film in (b) is carried out in a reaction chamber, and the deposition of the protective film in (b) further comprises the step of purging the reaction chamber at least once between each iteration of operation (b).

12. The method according to claim 1, The lamination method comprises alternating layers of (i) a silicon oxide material and (ii) a silicon nitride material or a polysilicon material.

13. A method for forming etched features in a laminate containing a dielectric material on a semiconductor substrate, wherein the method is: (a) A step of generating a first plasma containing etching reactants, exposing the substrate to the first plasma, and partially etching the features in the lamination, (b) After (a), a protective film is applied to the sidewall of the feature. (i) A step of exposing the substrate to a first reactant and adsorbing the first reactant onto the substrate, wherein the first reactant contains an isocyanate functional group, (ii) A step of exposing the substrate to a second reactant, wherein the first and second reactants react with each other to form the protective film, (iii) A step of periodically repeating (i) and (ii) until the protective film reaches a target thickness, wherein the protective film is an organic polymer film. The process of depositing by, (c) A step of repeating (a) and (b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etching of the feature during (a), and the feature has an aspect ratio of about 5 or more at its final depth. Methods that include...

14. The method according to claim 13, The method wherein the first reactant comprises a diisocyanate.

15. The method according to claim 14, The method wherein the diisocyanate comprises at least one of torylene 2,4-diisocyanate, 1,3-bis(isocyanatomethyl)cyclohexane, hexamethylene diisocyanate, m-xylylene diisocyanate, 1,3-bis(1-isocyanato-1-methylethyl)benzene, isophorone diisocyanate, diphenylmethane-4,4'-diisocyanate, 4,4'-methylene-bis(cyclohexyl isocyanate), torylene-2,6-diisocyanate, 1,4-phenylenediisocyanate, 1,3-phenylenediisocyanate, and 3,3'-dimethyl-4,4'-biphenylenediisocyanate.

16. The method according to claim 13, The method wherein the second reactant comprises at least one of a diamine, a diol, a thiol, and a trifunctional compound.

17. The method according to claim 16, The method wherein the second reactant comprises a diamine.

18. The method according to claim 17, The method wherein the diamine comprises at least one of 1,2-ethanediamine, 1,3-propanediamine, 1,4-butanediamine, ethylenediamine, m-xylylenediamine, isophoronediamine, 1,3-cyclohexanebis(methylamine), 1,4-bis(aminomethyl)cyclohexane, 4,4'-methylenebis(2-methylcyclohexylamine), 4,4'-methylene-bis(cyclohexylamine), m-phenylenediamine, p-phenylenediamine, 4-aminobenzylamine, 3-aminobenzylamine, 4-(2-aminoethyl)aniline, p-xylylenediamine, and m-xylylenediamine.

19. The method according to claim 13, (b) A method wherein the deposition of the protective film is carried out without exposing the substrate to plasma energy.

20. The method according to claim 13, The method wherein the protective film comprises polyurea or polyurethane.

21. The method according to claim 13, A method wherein the deposition of the protective film in (b) is carried out in a reaction chamber, and the deposition of the protective film in (b) further comprises the step of purging the reaction chamber at least once between each iteration of operation (b).

22. The method according to claim 13, The lamination method comprises alternating layers of (i) a silicon oxide material and (ii) a silicon nitride material or a polysilicon material.

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