Method, apparatus, integrated circuits and printed circuit boards for reduced parasitic power conversion - Patents.com

Abstract

An apparatus can include a printed circuit board having an integrated circuit with a buck converter circuit and an inductor connected to the integrated circuit.

Description

[Technical field]

[0001] The present disclosure relates to power conversion, and more particularly to methods, apparatus, integrated circuits and printed circuit boards for power conversion with reduced parasitic losses. [Background technology]

[0002] Many electronic products, particularly mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices, LCD and LED displays), require multiple voltage levels. For example, a power amplifier for a radio frequency transmitter may require a relatively high voltage (e.g., 12 volts (V) or more), while logic circuits may require a lower voltage level (e.g., 1-2 V). Some other circuits may require an intermediate voltage level (e.g., 5-10 V). Power converters are often used to generate lower or higher voltages from a common power source, such as a battery, to meet the power requirements of various components in an electronic product. Summary of the Invention

[0003] Embodiments of the present disclosure may provide methods, apparatus, integrated circuits, and printed circuit boards for power conversion with reduced parasitic losses.

[0004] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. [Brief description of the drawings]

[0005] [Figure 1] FIG. 2 is a block diagram of an example controller for power conversion according to an embodiment of the disclosure. [Diagram 2] FIG. 2 is a circuit diagram of an example controller having a power switch according to an embodiment of the present disclosure. [Diagram 3] FIG. 1 is a perspective view of an exemplary apparatus for power conversion, according to an embodiment of the present disclosure. [Figure 4] FIG. 2 illustrates a top view of an exemplary printed circuit board for power conversion, according to an embodiment of the present disclosure. [Diagram 5] FIG. 1 illustrates a top view of an exemplary printed circuit board for power conversion in accordance with disclosed embodiments. [Figure 6] FIG. 2 is a diagram of electrical and optical signals on a printed circuit board layer. [Figure 7A] FIG. 1 is a perspective view of an exemplary portion of an integrated circuit for power conversion according to an embodiment of the present disclosure. [Figure 7B] 7B is an expanded perspective view of an exemplary portion of an integrated circuit for power conversion of FIG. 7A in accordance with an embodiment of the present disclosure. FIG. [Figure 7C] 7C is a side view of an example portion of an integrated circuit for power conversion of FIGS. 7A and 7B in accordance with an embodiment of the present disclosure. FIG. [Figure 8] 1 is a cross-sectional view of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure. [Figure 9] 1 is a cross-sectional view of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is a top view of an exemplary portion of an integrated circuit for power conversion, according to an embodiment of the present disclosure. [Figure 11] FIG. 2 illustrates a top view of an exemplary lead frame for power conversion, according to an embodiment of the present disclosure. [Figure 12] FIG. 2 is a bottom view of an exemplary lead frame for power conversion, according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a top view of an example transistor of a portion of an integrated circuit for power conversion, according to an embodiment of the present disclosure. [Figure 14] 14 is a top view of an exemplary portion of the transistor of FIG. 13 in accordance with an embodiment of the present disclosure. [Figure 15] 2 is a top view of an exemplary redistribution layer of an integrated circuit according to an embodiment of the present disclosure. [Figure 16] FIG. 2 is a top view of an example transistor of a portion of an integrated circuit for power conversion, according to an embodiment of the present disclosure. [Figure 17] 17 is a top view of an exemplary portion of the transistor of FIG. 16 in accordance with an embodiment of the present disclosure. [Figure 18] 17 is a top view of an exemplary portion of the transistor of FIG. 16 in accordance with an embodiment of the present disclosure. [Figure 19] 17 is a top view of an exemplary portion of the transistor of FIG. 16 in accordance with an embodiment of the present disclosure. [Figure 20] 17 is a top view of an exemplary portion of the transistor of FIG. 16 in accordance with an embodiment of the present disclosure. [Figure 21] 17 is a top view of an exemplary portion of the transistor of FIG. 16 in accordance with an embodiment of the present disclosure. [Figure 22] 22 is a top view of an exemplary portion of the transistor of FIG. 21 in accordance with an embodiment of the present disclosure. [Diagram 23] FIG. 1 is a circuit diagram of an exemplary device including an integrated circuit or controller for power conversion, according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] The following disclosure provides different exemplary embodiments or examples for implementing different features of the provided subject matter. To explain the present disclosure, certain simplified examples of components and configurations are described below. These embodiments are examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0007] The terms used herein generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples herein, including examples of any term discussed herein, is illustrative only and does not limit in any way the scope and meaning of the disclosure or of any exemplified term. Similarly, the disclosure is not limited to the various embodiments provided herein.

[0008] Terms such as "first", "second", etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0009] Spatially relative terms such as "lower," "below," "bottom," "upper," "top," "toward," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] In this disclosure, the term “coupled” can also be referred to as “electrically coupled,” and the term “connected” can also be referred to as “electrically connected.” “Coupled” and “connected” can also be used to indicate that two or more elements cooperate or interact with each other.

[0011] A power converter may receive, deliver, or operate with high current in one or more of its current paths. Power delivery paths and operation at high currents may be subject to parasitic losses that negatively impact performance. Parasitic losses include I 2and R, where "I" is the current and "R" is the resistance. As the current increases, the power loss becomes more significant. For example, the power delivery path and high current of a certain buck converter can reduce the power conversion efficiency due to parasitic losses. Additional constraints can exacerbate the undesirable parasitic losses. For example, limited die space can encourage signals to be spread out on the printed circuit board (PCB) and routed as needed.

[0012] For example, in some applications (e.g., servers, routers, etc.), optical cables can be interfaced with small form-factor pluggable (SFP) modules (e.g., optical transceivers with transmission rates of over 200 gigabits (G) per second, over 400G, over 200G, etc., quad SFP (QSFP), octal SFP (OSFP), bidirectional QSFP28 (BIDI QSFP28), and QSFP double density (QSFP-DD) applications). These modules require high current (e.g., 20 amperes (A)) and low voltage (e.g., 0.5 volts (V)) output to operate with high performance. However, the high current, low voltage path is highly susceptible to parasitic losses in the PCB. In addition, SFP modules use narrow and long PCBs, which may further exacerbate undesirable parasitic losses in the PCB.

[0013] A typical SFP module may suffer from parasitic losses. For example, a typical SFP module uses a single integrated circuit connected to one or more inductors to convert an input voltage (e.g., 3.3V to 0.5V at 20A) to an output voltage for a connected main signal processing application-specific integrated circuit (ASIC). One or more terminals of the single integrated circuit are connected to one or more inductors, which are further connected to the main signal processing ASIC. Typically, terminals are placed on multiple sides of the integrated circuit to increase the current provided by the single integrated circuit and the one or more inductors to the ASIC. However, using multiple terminals in close proximity to transfer the current from the single integrated circuit to the inductor results in so-called "current crowding" along the current path. Current crowding may cause increased parasitic losses in the PCB by increasing the current density.

[0014] Among other things, the disclosed embodiments can reduce such parasitic losses by routing current from an input voltage to one or more integrated circuits, each integrated circuit comprising a buck converter circuit. For example, the one or more integrated circuits can be positioned adjacent to one another along the width of the PCB, such that current crowding in each integrated circuit is reduced or eliminated. In some embodiments, each integrated circuit can be connected to one or more inductors by corresponding terminals. For example, the terminals can be positioned on the same or common side of each integrated circuit, such that each inductor of the one or more inductors is adjacent to one another on the same or common side of the one or more integrated circuits. The disclosed embodiments can reduce or eliminate current crowding in any of the one or more integrated circuits by routing current from the input voltage to one or more terminals across the width of the PCB, thereby reducing or eliminating parasitic losses and increasing efficiency in the PCB.

[0015] The disclosed embodiments may include designs that reduce the inductor requirements for the buck converters. For example, embodiments may include one or more charge pumps, either as part of each integrated circuit or in separate integrated circuits, to reduce the input voltage provided to each buck converter.

[0016] This arrangement reduces the inductor requirements of the buck converter (e.g., each inductor can have dimensions of 2.5 mm x 2.0 mm x 1.2 mm), allowing embodiments to use chip inductors for the buck converters even with relatively high input voltages (e.g., 3.3 V). For example, each integrated circuit can connect to a corresponding charge pump, and each charge pump can step down the input voltage before it is provided to the corresponding buck converter. By allowing the buck converters to operate using a step-down voltage, the requirements for the associated inductors can be reduced, thereby allowing chip conductors to be used instead of larger inductors that would take up additional space.

[0017] While embodiments of the present disclosure may address these problems and provide these advantages, the problems and features described are intended to be examples and are not limiting of the claims and scope of the present disclosure. Indeed, the disclosed embodiments may address problems and provide advantages that are not expressly recited.

[0018] FIG. 1 illustrates an example integrated circuit or controller (e.g., the integrated circuit IC1, the integrated circuit IC2, the integrated circuit IC3, the integrated circuit IC4, the integrated circuit IC5, the integrated circuit IC6, the integrated circuit IC7, the integrated circuit IC8, the integrated circuit IC9, the integrated circuit IC10, the integrated circuit IC110, the integrated circuit IC120, the integrated circuit IC130, the integrated circuit IC140, the integrated circuit IC150, the integrated circuit IC160, the integrated circuit IC170, the integrated circuit IC180, the integrated circuit IC190, the integrated circuit IC210, the integrated circuit IC220, the integrated circuit IC230, the integrated circuit IC240, the integrated circuit IC250, the integrated circuit IC260, the integrated circuit IC270, the integrated circuit IC280, the integrated circuit IC290, the integrated circuit IC290, the integrated circuit IC210, the integrated circuit IC240, the integrated circuit IC250, the N1, the integrated circuit or controller may provide a two-phase charge pump having dual outputs represented by terminals LX1 and LX2. It should be understood that when two integrated circuits are used, the two integrated circuits may use a total of four terminals (e.g., terminals LX1, LX2, LX3, and LX4). The integrated circuit or controller may include an input voltage VIN and a charge pump having capacitors C1, C2 (e.g., flying capacitors). The integrated circuit or controller may have terminals VX, LX1, LX2, and PGND. The integrated circuit or controller may have a compensation terminal COMP, an enable input EN, a synchronization terminal SYNC, and a feedback terminal FB. The PCB 100 may include transistors MH1, MH2, ML1, and ML2.

[0019] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0020] FIG. 2 illustrates an integrated circuit or controller (e.g., integrated circuit IC1, integrated circuit IC2, integrated circuit IC3, integrated circuit IC4, integrated circuit IC5, integrated circuit IC6, integrated circuit IC7, integrated circuit IC8, integrated circuit IC9, integrated circuit IC100, integrated circuit IC110, integrated circuit IC120, integrated circuit IC130, integrated circuit IC140, integrated circuit IC150, integrated circuit IC160, integrated circuit IC170, integrated circuit IC180, integrated circuit IC190, integrated circuit IC200, integrated circuit IC210, integrated circuit IC220, integrated circuit IC230, integrated circuit IC240, integrated circuit IC250, integrated circuit IC260, integrated circuit IC270, integrated circuit IC280, integrated circuit IC290, integrated circuit IC310, integrated circuit IC320, integrated circuit IC330, integrated circuit IC410, integrated circuit IC510, integrated circuit IC520, integrated circuit IC530, integrated circuit IC64 N 2 is a circuit diagram 1200 of an example device comprising: a first input terminal PGND; a second output terminal VOUT; a third output terminal VOUT; a fourth output terminal VOUT; a fifth output terminal VOUT; a fifth output terminal VOUT; a sixth output terminal VOUT; a fifth output terminal VOUT; a sixth output terminal VOUT; a sixth output terminal VOUT; a seventh ...

[0021] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0022] FIG. 3 is a perspective view of an exemplary device 10 (e.g., a SFP module) for power conversion according to the disclosed embodiments. FIG. 4 is a top view of an exemplary PCB 100 for power conversion according to the disclosed embodiments. As shown in FIG. 3, the device 10 may include the PCB 100. As shown in FIGS. 3 and 4, the PCB 100 may include a charge pump CP1, a charge pump CP2, an integrated circuit IC1, an integrated circuit IC2, an inductor L1, an inductor L2, an inductor L3, and an inductor L4. The charge pump CP1 may include a capacitor C1 and a capacitor C2. The charge pump CP2 may include a capacitor C3 and a capacitor C4. The integrated circuit IC1 and the integrated circuit IC2 may each include a buck converter circuit for power conversion. In some embodiments, the PCB 100 may include a capacitor C5. In some embodiments, the capacitor (e.g., the capacitor C1, C2, C3, C4, or C5) may be a 22 microfarad (μF) capacitor.

[0023] FIG. 5 is a top view of an exemplary PCB for power conversion according to disclosed embodiments. In some embodiments, the power converter can be placed under the ASIC. In some embodiments, the PCB can have a dual PCB layer as shown by the dotted line in FIG. 5. For example, the PCB can have a first PCB layer 510 and a second PCB layer 520, where the second PCB layer 520 can include a digital signal processor (DSP) component, a transoptical subassembly (TOSA), and a receiver optical subassembly (ROSA). The dual PCB allows for designs with taller inductors that may not fit in a single PCB layer with a smaller inductor. Applications can benefit from the embodiments described above and further below.

[0024] 6 is a diagram of electrical and optical signals on the second PCB layer 520. The TOSA can include one or more drivers and one or more laser diodes LD. The ROSA can include one or more transimpedance amplifiers TIA and one or more photodiodes PD.

[0025] As shown in FIG. 4, integrated circuit IC1 may be connected to inductor L1 by terminal LX1 and to inductor L2 by terminal LX2. Similarly, integrated circuit IC2 may be connected to inductor L3 by terminal LX3 and to inductor L4 by terminal LX4. In some embodiments, the inductor (e.g., inductor L1, L2, L3, or L4) may have a pin on one side of the inductor to which the chip inductor connects. The other side of the inductor may be connected to a pin (e.g., a VX pin) or a ground pin (e.g., terminal GND1, GND2, GND3, or GND4) via a power switch. In some embodiments, integrated circuit IC1 and inductor L1 may be connected to an input voltage V IN-1The output voltage V OUT The integrated circuit IC1 and the inductor L2 convert the input voltage V IN-2 The output voltage V OUT Similarly, integrated circuit IC2 and inductor L3 convert the input voltage V IN-3 The output voltage V OUT The integrated circuit IC2 and the inductor L4 convert the input voltage V IN-4 The output voltage V OUT In one example, V IN-1 ~V IN-4 may receive an input voltage that is supplied from a common source. IN-1 ~V IN-4 may receive input voltages provided from multiple sources.

[0026] In some embodiments, the layout of PCB 100 can be designed to reduce or eliminate parasitic losses along certain conductive paths of PCB 100. For example, a field effect transistor (FET) formed with terminals between a buck converter and an inductor may be particularly susceptible to parasitic losses caused by current crowding in the integrated circuit of the buck converter. Among other things, the disclosed embodiments can reduce such undesirable parasitic losses by routing current from an input voltage to integrated circuit IC1 and integrated circuit IC2. Integrated circuits IC1 and IC2 can be positioned adjacent to one another along the width of PCB 100 such that current crowding in integrated circuits IC1 and IC2 is reduced or eliminated.

[0027] The disclosed embodiments can advantageously reduce parasitic losses by optimizing the critical paths of an integrated circuit (IC) at the expense of non-critical paths. Buck converters operating at low duty cycles (e.g., less than 50%) rely more on the low-side FET current path (e.g., ML1) for better efficiency than the high-side current path (e.g., MH1). For example, the disclosed embodiments may optimize the critical path of an integrated circuit (e.g., IC1, IC2, or IC2) from a switch on one side of the integrated circuit to a terminal (e.g., terminal LX1, LX2, LX3, or LX4) at the expense of the non-critical path LX-MH1-VX from a switch to a charge pump (e.g., charge pump CP1 or CP2) on another side of the integrated circuit. N ) can be optimized. The disclosed embodiments can reduce parasitic losses by bridging the distance between the critical and non-critical paths using a lead frame. For example, charge pumps and integrated circuits can use lead frames.

[0028] As shown in Figures 3 and 4, the terminals GND1, GND2, GND3, and GND4 can be arranged on the same side or common side of the integrated circuits IC1 and IC2 such that the inductors L1, L2, L3, and L4 are adjacent to each other on the same side or common side of the integrated circuits IC1 and IC2. The disclosed embodiment can reduce or eliminate current crowding in the integrated circuits IC1 and IC2 by routing current from the input voltage to the terminals GND1, GND2, GND3, and GND4 across the width of the PCB 100, thereby reducing or eliminating parasitic losses and increasing power conversion efficiency in the PCB 100. That is, the terminals GND1, GND2, GND3, and GND4 are arranged across the width of the PCB 100, and the current transferred from the input voltage to each inductor of the inductors L1, L2, L3, and L4 is a low-density current, resulting in low resistive losses in the PCB 100. Because terminals GND1, GND2, GND3, GND4, LX1, LX2, LX3 and LX4 are positioned adjacent to one another across the width of PCB 100, current from the input voltage can be advantageously maximized and prevented from concentrating in any of inductors L1, L2, L3 or L4.

[0029] Inductors L1, L2, L3, and L4 may be chip inductors that may feature small packages and may be used in a variety of applications including power conversion and high frequency circuits. Chip inductors may be inductors provided in a chip form factor for use in integrated circuits of electronic devices. Chip inductors may be used in power converters, RF transceivers, computers, and other electronic devices. Exemplary chip inductors may have a ferrite core with wire windings or may have multiple wiring layers. Chip inductors may provide voltage holding advantages and may be used to form filter circuits and resonant circuits. Compared to traditional separate inductors, chip inductors may be smaller and lighter.

[0030] 3 and 4 show two integrated circuits and four inductors, it should be understood that embodiments of the present disclosure are not limited to such configurations. For example, any combination of any number of integrated circuits (e.g., one or more integrated circuits) and any number of inductors (e.g., one or more inductors) may be used in the present disclosure.

[0031] As shown in Figures 3 and 4, the PCB 100 is IN-1 and V IN-2 The integrated circuit IC1 may include a charge pump CP1 for stepping down the input of ...

[0032] Charge pump CP1 operates on an input voltage V IN-1 and V IN-2 and integrated circuit IC1. Similarly, the PCB 100 may be arranged between the input voltage V IN-3 and V IN-4 , which may be a two-phase charge pump formed by integrated circuit IC2 in conjunction with capacitors C3 and C4, with each phase divided by two. IN-3 and V IN-4 and integrated circuit IC2.

[0033] Integrated circuit IC1 may form a first buck regulator in conjunction with inductors L1 and L2. Similarly, integrated circuit IC2 may form a second buck regulator in conjunction with inductors L3 and L4. Integrated circuit IC1 and integrated circuit IC2 may include power switches for the first and second buck regulators, respectively.

[0034] Charge pump CP1 operates on an input voltage V IN-1 and V IN-2 before being provided to the integrated circuit IC1. Similarly, the charge pump CP2 can step down the input voltage V IN-3 and V IN-4 can be stepped down before being provided to integrated circuit IC2. The lower input voltage to the buck converter can reduce the requirements for inductors L1, L2, L3, and L4. Thus, in some embodiments, inductors L1, L2, L3, and L4 can be implemented with chip inductors instead of larger inductors that take up additional space.

[0035] In some embodiments, current can be transferred non-simultaneously from a corresponding charge pump (e.g., charge pump CP1) to a terminal (e.g., terminal GND1 or GND2) on an integrated circuit (e.g., integrated circuit IC1). For example, current can be transferred from charge pump CP1 to terminal GND1 at a time when there is no current transfer from charge pump CP1 to terminal GND2. This operation can further reduce or eliminate negative parasitic losses from current crowding at any terminal or inductor, thereby increasing power conversion efficiency. This non-simultaneous current transfer can occur simultaneously at terminals GND2, GND3, or GND4.

[0036] An integrated circuit (e.g., integrated circuits IC1, IC2 or IC N) provides several advantages and includes power switches connecting to capacitors and inductors to form a charge pump and buck regulator, as shown in FIGS. 3 and 4, although it should be understood that the present disclosure may include layouts of PCB 100 without a charge pump. The embodiments described herein without a charge pump may reduce or eliminate parasitic losses in PCB 100. Additionally, while FIGS. 3 and 4 show two charge pumps, it should be understood that the present disclosure does not limit the embodiments to two charge pumps and any number of charge pumps (e.g., one or more charge pumps) may be used. The one or more charge pumps may operate as single phase, two phase, or N phase. In other examples, any number of regulators may be used (e.g., one or more buck regulators, Cuk converters, multi-level, etc.). The one or more regulators may operate as single phase, two phase, or N phase.

[0037] During power conversion, current can flow from charge pump C1 to integrated circuit IC1 through conductive lines 111 and 113, and current can flow from charge pump C2 to integrated circuit IC2 through conductive lines 112 and 114. It should be understood that other conductive lines and terminals are shown but not labeled in Figure 4 and operate in a manner similar to conductive lines 111, 112, 113, and 114 and terminals GND1, GND2, GND3, GND4, LX1, LX2, LX3, and LX4.

[0038] Although the disclosed embodiments describe power conversion in the direction from a charge pump to a buck converter, it should be understood that the disclosed embodiments are also applicable to power conversion in the opposite direction (e.g., from a buck converter to a charge pump; a buck converter run in the reverse direction is referred to as a boost converter).

[0039] Although the disclosed embodiments have been described with respect to SFP modules, it should be understood that the disclosed embodiments are also applicable to other applications, such as, for example, any high current, low output voltage application where the total available width or area of ​​the PCB is limited, although the disclosed embodiments are not limited to such applications.

[0040] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0041] 7A is a perspective view of a portion of an IC (e.g., a portion of an IC) according to a disclosed embodiment, FIG. 7B is an exploded perspective view of the portion of the IC, and FIG. 7C is a side view of the portion of the IC. As shown in FIG. 7A, FIG. 7B, and FIG. 7C, an integrated circuit IC N An integrated circuit (eg, IC1 or IC2 of FIG. 3 or FIG. 4) can be attached to leadframe 301 by pillars 302 (eg, copper pillars).

[0042] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0043] 8 is a cross-sectional view of a portion of an IC (e.g., a portion of an IC, a portion of an IC of FIG. 7A, FIG. 7B, and FIG. 7C, etc.) according to a disclosed embodiment. As shown in FIG. 8, an integrated circuit IC N (For example, the integrated circuit IC1 or IC2 of FIG. 3 or FIG. 4, the integrated circuit IC N etc.) may comprise a die 303 (e.g., a silicon die) and interconnects 304. NThe integrated circuit IC may be attached to a lead frame 301 (such as the lead frame 301 in FIGS. 7A, 7B, and 7C) by pillars 302 (such as the pillars 302 in FIGS. 7A, 7B, and 7C). N , the leadframe 301 and pillars 302 may be encapsulated by a material (e.g., molding compound, insulating material, etc.). The leadframe 301 may comprise a thick metal (e.g., 150 micrometers of copper) that improves the routing of current from the input voltage, thereby reducing current crowding and reducing or eliminating undesirable parasitic losses in the PCB 100.

[0044] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0045] 9 is a cross-sectional view of a portion of an integrated circuit (IC) (e.g., a portion of an IC, a portion of an IC in FIGS. 7A, 7B, 7C, and 8, etc.) according to a disclosed embodiment. As shown in FIG. 9, a portion of a PCB is an integrated circuit IC N (For example, the integrated circuit IC1 or IC2 of FIG. 3 or FIG. 4, the integrated circuit IC N 7A, 7B, 7C, and 8). The IC may have solder 306 on a first end of the pillar 302 to bond the pillar 302 to a lead frame 301 (e.g., lead frame 301 of FIGS. 7A, 7B, 7C, and 8). The IC may have solder 306 on a first end of the pillar 302 to bond the pillar 302 to a lead frame 301 (e.g., lead frame 301 of FIGS. 7A, 7B, 7C, and 8). The IC may have solder 306 on a second end of the pillar 302, opposite the first end, to bond the pillar 302 (and lead frame 301) to an integrated circuit IC N 3. The semiconductor device may include an under bump metallization (UBM) 307 for connection to the semiconductor device.

[0046] As shown in Figure 9, the integrated circuit IC Nmay include a redistribution layer (RDL) 308 (e.g., copper metal interconnect) and metal layers 309 for connecting or bonding various components of the PCB. N may include an insulating layer 310 (e.g., polyimide) between the UBM 307 and the RDL 308, an insulating layer 311 (e.g., polyimide) between the RDL 308 and an insulating layer 312 (e.g., Si3N4), which may be between the insulating layer 311 and the metal layer 309. The insulating layer 310 may include openings 310A around or near the pillars 302 and the UBM 307, the insulating layer 311 may include openings 311A ​​around or near the RDL 308 and the metal layer 309, and the insulating layer 312 may include openings 312A around or near the metal layer 309. Integrated Circuit IC N may include a back end of line (BEOL) layer 313 having one or more devices 314 and a substrate 315 (eg, a silicon substrate).

[0047] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0048] FIG. 10 is a top view of a portion of an IC (e.g., a portion of an IC, a portion of an IC in FIG. 7A, FIG. 7B, FIG. 7C, FIG. 8, and FIG. 9, etc.) according to disclosed embodiments. As shown in FIG. 10, a portion of a PCB can include an integrated circuit IC1, an inductor L1, and terminals GND1, GND2, GND, LX1, and LX2. As explained above, a current flow 601 is shown in the direction from the integrated circuit IC1 to the inductor L1. FIG. 10 shows a field effect transistor (FET) formed on the PCB, including a transistor MH2 and a transistor ML2. The disclosed embodiments include a transistor formed with terminals GND1 and LX1. In some embodiments, for this converter (optical transceiver) application, the PCB can have a resistance of 0.4 milliohms (mOhm), the lead frame can have a resistance of 0.4 mOhm, the transistor can have a resistance of 1.5 mOhm or 2.1 mOhm, and the die metal can have a resistance of 1.5 mOhm, although other resistances are possible.

[0049] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0050] 11 is a top view 700 of a leadframe 301 (such as leadframe 301 of FIGS. 7A, 7B, 7C, 8, 9, etc.) according to a disclosed embodiment. As shown in FIG. 11, leadframe 301 includes plated areas 701. Top view 700 of leadframe 301 shows IC connections to terminals C1, C2, and VX, input voltage VIN, and terminals GND, LX1, LX2, P1, and P2. Top view 700 of leadframe 301 shows transistors M11, M12, M21, M22, M31, M32, M41, M42, MH1, MH2, ML1, and ML2. Leadframe 301 can have thick metal (e.g., 150 micrometers of copper) that improves current routing from the input voltage, thereby reducing current crowding and reducing or eliminating undesirable parasitic losses in PCB 100.

[0051] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0052] 12 is a bottom view 800 of a leadframe 301 (such as leadframe 301 of FIGS. 7A, 7B, 7C, 8, 9, 11, etc.) in accordance with a disclosed embodiment. As shown in FIG. 12, leadframe 301 includes bottom half etched regions 801 and bare copper areas 802.

[0053] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0054] 13 is a top view of transistors MH2 and ML2 of a portion of an IC (e.g., a portion of an IC, a portion of an IC in FIGS. 7A, 7B, 7C, 8, 9, and 10, etc.) in accordance with disclosed embodiments. FIG. 13 includes a first view 900A of transistors MH2 and ML2 and a second view 900B of transistors MH2 and ML2. The first view 900A shows an edge IC1 of integrated circuit IC1. E , metal layer 309, the intermediate VX node, and terminals LX2 and GND2. E , pillar 302, RDL 308, source S, drain D, intermediate VX node, and terminals LX2 and GND2 are shown. The first diagram 900A and the second diagram 900B include portions 1001A and 1001B, respectively, shown in FIG.

[0055] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0056] 14 is a top view of portions 1001A and 1001B of transistors MH2 and ML2 according to disclosed embodiments. Portion 1001A shows metal layer 309, opening 311A ​​in insulating layer 311, opening 312A in insulating layer 312A, source S, and drain D. Portion 1001B shows opening 310A in insulating layer 310, RDL 308, UBM 307, pillar 302, source S, and drain D.

[0057] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0058] FIG. 15 illustrates an integrated circuit (e.g., integrated circuits IC1, IC2, IC N 15 is a top view 1500 of an RDL (e.g., RDL 308) of a conventional LDOF. As shown in FIG. 15, the top view 1500 of the RDL illustrates the connections of the integrated circuit to terminals C1, C2, and VX, an input voltage VIN, and terminals PGND, LX1, LX2, P1, and P2. The top view 1500 of the RDL illustrates a compensation pin COMP, an enable input EN, a synchronization pin SYNC, a feedback pin FB, and a power good pin PGOOD. In some embodiments, the terminals PGND and GND are synonymous.

[0059] Figure 16 is a top view of transistor ML2 of a portion of an IC (e.g., a portion of an IC, a portion of a PCB in Figures 7A, 7B, 7C, 8, 9, and 10, etc.) in accordance with disclosed embodiments. Figure 16 shows the source side, drain side, and portion 1601 shown in Figures 17, 18, 19, 20, and 21.

[0060] 17 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows a first metal layer, a via between the first and second metal layers, a source S, and a drain D.

[0061] 18 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows the second metal layer, a via between the second metal layer and the third metal layer, a source S, and a drain D.

[0062] 19 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows the third metal layer, a via between the third and fourth metal layers, a source S, and a drain D.

[0063] 20 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows an upper metal layer (e.g., metal layer 309), an insulating layer (e.g., insulating layers 310, 311, and / or 312), openings (e.g., openings 310A, 311A, and / or 312A), source S, and drain D.

[0064] 21 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows the polysilicon layer, diffusion layer, and portion 2100 shown in FIG.

[0065] 22 is a top view of a portion 2100 of transistor ML2 according to a disclosed embodiment. Portion 2100 shows gate G, source S, and drain D.

[0066] FIG. 23 illustrates an integrated circuit or controller (integrated circuits IC1, IC2, IC N 23 is a circuit diagram 2300 of an example device having a buck converter Buck and an output voltage V OUT It can be provided with:

[0067] It should be understood that in some embodiments, repeated reference numbers and / or letters in the various figures of the disclosure relate to one another and indicate that the figures relate to one another, while in some other embodiments, this repetition does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed.

[0068] In the above specification, the embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications to the described embodiments may be made. Other embodiments may become apparent to those skilled in the art upon consideration of the specification and practice of the disclosure disclosed herein. Additionally, the order of steps depicted in the figures is for illustrative purposes only and is not intended to limit the scope of the invention to any particular order of steps. Thus, those skilled in the art may understand that steps may be performed in different orders while implementing the same method.

[0069] It is understood that certain features of the specification that are described for clarity in the context of separate embodiments can also be provided in combination in a single embodiment. Conversely, various features of the specification that are described for brevity in the context of a single embodiment can also be provided separately or in any suitable subcombination or manner in any other described embodiment of the specification. Certain features described in the context of various embodiments are not to be construed as essential features of an embodiment unless the embodiment is inoperable without those elements.

[0070] The embodiments can be further described using the following clauses. 1. A printed circuit board (PCB) for power conversion, comprising: an integrated circuit having a buck converter circuit; an inductor connected to the integrated circuit; Including the PCB. 2. A printed circuit board (PCB) for power conversion, comprising: a plurality of integrated circuits, each integrated circuit of the plurality of integrated circuits including a buck converter circuit; a plurality of inductors connected to each integrated circuit of the plurality of integrated circuits; Including the PCB. 3. The PCB of item 2, in which each integrated circuit of the multiple integrated circuits is connected to each inductor of the multiple inductors by a corresponding terminal. 4. The PCB of item 3, wherein each corresponding terminal is located on a common side of each integrated circuit of the multiple integrated circuits. 5. The PCB of item 2, in which multiple integrated circuits are adjacent to each other. 6. The PCB of item 2, in which multiple inductors are adjacent to each other on a common side of multiple integrated circuits. 7. The PCB of item 2, in which each integrated circuit of the multiple integrated circuits is connected to a corresponding charge pump. 8. The PCB of clause 7, wherein each corresponding charge pump comprises one or more capacitors. 9. An apparatus equipped with a PCB according to any one of items 1 to 8. 10. A printed circuit board (PCB) for power conversion, comprising: a first integrated circuit and a second integrated circuit, each of the first integrated circuit and the second integrated circuit including a buck converter circuit, the first integrated circuit and the second integrated circuit being disposed adjacent to one another; a first inductor and a second inductor connected to the first integrated circuit; a third inductor and a fourth inductor connected to the second integrated circuit; Including the PCB. 11. A first integrated circuit is connected to a first inductor by a first corresponding terminal, and the first integrated circuit is connected to a second inductor by a second corresponding terminal; Item 11. The PCB of item 10, wherein the second integrated circuit is connected to the third inductor by a third corresponding terminal, and the second integrated circuit is connected to the fourth inductor by a fourth corresponding terminal. 12. The PCB of item 10, wherein each of the first terminal, the second terminal, the third terminal, and the fourth terminal is disposed on a common side of each integrated circuit of the plurality of integrated circuits. 13. The PCB of item 10, wherein the first inductor, the second inductor, the third inductor and the fourth inductor are adjacent to each other on a common side of the first integrated circuit and the second integrated circuit. 14. The PCB of item 10, wherein a first integrated circuit is connected to the first charge pump and a second integrated circuit is connected to the second charge pump. 15. The PCB of claim 14, wherein the first charge pump and the second charge pump each comprise one or more capacitors. 16. An apparatus equipped with a PCB according to any one of items 10 to 15.

Claims

1. A printed circuit board (PCB) for power conversion, A plurality of integrated circuits, wherein each of the plurality of integrated circuits has a buck converter circuit, A plurality of inductors, wherein each inductor of the plurality of inductors is connected to each integrated circuit of the plurality of integrated circuits, each integrated circuit of the plurality of integrated circuits is connected to each inductor of the plurality of inductors by a corresponding terminal, and each corresponding terminal is located on the common side of each integrated circuit of the plurality of integrated circuits, and The PCB comprising the above.

2. The PCB according to claim 1, wherein the plurality of integrated circuits are adjacent to each other.

3. The PCB according to claim 1 or 2, wherein the plurality of inductors are adjacent to each other on the common side of the plurality of integrated circuits.

4. The PCB according to claim 1 or 2, wherein each of the plurality of integrated circuits is connected to a corresponding charging pump.

5. The PCB according to claim 2, wherein each corresponding charging pump comprises one or more capacitors.

6. The PCB according to claim 1 or 2, further comprising a plurality of adjacent ground terminals on a common side of the plurality of integrated circuits, wherein the plurality of ground terminals are further adjacent to the plurality of inductors.

7. The common side of the plurality of integrated circuits further comprises a plurality of adjacent ground terminals, the plurality of ground terminals further adjacent to the plurality of inductors, The PCB according to claim 2, configured to receive input voltages routed to the plurality of ground terminals and further routed to their respective corresponding terminals and the plurality of inductors across the width of the PCB.

8. A printed circuit board (PCB) for power conversion, A first integrated circuit and a second integrated circuit, wherein each of the first integrated circuit and the second integrated circuit includes a buck converter circuit, and the first integrated circuit and the second integrated circuit are arranged adjacent to each other. A first inductor and a second inductor connected to the first integrated circuit, A third inductor and a fourth inductor connected to the second integrated circuit, Equipped with, The first integrated circuit is connected to the first inductor by a first corresponding terminal, and the first integrated circuit is connected to the second inductor by a second corresponding terminal. The PCB wherein the second integrated circuit is connected to the third inductor by a third corresponding terminal, the second integrated circuit is connected to the fourth inductor by a fourth corresponding terminal, and each of the first terminal, the second terminal, the third terminal and the fourth terminal is located on the common side of each of the plurality of integrated circuits.

9. The PCB according to claim 8, wherein the first inductor, the second inductor, the third inductor and the fourth inductor are adjacent to each other on the common side of the first integrated circuit and the second integrated circuit.

10. The PCB according to claim 8 or 9, wherein the first integrated circuit is connected to a first charge pump and the second integrated circuit is connected to a second charge pump.

11. The PCB according to claim 10, wherein the first charge pump and the second charge pump each comprise one or more capacitors.

12. The PCB according to claim 8 or 9, wherein a first ground terminal is connected to the first terminal, a second ground terminal is connected to the second terminal, a third ground terminal is connected to the third terminal, and a fourth ground terminal is connected to the fourth terminal.

13. The PCB according to claim 9, wherein a first ground terminal is connected to the first terminal, a second ground terminal is connected to the second terminal, a third ground terminal is connected to the third terminal, a fourth ground terminal is connected to the fourth terminal, and is configured to receive input voltages routed to the first, second, third and fourth ground terminals and further routed to the first, second, third and fourth terminals and to the inductor, respectively, across the width of the PCB.

14. A printed circuit board (PCB) for power conversion, An integrated circuit including a buck converter circuit, A plurality of inductors connected to the aforementioned integrated circuit, wherein the integrated circuit is connected to each of the plurality of inductors by corresponding terminals, and each corresponding terminal is located on the common side of each of the plurality of integrated circuits, The PCB comprising the above.

15. An apparatus comprising the PCB described in Claim 1.

16. An apparatus comprising the PCB described in Claim 3.

17. An apparatus comprising the PCB described in Claim 5.

18. An apparatus comprising the PCB described in Claim 8.

19. An apparatus comprising the PCB described in Claim 11.

20. An apparatus comprising the PCB described in Claim 14.

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